1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2018, The Linux Foundation. All rights reserved. 3 #include <linux/clk-provider.h> 4 #include <linux/module.h> 5 #include <linux/of_device.h> 6 #include <linux/platform_device.h> 7 #include <linux/regmap.h> 8 9 #include "clk-alpha-pll.h" 10 11 static const u8 ipq_pll_offsets[] = { 12 [PLL_OFF_L_VAL] = 0x08, 13 [PLL_OFF_ALPHA_VAL] = 0x10, 14 [PLL_OFF_USER_CTL] = 0x18, 15 [PLL_OFF_CONFIG_CTL] = 0x20, 16 [PLL_OFF_CONFIG_CTL_U] = 0x24, 17 [PLL_OFF_STATUS] = 0x28, 18 [PLL_OFF_TEST_CTL] = 0x30, 19 [PLL_OFF_TEST_CTL_U] = 0x34, 20 }; 21 22 static struct clk_alpha_pll ipq_pll = { 23 .offset = 0x0, 24 .regs = ipq_pll_offsets, 25 .flags = SUPPORTS_DYNAMIC_UPDATE, 26 .clkr = { 27 .enable_reg = 0x0, 28 .enable_mask = BIT(0), 29 .hw.init = &(struct clk_init_data){ 30 .name = "a53pll", 31 .parent_data = &(const struct clk_parent_data) { 32 .fw_name = "xo", 33 }, 34 .num_parents = 1, 35 .ops = &clk_alpha_pll_huayra_ops, 36 }, 37 }, 38 }; 39 40 static const struct alpha_pll_config ipq6018_pll_config = { 41 .l = 0x37, 42 .config_ctl_val = 0x240d4828, 43 .config_ctl_hi_val = 0x6, 44 .early_output_mask = BIT(3), 45 .aux2_output_mask = BIT(2), 46 .aux_output_mask = BIT(1), 47 .main_output_mask = BIT(0), 48 .test_ctl_val = 0x1c0000C0, 49 .test_ctl_hi_val = 0x4000, 50 }; 51 52 static const struct alpha_pll_config ipq8074_pll_config = { 53 .l = 0x48, 54 .config_ctl_val = 0x200d4828, 55 .config_ctl_hi_val = 0x6, 56 .early_output_mask = BIT(3), 57 .aux2_output_mask = BIT(2), 58 .aux_output_mask = BIT(1), 59 .main_output_mask = BIT(0), 60 .test_ctl_val = 0x1c000000, 61 .test_ctl_hi_val = 0x4000, 62 }; 63 64 static const struct regmap_config ipq_pll_regmap_config = { 65 .reg_bits = 32, 66 .reg_stride = 4, 67 .val_bits = 32, 68 .max_register = 0x40, 69 .fast_io = true, 70 }; 71 72 static int apss_ipq_pll_probe(struct platform_device *pdev) 73 { 74 const struct alpha_pll_config *ipq_pll_config; 75 struct device *dev = &pdev->dev; 76 struct regmap *regmap; 77 void __iomem *base; 78 int ret; 79 80 base = devm_platform_ioremap_resource(pdev, 0); 81 if (IS_ERR(base)) 82 return PTR_ERR(base); 83 84 regmap = devm_regmap_init_mmio(dev, base, &ipq_pll_regmap_config); 85 if (IS_ERR(regmap)) 86 return PTR_ERR(regmap); 87 88 ipq_pll_config = of_device_get_match_data(&pdev->dev); 89 if (!ipq_pll_config) 90 return -ENODEV; 91 92 clk_alpha_pll_configure(&ipq_pll, regmap, ipq_pll_config); 93 94 ret = devm_clk_register_regmap(dev, &ipq_pll.clkr); 95 if (ret) 96 return ret; 97 98 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 99 &ipq_pll.clkr.hw); 100 } 101 102 static const struct of_device_id apss_ipq_pll_match_table[] = { 103 { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config }, 104 { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_config }, 105 { } 106 }; 107 MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table); 108 109 static struct platform_driver apss_ipq_pll_driver = { 110 .probe = apss_ipq_pll_probe, 111 .driver = { 112 .name = "qcom-ipq-apss-pll", 113 .of_match_table = apss_ipq_pll_match_table, 114 }, 115 }; 116 module_platform_driver(apss_ipq_pll_driver); 117 118 MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver"); 119 MODULE_LICENSE("GPL v2"); 120