1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 4 * 5 * Header file for Host Controller registers and I/O accessors. 6 * 7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 8 */ 9 #ifndef __SDHCI_HW_H 10 #define __SDHCI_HW_H 11 12 #include <linux/bits.h> 13 #include <linux/scatterlist.h> 14 #include <linux/compiler.h> 15 #include <linux/types.h> 16 #include <linux/io.h> 17 #include <linux/leds.h> 18 #include <linux/interrupt.h> 19 20 #include <linux/mmc/host.h> 21 22 /* 23 * Controller registers 24 */ 25 26 #define SDHCI_DMA_ADDRESS 0x00 27 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 28 #define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS 29 30 #define SDHCI_BLOCK_SIZE 0x04 31 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 32 33 #define SDHCI_BLOCK_COUNT 0x06 34 35 #define SDHCI_ARGUMENT 0x08 36 37 #define SDHCI_TRANSFER_MODE 0x0C 38 #define SDHCI_TRNS_DMA 0x01 39 #define SDHCI_TRNS_BLK_CNT_EN 0x02 40 #define SDHCI_TRNS_AUTO_CMD12 0x04 41 #define SDHCI_TRNS_AUTO_CMD23 0x08 42 #define SDHCI_TRNS_AUTO_SEL 0x0C 43 #define SDHCI_TRNS_READ 0x10 44 #define SDHCI_TRNS_MULTI 0x20 45 46 #define SDHCI_COMMAND 0x0E 47 #define SDHCI_CMD_RESP_MASK 0x03 48 #define SDHCI_CMD_CRC 0x08 49 #define SDHCI_CMD_INDEX 0x10 50 #define SDHCI_CMD_DATA 0x20 51 #define SDHCI_CMD_ABORTCMD 0xC0 52 53 #define SDHCI_CMD_RESP_NONE 0x00 54 #define SDHCI_CMD_RESP_LONG 0x01 55 #define SDHCI_CMD_RESP_SHORT 0x02 56 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 57 58 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 59 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 60 61 #define SDHCI_RESPONSE 0x10 62 63 #define SDHCI_BUFFER 0x20 64 65 #define SDHCI_PRESENT_STATE 0x24 66 #define SDHCI_CMD_INHIBIT 0x00000001 67 #define SDHCI_DATA_INHIBIT 0x00000002 68 #define SDHCI_DOING_WRITE 0x00000100 69 #define SDHCI_DOING_READ 0x00000200 70 #define SDHCI_SPACE_AVAILABLE 0x00000400 71 #define SDHCI_DATA_AVAILABLE 0x00000800 72 #define SDHCI_CARD_PRESENT 0x00010000 73 #define SDHCI_CARD_PRES_SHIFT 16 74 #define SDHCI_CD_STABLE 0x00020000 75 #define SDHCI_CD_LVL 0x00040000 76 #define SDHCI_CD_LVL_SHIFT 18 77 #define SDHCI_WRITE_PROTECT 0x00080000 78 #define SDHCI_DATA_LVL_MASK 0x00F00000 79 #define SDHCI_DATA_LVL_SHIFT 20 80 #define SDHCI_DATA_0_LVL_MASK 0x00100000 81 #define SDHCI_CMD_LVL 0x01000000 82 83 #define SDHCI_HOST_CONTROL 0x28 84 #define SDHCI_CTRL_LED 0x01 85 #define SDHCI_CTRL_4BITBUS 0x02 86 #define SDHCI_CTRL_HISPD 0x04 87 #define SDHCI_CTRL_DMA_MASK 0x18 88 #define SDHCI_CTRL_SDMA 0x00 89 #define SDHCI_CTRL_ADMA1 0x08 90 #define SDHCI_CTRL_ADMA32 0x10 91 #define SDHCI_CTRL_ADMA64 0x18 92 #define SDHCI_CTRL_ADMA3 0x18 93 #define SDHCI_CTRL_8BITBUS 0x20 94 #define SDHCI_CTRL_CDTEST_INS 0x40 95 #define SDHCI_CTRL_CDTEST_EN 0x80 96 97 #define SDHCI_POWER_CONTROL 0x29 98 #define SDHCI_POWER_ON 0x01 99 #define SDHCI_POWER_180 0x0A 100 #define SDHCI_POWER_300 0x0C 101 #define SDHCI_POWER_330 0x0E 102 103 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 104 105 #define SDHCI_WAKE_UP_CONTROL 0x2B 106 #define SDHCI_WAKE_ON_INT 0x01 107 #define SDHCI_WAKE_ON_INSERT 0x02 108 #define SDHCI_WAKE_ON_REMOVE 0x04 109 110 #define SDHCI_CLOCK_CONTROL 0x2C 111 #define SDHCI_DIVIDER_SHIFT 8 112 #define SDHCI_DIVIDER_HI_SHIFT 6 113 #define SDHCI_DIV_MASK 0xFF 114 #define SDHCI_DIV_MASK_LEN 8 115 #define SDHCI_DIV_HI_MASK 0x300 116 #define SDHCI_PROG_CLOCK_MODE 0x0020 117 #define SDHCI_CLOCK_CARD_EN 0x0004 118 #define SDHCI_CLOCK_PLL_EN 0x0008 119 #define SDHCI_CLOCK_INT_STABLE 0x0002 120 #define SDHCI_CLOCK_INT_EN 0x0001 121 122 #define SDHCI_TIMEOUT_CONTROL 0x2E 123 124 #define SDHCI_SOFTWARE_RESET 0x2F 125 #define SDHCI_RESET_ALL 0x01 126 #define SDHCI_RESET_CMD 0x02 127 #define SDHCI_RESET_DATA 0x04 128 129 #define SDHCI_INT_STATUS 0x30 130 #define SDHCI_INT_ENABLE 0x34 131 #define SDHCI_SIGNAL_ENABLE 0x38 132 #define SDHCI_INT_RESPONSE 0x00000001 133 #define SDHCI_INT_DATA_END 0x00000002 134 #define SDHCI_INT_BLK_GAP 0x00000004 135 #define SDHCI_INT_DMA_END 0x00000008 136 #define SDHCI_INT_SPACE_AVAIL 0x00000010 137 #define SDHCI_INT_DATA_AVAIL 0x00000020 138 #define SDHCI_INT_CARD_INSERT 0x00000040 139 #define SDHCI_INT_CARD_REMOVE 0x00000080 140 #define SDHCI_INT_CARD_INT 0x00000100 141 #define SDHCI_INT_RETUNE 0x00001000 142 #define SDHCI_INT_CQE 0x00004000 143 #define SDHCI_INT_ERROR 0x00008000 144 #define SDHCI_INT_TIMEOUT 0x00010000 145 #define SDHCI_INT_CRC 0x00020000 146 #define SDHCI_INT_END_BIT 0x00040000 147 #define SDHCI_INT_INDEX 0x00080000 148 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 149 #define SDHCI_INT_DATA_CRC 0x00200000 150 #define SDHCI_INT_DATA_END_BIT 0x00400000 151 #define SDHCI_INT_BUS_POWER 0x00800000 152 #define SDHCI_INT_AUTO_CMD_ERR 0x01000000 153 #define SDHCI_INT_ADMA_ERROR 0x02000000 154 155 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 156 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 157 158 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 159 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \ 160 SDHCI_INT_AUTO_CMD_ERR) 161 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 162 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 163 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 164 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 165 SDHCI_INT_BLK_GAP) 166 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 167 168 #define SDHCI_CQE_INT_ERR_MASK ( \ 169 SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \ 170 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \ 171 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT) 172 173 #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE) 174 175 #define SDHCI_AUTO_CMD_STATUS 0x3C 176 #define SDHCI_AUTO_CMD_TIMEOUT 0x00000002 177 #define SDHCI_AUTO_CMD_CRC 0x00000004 178 #define SDHCI_AUTO_CMD_END_BIT 0x00000008 179 #define SDHCI_AUTO_CMD_INDEX 0x00000010 180 181 #define SDHCI_HOST_CONTROL2 0x3E 182 #define SDHCI_CTRL_UHS_MASK 0x0007 183 #define SDHCI_CTRL_UHS_SDR12 0x0000 184 #define SDHCI_CTRL_UHS_SDR25 0x0001 185 #define SDHCI_CTRL_UHS_SDR50 0x0002 186 #define SDHCI_CTRL_UHS_SDR104 0x0003 187 #define SDHCI_CTRL_UHS_DDR50 0x0004 188 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ 189 #define SDHCI_CTRL_VDD_180 0x0008 190 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 191 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 192 #define SDHCI_CTRL_DRV_TYPE_A 0x0010 193 #define SDHCI_CTRL_DRV_TYPE_C 0x0020 194 #define SDHCI_CTRL_DRV_TYPE_D 0x0030 195 #define SDHCI_CTRL_EXEC_TUNING 0x0040 196 #define SDHCI_CTRL_TUNED_CLK 0x0080 197 #define SDHCI_CMD23_ENABLE 0x0800 198 #define SDHCI_CTRL_V4_MODE 0x1000 199 #define SDHCI_CTRL_64BIT_ADDR 0x2000 200 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 201 202 #define SDHCI_CAPABILITIES 0x40 203 #define SDHCI_TIMEOUT_CLK_MASK GENMASK(5, 0) 204 #define SDHCI_TIMEOUT_CLK_SHIFT 0 205 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 206 #define SDHCI_CLOCK_BASE_MASK GENMASK(13, 8) 207 #define SDHCI_CLOCK_BASE_SHIFT 8 208 #define SDHCI_CLOCK_V3_BASE_MASK GENMASK(15, 8) 209 #define SDHCI_MAX_BLOCK_MASK 0x00030000 210 #define SDHCI_MAX_BLOCK_SHIFT 16 211 #define SDHCI_CAN_DO_8BIT 0x00040000 212 #define SDHCI_CAN_DO_ADMA2 0x00080000 213 #define SDHCI_CAN_DO_ADMA1 0x00100000 214 #define SDHCI_CAN_DO_HISPD 0x00200000 215 #define SDHCI_CAN_DO_SDMA 0x00400000 216 #define SDHCI_CAN_DO_SUSPEND 0x00800000 217 #define SDHCI_CAN_VDD_330 0x01000000 218 #define SDHCI_CAN_VDD_300 0x02000000 219 #define SDHCI_CAN_VDD_180 0x04000000 220 #define SDHCI_CAN_64BIT_V4 0x08000000 221 #define SDHCI_CAN_64BIT 0x10000000 222 223 #define SDHCI_CAPABILITIES_1 0x44 224 #define SDHCI_SUPPORT_SDR50 0x00000001 225 #define SDHCI_SUPPORT_SDR104 0x00000002 226 #define SDHCI_SUPPORT_DDR50 0x00000004 227 #define SDHCI_DRIVER_TYPE_A 0x00000010 228 #define SDHCI_DRIVER_TYPE_C 0x00000020 229 #define SDHCI_DRIVER_TYPE_D 0x00000040 230 #define SDHCI_RETUNING_TIMER_COUNT_MASK GENMASK(11, 8) 231 #define SDHCI_USE_SDR50_TUNING 0x00002000 232 #define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14) 233 #define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16) 234 #define SDHCI_CAN_DO_ADMA3 0x08000000 235 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ 236 237 #define SDHCI_MAX_CURRENT 0x48 238 #define SDHCI_MAX_CURRENT_LIMIT GENMASK(7, 0) 239 #define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0) 240 #define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8) 241 #define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16) 242 #define SDHCI_MAX_CURRENT_MULTIPLIER 4 243 244 /* 4C-4F reserved for more max current */ 245 246 #define SDHCI_SET_ACMD12_ERROR 0x50 247 #define SDHCI_SET_INT_ERROR 0x52 248 249 #define SDHCI_ADMA_ERROR 0x54 250 251 /* 55-57 reserved */ 252 253 #define SDHCI_ADMA_ADDRESS 0x58 254 #define SDHCI_ADMA_ADDRESS_HI 0x5C 255 256 /* 60-FB reserved */ 257 258 #define SDHCI_PRESET_FOR_HIGH_SPEED 0x64 259 #define SDHCI_PRESET_FOR_SDR12 0x66 260 #define SDHCI_PRESET_FOR_SDR25 0x68 261 #define SDHCI_PRESET_FOR_SDR50 0x6A 262 #define SDHCI_PRESET_FOR_SDR104 0x6C 263 #define SDHCI_PRESET_FOR_DDR50 0x6E 264 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ 265 #define SDHCI_PRESET_DRV_MASK GENMASK(15, 14) 266 #define SDHCI_PRESET_CLKGEN_SEL BIT(10) 267 #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0) 268 269 #define SDHCI_SLOT_INT_STATUS 0xFC 270 271 #define SDHCI_HOST_VERSION 0xFE 272 #define SDHCI_VENDOR_VER_MASK 0xFF00 273 #define SDHCI_VENDOR_VER_SHIFT 8 274 #define SDHCI_SPEC_VER_MASK 0x00FF 275 #define SDHCI_SPEC_VER_SHIFT 0 276 #define SDHCI_SPEC_100 0 277 #define SDHCI_SPEC_200 1 278 #define SDHCI_SPEC_300 2 279 #define SDHCI_SPEC_400 3 280 #define SDHCI_SPEC_410 4 281 #define SDHCI_SPEC_420 5 282 283 /* 284 * End of controller registers. 285 */ 286 287 #define SDHCI_MAX_DIV_SPEC_200 256 288 #define SDHCI_MAX_DIV_SPEC_300 2046 289 290 /* 291 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 292 */ 293 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 294 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 295 296 /* ADMA2 32-bit DMA descriptor size */ 297 #define SDHCI_ADMA2_32_DESC_SZ 8 298 299 /* ADMA2 32-bit descriptor */ 300 struct sdhci_adma2_32_desc { 301 __le16 cmd; 302 __le16 len; 303 __le32 addr; 304 } __packed __aligned(4); 305 306 /* ADMA2 data alignment */ 307 #define SDHCI_ADMA2_ALIGN 4 308 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) 309 310 /* 311 * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte 312 * alignment for the descriptor table even in 32-bit DMA mode. Memory 313 * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. 314 */ 315 #define SDHCI_ADMA2_DESC_ALIGN 8 316 317 /* 318 * ADMA2 64-bit DMA descriptor size 319 * According to SD Host Controller spec v4.10, there are two kinds of 320 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit 321 * Descriptor, if Host Version 4 Enable is set in the Host Control 2 322 * register, 128-bit Descriptor will be selected. 323 */ 324 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) 325 326 /* 327 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte 328 * aligned. 329 */ 330 struct sdhci_adma2_64_desc { 331 __le16 cmd; 332 __le16 len; 333 __le32 addr_lo; 334 __le32 addr_hi; 335 } __packed __aligned(4); 336 337 #define ADMA2_TRAN_VALID 0x21 338 #define ADMA2_NOP_END_VALID 0x3 339 #define ADMA2_END 0x2 340 341 /* 342 * Maximum segments assuming a 512KiB maximum requisition size and a minimum 343 * 4KiB page size. 344 */ 345 #define SDHCI_MAX_SEGS 128 346 347 /* Allow for a a command request and a data request at the same time */ 348 #define SDHCI_MAX_MRQS 2 349 350 /* 351 * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms. 352 * However since the start time of the command, the time between 353 * command and response, and the time between response and start of data is 354 * not known, set the command transfer time to 10ms. 355 */ 356 #define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */ 357 358 enum sdhci_cookie { 359 COOKIE_UNMAPPED, 360 COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ 361 COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ 362 }; 363 364 struct sdhci_host { 365 /* Data set by hardware interface driver */ 366 const char *hw_name; /* Hardware bus name */ 367 368 unsigned int quirks; /* Deviations from spec. */ 369 370 /* Controller doesn't honor resets unless we touch the clock register */ 371 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 372 /* Controller has bad caps bits, but really supports DMA */ 373 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 374 /* Controller doesn't like to be reset when there is no card inserted. */ 375 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 376 /* Controller doesn't like clearing the power reg before a change */ 377 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 378 /* Controller has flaky internal state so reset it on each ios change */ 379 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 380 /* Controller has an unusable DMA engine */ 381 #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 382 /* Controller has an unusable ADMA engine */ 383 #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 384 /* Controller can only DMA from 32-bit aligned addresses */ 385 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 386 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 387 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 388 /* Controller can only ADMA chunks that are a multiple of 32 bits */ 389 #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 390 /* Controller needs to be reset after each request to stay stable */ 391 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 392 /* Controller needs voltage and power writes to happen separately */ 393 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 394 /* Controller provides an incorrect timeout value for transfers */ 395 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 396 /* Controller has an issue with buffer bits for small transfers */ 397 #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 398 /* Controller does not provide transfer-complete interrupt when not busy */ 399 #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 400 /* Controller has unreliable card detection */ 401 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 402 /* Controller reports inverted write-protect state */ 403 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 404 /* Controller has unusable command queue engine */ 405 #define SDHCI_QUIRK_BROKEN_CQE (1<<17) 406 /* Controller does not like fast PIO transfers */ 407 #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 408 /* Controller does not have a LED */ 409 #define SDHCI_QUIRK_NO_LED (1<<19) 410 /* Controller has to be forced to use block size of 2048 bytes */ 411 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 412 /* Controller cannot do multi-block transfers */ 413 #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 414 /* Controller can only handle 1-bit data transfers */ 415 #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 416 /* Controller needs 10ms delay between applying power and clock */ 417 #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 418 /* Controller uses SDCLK instead of TMCLK for data timeouts */ 419 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 420 /* Controller reports wrong base clock capability */ 421 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 422 /* Controller cannot support End Attribute in NOP ADMA descriptor */ 423 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 424 /* Controller is missing device caps. Use caps provided by host */ 425 #define SDHCI_QUIRK_MISSING_CAPS (1<<27) 426 /* Controller uses Auto CMD12 command to stop the transfer */ 427 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 428 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 429 #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 430 /* Controller treats ADMA descriptors with length 0000h incorrectly */ 431 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 432 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ 433 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) 434 435 unsigned int quirks2; /* More deviations from spec. */ 436 437 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 438 #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 439 /* The system physically doesn't support 1.8v, even if the host does */ 440 #define SDHCI_QUIRK2_NO_1_8_V (1<<2) 441 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 442 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 443 /* Controller has a non-standard host control register */ 444 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 445 /* Controller does not support HS200 */ 446 #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 447 /* Controller does not support DDR50 */ 448 #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 449 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 450 #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 451 /* Controller does not support 64-bit DMA */ 452 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 453 /* need clear transfer mode register before send cmd */ 454 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 455 /* Capability register bit-63 indicates HS400 support */ 456 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 457 /* forced tuned clock */ 458 #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) 459 /* disable the block count for single block transactions */ 460 #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) 461 /* Controller broken with using ACMD23 */ 462 #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) 463 /* Broken Clock divider zero in controller */ 464 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) 465 /* Controller has CRC in 136 bit Command Response */ 466 #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) 467 /* 468 * Disable HW timeout if the requested timeout is more than the maximum 469 * obtainable timeout. 470 */ 471 #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) 472 /* 473 * 32-bit block count may not support eMMC where upper bits of CMD23 are used 474 * for other purposes. Consequently we support 16-bit block count by default. 475 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit 476 * block count. 477 */ 478 #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) 479 480 int irq; /* Device IRQ */ 481 void __iomem *ioaddr; /* Mapped address */ 482 phys_addr_t mapbase; /* physical address base */ 483 char *bounce_buffer; /* For packing SDMA reads/writes */ 484 dma_addr_t bounce_addr; 485 unsigned int bounce_buffer_size; 486 487 const struct sdhci_ops *ops; /* Low level hw interface */ 488 489 /* Internal data */ 490 struct mmc_host *mmc; /* MMC structure */ 491 struct mmc_host_ops mmc_host_ops; /* MMC host ops */ 492 u64 dma_mask; /* custom DMA mask */ 493 494 #if IS_ENABLED(CONFIG_LEDS_CLASS) 495 struct led_classdev led; /* LED control */ 496 char led_name[32]; 497 #endif 498 499 spinlock_t lock; /* Mutex */ 500 501 int flags; /* Host attributes */ 502 #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 503 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 504 #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 505 #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 506 #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 507 #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 508 #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 509 #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 510 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 511 #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 512 #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ 513 #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ 514 #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ 515 516 unsigned int version; /* SDHCI spec. version */ 517 518 unsigned int max_clk; /* Max possible freq (MHz) */ 519 unsigned int timeout_clk; /* Timeout freq (KHz) */ 520 u8 max_timeout_count; /* Vendor specific max timeout count */ 521 unsigned int clk_mul; /* Clock Muliplier value */ 522 523 unsigned int clock; /* Current clock (MHz) */ 524 u8 pwr; /* Current voltage */ 525 526 bool runtime_suspended; /* Host is runtime suspended */ 527 bool bus_on; /* Bus power prevents runtime suspend */ 528 bool preset_enabled; /* Preset is enabled */ 529 bool pending_reset; /* Cmd/data reset is pending */ 530 bool irq_wake_enabled; /* IRQ wakeup is enabled */ 531 bool v4_mode; /* Host Version 4 Enable */ 532 bool use_external_dma; /* Host selects to use external DMA */ 533 bool always_defer_done; /* Always defer to complete requests */ 534 535 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ 536 struct mmc_command *cmd; /* Current command */ 537 struct mmc_command *data_cmd; /* Current data command */ 538 struct mmc_command *deferred_cmd; /* Deferred command */ 539 struct mmc_data *data; /* Current data request */ 540 unsigned int data_early:1; /* Data finished before cmd */ 541 542 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 543 unsigned int blocks; /* remaining PIO blocks */ 544 545 int sg_count; /* Mapped sg entries */ 546 547 void *adma_table; /* ADMA descriptor table */ 548 void *align_buffer; /* Bounce buffer */ 549 550 size_t adma_table_sz; /* ADMA descriptor table size */ 551 size_t align_buffer_sz; /* Bounce buffer size */ 552 553 dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 554 dma_addr_t align_addr; /* Mapped bounce buffer */ 555 556 unsigned int desc_sz; /* ADMA current descriptor size */ 557 unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */ 558 559 struct workqueue_struct *complete_wq; /* Request completion wq */ 560 struct work_struct complete_work; /* Request completion work */ 561 562 struct timer_list timer; /* Timer for timeouts */ 563 struct timer_list data_timer; /* Timer for data timeouts */ 564 565 #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA) 566 struct dma_chan *rx_chan; 567 struct dma_chan *tx_chan; 568 #endif 569 570 u32 caps; /* CAPABILITY_0 */ 571 u32 caps1; /* CAPABILITY_1 */ 572 bool read_caps; /* Capability flags have been read */ 573 574 bool sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */ 575 unsigned int ocr_avail_sdio; /* OCR bit masks */ 576 unsigned int ocr_avail_sd; 577 unsigned int ocr_avail_mmc; 578 u32 ocr_mask; /* available voltages */ 579 580 unsigned timing; /* Current timing */ 581 582 u32 thread_isr; 583 584 /* cached registers */ 585 u32 ier; 586 587 bool cqe_on; /* CQE is operating */ 588 u32 cqe_ier; /* CQE interrupt mask */ 589 u32 cqe_err_ier; /* CQE error interrupt mask */ 590 591 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 592 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 593 594 unsigned int tuning_count; /* Timer count for re-tuning */ 595 unsigned int tuning_mode; /* Re-tuning mode supported by host */ 596 unsigned int tuning_err; /* Error code for re-tuning */ 597 #define SDHCI_TUNING_MODE_1 0 598 #define SDHCI_TUNING_MODE_2 1 599 #define SDHCI_TUNING_MODE_3 2 600 /* Delay (ms) between tuning commands */ 601 int tuning_delay; 602 int tuning_loop_count; 603 604 /* Host SDMA buffer boundary. */ 605 u32 sdma_boundary; 606 607 /* Host ADMA table count */ 608 u32 adma_table_cnt; 609 610 u64 data_timeout; 611 612 unsigned long private[] ____cacheline_aligned; 613 }; 614 615 struct sdhci_ops { 616 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 617 u32 (*read_l)(struct sdhci_host *host, int reg); 618 u16 (*read_w)(struct sdhci_host *host, int reg); 619 u8 (*read_b)(struct sdhci_host *host, int reg); 620 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 621 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 622 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 623 #endif 624 625 void (*set_clock)(struct sdhci_host *host, unsigned int clock); 626 void (*set_power)(struct sdhci_host *host, unsigned char mode, 627 unsigned short vdd); 628 629 u32 (*irq)(struct sdhci_host *host, u32 intmask); 630 631 int (*set_dma_mask)(struct sdhci_host *host); 632 int (*enable_dma)(struct sdhci_host *host); 633 unsigned int (*get_max_clock)(struct sdhci_host *host); 634 unsigned int (*get_min_clock)(struct sdhci_host *host); 635 /* get_timeout_clock should return clk rate in unit of Hz */ 636 unsigned int (*get_timeout_clock)(struct sdhci_host *host); 637 unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 638 void (*set_timeout)(struct sdhci_host *host, 639 struct mmc_command *cmd); 640 void (*set_bus_width)(struct sdhci_host *host, int width); 641 void (*platform_send_init_74_clocks)(struct sdhci_host *host, 642 u8 power_mode); 643 unsigned int (*get_ro)(struct sdhci_host *host); 644 void (*reset)(struct sdhci_host *host, u8 mask); 645 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 646 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 647 void (*hw_reset)(struct sdhci_host *host); 648 void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 649 void (*card_event)(struct sdhci_host *host); 650 void (*voltage_switch)(struct sdhci_host *host); 651 void (*adma_write_desc)(struct sdhci_host *host, void **desc, 652 dma_addr_t addr, int len, unsigned int cmd); 653 void (*copy_to_bounce_buffer)(struct sdhci_host *host, 654 struct mmc_data *data, 655 unsigned int length); 656 void (*request_done)(struct sdhci_host *host, 657 struct mmc_request *mrq); 658 void (*dump_vendor_regs)(struct sdhci_host *host); 659 }; 660 661 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 662 663 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 664 { 665 if (unlikely(host->ops->write_l)) 666 host->ops->write_l(host, val, reg); 667 else 668 writel(val, host->ioaddr + reg); 669 } 670 671 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 672 { 673 if (unlikely(host->ops->write_w)) 674 host->ops->write_w(host, val, reg); 675 else 676 writew(val, host->ioaddr + reg); 677 } 678 679 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 680 { 681 if (unlikely(host->ops->write_b)) 682 host->ops->write_b(host, val, reg); 683 else 684 writeb(val, host->ioaddr + reg); 685 } 686 687 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 688 { 689 if (unlikely(host->ops->read_l)) 690 return host->ops->read_l(host, reg); 691 else 692 return readl(host->ioaddr + reg); 693 } 694 695 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 696 { 697 if (unlikely(host->ops->read_w)) 698 return host->ops->read_w(host, reg); 699 else 700 return readw(host->ioaddr + reg); 701 } 702 703 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 704 { 705 if (unlikely(host->ops->read_b)) 706 return host->ops->read_b(host, reg); 707 else 708 return readb(host->ioaddr + reg); 709 } 710 711 #else 712 713 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 714 { 715 writel(val, host->ioaddr + reg); 716 } 717 718 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 719 { 720 writew(val, host->ioaddr + reg); 721 } 722 723 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 724 { 725 writeb(val, host->ioaddr + reg); 726 } 727 728 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 729 { 730 return readl(host->ioaddr + reg); 731 } 732 733 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 734 { 735 return readw(host->ioaddr + reg); 736 } 737 738 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 739 { 740 return readb(host->ioaddr + reg); 741 } 742 743 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 744 745 struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size); 746 void sdhci_free_host(struct sdhci_host *host); 747 748 static inline void *sdhci_priv(struct sdhci_host *host) 749 { 750 return host->private; 751 } 752 753 void sdhci_card_detect(struct sdhci_host *host); 754 void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver, 755 const u32 *caps, const u32 *caps1); 756 int sdhci_setup_host(struct sdhci_host *host); 757 void sdhci_cleanup_host(struct sdhci_host *host); 758 int __sdhci_add_host(struct sdhci_host *host); 759 int sdhci_add_host(struct sdhci_host *host); 760 void sdhci_remove_host(struct sdhci_host *host, int dead); 761 762 static inline void sdhci_read_caps(struct sdhci_host *host) 763 { 764 __sdhci_read_caps(host, NULL, NULL, NULL); 765 } 766 767 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 768 unsigned int *actual_clock); 769 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 770 void sdhci_enable_clk(struct sdhci_host *host, u16 clk); 771 void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 772 unsigned short vdd); 773 void sdhci_set_power_and_bus_voltage(struct sdhci_host *host, 774 unsigned char mode, 775 unsigned short vdd); 776 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 777 unsigned short vdd); 778 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq); 779 int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq); 780 void sdhci_set_bus_width(struct sdhci_host *host, int width); 781 void sdhci_reset(struct sdhci_host *host, u8 mask); 782 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 783 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 784 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 785 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 786 struct mmc_ios *ios); 787 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); 788 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, 789 dma_addr_t addr, int len, unsigned int cmd); 790 791 #ifdef CONFIG_PM 792 int sdhci_suspend_host(struct sdhci_host *host); 793 int sdhci_resume_host(struct sdhci_host *host); 794 int sdhci_runtime_suspend_host(struct sdhci_host *host); 795 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset); 796 #endif 797 798 void sdhci_cqe_enable(struct mmc_host *mmc); 799 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery); 800 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, 801 int *data_error); 802 803 void sdhci_dumpregs(struct sdhci_host *host); 804 void sdhci_enable_v4_mode(struct sdhci_host *host); 805 806 void sdhci_start_tuning(struct sdhci_host *host); 807 void sdhci_end_tuning(struct sdhci_host *host); 808 void sdhci_reset_tuning(struct sdhci_host *host); 809 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); 810 void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode); 811 void sdhci_switch_external_dma(struct sdhci_host *host, bool en); 812 void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable); 813 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); 814 815 #endif /* __SDHCI_HW_H */ 816