1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADS1015 - Texas Instruments Analog-to-Digital Converter 4 * 5 * Copyright (c) 2016, Intel Corporation. 6 * 7 * IIO driver for ADS1015 ADC 7-bit I2C slave address: 8 * * 0x48 - ADDR connected to Ground 9 * * 0x49 - ADDR connected to Vdd 10 * * 0x4A - ADDR connected to SDA 11 * * 0x4B - ADDR connected to SCL 12 */ 13 14 #include <linux/module.h> 15 #include <linux/init.h> 16 #include <linux/irq.h> 17 #include <linux/i2c.h> 18 #include <linux/property.h> 19 #include <linux/regmap.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/mutex.h> 22 #include <linux/delay.h> 23 24 #include <linux/iio/iio.h> 25 #include <linux/iio/types.h> 26 #include <linux/iio/sysfs.h> 27 #include <linux/iio/events.h> 28 #include <linux/iio/buffer.h> 29 #include <linux/iio/triggered_buffer.h> 30 #include <linux/iio/trigger_consumer.h> 31 32 #define ADS1015_DRV_NAME "ads1015" 33 34 #define ADS1015_CHANNELS 8 35 36 #define ADS1015_CONV_REG 0x00 37 #define ADS1015_CFG_REG 0x01 38 #define ADS1015_LO_THRESH_REG 0x02 39 #define ADS1015_HI_THRESH_REG 0x03 40 41 #define ADS1015_CFG_COMP_QUE_SHIFT 0 42 #define ADS1015_CFG_COMP_LAT_SHIFT 2 43 #define ADS1015_CFG_COMP_POL_SHIFT 3 44 #define ADS1015_CFG_COMP_MODE_SHIFT 4 45 #define ADS1015_CFG_DR_SHIFT 5 46 #define ADS1015_CFG_MOD_SHIFT 8 47 #define ADS1015_CFG_PGA_SHIFT 9 48 #define ADS1015_CFG_MUX_SHIFT 12 49 50 #define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0) 51 #define ADS1015_CFG_COMP_LAT_MASK BIT(2) 52 #define ADS1015_CFG_COMP_POL_MASK BIT(3) 53 #define ADS1015_CFG_COMP_MODE_MASK BIT(4) 54 #define ADS1015_CFG_DR_MASK GENMASK(7, 5) 55 #define ADS1015_CFG_MOD_MASK BIT(8) 56 #define ADS1015_CFG_PGA_MASK GENMASK(11, 9) 57 #define ADS1015_CFG_MUX_MASK GENMASK(14, 12) 58 59 /* Comparator queue and disable field */ 60 #define ADS1015_CFG_COMP_DISABLE 3 61 62 /* Comparator polarity field */ 63 #define ADS1015_CFG_COMP_POL_LOW 0 64 #define ADS1015_CFG_COMP_POL_HIGH 1 65 66 /* Comparator mode field */ 67 #define ADS1015_CFG_COMP_MODE_TRAD 0 68 #define ADS1015_CFG_COMP_MODE_WINDOW 1 69 70 /* device operating modes */ 71 #define ADS1015_CONTINUOUS 0 72 #define ADS1015_SINGLESHOT 1 73 74 #define ADS1015_SLEEP_DELAY_MS 2000 75 #define ADS1015_DEFAULT_PGA 2 76 #define ADS1015_DEFAULT_DATA_RATE 4 77 #define ADS1015_DEFAULT_CHAN 0 78 79 enum chip_ids { 80 ADSXXXX = 0, 81 ADS1015, 82 ADS1115, 83 }; 84 85 enum ads1015_channels { 86 ADS1015_AIN0_AIN1 = 0, 87 ADS1015_AIN0_AIN3, 88 ADS1015_AIN1_AIN3, 89 ADS1015_AIN2_AIN3, 90 ADS1015_AIN0, 91 ADS1015_AIN1, 92 ADS1015_AIN2, 93 ADS1015_AIN3, 94 ADS1015_TIMESTAMP, 95 }; 96 97 static const unsigned int ads1015_data_rate[] = { 98 128, 250, 490, 920, 1600, 2400, 3300, 3300 99 }; 100 101 static const unsigned int ads1115_data_rate[] = { 102 8, 16, 32, 64, 128, 250, 475, 860 103 }; 104 105 /* 106 * Translation from PGA bits to full-scale positive and negative input voltage 107 * range in mV 108 */ 109 static int ads1015_fullscale_range[] = { 110 6144, 4096, 2048, 1024, 512, 256, 256, 256 111 }; 112 113 /* 114 * Translation from COMP_QUE field value to the number of successive readings 115 * exceed the threshold values before an interrupt is generated 116 */ 117 static const int ads1015_comp_queue[] = { 1, 2, 4 }; 118 119 static const struct iio_event_spec ads1015_events[] = { 120 { 121 .type = IIO_EV_TYPE_THRESH, 122 .dir = IIO_EV_DIR_RISING, 123 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 124 BIT(IIO_EV_INFO_ENABLE), 125 }, { 126 .type = IIO_EV_TYPE_THRESH, 127 .dir = IIO_EV_DIR_FALLING, 128 .mask_separate = BIT(IIO_EV_INFO_VALUE), 129 }, { 130 .type = IIO_EV_TYPE_THRESH, 131 .dir = IIO_EV_DIR_EITHER, 132 .mask_separate = BIT(IIO_EV_INFO_ENABLE) | 133 BIT(IIO_EV_INFO_PERIOD), 134 }, 135 }; 136 137 #define ADS1015_V_CHAN(_chan, _addr) { \ 138 .type = IIO_VOLTAGE, \ 139 .indexed = 1, \ 140 .address = _addr, \ 141 .channel = _chan, \ 142 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 143 BIT(IIO_CHAN_INFO_SCALE) | \ 144 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 145 .scan_index = _addr, \ 146 .scan_type = { \ 147 .sign = 's', \ 148 .realbits = 12, \ 149 .storagebits = 16, \ 150 .shift = 4, \ 151 .endianness = IIO_CPU, \ 152 }, \ 153 .event_spec = ads1015_events, \ 154 .num_event_specs = ARRAY_SIZE(ads1015_events), \ 155 .datasheet_name = "AIN"#_chan, \ 156 } 157 158 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \ 159 .type = IIO_VOLTAGE, \ 160 .differential = 1, \ 161 .indexed = 1, \ 162 .address = _addr, \ 163 .channel = _chan, \ 164 .channel2 = _chan2, \ 165 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 166 BIT(IIO_CHAN_INFO_SCALE) | \ 167 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 168 .scan_index = _addr, \ 169 .scan_type = { \ 170 .sign = 's', \ 171 .realbits = 12, \ 172 .storagebits = 16, \ 173 .shift = 4, \ 174 .endianness = IIO_CPU, \ 175 }, \ 176 .event_spec = ads1015_events, \ 177 .num_event_specs = ARRAY_SIZE(ads1015_events), \ 178 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \ 179 } 180 181 #define ADS1115_V_CHAN(_chan, _addr) { \ 182 .type = IIO_VOLTAGE, \ 183 .indexed = 1, \ 184 .address = _addr, \ 185 .channel = _chan, \ 186 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 187 BIT(IIO_CHAN_INFO_SCALE) | \ 188 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 189 .scan_index = _addr, \ 190 .scan_type = { \ 191 .sign = 's', \ 192 .realbits = 16, \ 193 .storagebits = 16, \ 194 .endianness = IIO_CPU, \ 195 }, \ 196 .event_spec = ads1015_events, \ 197 .num_event_specs = ARRAY_SIZE(ads1015_events), \ 198 .datasheet_name = "AIN"#_chan, \ 199 } 200 201 #define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \ 202 .type = IIO_VOLTAGE, \ 203 .differential = 1, \ 204 .indexed = 1, \ 205 .address = _addr, \ 206 .channel = _chan, \ 207 .channel2 = _chan2, \ 208 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 209 BIT(IIO_CHAN_INFO_SCALE) | \ 210 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 211 .scan_index = _addr, \ 212 .scan_type = { \ 213 .sign = 's', \ 214 .realbits = 16, \ 215 .storagebits = 16, \ 216 .endianness = IIO_CPU, \ 217 }, \ 218 .event_spec = ads1015_events, \ 219 .num_event_specs = ARRAY_SIZE(ads1015_events), \ 220 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \ 221 } 222 223 struct ads1015_channel_data { 224 bool enabled; 225 unsigned int pga; 226 unsigned int data_rate; 227 }; 228 229 struct ads1015_thresh_data { 230 unsigned int comp_queue; 231 int high_thresh; 232 int low_thresh; 233 }; 234 235 struct ads1015_data { 236 struct regmap *regmap; 237 /* 238 * Protects ADC ops, e.g: concurrent sysfs/buffered 239 * data reads, configuration updates 240 */ 241 struct mutex lock; 242 struct ads1015_channel_data channel_data[ADS1015_CHANNELS]; 243 244 unsigned int event_channel; 245 unsigned int comp_mode; 246 struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS]; 247 248 unsigned int *data_rate; 249 /* 250 * Set to true when the ADC is switched to the continuous-conversion 251 * mode and exits from a power-down state. This flag is used to avoid 252 * getting the stale result from the conversion register. 253 */ 254 bool conv_invalid; 255 }; 256 257 static bool ads1015_event_channel_enabled(struct ads1015_data *data) 258 { 259 return (data->event_channel != ADS1015_CHANNELS); 260 } 261 262 static void ads1015_event_channel_enable(struct ads1015_data *data, int chan, 263 int comp_mode) 264 { 265 WARN_ON(ads1015_event_channel_enabled(data)); 266 267 data->event_channel = chan; 268 data->comp_mode = comp_mode; 269 } 270 271 static void ads1015_event_channel_disable(struct ads1015_data *data, int chan) 272 { 273 data->event_channel = ADS1015_CHANNELS; 274 } 275 276 static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg) 277 { 278 switch (reg) { 279 case ADS1015_CFG_REG: 280 case ADS1015_LO_THRESH_REG: 281 case ADS1015_HI_THRESH_REG: 282 return true; 283 default: 284 return false; 285 } 286 } 287 288 static const struct regmap_config ads1015_regmap_config = { 289 .reg_bits = 8, 290 .val_bits = 16, 291 .max_register = ADS1015_HI_THRESH_REG, 292 .writeable_reg = ads1015_is_writeable_reg, 293 }; 294 295 static const struct iio_chan_spec ads1015_channels[] = { 296 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1), 297 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3), 298 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3), 299 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3), 300 ADS1015_V_CHAN(0, ADS1015_AIN0), 301 ADS1015_V_CHAN(1, ADS1015_AIN1), 302 ADS1015_V_CHAN(2, ADS1015_AIN2), 303 ADS1015_V_CHAN(3, ADS1015_AIN3), 304 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP), 305 }; 306 307 static const struct iio_chan_spec ads1115_channels[] = { 308 ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1), 309 ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3), 310 ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3), 311 ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3), 312 ADS1115_V_CHAN(0, ADS1015_AIN0), 313 ADS1115_V_CHAN(1, ADS1015_AIN1), 314 ADS1115_V_CHAN(2, ADS1015_AIN2), 315 ADS1115_V_CHAN(3, ADS1015_AIN3), 316 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP), 317 }; 318 319 #ifdef CONFIG_PM 320 static int ads1015_set_power_state(struct ads1015_data *data, bool on) 321 { 322 int ret; 323 struct device *dev = regmap_get_device(data->regmap); 324 325 if (on) { 326 ret = pm_runtime_resume_and_get(dev); 327 } else { 328 pm_runtime_mark_last_busy(dev); 329 ret = pm_runtime_put_autosuspend(dev); 330 } 331 332 return ret < 0 ? ret : 0; 333 } 334 335 #else /* !CONFIG_PM */ 336 337 static int ads1015_set_power_state(struct ads1015_data *data, bool on) 338 { 339 return 0; 340 } 341 342 #endif /* !CONFIG_PM */ 343 344 static 345 int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val) 346 { 347 int ret, pga, dr, dr_old, conv_time; 348 unsigned int old, mask, cfg; 349 350 if (chan < 0 || chan >= ADS1015_CHANNELS) 351 return -EINVAL; 352 353 ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old); 354 if (ret) 355 return ret; 356 357 pga = data->channel_data[chan].pga; 358 dr = data->channel_data[chan].data_rate; 359 mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK | 360 ADS1015_CFG_DR_MASK; 361 cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT | 362 dr << ADS1015_CFG_DR_SHIFT; 363 364 if (ads1015_event_channel_enabled(data)) { 365 mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK; 366 cfg |= data->thresh_data[chan].comp_queue << 367 ADS1015_CFG_COMP_QUE_SHIFT | 368 data->comp_mode << 369 ADS1015_CFG_COMP_MODE_SHIFT; 370 } 371 372 cfg = (old & ~mask) | (cfg & mask); 373 if (old != cfg) { 374 ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg); 375 if (ret) 376 return ret; 377 data->conv_invalid = true; 378 } 379 if (data->conv_invalid) { 380 dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT; 381 conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr_old]); 382 conv_time += DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]); 383 conv_time += conv_time / 10; /* 10% internal clock inaccuracy */ 384 usleep_range(conv_time, conv_time + 1); 385 data->conv_invalid = false; 386 } 387 388 return regmap_read(data->regmap, ADS1015_CONV_REG, val); 389 } 390 391 static irqreturn_t ads1015_trigger_handler(int irq, void *p) 392 { 393 struct iio_poll_func *pf = p; 394 struct iio_dev *indio_dev = pf->indio_dev; 395 struct ads1015_data *data = iio_priv(indio_dev); 396 /* Ensure natural alignment of timestamp */ 397 struct { 398 s16 chan; 399 s64 timestamp __aligned(8); 400 } scan; 401 int chan, ret, res; 402 403 memset(&scan, 0, sizeof(scan)); 404 405 mutex_lock(&data->lock); 406 chan = find_first_bit(indio_dev->active_scan_mask, 407 indio_dev->masklength); 408 ret = ads1015_get_adc_result(data, chan, &res); 409 if (ret < 0) { 410 mutex_unlock(&data->lock); 411 goto err; 412 } 413 414 scan.chan = res; 415 mutex_unlock(&data->lock); 416 417 iio_push_to_buffers_with_timestamp(indio_dev, &scan, 418 iio_get_time_ns(indio_dev)); 419 420 err: 421 iio_trigger_notify_done(indio_dev->trig); 422 423 return IRQ_HANDLED; 424 } 425 426 static int ads1015_set_scale(struct ads1015_data *data, 427 struct iio_chan_spec const *chan, 428 int scale, int uscale) 429 { 430 int i; 431 int fullscale = div_s64((scale * 1000000LL + uscale) << 432 (chan->scan_type.realbits - 1), 1000000); 433 434 for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) { 435 if (ads1015_fullscale_range[i] == fullscale) { 436 data->channel_data[chan->address].pga = i; 437 return 0; 438 } 439 } 440 441 return -EINVAL; 442 } 443 444 static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate) 445 { 446 int i; 447 448 for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) { 449 if (data->data_rate[i] == rate) { 450 data->channel_data[chan].data_rate = i; 451 return 0; 452 } 453 } 454 455 return -EINVAL; 456 } 457 458 static int ads1015_read_raw(struct iio_dev *indio_dev, 459 struct iio_chan_spec const *chan, int *val, 460 int *val2, long mask) 461 { 462 int ret, idx; 463 struct ads1015_data *data = iio_priv(indio_dev); 464 465 mutex_lock(&data->lock); 466 switch (mask) { 467 case IIO_CHAN_INFO_RAW: { 468 int shift = chan->scan_type.shift; 469 470 ret = iio_device_claim_direct_mode(indio_dev); 471 if (ret) 472 break; 473 474 if (ads1015_event_channel_enabled(data) && 475 data->event_channel != chan->address) { 476 ret = -EBUSY; 477 goto release_direct; 478 } 479 480 ret = ads1015_set_power_state(data, true); 481 if (ret < 0) 482 goto release_direct; 483 484 ret = ads1015_get_adc_result(data, chan->address, val); 485 if (ret < 0) { 486 ads1015_set_power_state(data, false); 487 goto release_direct; 488 } 489 490 *val = sign_extend32(*val >> shift, 15 - shift); 491 492 ret = ads1015_set_power_state(data, false); 493 if (ret < 0) 494 goto release_direct; 495 496 ret = IIO_VAL_INT; 497 release_direct: 498 iio_device_release_direct_mode(indio_dev); 499 break; 500 } 501 case IIO_CHAN_INFO_SCALE: 502 idx = data->channel_data[chan->address].pga; 503 *val = ads1015_fullscale_range[idx]; 504 *val2 = chan->scan_type.realbits - 1; 505 ret = IIO_VAL_FRACTIONAL_LOG2; 506 break; 507 case IIO_CHAN_INFO_SAMP_FREQ: 508 idx = data->channel_data[chan->address].data_rate; 509 *val = data->data_rate[idx]; 510 ret = IIO_VAL_INT; 511 break; 512 default: 513 ret = -EINVAL; 514 break; 515 } 516 mutex_unlock(&data->lock); 517 518 return ret; 519 } 520 521 static int ads1015_write_raw(struct iio_dev *indio_dev, 522 struct iio_chan_spec const *chan, int val, 523 int val2, long mask) 524 { 525 struct ads1015_data *data = iio_priv(indio_dev); 526 int ret; 527 528 mutex_lock(&data->lock); 529 switch (mask) { 530 case IIO_CHAN_INFO_SCALE: 531 ret = ads1015_set_scale(data, chan, val, val2); 532 break; 533 case IIO_CHAN_INFO_SAMP_FREQ: 534 ret = ads1015_set_data_rate(data, chan->address, val); 535 break; 536 default: 537 ret = -EINVAL; 538 break; 539 } 540 mutex_unlock(&data->lock); 541 542 return ret; 543 } 544 545 static int ads1015_read_event(struct iio_dev *indio_dev, 546 const struct iio_chan_spec *chan, enum iio_event_type type, 547 enum iio_event_direction dir, enum iio_event_info info, int *val, 548 int *val2) 549 { 550 struct ads1015_data *data = iio_priv(indio_dev); 551 int ret; 552 unsigned int comp_queue; 553 int period; 554 int dr; 555 556 mutex_lock(&data->lock); 557 558 switch (info) { 559 case IIO_EV_INFO_VALUE: 560 *val = (dir == IIO_EV_DIR_RISING) ? 561 data->thresh_data[chan->address].high_thresh : 562 data->thresh_data[chan->address].low_thresh; 563 ret = IIO_VAL_INT; 564 break; 565 case IIO_EV_INFO_PERIOD: 566 dr = data->channel_data[chan->address].data_rate; 567 comp_queue = data->thresh_data[chan->address].comp_queue; 568 period = ads1015_comp_queue[comp_queue] * 569 USEC_PER_SEC / data->data_rate[dr]; 570 571 *val = period / USEC_PER_SEC; 572 *val2 = period % USEC_PER_SEC; 573 ret = IIO_VAL_INT_PLUS_MICRO; 574 break; 575 default: 576 ret = -EINVAL; 577 break; 578 } 579 580 mutex_unlock(&data->lock); 581 582 return ret; 583 } 584 585 static int ads1015_write_event(struct iio_dev *indio_dev, 586 const struct iio_chan_spec *chan, enum iio_event_type type, 587 enum iio_event_direction dir, enum iio_event_info info, int val, 588 int val2) 589 { 590 struct ads1015_data *data = iio_priv(indio_dev); 591 int realbits = chan->scan_type.realbits; 592 int ret = 0; 593 long long period; 594 int i; 595 int dr; 596 597 mutex_lock(&data->lock); 598 599 switch (info) { 600 case IIO_EV_INFO_VALUE: 601 if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) { 602 ret = -EINVAL; 603 break; 604 } 605 if (dir == IIO_EV_DIR_RISING) 606 data->thresh_data[chan->address].high_thresh = val; 607 else 608 data->thresh_data[chan->address].low_thresh = val; 609 break; 610 case IIO_EV_INFO_PERIOD: 611 dr = data->channel_data[chan->address].data_rate; 612 period = val * USEC_PER_SEC + val2; 613 614 for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) { 615 if (period <= ads1015_comp_queue[i] * 616 USEC_PER_SEC / data->data_rate[dr]) 617 break; 618 } 619 data->thresh_data[chan->address].comp_queue = i; 620 break; 621 default: 622 ret = -EINVAL; 623 break; 624 } 625 626 mutex_unlock(&data->lock); 627 628 return ret; 629 } 630 631 static int ads1015_read_event_config(struct iio_dev *indio_dev, 632 const struct iio_chan_spec *chan, enum iio_event_type type, 633 enum iio_event_direction dir) 634 { 635 struct ads1015_data *data = iio_priv(indio_dev); 636 int ret = 0; 637 638 mutex_lock(&data->lock); 639 if (data->event_channel == chan->address) { 640 switch (dir) { 641 case IIO_EV_DIR_RISING: 642 ret = 1; 643 break; 644 case IIO_EV_DIR_EITHER: 645 ret = (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW); 646 break; 647 default: 648 ret = -EINVAL; 649 break; 650 } 651 } 652 mutex_unlock(&data->lock); 653 654 return ret; 655 } 656 657 static int ads1015_enable_event_config(struct ads1015_data *data, 658 const struct iio_chan_spec *chan, int comp_mode) 659 { 660 int low_thresh = data->thresh_data[chan->address].low_thresh; 661 int high_thresh = data->thresh_data[chan->address].high_thresh; 662 int ret; 663 unsigned int val; 664 665 if (ads1015_event_channel_enabled(data)) { 666 if (data->event_channel != chan->address || 667 (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD && 668 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)) 669 return -EBUSY; 670 671 return 0; 672 } 673 674 if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) { 675 low_thresh = max(-1 << (chan->scan_type.realbits - 1), 676 high_thresh - 1); 677 } 678 ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG, 679 low_thresh << chan->scan_type.shift); 680 if (ret) 681 return ret; 682 683 ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG, 684 high_thresh << chan->scan_type.shift); 685 if (ret) 686 return ret; 687 688 ret = ads1015_set_power_state(data, true); 689 if (ret < 0) 690 return ret; 691 692 ads1015_event_channel_enable(data, chan->address, comp_mode); 693 694 ret = ads1015_get_adc_result(data, chan->address, &val); 695 if (ret) { 696 ads1015_event_channel_disable(data, chan->address); 697 ads1015_set_power_state(data, false); 698 } 699 700 return ret; 701 } 702 703 static int ads1015_disable_event_config(struct ads1015_data *data, 704 const struct iio_chan_spec *chan, int comp_mode) 705 { 706 int ret; 707 708 if (!ads1015_event_channel_enabled(data)) 709 return 0; 710 711 if (data->event_channel != chan->address) 712 return 0; 713 714 if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD && 715 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW) 716 return 0; 717 718 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG, 719 ADS1015_CFG_COMP_QUE_MASK, 720 ADS1015_CFG_COMP_DISABLE << 721 ADS1015_CFG_COMP_QUE_SHIFT); 722 if (ret) 723 return ret; 724 725 ads1015_event_channel_disable(data, chan->address); 726 727 return ads1015_set_power_state(data, false); 728 } 729 730 static int ads1015_write_event_config(struct iio_dev *indio_dev, 731 const struct iio_chan_spec *chan, enum iio_event_type type, 732 enum iio_event_direction dir, int state) 733 { 734 struct ads1015_data *data = iio_priv(indio_dev); 735 int ret; 736 int comp_mode = (dir == IIO_EV_DIR_EITHER) ? 737 ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD; 738 739 mutex_lock(&data->lock); 740 741 /* Prevent from enabling both buffer and event at a time */ 742 ret = iio_device_claim_direct_mode(indio_dev); 743 if (ret) { 744 mutex_unlock(&data->lock); 745 return ret; 746 } 747 748 if (state) 749 ret = ads1015_enable_event_config(data, chan, comp_mode); 750 else 751 ret = ads1015_disable_event_config(data, chan, comp_mode); 752 753 iio_device_release_direct_mode(indio_dev); 754 mutex_unlock(&data->lock); 755 756 return ret; 757 } 758 759 static irqreturn_t ads1015_event_handler(int irq, void *priv) 760 { 761 struct iio_dev *indio_dev = priv; 762 struct ads1015_data *data = iio_priv(indio_dev); 763 int val; 764 int ret; 765 766 /* Clear the latched ALERT/RDY pin */ 767 ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val); 768 if (ret) 769 return IRQ_HANDLED; 770 771 if (ads1015_event_channel_enabled(data)) { 772 enum iio_event_direction dir; 773 u64 code; 774 775 dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ? 776 IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER; 777 code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel, 778 IIO_EV_TYPE_THRESH, dir); 779 iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev)); 780 } 781 782 return IRQ_HANDLED; 783 } 784 785 static int ads1015_buffer_preenable(struct iio_dev *indio_dev) 786 { 787 struct ads1015_data *data = iio_priv(indio_dev); 788 789 /* Prevent from enabling both buffer and event at a time */ 790 if (ads1015_event_channel_enabled(data)) 791 return -EBUSY; 792 793 return ads1015_set_power_state(iio_priv(indio_dev), true); 794 } 795 796 static int ads1015_buffer_postdisable(struct iio_dev *indio_dev) 797 { 798 return ads1015_set_power_state(iio_priv(indio_dev), false); 799 } 800 801 static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = { 802 .preenable = ads1015_buffer_preenable, 803 .postdisable = ads1015_buffer_postdisable, 804 .validate_scan_mask = &iio_validate_scan_mask_onehot, 805 }; 806 807 static IIO_CONST_ATTR_NAMED(ads1015_scale_available, scale_available, 808 "3 2 1 0.5 0.25 0.125"); 809 static IIO_CONST_ATTR_NAMED(ads1115_scale_available, scale_available, 810 "0.1875 0.125 0.0625 0.03125 0.015625 0.007813"); 811 812 static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available, 813 sampling_frequency_available, "128 250 490 920 1600 2400 3300"); 814 static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available, 815 sampling_frequency_available, "8 16 32 64 128 250 475 860"); 816 817 static struct attribute *ads1015_attributes[] = { 818 &iio_const_attr_ads1015_scale_available.dev_attr.attr, 819 &iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr, 820 NULL, 821 }; 822 823 static const struct attribute_group ads1015_attribute_group = { 824 .attrs = ads1015_attributes, 825 }; 826 827 static struct attribute *ads1115_attributes[] = { 828 &iio_const_attr_ads1115_scale_available.dev_attr.attr, 829 &iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr, 830 NULL, 831 }; 832 833 static const struct attribute_group ads1115_attribute_group = { 834 .attrs = ads1115_attributes, 835 }; 836 837 static const struct iio_info ads1015_info = { 838 .read_raw = ads1015_read_raw, 839 .write_raw = ads1015_write_raw, 840 .read_event_value = ads1015_read_event, 841 .write_event_value = ads1015_write_event, 842 .read_event_config = ads1015_read_event_config, 843 .write_event_config = ads1015_write_event_config, 844 .attrs = &ads1015_attribute_group, 845 }; 846 847 static const struct iio_info ads1115_info = { 848 .read_raw = ads1015_read_raw, 849 .write_raw = ads1015_write_raw, 850 .read_event_value = ads1015_read_event, 851 .write_event_value = ads1015_write_event, 852 .read_event_config = ads1015_read_event_config, 853 .write_event_config = ads1015_write_event_config, 854 .attrs = &ads1115_attribute_group, 855 }; 856 857 static int ads1015_client_get_channels_config(struct i2c_client *client) 858 { 859 struct iio_dev *indio_dev = i2c_get_clientdata(client); 860 struct ads1015_data *data = iio_priv(indio_dev); 861 struct device *dev = &client->dev; 862 struct fwnode_handle *node; 863 int i = -1; 864 865 device_for_each_child_node(dev, node) { 866 u32 pval; 867 unsigned int channel; 868 unsigned int pga = ADS1015_DEFAULT_PGA; 869 unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE; 870 871 if (fwnode_property_read_u32(node, "reg", &pval)) { 872 dev_err(dev, "invalid reg on %pfw\n", node); 873 continue; 874 } 875 876 channel = pval; 877 if (channel >= ADS1015_CHANNELS) { 878 dev_err(dev, "invalid channel index %d on %pfw\n", 879 channel, node); 880 continue; 881 } 882 883 if (!fwnode_property_read_u32(node, "ti,gain", &pval)) { 884 pga = pval; 885 if (pga > 6) { 886 dev_err(dev, "invalid gain on %pfw\n", node); 887 fwnode_handle_put(node); 888 return -EINVAL; 889 } 890 } 891 892 if (!fwnode_property_read_u32(node, "ti,datarate", &pval)) { 893 data_rate = pval; 894 if (data_rate > 7) { 895 dev_err(dev, "invalid data_rate on %pfw\n", node); 896 fwnode_handle_put(node); 897 return -EINVAL; 898 } 899 } 900 901 data->channel_data[channel].pga = pga; 902 data->channel_data[channel].data_rate = data_rate; 903 904 i++; 905 } 906 907 return i < 0 ? -EINVAL : 0; 908 } 909 910 static void ads1015_get_channels_config(struct i2c_client *client) 911 { 912 unsigned int k; 913 914 struct iio_dev *indio_dev = i2c_get_clientdata(client); 915 struct ads1015_data *data = iio_priv(indio_dev); 916 917 if (!ads1015_client_get_channels_config(client)) 918 return; 919 920 /* fallback on default configuration */ 921 for (k = 0; k < ADS1015_CHANNELS; ++k) { 922 data->channel_data[k].pga = ADS1015_DEFAULT_PGA; 923 data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE; 924 } 925 } 926 927 static int ads1015_set_conv_mode(struct ads1015_data *data, int mode) 928 { 929 return regmap_update_bits(data->regmap, ADS1015_CFG_REG, 930 ADS1015_CFG_MOD_MASK, 931 mode << ADS1015_CFG_MOD_SHIFT); 932 } 933 934 static int ads1015_probe(struct i2c_client *client, 935 const struct i2c_device_id *id) 936 { 937 struct iio_dev *indio_dev; 938 struct ads1015_data *data; 939 int ret; 940 enum chip_ids chip; 941 int i; 942 943 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 944 if (!indio_dev) 945 return -ENOMEM; 946 947 data = iio_priv(indio_dev); 948 i2c_set_clientdata(client, indio_dev); 949 950 mutex_init(&data->lock); 951 952 indio_dev->name = ADS1015_DRV_NAME; 953 indio_dev->modes = INDIO_DIRECT_MODE; 954 955 chip = (enum chip_ids)device_get_match_data(&client->dev); 956 if (chip == ADSXXXX) 957 chip = id->driver_data; 958 switch (chip) { 959 case ADS1015: 960 indio_dev->channels = ads1015_channels; 961 indio_dev->num_channels = ARRAY_SIZE(ads1015_channels); 962 indio_dev->info = &ads1015_info; 963 data->data_rate = (unsigned int *) &ads1015_data_rate; 964 break; 965 case ADS1115: 966 indio_dev->channels = ads1115_channels; 967 indio_dev->num_channels = ARRAY_SIZE(ads1115_channels); 968 indio_dev->info = &ads1115_info; 969 data->data_rate = (unsigned int *) &ads1115_data_rate; 970 break; 971 default: 972 dev_err(&client->dev, "Unknown chip %d\n", chip); 973 return -EINVAL; 974 } 975 976 data->event_channel = ADS1015_CHANNELS; 977 /* 978 * Set default lower and upper threshold to min and max value 979 * respectively. 980 */ 981 for (i = 0; i < ADS1015_CHANNELS; i++) { 982 int realbits = indio_dev->channels[i].scan_type.realbits; 983 984 data->thresh_data[i].low_thresh = -1 << (realbits - 1); 985 data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1; 986 } 987 988 /* we need to keep this ABI the same as used by hwmon ADS1015 driver */ 989 ads1015_get_channels_config(client); 990 991 data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config); 992 if (IS_ERR(data->regmap)) { 993 dev_err(&client->dev, "Failed to allocate register map\n"); 994 return PTR_ERR(data->regmap); 995 } 996 997 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL, 998 ads1015_trigger_handler, 999 &ads1015_buffer_setup_ops); 1000 if (ret < 0) { 1001 dev_err(&client->dev, "iio triggered buffer setup failed\n"); 1002 return ret; 1003 } 1004 1005 if (client->irq) { 1006 unsigned long irq_trig = 1007 irqd_get_trigger_type(irq_get_irq_data(client->irq)); 1008 unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK | 1009 ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK; 1010 unsigned int cfg_comp = 1011 ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT | 1012 1 << ADS1015_CFG_COMP_LAT_SHIFT; 1013 1014 switch (irq_trig) { 1015 case IRQF_TRIGGER_LOW: 1016 cfg_comp |= ADS1015_CFG_COMP_POL_LOW << 1017 ADS1015_CFG_COMP_POL_SHIFT; 1018 break; 1019 case IRQF_TRIGGER_HIGH: 1020 cfg_comp |= ADS1015_CFG_COMP_POL_HIGH << 1021 ADS1015_CFG_COMP_POL_SHIFT; 1022 break; 1023 default: 1024 return -EINVAL; 1025 } 1026 1027 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG, 1028 cfg_comp_mask, cfg_comp); 1029 if (ret) 1030 return ret; 1031 1032 ret = devm_request_threaded_irq(&client->dev, client->irq, 1033 NULL, ads1015_event_handler, 1034 irq_trig | IRQF_ONESHOT, 1035 client->name, indio_dev); 1036 if (ret) 1037 return ret; 1038 } 1039 1040 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS); 1041 if (ret) 1042 return ret; 1043 1044 data->conv_invalid = true; 1045 1046 ret = pm_runtime_set_active(&client->dev); 1047 if (ret) 1048 return ret; 1049 pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS); 1050 pm_runtime_use_autosuspend(&client->dev); 1051 pm_runtime_enable(&client->dev); 1052 1053 ret = iio_device_register(indio_dev); 1054 if (ret < 0) { 1055 dev_err(&client->dev, "Failed to register IIO device\n"); 1056 return ret; 1057 } 1058 1059 return 0; 1060 } 1061 1062 static int ads1015_remove(struct i2c_client *client) 1063 { 1064 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1065 struct ads1015_data *data = iio_priv(indio_dev); 1066 1067 iio_device_unregister(indio_dev); 1068 1069 pm_runtime_disable(&client->dev); 1070 pm_runtime_set_suspended(&client->dev); 1071 1072 /* power down single shot mode */ 1073 return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT); 1074 } 1075 1076 #ifdef CONFIG_PM 1077 static int ads1015_runtime_suspend(struct device *dev) 1078 { 1079 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1080 struct ads1015_data *data = iio_priv(indio_dev); 1081 1082 return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT); 1083 } 1084 1085 static int ads1015_runtime_resume(struct device *dev) 1086 { 1087 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1088 struct ads1015_data *data = iio_priv(indio_dev); 1089 int ret; 1090 1091 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS); 1092 if (!ret) 1093 data->conv_invalid = true; 1094 1095 return ret; 1096 } 1097 #endif 1098 1099 static const struct dev_pm_ops ads1015_pm_ops = { 1100 SET_RUNTIME_PM_OPS(ads1015_runtime_suspend, 1101 ads1015_runtime_resume, NULL) 1102 }; 1103 1104 static const struct i2c_device_id ads1015_id[] = { 1105 {"ads1015", ADS1015}, 1106 {"ads1115", ADS1115}, 1107 {} 1108 }; 1109 MODULE_DEVICE_TABLE(i2c, ads1015_id); 1110 1111 static const struct of_device_id ads1015_of_match[] = { 1112 { 1113 .compatible = "ti,ads1015", 1114 .data = (void *)ADS1015 1115 }, 1116 { 1117 .compatible = "ti,ads1115", 1118 .data = (void *)ADS1115 1119 }, 1120 {} 1121 }; 1122 MODULE_DEVICE_TABLE(of, ads1015_of_match); 1123 1124 static struct i2c_driver ads1015_driver = { 1125 .driver = { 1126 .name = ADS1015_DRV_NAME, 1127 .of_match_table = ads1015_of_match, 1128 .pm = &ads1015_pm_ops, 1129 }, 1130 .probe = ads1015_probe, 1131 .remove = ads1015_remove, 1132 .id_table = ads1015_id, 1133 }; 1134 1135 module_i2c_driver(ads1015_driver); 1136 1137 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>"); 1138 MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver"); 1139 MODULE_LICENSE("GPL v2"); 1140