1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "ObjectID.h" 31 #include "atomfirmware.h" 32 33 #include "dc_bios_types.h" 34 #include "include/grph_object_ctrl_defs.h" 35 #include "include/bios_parser_interface.h" 36 #include "include/i2caux_interface.h" 37 #include "include/logger_interface.h" 38 39 #include "command_table2.h" 40 41 #include "bios_parser_helper.h" 42 #include "command_table_helper2.h" 43 #include "bios_parser2.h" 44 #include "bios_parser_types_internal2.h" 45 #include "bios_parser_interface.h" 46 47 #include "bios_parser_common.h" 48 49 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */ 50 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT 51 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05 52 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */ 53 54 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 55 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \ 56 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 57 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 58 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 59 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */ 60 61 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 62 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \ 63 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 64 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 65 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 66 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */ 67 68 #define DC_LOGGER \ 69 bp->base.ctx->logger 70 71 #define LAST_RECORD_TYPE 0xff 72 #define SMU9_SYSPLL0_ID 0 73 74 struct i2c_id_config_access { 75 uint8_t bfI2C_LineMux:4; 76 uint8_t bfHW_EngineID:3; 77 uint8_t bfHW_Capable:1; 78 uint8_t ucAccess; 79 }; 80 81 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 82 struct atom_i2c_record *record, 83 struct graphics_object_i2c_info *info); 84 85 static enum bp_result bios_parser_get_firmware_info( 86 struct dc_bios *dcb, 87 struct dc_firmware_info *info); 88 89 static enum bp_result bios_parser_get_encoder_cap_info( 90 struct dc_bios *dcb, 91 struct graphics_object_id object_id, 92 struct bp_encoder_cap_info *info); 93 94 static enum bp_result get_firmware_info_v3_1( 95 struct bios_parser *bp, 96 struct dc_firmware_info *info); 97 98 static enum bp_result get_firmware_info_v3_2( 99 struct bios_parser *bp, 100 struct dc_firmware_info *info); 101 102 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 103 struct atom_display_object_path_v2 *object); 104 105 static struct atom_encoder_caps_record *get_encoder_cap_record( 106 struct bios_parser *bp, 107 struct atom_display_object_path_v2 *object); 108 109 #define BIOS_IMAGE_SIZE_OFFSET 2 110 #define BIOS_IMAGE_SIZE_UNIT 512 111 112 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 113 114 static void bios_parser2_destruct(struct bios_parser *bp) 115 { 116 kfree(bp->base.bios_local_image); 117 kfree(bp->base.integrated_info); 118 } 119 120 static void firmware_parser_destroy(struct dc_bios **dcb) 121 { 122 struct bios_parser *bp = BP_FROM_DCB(*dcb); 123 124 if (!bp) { 125 BREAK_TO_DEBUGGER(); 126 return; 127 } 128 129 bios_parser2_destruct(bp); 130 131 kfree(bp); 132 *dcb = NULL; 133 } 134 135 static void get_atom_data_table_revision( 136 struct atom_common_table_header *atom_data_tbl, 137 struct atom_data_revision *tbl_revision) 138 { 139 if (!tbl_revision) 140 return; 141 142 /* initialize the revision to 0 which is invalid revision */ 143 tbl_revision->major = 0; 144 tbl_revision->minor = 0; 145 146 if (!atom_data_tbl) 147 return; 148 149 tbl_revision->major = 150 (uint32_t) atom_data_tbl->format_revision & 0x3f; 151 tbl_revision->minor = 152 (uint32_t) atom_data_tbl->content_revision & 0x3f; 153 } 154 155 /* BIOS oject table displaypath is per connector. 156 * There is extra path not for connector. BIOS fill its encoderid as 0 157 */ 158 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 159 { 160 struct bios_parser *bp = BP_FROM_DCB(dcb); 161 unsigned int count = 0; 162 unsigned int i; 163 164 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 165 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 166 count++; 167 } 168 return count; 169 } 170 171 static struct graphics_object_id bios_parser_get_connector_id( 172 struct dc_bios *dcb, 173 uint8_t i) 174 { 175 struct bios_parser *bp = BP_FROM_DCB(dcb); 176 struct graphics_object_id object_id = dal_graphics_object_id_init( 177 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 178 struct object_info_table *tbl = &bp->object_info_tbl; 179 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 180 181 if (v1_4->number_of_path > i) { 182 /* If display_objid is generic object id, the encoderObj 183 * /extencoderobjId should be 0 184 */ 185 if (v1_4->display_path[i].encoderobjid != 0 && 186 v1_4->display_path[i].display_objid != 0) 187 object_id = object_id_from_bios_object_id( 188 v1_4->display_path[i].display_objid); 189 } 190 191 return object_id; 192 } 193 194 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 195 struct graphics_object_id object_id, uint32_t index, 196 struct graphics_object_id *src_object_id) 197 { 198 struct bios_parser *bp = BP_FROM_DCB(dcb); 199 unsigned int i; 200 enum bp_result bp_result = BP_RESULT_BADINPUT; 201 struct graphics_object_id obj_id = {0}; 202 struct object_info_table *tbl = &bp->object_info_tbl; 203 204 if (!src_object_id) 205 return bp_result; 206 207 switch (object_id.type) { 208 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 209 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 210 */ 211 case OBJECT_TYPE_ENCODER: 212 /* TODO: since num of src must be less than 2. 213 * If found in for loop, should break. 214 * DAL2 implementation may be changed too 215 */ 216 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 217 obj_id = object_id_from_bios_object_id( 218 tbl->v1_4->display_path[i].encoderobjid); 219 if (object_id.type == obj_id.type && 220 object_id.id == obj_id.id && 221 object_id.enum_id == 222 obj_id.enum_id) { 223 *src_object_id = 224 object_id_from_bios_object_id(0x1100); 225 /* break; */ 226 } 227 } 228 bp_result = BP_RESULT_OK; 229 break; 230 case OBJECT_TYPE_CONNECTOR: 231 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 232 obj_id = object_id_from_bios_object_id( 233 tbl->v1_4->display_path[i].display_objid); 234 235 if (object_id.type == obj_id.type && 236 object_id.id == obj_id.id && 237 object_id.enum_id == obj_id.enum_id) { 238 *src_object_id = 239 object_id_from_bios_object_id( 240 tbl->v1_4->display_path[i].encoderobjid); 241 /* break; */ 242 } 243 } 244 bp_result = BP_RESULT_OK; 245 break; 246 default: 247 break; 248 } 249 250 return bp_result; 251 } 252 253 /* from graphics_object_id, find display path which includes the object_id */ 254 static struct atom_display_object_path_v2 *get_bios_object( 255 struct bios_parser *bp, 256 struct graphics_object_id id) 257 { 258 unsigned int i; 259 struct graphics_object_id obj_id = {0}; 260 261 switch (id.type) { 262 case OBJECT_TYPE_ENCODER: 263 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 264 obj_id = object_id_from_bios_object_id( 265 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 266 if (id.type == obj_id.type && id.id == obj_id.id 267 && id.enum_id == obj_id.enum_id) 268 return &bp->object_info_tbl.v1_4->display_path[i]; 269 } 270 fallthrough; 271 case OBJECT_TYPE_CONNECTOR: 272 case OBJECT_TYPE_GENERIC: 273 /* Both Generic and Connector Object ID 274 * will be stored on display_objid 275 */ 276 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 277 obj_id = object_id_from_bios_object_id( 278 bp->object_info_tbl.v1_4->display_path[i].display_objid); 279 if (id.type == obj_id.type && id.id == obj_id.id 280 && id.enum_id == obj_id.enum_id) 281 return &bp->object_info_tbl.v1_4->display_path[i]; 282 } 283 fallthrough; 284 default: 285 return NULL; 286 } 287 } 288 289 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 290 struct graphics_object_id id, 291 struct graphics_object_i2c_info *info) 292 { 293 uint32_t offset; 294 struct atom_display_object_path_v2 *object; 295 struct atom_common_record_header *header; 296 struct atom_i2c_record *record; 297 struct atom_i2c_record dummy_record = {0}; 298 struct bios_parser *bp = BP_FROM_DCB(dcb); 299 300 if (!info) 301 return BP_RESULT_BADINPUT; 302 303 if (id.type == OBJECT_TYPE_GENERIC) { 304 dummy_record.i2c_id = id.id; 305 306 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) 307 return BP_RESULT_OK; 308 else 309 return BP_RESULT_NORECORD; 310 } 311 312 object = get_bios_object(bp, id); 313 314 if (!object) 315 return BP_RESULT_BADINPUT; 316 317 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 318 319 for (;;) { 320 header = GET_IMAGE(struct atom_common_record_header, offset); 321 322 if (!header) 323 return BP_RESULT_BADBIOSTABLE; 324 325 if (header->record_type == LAST_RECORD_TYPE || 326 !header->record_size) 327 break; 328 329 if (header->record_type == ATOM_I2C_RECORD_TYPE 330 && sizeof(struct atom_i2c_record) <= 331 header->record_size) { 332 /* get the I2C info */ 333 record = (struct atom_i2c_record *) header; 334 335 if (get_gpio_i2c_info(bp, record, info) == 336 BP_RESULT_OK) 337 return BP_RESULT_OK; 338 } 339 340 offset += header->record_size; 341 } 342 343 return BP_RESULT_NORECORD; 344 } 345 346 static enum bp_result get_gpio_i2c_info( 347 struct bios_parser *bp, 348 struct atom_i2c_record *record, 349 struct graphics_object_i2c_info *info) 350 { 351 struct atom_gpio_pin_lut_v2_1 *header; 352 uint32_t count = 0; 353 unsigned int table_index = 0; 354 bool find_valid = false; 355 356 if (!info) 357 return BP_RESULT_BADINPUT; 358 359 /* get the GPIO_I2C info */ 360 if (!DATA_TABLES(gpio_pin_lut)) 361 return BP_RESULT_BADBIOSTABLE; 362 363 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 364 DATA_TABLES(gpio_pin_lut)); 365 if (!header) 366 return BP_RESULT_BADBIOSTABLE; 367 368 if (sizeof(struct atom_common_table_header) + 369 sizeof(struct atom_gpio_pin_assignment) > 370 le16_to_cpu(header->table_header.structuresize)) 371 return BP_RESULT_BADBIOSTABLE; 372 373 /* TODO: is version change? */ 374 if (header->table_header.content_revision != 1) 375 return BP_RESULT_UNSUPPORTED; 376 377 /* get data count */ 378 count = (le16_to_cpu(header->table_header.structuresize) 379 - sizeof(struct atom_common_table_header)) 380 / sizeof(struct atom_gpio_pin_assignment); 381 382 for (table_index = 0; table_index < count; table_index++) { 383 if (((record->i2c_id & I2C_HW_CAP) == ( 384 header->gpio_pin[table_index].gpio_id & 385 I2C_HW_CAP)) && 386 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == 387 (header->gpio_pin[table_index].gpio_id & 388 I2C_HW_ENGINE_ID_MASK)) && 389 ((record->i2c_id & I2C_HW_LANE_MUX) == 390 (header->gpio_pin[table_index].gpio_id & 391 I2C_HW_LANE_MUX))) { 392 /* still valid */ 393 find_valid = true; 394 break; 395 } 396 } 397 398 /* If we don't find the entry that we are looking for then 399 * we will return BP_Result_BadBiosTable. 400 */ 401 if (find_valid == false) 402 return BP_RESULT_BADBIOSTABLE; 403 404 /* get the GPIO_I2C_INFO */ 405 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 406 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 407 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 408 info->i2c_slave_address = record->i2c_slave_addr; 409 410 /* TODO: check how to get register offset for en, Y, etc. */ 411 info->gpio_info.clk_a_register_index = 412 le16_to_cpu( 413 header->gpio_pin[table_index].data_a_reg_index); 414 info->gpio_info.clk_a_shift = 415 header->gpio_pin[table_index].gpio_bitshift; 416 417 return BP_RESULT_OK; 418 } 419 420 static enum bp_result bios_parser_get_hpd_info( 421 struct dc_bios *dcb, 422 struct graphics_object_id id, 423 struct graphics_object_hpd_info *info) 424 { 425 struct bios_parser *bp = BP_FROM_DCB(dcb); 426 struct atom_display_object_path_v2 *object; 427 struct atom_hpd_int_record *record = NULL; 428 429 if (!info) 430 return BP_RESULT_BADINPUT; 431 432 object = get_bios_object(bp, id); 433 434 if (!object) 435 return BP_RESULT_BADINPUT; 436 437 record = get_hpd_record(bp, object); 438 439 if (record != NULL) { 440 info->hpd_int_gpio_uid = record->pin_id; 441 info->hpd_active = record->plugin_pin_state; 442 return BP_RESULT_OK; 443 } 444 445 return BP_RESULT_NORECORD; 446 } 447 448 static struct atom_hpd_int_record *get_hpd_record( 449 struct bios_parser *bp, 450 struct atom_display_object_path_v2 *object) 451 { 452 struct atom_common_record_header *header; 453 uint32_t offset; 454 455 if (!object) { 456 BREAK_TO_DEBUGGER(); /* Invalid object */ 457 return NULL; 458 } 459 460 offset = le16_to_cpu(object->disp_recordoffset) 461 + bp->object_info_tbl_offset; 462 463 for (;;) { 464 header = GET_IMAGE(struct atom_common_record_header, offset); 465 466 if (!header) 467 return NULL; 468 469 if (header->record_type == LAST_RECORD_TYPE || 470 !header->record_size) 471 break; 472 473 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 474 && sizeof(struct atom_hpd_int_record) <= 475 header->record_size) 476 return (struct atom_hpd_int_record *) header; 477 478 offset += header->record_size; 479 } 480 481 return NULL; 482 } 483 484 /** 485 * bios_parser_get_gpio_pin_info 486 * Get GpioPin information of input gpio id 487 * 488 * @dcb: pointer to the DC BIOS 489 * @gpio_id: GPIO ID 490 * @info: GpioPin information structure 491 * return: Bios parser result code 492 * note: 493 * to get the GPIO PIN INFO, we need: 494 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 495 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 496 * to get the registerA offset/mask 497 */ 498 static enum bp_result bios_parser_get_gpio_pin_info( 499 struct dc_bios *dcb, 500 uint32_t gpio_id, 501 struct gpio_pin_info *info) 502 { 503 struct bios_parser *bp = BP_FROM_DCB(dcb); 504 struct atom_gpio_pin_lut_v2_1 *header; 505 uint32_t count = 0; 506 uint32_t i = 0; 507 508 if (!DATA_TABLES(gpio_pin_lut)) 509 return BP_RESULT_BADBIOSTABLE; 510 511 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 512 DATA_TABLES(gpio_pin_lut)); 513 if (!header) 514 return BP_RESULT_BADBIOSTABLE; 515 516 if (sizeof(struct atom_common_table_header) + 517 sizeof(struct atom_gpio_pin_assignment) 518 > le16_to_cpu(header->table_header.structuresize)) 519 return BP_RESULT_BADBIOSTABLE; 520 521 if (header->table_header.content_revision != 1) 522 return BP_RESULT_UNSUPPORTED; 523 524 /* Temporary hard code gpio pin info */ 525 #if defined(FOR_SIMNOW_BOOT) 526 { 527 struct atom_gpio_pin_assignment gpio_pin[8] = { 528 {0x5db5, 0, 0, 1, 0}, 529 {0x5db5, 8, 8, 2, 0}, 530 {0x5db5, 0x10, 0x10, 3, 0}, 531 {0x5db5, 0x18, 0x14, 4, 0}, 532 {0x5db5, 0x1A, 0x18, 5, 0}, 533 {0x5db5, 0x1C, 0x1C, 6, 0}, 534 }; 535 536 count = 6; 537 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin)); 538 } 539 #else 540 count = (le16_to_cpu(header->table_header.structuresize) 541 - sizeof(struct atom_common_table_header)) 542 / sizeof(struct atom_gpio_pin_assignment); 543 #endif 544 for (i = 0; i < count; ++i) { 545 if (header->gpio_pin[i].gpio_id != gpio_id) 546 continue; 547 548 info->offset = 549 (uint32_t) le16_to_cpu( 550 header->gpio_pin[i].data_a_reg_index); 551 info->offset_y = info->offset + 2; 552 info->offset_en = info->offset + 1; 553 info->offset_mask = info->offset - 1; 554 555 info->mask = (uint32_t) (1 << 556 header->gpio_pin[i].gpio_bitshift); 557 info->mask_y = info->mask + 2; 558 info->mask_en = info->mask + 1; 559 info->mask_mask = info->mask - 1; 560 561 return BP_RESULT_OK; 562 } 563 564 return BP_RESULT_NORECORD; 565 } 566 567 static struct device_id device_type_from_device_id(uint16_t device_id) 568 { 569 570 struct device_id result_device_id; 571 572 result_device_id.raw_device_tag = device_id; 573 574 switch (device_id) { 575 case ATOM_DISPLAY_LCD1_SUPPORT: 576 result_device_id.device_type = DEVICE_TYPE_LCD; 577 result_device_id.enum_id = 1; 578 break; 579 580 case ATOM_DISPLAY_LCD2_SUPPORT: 581 result_device_id.device_type = DEVICE_TYPE_LCD; 582 result_device_id.enum_id = 2; 583 break; 584 585 case ATOM_DISPLAY_DFP1_SUPPORT: 586 result_device_id.device_type = DEVICE_TYPE_DFP; 587 result_device_id.enum_id = 1; 588 break; 589 590 case ATOM_DISPLAY_DFP2_SUPPORT: 591 result_device_id.device_type = DEVICE_TYPE_DFP; 592 result_device_id.enum_id = 2; 593 break; 594 595 case ATOM_DISPLAY_DFP3_SUPPORT: 596 result_device_id.device_type = DEVICE_TYPE_DFP; 597 result_device_id.enum_id = 3; 598 break; 599 600 case ATOM_DISPLAY_DFP4_SUPPORT: 601 result_device_id.device_type = DEVICE_TYPE_DFP; 602 result_device_id.enum_id = 4; 603 break; 604 605 case ATOM_DISPLAY_DFP5_SUPPORT: 606 result_device_id.device_type = DEVICE_TYPE_DFP; 607 result_device_id.enum_id = 5; 608 break; 609 610 case ATOM_DISPLAY_DFP6_SUPPORT: 611 result_device_id.device_type = DEVICE_TYPE_DFP; 612 result_device_id.enum_id = 6; 613 break; 614 615 default: 616 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 617 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 618 result_device_id.enum_id = 0; 619 } 620 return result_device_id; 621 } 622 623 static enum bp_result bios_parser_get_device_tag( 624 struct dc_bios *dcb, 625 struct graphics_object_id connector_object_id, 626 uint32_t device_tag_index, 627 struct connector_device_tag_info *info) 628 { 629 struct bios_parser *bp = BP_FROM_DCB(dcb); 630 struct atom_display_object_path_v2 *object; 631 632 if (!info) 633 return BP_RESULT_BADINPUT; 634 635 /* getBiosObject will return MXM object */ 636 object = get_bios_object(bp, connector_object_id); 637 638 if (!object) { 639 BREAK_TO_DEBUGGER(); /* Invalid object id */ 640 return BP_RESULT_BADINPUT; 641 } 642 643 info->acpi_device = 0; /* BIOS no longer provides this */ 644 info->dev_id = device_type_from_device_id(object->device_tag); 645 646 return BP_RESULT_OK; 647 } 648 649 static enum bp_result get_ss_info_v4_1( 650 struct bios_parser *bp, 651 uint32_t id, 652 uint32_t index, 653 struct spread_spectrum_info *ss_info) 654 { 655 enum bp_result result = BP_RESULT_OK; 656 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 657 struct atom_smu_info_v3_3 *smu_info = NULL; 658 659 if (!ss_info) 660 return BP_RESULT_BADINPUT; 661 662 if (!DATA_TABLES(dce_info)) 663 return BP_RESULT_BADBIOSTABLE; 664 665 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 666 DATA_TABLES(dce_info)); 667 if (!disp_cntl_tbl) 668 return BP_RESULT_BADBIOSTABLE; 669 670 671 ss_info->type.STEP_AND_DELAY_INFO = false; 672 ss_info->spread_percentage_divider = 1000; 673 /* BIOS no longer uses target clock. Always enable for now */ 674 ss_info->target_clock_range = 0xffffffff; 675 676 switch (id) { 677 case AS_SIGNAL_TYPE_DVI: 678 ss_info->spread_spectrum_percentage = 679 disp_cntl_tbl->dvi_ss_percentage; 680 ss_info->spread_spectrum_range = 681 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 682 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 683 ss_info->type.CENTER_MODE = true; 684 break; 685 case AS_SIGNAL_TYPE_HDMI: 686 ss_info->spread_spectrum_percentage = 687 disp_cntl_tbl->hdmi_ss_percentage; 688 ss_info->spread_spectrum_range = 689 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 690 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 691 ss_info->type.CENTER_MODE = true; 692 break; 693 /* TODO LVDS not support anymore? */ 694 case AS_SIGNAL_TYPE_DISPLAY_PORT: 695 ss_info->spread_spectrum_percentage = 696 disp_cntl_tbl->dp_ss_percentage; 697 ss_info->spread_spectrum_range = 698 disp_cntl_tbl->dp_ss_rate_10hz * 10; 699 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 700 ss_info->type.CENTER_MODE = true; 701 break; 702 case AS_SIGNAL_TYPE_GPU_PLL: 703 /* atom_firmware: DAL only get data from dce_info table. 704 * if data within smu_info is needed for DAL, VBIOS should 705 * copy it into dce_info 706 */ 707 result = BP_RESULT_UNSUPPORTED; 708 break; 709 case AS_SIGNAL_TYPE_XGMI: 710 smu_info = GET_IMAGE(struct atom_smu_info_v3_3, 711 DATA_TABLES(smu_info)); 712 if (!smu_info) 713 return BP_RESULT_BADBIOSTABLE; 714 715 ss_info->spread_spectrum_percentage = 716 smu_info->waflclk_ss_percentage; 717 ss_info->spread_spectrum_range = 718 smu_info->gpuclk_ss_rate_10hz * 10; 719 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 720 ss_info->type.CENTER_MODE = true; 721 break; 722 default: 723 result = BP_RESULT_UNSUPPORTED; 724 } 725 726 return result; 727 } 728 729 static enum bp_result get_ss_info_v4_2( 730 struct bios_parser *bp, 731 uint32_t id, 732 uint32_t index, 733 struct spread_spectrum_info *ss_info) 734 { 735 enum bp_result result = BP_RESULT_OK; 736 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 737 struct atom_smu_info_v3_1 *smu_info = NULL; 738 739 if (!ss_info) 740 return BP_RESULT_BADINPUT; 741 742 if (!DATA_TABLES(dce_info)) 743 return BP_RESULT_BADBIOSTABLE; 744 745 if (!DATA_TABLES(smu_info)) 746 return BP_RESULT_BADBIOSTABLE; 747 748 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 749 DATA_TABLES(dce_info)); 750 if (!disp_cntl_tbl) 751 return BP_RESULT_BADBIOSTABLE; 752 753 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 754 if (!smu_info) 755 return BP_RESULT_BADBIOSTABLE; 756 757 ss_info->type.STEP_AND_DELAY_INFO = false; 758 ss_info->spread_percentage_divider = 1000; 759 /* BIOS no longer uses target clock. Always enable for now */ 760 ss_info->target_clock_range = 0xffffffff; 761 762 switch (id) { 763 case AS_SIGNAL_TYPE_DVI: 764 ss_info->spread_spectrum_percentage = 765 disp_cntl_tbl->dvi_ss_percentage; 766 ss_info->spread_spectrum_range = 767 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 768 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 769 ss_info->type.CENTER_MODE = true; 770 break; 771 case AS_SIGNAL_TYPE_HDMI: 772 ss_info->spread_spectrum_percentage = 773 disp_cntl_tbl->hdmi_ss_percentage; 774 ss_info->spread_spectrum_range = 775 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 776 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 777 ss_info->type.CENTER_MODE = true; 778 break; 779 /* TODO LVDS not support anymore? */ 780 case AS_SIGNAL_TYPE_DISPLAY_PORT: 781 ss_info->spread_spectrum_percentage = 782 smu_info->gpuclk_ss_percentage; 783 ss_info->spread_spectrum_range = 784 smu_info->gpuclk_ss_rate_10hz * 10; 785 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 786 ss_info->type.CENTER_MODE = true; 787 break; 788 case AS_SIGNAL_TYPE_GPU_PLL: 789 /* atom_firmware: DAL only get data from dce_info table. 790 * if data within smu_info is needed for DAL, VBIOS should 791 * copy it into dce_info 792 */ 793 result = BP_RESULT_UNSUPPORTED; 794 break; 795 default: 796 result = BP_RESULT_UNSUPPORTED; 797 } 798 799 return result; 800 } 801 802 /** 803 * bios_parser_get_spread_spectrum_info 804 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 805 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 806 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 807 * ver 3.1, 808 * there is only one entry for each signal /ss id. However, there is 809 * no planning of supporting multiple spread Sprectum entry for EverGreen 810 * @dcb: pointer to the DC BIOS 811 * @signal: ASSignalType to be converted to info index 812 * @index: number of entries that match the converted info index 813 * @ss_info: sprectrum information structure, 814 * return: Bios parser result code 815 */ 816 static enum bp_result bios_parser_get_spread_spectrum_info( 817 struct dc_bios *dcb, 818 enum as_signal_type signal, 819 uint32_t index, 820 struct spread_spectrum_info *ss_info) 821 { 822 struct bios_parser *bp = BP_FROM_DCB(dcb); 823 enum bp_result result = BP_RESULT_UNSUPPORTED; 824 struct atom_common_table_header *header; 825 struct atom_data_revision tbl_revision; 826 827 if (!ss_info) /* check for bad input */ 828 return BP_RESULT_BADINPUT; 829 830 if (!DATA_TABLES(dce_info)) 831 return BP_RESULT_UNSUPPORTED; 832 833 header = GET_IMAGE(struct atom_common_table_header, 834 DATA_TABLES(dce_info)); 835 get_atom_data_table_revision(header, &tbl_revision); 836 837 switch (tbl_revision.major) { 838 case 4: 839 switch (tbl_revision.minor) { 840 case 1: 841 return get_ss_info_v4_1(bp, signal, index, ss_info); 842 case 2: 843 case 3: 844 case 4: 845 return get_ss_info_v4_2(bp, signal, index, ss_info); 846 default: 847 ASSERT(0); 848 break; 849 } 850 break; 851 default: 852 break; 853 } 854 /* there can not be more then one entry for SS Info table */ 855 return result; 856 } 857 858 static enum bp_result get_soc_bb_info_v4_4( 859 struct bios_parser *bp, 860 struct bp_soc_bb_info *soc_bb_info) 861 { 862 enum bp_result result = BP_RESULT_OK; 863 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 864 865 if (!soc_bb_info) 866 return BP_RESULT_BADINPUT; 867 868 if (!DATA_TABLES(dce_info)) 869 return BP_RESULT_BADBIOSTABLE; 870 871 if (!DATA_TABLES(smu_info)) 872 return BP_RESULT_BADBIOSTABLE; 873 874 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 875 DATA_TABLES(dce_info)); 876 if (!disp_cntl_tbl) 877 return BP_RESULT_BADBIOSTABLE; 878 879 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 880 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 881 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 882 883 return result; 884 } 885 886 static enum bp_result bios_parser_get_soc_bb_info( 887 struct dc_bios *dcb, 888 struct bp_soc_bb_info *soc_bb_info) 889 { 890 struct bios_parser *bp = BP_FROM_DCB(dcb); 891 enum bp_result result = BP_RESULT_UNSUPPORTED; 892 struct atom_common_table_header *header; 893 struct atom_data_revision tbl_revision; 894 895 if (!soc_bb_info) /* check for bad input */ 896 return BP_RESULT_BADINPUT; 897 898 if (!DATA_TABLES(dce_info)) 899 return BP_RESULT_UNSUPPORTED; 900 901 header = GET_IMAGE(struct atom_common_table_header, 902 DATA_TABLES(dce_info)); 903 get_atom_data_table_revision(header, &tbl_revision); 904 905 switch (tbl_revision.major) { 906 case 4: 907 switch (tbl_revision.minor) { 908 case 1: 909 case 2: 910 case 3: 911 break; 912 case 4: 913 result = get_soc_bb_info_v4_4(bp, soc_bb_info); 914 break; 915 default: 916 break; 917 } 918 break; 919 default: 920 break; 921 } 922 923 return result; 924 } 925 926 static enum bp_result get_disp_caps_v4_1( 927 struct bios_parser *bp, 928 uint8_t *dce_caps) 929 { 930 enum bp_result result = BP_RESULT_OK; 931 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 932 933 if (!dce_caps) 934 return BP_RESULT_BADINPUT; 935 936 if (!DATA_TABLES(dce_info)) 937 return BP_RESULT_BADBIOSTABLE; 938 939 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 940 DATA_TABLES(dce_info)); 941 942 if (!disp_cntl_tbl) 943 return BP_RESULT_BADBIOSTABLE; 944 945 *dce_caps = disp_cntl_tbl->display_caps; 946 947 return result; 948 } 949 950 static enum bp_result get_disp_caps_v4_2( 951 struct bios_parser *bp, 952 uint8_t *dce_caps) 953 { 954 enum bp_result result = BP_RESULT_OK; 955 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 956 957 if (!dce_caps) 958 return BP_RESULT_BADINPUT; 959 960 if (!DATA_TABLES(dce_info)) 961 return BP_RESULT_BADBIOSTABLE; 962 963 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 964 DATA_TABLES(dce_info)); 965 966 if (!disp_cntl_tbl) 967 return BP_RESULT_BADBIOSTABLE; 968 969 *dce_caps = disp_cntl_tbl->display_caps; 970 971 return result; 972 } 973 974 static enum bp_result get_disp_caps_v4_3( 975 struct bios_parser *bp, 976 uint8_t *dce_caps) 977 { 978 enum bp_result result = BP_RESULT_OK; 979 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL; 980 981 if (!dce_caps) 982 return BP_RESULT_BADINPUT; 983 984 if (!DATA_TABLES(dce_info)) 985 return BP_RESULT_BADBIOSTABLE; 986 987 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3, 988 DATA_TABLES(dce_info)); 989 990 if (!disp_cntl_tbl) 991 return BP_RESULT_BADBIOSTABLE; 992 993 *dce_caps = disp_cntl_tbl->display_caps; 994 995 return result; 996 } 997 998 static enum bp_result get_disp_caps_v4_4( 999 struct bios_parser *bp, 1000 uint8_t *dce_caps) 1001 { 1002 enum bp_result result = BP_RESULT_OK; 1003 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1004 1005 if (!dce_caps) 1006 return BP_RESULT_BADINPUT; 1007 1008 if (!DATA_TABLES(dce_info)) 1009 return BP_RESULT_BADBIOSTABLE; 1010 1011 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1012 DATA_TABLES(dce_info)); 1013 1014 if (!disp_cntl_tbl) 1015 return BP_RESULT_BADBIOSTABLE; 1016 1017 *dce_caps = disp_cntl_tbl->display_caps; 1018 1019 return result; 1020 } 1021 1022 static enum bp_result bios_parser_get_lttpr_interop( 1023 struct dc_bios *dcb, 1024 uint8_t *dce_caps) 1025 { 1026 struct bios_parser *bp = BP_FROM_DCB(dcb); 1027 enum bp_result result = BP_RESULT_UNSUPPORTED; 1028 struct atom_common_table_header *header; 1029 struct atom_data_revision tbl_revision; 1030 1031 if (!DATA_TABLES(dce_info)) 1032 return BP_RESULT_UNSUPPORTED; 1033 1034 header = GET_IMAGE(struct atom_common_table_header, 1035 DATA_TABLES(dce_info)); 1036 get_atom_data_table_revision(header, &tbl_revision); 1037 switch (tbl_revision.major) { 1038 case 4: 1039 switch (tbl_revision.minor) { 1040 case 1: 1041 result = get_disp_caps_v4_1(bp, dce_caps); 1042 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1043 break; 1044 case 2: 1045 result = get_disp_caps_v4_2(bp, dce_caps); 1046 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1047 break; 1048 case 3: 1049 result = get_disp_caps_v4_3(bp, dce_caps); 1050 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1051 break; 1052 case 4: 1053 result = get_disp_caps_v4_4(bp, dce_caps); 1054 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1055 break; 1056 default: 1057 break; 1058 } 1059 break; 1060 default: 1061 break; 1062 } 1063 1064 return result; 1065 } 1066 1067 static enum bp_result bios_parser_get_lttpr_caps( 1068 struct dc_bios *dcb, 1069 uint8_t *dce_caps) 1070 { 1071 struct bios_parser *bp = BP_FROM_DCB(dcb); 1072 enum bp_result result = BP_RESULT_UNSUPPORTED; 1073 struct atom_common_table_header *header; 1074 struct atom_data_revision tbl_revision; 1075 1076 if (!DATA_TABLES(dce_info)) 1077 return BP_RESULT_UNSUPPORTED; 1078 1079 header = GET_IMAGE(struct atom_common_table_header, 1080 DATA_TABLES(dce_info)); 1081 get_atom_data_table_revision(header, &tbl_revision); 1082 switch (tbl_revision.major) { 1083 case 4: 1084 switch (tbl_revision.minor) { 1085 case 1: 1086 result = get_disp_caps_v4_1(bp, dce_caps); 1087 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1088 break; 1089 case 2: 1090 result = get_disp_caps_v4_2(bp, dce_caps); 1091 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1092 break; 1093 case 3: 1094 result = get_disp_caps_v4_3(bp, dce_caps); 1095 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1096 break; 1097 case 4: 1098 result = get_disp_caps_v4_4(bp, dce_caps); 1099 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1100 break; 1101 default: 1102 break; 1103 } 1104 break; 1105 default: 1106 break; 1107 } 1108 1109 return result; 1110 } 1111 1112 static enum bp_result get_embedded_panel_info_v2_1( 1113 struct bios_parser *bp, 1114 struct embedded_panel_info *info) 1115 { 1116 struct lcd_info_v2_1 *lvds; 1117 1118 if (!info) 1119 return BP_RESULT_BADINPUT; 1120 1121 if (!DATA_TABLES(lcd_info)) 1122 return BP_RESULT_UNSUPPORTED; 1123 1124 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 1125 1126 if (!lvds) 1127 return BP_RESULT_BADBIOSTABLE; 1128 1129 /* TODO: previous vv1_3, should v2_1 */ 1130 if (!((lvds->table_header.format_revision == 2) 1131 && (lvds->table_header.content_revision >= 1))) 1132 return BP_RESULT_UNSUPPORTED; 1133 1134 memset(info, 0, sizeof(struct embedded_panel_info)); 1135 1136 /* We need to convert from 10KHz units into KHz units */ 1137 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 1138 /* usHActive does not include borders, according to VBIOS team */ 1139 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); 1140 /* usHBlanking_Time includes borders, so we should really be 1141 * subtractingborders duing this translation, but LVDS generally 1142 * doesn't have borders, so we should be okay leaving this as is for 1143 * now. May need to revisit if we ever have LVDS with borders 1144 */ 1145 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); 1146 /* usVActive does not include borders, according to VBIOS team*/ 1147 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); 1148 /* usVBlanking_Time includes borders, so we should really be 1149 * subtracting borders duing this translation, but LVDS generally 1150 * doesn't have borders, so we should be okay leaving this as is for 1151 * now. May need to revisit if we ever have LVDS with borders 1152 */ 1153 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); 1154 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); 1155 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); 1156 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); 1157 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); 1158 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 1159 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 1160 1161 /* not provided by VBIOS */ 1162 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 1163 1164 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1165 & ATOM_HSYNC_POLARITY); 1166 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1167 & ATOM_VSYNC_POLARITY); 1168 1169 /* not provided by VBIOS */ 1170 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 1171 1172 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1173 & ATOM_H_REPLICATIONBY2); 1174 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1175 & ATOM_V_REPLICATIONBY2); 1176 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo 1177 & ATOM_COMPOSITESYNC); 1178 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); 1179 1180 /* not provided by VBIOS*/ 1181 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 1182 /* not provided by VBIOS*/ 1183 info->ss_id = 0; 1184 1185 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); 1186 1187 return BP_RESULT_OK; 1188 } 1189 1190 static enum bp_result bios_parser_get_embedded_panel_info( 1191 struct dc_bios *dcb, 1192 struct embedded_panel_info *info) 1193 { 1194 struct bios_parser 1195 *bp = BP_FROM_DCB(dcb); 1196 struct atom_common_table_header *header; 1197 struct atom_data_revision tbl_revision; 1198 1199 if (!DATA_TABLES(lcd_info)) 1200 return BP_RESULT_FAILURE; 1201 1202 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info)); 1203 1204 if (!header) 1205 return BP_RESULT_BADBIOSTABLE; 1206 1207 get_atom_data_table_revision(header, &tbl_revision); 1208 1209 switch (tbl_revision.major) { 1210 case 2: 1211 switch (tbl_revision.minor) { 1212 case 1: 1213 return get_embedded_panel_info_v2_1(bp, info); 1214 default: 1215 break; 1216 } 1217 break; 1218 default: 1219 break; 1220 } 1221 1222 return BP_RESULT_FAILURE; 1223 } 1224 1225 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1226 { 1227 enum dal_device_type device_type = device_id.device_type; 1228 uint32_t enum_id = device_id.enum_id; 1229 1230 switch (device_type) { 1231 case DEVICE_TYPE_LCD: 1232 switch (enum_id) { 1233 case 1: 1234 return ATOM_DISPLAY_LCD1_SUPPORT; 1235 default: 1236 break; 1237 } 1238 break; 1239 case DEVICE_TYPE_DFP: 1240 switch (enum_id) { 1241 case 1: 1242 return ATOM_DISPLAY_DFP1_SUPPORT; 1243 case 2: 1244 return ATOM_DISPLAY_DFP2_SUPPORT; 1245 case 3: 1246 return ATOM_DISPLAY_DFP3_SUPPORT; 1247 case 4: 1248 return ATOM_DISPLAY_DFP4_SUPPORT; 1249 case 5: 1250 return ATOM_DISPLAY_DFP5_SUPPORT; 1251 case 6: 1252 return ATOM_DISPLAY_DFP6_SUPPORT; 1253 default: 1254 break; 1255 } 1256 break; 1257 default: 1258 break; 1259 } 1260 1261 /* Unidentified device ID, return empty support mask. */ 1262 return 0; 1263 } 1264 1265 static bool bios_parser_is_device_id_supported( 1266 struct dc_bios *dcb, 1267 struct device_id id) 1268 { 1269 struct bios_parser *bp = BP_FROM_DCB(dcb); 1270 1271 uint32_t mask = get_support_mask_for_device_id(id); 1272 1273 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & 1274 mask) != 0; 1275 } 1276 1277 static uint32_t bios_parser_get_ss_entry_number( 1278 struct dc_bios *dcb, 1279 enum as_signal_type signal) 1280 { 1281 /* TODO: DAL2 atomfirmware implementation does not need this. 1282 * why DAL3 need this? 1283 */ 1284 return 1; 1285 } 1286 1287 static enum bp_result bios_parser_transmitter_control( 1288 struct dc_bios *dcb, 1289 struct bp_transmitter_control *cntl) 1290 { 1291 struct bios_parser *bp = BP_FROM_DCB(dcb); 1292 1293 if (!bp->cmd_tbl.transmitter_control) 1294 return BP_RESULT_FAILURE; 1295 1296 return bp->cmd_tbl.transmitter_control(bp, cntl); 1297 } 1298 1299 static enum bp_result bios_parser_encoder_control( 1300 struct dc_bios *dcb, 1301 struct bp_encoder_control *cntl) 1302 { 1303 struct bios_parser *bp = BP_FROM_DCB(dcb); 1304 1305 if (!bp->cmd_tbl.dig_encoder_control) 1306 return BP_RESULT_FAILURE; 1307 1308 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1309 } 1310 1311 static enum bp_result bios_parser_set_pixel_clock( 1312 struct dc_bios *dcb, 1313 struct bp_pixel_clock_parameters *bp_params) 1314 { 1315 struct bios_parser *bp = BP_FROM_DCB(dcb); 1316 1317 if (!bp->cmd_tbl.set_pixel_clock) 1318 return BP_RESULT_FAILURE; 1319 1320 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1321 } 1322 1323 static enum bp_result bios_parser_set_dce_clock( 1324 struct dc_bios *dcb, 1325 struct bp_set_dce_clock_parameters *bp_params) 1326 { 1327 struct bios_parser *bp = BP_FROM_DCB(dcb); 1328 1329 if (!bp->cmd_tbl.set_dce_clock) 1330 return BP_RESULT_FAILURE; 1331 1332 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1333 } 1334 1335 static enum bp_result bios_parser_program_crtc_timing( 1336 struct dc_bios *dcb, 1337 struct bp_hw_crtc_timing_parameters *bp_params) 1338 { 1339 struct bios_parser *bp = BP_FROM_DCB(dcb); 1340 1341 if (!bp->cmd_tbl.set_crtc_timing) 1342 return BP_RESULT_FAILURE; 1343 1344 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1345 } 1346 1347 static enum bp_result bios_parser_enable_crtc( 1348 struct dc_bios *dcb, 1349 enum controller_id id, 1350 bool enable) 1351 { 1352 struct bios_parser *bp = BP_FROM_DCB(dcb); 1353 1354 if (!bp->cmd_tbl.enable_crtc) 1355 return BP_RESULT_FAILURE; 1356 1357 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1358 } 1359 1360 static enum bp_result bios_parser_enable_disp_power_gating( 1361 struct dc_bios *dcb, 1362 enum controller_id controller_id, 1363 enum bp_pipe_control_action action) 1364 { 1365 struct bios_parser *bp = BP_FROM_DCB(dcb); 1366 1367 if (!bp->cmd_tbl.enable_disp_power_gating) 1368 return BP_RESULT_FAILURE; 1369 1370 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1371 action); 1372 } 1373 1374 static enum bp_result bios_parser_enable_lvtma_control( 1375 struct dc_bios *dcb, 1376 uint8_t uc_pwr_on, 1377 uint8_t panel_instance) 1378 { 1379 struct bios_parser *bp = BP_FROM_DCB(dcb); 1380 1381 if (!bp->cmd_tbl.enable_lvtma_control) 1382 return BP_RESULT_FAILURE; 1383 1384 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, panel_instance); 1385 } 1386 1387 static bool bios_parser_is_accelerated_mode( 1388 struct dc_bios *dcb) 1389 { 1390 return bios_is_accelerated_mode(dcb); 1391 } 1392 1393 /** 1394 * bios_parser_set_scratch_critical_state - update critical state bit 1395 * in VBIOS scratch register 1396 * 1397 * @dcb: pointer to the DC BIO 1398 * @state: set or reset state 1399 */ 1400 static void bios_parser_set_scratch_critical_state( 1401 struct dc_bios *dcb, 1402 bool state) 1403 { 1404 bios_set_scratch_critical_state(dcb, state); 1405 } 1406 1407 static enum bp_result bios_parser_get_firmware_info( 1408 struct dc_bios *dcb, 1409 struct dc_firmware_info *info) 1410 { 1411 struct bios_parser *bp = BP_FROM_DCB(dcb); 1412 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1413 struct atom_common_table_header *header; 1414 1415 struct atom_data_revision revision; 1416 1417 if (info && DATA_TABLES(firmwareinfo)) { 1418 header = GET_IMAGE(struct atom_common_table_header, 1419 DATA_TABLES(firmwareinfo)); 1420 get_atom_data_table_revision(header, &revision); 1421 switch (revision.major) { 1422 case 3: 1423 switch (revision.minor) { 1424 case 1: 1425 result = get_firmware_info_v3_1(bp, info); 1426 break; 1427 case 2: 1428 case 3: 1429 case 4: 1430 result = get_firmware_info_v3_2(bp, info); 1431 break; 1432 default: 1433 break; 1434 } 1435 break; 1436 default: 1437 break; 1438 } 1439 } 1440 1441 return result; 1442 } 1443 1444 static enum bp_result get_firmware_info_v3_1( 1445 struct bios_parser *bp, 1446 struct dc_firmware_info *info) 1447 { 1448 struct atom_firmware_info_v3_1 *firmware_info; 1449 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1450 1451 if (!info) 1452 return BP_RESULT_BADINPUT; 1453 1454 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1455 DATA_TABLES(firmwareinfo)); 1456 1457 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1458 DATA_TABLES(dce_info)); 1459 1460 if (!firmware_info || !dce_info) 1461 return BP_RESULT_BADBIOSTABLE; 1462 1463 memset(info, 0, sizeof(*info)); 1464 1465 /* Pixel clock pll information. */ 1466 /* We need to convert from 10KHz units into KHz units */ 1467 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1468 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1469 1470 /* 27MHz for Vega10: */ 1471 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1472 1473 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1474 if (info->pll_info.crystal_frequency == 0) 1475 info->pll_info.crystal_frequency = 27000; 1476 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1477 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1478 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1479 1480 /* Get GPU PLL VCO Clock */ 1481 1482 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1483 /* VBIOS gives in 10KHz */ 1484 info->smu_gpu_pll_output_freq = 1485 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1486 } 1487 1488 info->oem_i2c_present = false; 1489 1490 return BP_RESULT_OK; 1491 } 1492 1493 static enum bp_result get_firmware_info_v3_2( 1494 struct bios_parser *bp, 1495 struct dc_firmware_info *info) 1496 { 1497 struct atom_firmware_info_v3_2 *firmware_info; 1498 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1499 struct atom_common_table_header *header; 1500 struct atom_data_revision revision; 1501 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; 1502 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; 1503 1504 if (!info) 1505 return BP_RESULT_BADINPUT; 1506 1507 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, 1508 DATA_TABLES(firmwareinfo)); 1509 1510 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1511 DATA_TABLES(dce_info)); 1512 1513 if (!firmware_info || !dce_info) 1514 return BP_RESULT_BADBIOSTABLE; 1515 1516 memset(info, 0, sizeof(*info)); 1517 1518 header = GET_IMAGE(struct atom_common_table_header, 1519 DATA_TABLES(smu_info)); 1520 get_atom_data_table_revision(header, &revision); 1521 1522 if (revision.minor == 2) { 1523 /* Vega12 */ 1524 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, 1525 DATA_TABLES(smu_info)); 1526 1527 if (!smu_info_v3_2) 1528 return BP_RESULT_BADBIOSTABLE; 1529 1530 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; 1531 } else if (revision.minor == 3) { 1532 /* Vega20 */ 1533 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, 1534 DATA_TABLES(smu_info)); 1535 1536 if (!smu_info_v3_3) 1537 return BP_RESULT_BADBIOSTABLE; 1538 1539 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; 1540 } 1541 1542 // We need to convert from 10KHz units into KHz units. 1543 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1544 1545 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ 1546 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1547 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1548 if (info->pll_info.crystal_frequency == 0) { 1549 if (revision.minor == 2) 1550 info->pll_info.crystal_frequency = 27000; 1551 else if (revision.minor == 3) 1552 info->pll_info.crystal_frequency = 100000; 1553 } 1554 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1555 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1556 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1557 1558 /* Get GPU PLL VCO Clock */ 1559 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1560 if (revision.minor == 2) 1561 info->smu_gpu_pll_output_freq = 1562 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1563 else if (revision.minor == 3) 1564 info->smu_gpu_pll_output_freq = 1565 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; 1566 } 1567 1568 if (firmware_info->board_i2c_feature_id == 0x2) { 1569 info->oem_i2c_present = true; 1570 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 1571 } else { 1572 info->oem_i2c_present = false; 1573 } 1574 1575 return BP_RESULT_OK; 1576 } 1577 1578 static enum bp_result bios_parser_get_encoder_cap_info( 1579 struct dc_bios *dcb, 1580 struct graphics_object_id object_id, 1581 struct bp_encoder_cap_info *info) 1582 { 1583 struct bios_parser *bp = BP_FROM_DCB(dcb); 1584 struct atom_display_object_path_v2 *object; 1585 struct atom_encoder_caps_record *record = NULL; 1586 1587 if (!info) 1588 return BP_RESULT_BADINPUT; 1589 1590 object = get_bios_object(bp, object_id); 1591 1592 if (!object) 1593 return BP_RESULT_BADINPUT; 1594 1595 record = get_encoder_cap_record(bp, object); 1596 if (!record) 1597 return BP_RESULT_NORECORD; 1598 1599 info->DP_HBR2_CAP = (record->encodercaps & 1600 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 1601 info->DP_HBR2_EN = (record->encodercaps & 1602 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 1603 info->DP_HBR3_EN = (record->encodercaps & 1604 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 1605 info->HDMI_6GB_EN = (record->encodercaps & 1606 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 1607 info->DP_IS_USB_C = (record->encodercaps & 1608 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; 1609 1610 return BP_RESULT_OK; 1611 } 1612 1613 1614 static struct atom_encoder_caps_record *get_encoder_cap_record( 1615 struct bios_parser *bp, 1616 struct atom_display_object_path_v2 *object) 1617 { 1618 struct atom_common_record_header *header; 1619 uint32_t offset; 1620 1621 if (!object) { 1622 BREAK_TO_DEBUGGER(); /* Invalid object */ 1623 return NULL; 1624 } 1625 1626 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 1627 1628 for (;;) { 1629 header = GET_IMAGE(struct atom_common_record_header, offset); 1630 1631 if (!header) 1632 return NULL; 1633 1634 offset += header->record_size; 1635 1636 if (header->record_type == LAST_RECORD_TYPE || 1637 !header->record_size) 1638 break; 1639 1640 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 1641 continue; 1642 1643 if (sizeof(struct atom_encoder_caps_record) <= 1644 header->record_size) 1645 return (struct atom_encoder_caps_record *)header; 1646 } 1647 1648 return NULL; 1649 } 1650 1651 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record( 1652 struct bios_parser *bp, 1653 struct atom_display_object_path_v2 *object) 1654 { 1655 struct atom_common_record_header *header; 1656 uint32_t offset; 1657 1658 if (!object) { 1659 BREAK_TO_DEBUGGER(); /* Invalid object */ 1660 return NULL; 1661 } 1662 1663 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 1664 1665 for (;;) { 1666 header = GET_IMAGE(struct atom_common_record_header, offset); 1667 1668 if (!header) 1669 return NULL; 1670 1671 offset += header->record_size; 1672 1673 if (header->record_type == LAST_RECORD_TYPE || 1674 !header->record_size) 1675 break; 1676 1677 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE) 1678 continue; 1679 1680 if (sizeof(struct atom_disp_connector_caps_record) <= 1681 header->record_size) 1682 return (struct atom_disp_connector_caps_record *)header; 1683 } 1684 1685 return NULL; 1686 } 1687 1688 static enum bp_result bios_parser_get_disp_connector_caps_info( 1689 struct dc_bios *dcb, 1690 struct graphics_object_id object_id, 1691 struct bp_disp_connector_caps_info *info) 1692 { 1693 struct bios_parser *bp = BP_FROM_DCB(dcb); 1694 struct atom_display_object_path_v2 *object; 1695 struct atom_disp_connector_caps_record *record = NULL; 1696 1697 if (!info) 1698 return BP_RESULT_BADINPUT; 1699 1700 object = get_bios_object(bp, object_id); 1701 1702 if (!object) 1703 return BP_RESULT_BADINPUT; 1704 1705 record = get_disp_connector_caps_record(bp, object); 1706 if (!record) 1707 return BP_RESULT_NORECORD; 1708 1709 info->INTERNAL_DISPLAY = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) 1710 ? 1 : 0; 1711 info->INTERNAL_DISPLAY_BL = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) 1712 ? 1 : 0; 1713 1714 return BP_RESULT_OK; 1715 } 1716 1717 static enum bp_result get_vram_info_v23( 1718 struct bios_parser *bp, 1719 struct dc_vram_info *info) 1720 { 1721 struct atom_vram_info_header_v2_3 *info_v23; 1722 enum bp_result result = BP_RESULT_OK; 1723 1724 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3, 1725 DATA_TABLES(vram_info)); 1726 1727 if (info_v23 == NULL) 1728 return BP_RESULT_BADBIOSTABLE; 1729 1730 info->num_chans = info_v23->vram_module[0].channel_num; 1731 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; 1732 1733 return result; 1734 } 1735 1736 static enum bp_result get_vram_info_v24( 1737 struct bios_parser *bp, 1738 struct dc_vram_info *info) 1739 { 1740 struct atom_vram_info_header_v2_4 *info_v24; 1741 enum bp_result result = BP_RESULT_OK; 1742 1743 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4, 1744 DATA_TABLES(vram_info)); 1745 1746 if (info_v24 == NULL) 1747 return BP_RESULT_BADBIOSTABLE; 1748 1749 info->num_chans = info_v24->vram_module[0].channel_num; 1750 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; 1751 1752 return result; 1753 } 1754 1755 static enum bp_result get_vram_info_v25( 1756 struct bios_parser *bp, 1757 struct dc_vram_info *info) 1758 { 1759 struct atom_vram_info_header_v2_5 *info_v25; 1760 enum bp_result result = BP_RESULT_OK; 1761 1762 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5, 1763 DATA_TABLES(vram_info)); 1764 1765 if (info_v25 == NULL) 1766 return BP_RESULT_BADBIOSTABLE; 1767 1768 info->num_chans = info_v25->vram_module[0].channel_num; 1769 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; 1770 1771 return result; 1772 } 1773 1774 /* 1775 * get_integrated_info_v11 1776 * 1777 * @brief 1778 * Get V8 integrated BIOS information 1779 * 1780 * @param 1781 * bios_parser *bp - [in]BIOS parser handler to get master data table 1782 * integrated_info *info - [out] store and output integrated info 1783 * 1784 * @return 1785 * enum bp_result - BP_RESULT_OK if information is available, 1786 * BP_RESULT_BADBIOSTABLE otherwise. 1787 */ 1788 static enum bp_result get_integrated_info_v11( 1789 struct bios_parser *bp, 1790 struct integrated_info *info) 1791 { 1792 struct atom_integrated_system_info_v1_11 *info_v11; 1793 uint32_t i; 1794 1795 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 1796 DATA_TABLES(integratedsysteminfo)); 1797 1798 if (info_v11 == NULL) 1799 return BP_RESULT_BADBIOSTABLE; 1800 1801 info->gpu_cap_info = 1802 le32_to_cpu(info_v11->gpucapinfo); 1803 /* 1804 * system_config: Bit[0] = 0 : PCIE power gating disabled 1805 * = 1 : PCIE power gating enabled 1806 * Bit[1] = 0 : DDR-PLL shut down disabled 1807 * = 1 : DDR-PLL shut down enabled 1808 * Bit[2] = 0 : DDR-PLL power down disabled 1809 * = 1 : DDR-PLL power down enabled 1810 */ 1811 info->system_config = le32_to_cpu(info_v11->system_config); 1812 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 1813 info->memory_type = info_v11->memorytype; 1814 info->ma_channel_number = info_v11->umachannelnumber; 1815 info->lvds_ss_percentage = 1816 le16_to_cpu(info_v11->lvds_ss_percentage); 1817 info->dp_ss_control = 1818 le16_to_cpu(info_v11->reserved1); 1819 info->lvds_sspread_rate_in_10hz = 1820 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 1821 info->hdmi_ss_percentage = 1822 le16_to_cpu(info_v11->hdmi_ss_percentage); 1823 info->hdmi_sspread_rate_in_10hz = 1824 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 1825 info->dvi_ss_percentage = 1826 le16_to_cpu(info_v11->dvi_ss_percentage); 1827 info->dvi_sspread_rate_in_10_hz = 1828 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 1829 info->lvds_misc = info_v11->lvds_misc; 1830 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 1831 info->ext_disp_conn_info.gu_id[i] = 1832 info_v11->extdispconninfo.guid[i]; 1833 } 1834 1835 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 1836 info->ext_disp_conn_info.path[i].device_connector_id = 1837 object_id_from_bios_object_id( 1838 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 1839 1840 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 1841 object_id_from_bios_object_id( 1842 le16_to_cpu( 1843 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 1844 1845 info->ext_disp_conn_info.path[i].device_tag = 1846 le16_to_cpu( 1847 info_v11->extdispconninfo.path[i].device_tag); 1848 info->ext_disp_conn_info.path[i].device_acpi_enum = 1849 le16_to_cpu( 1850 info_v11->extdispconninfo.path[i].device_acpi_enum); 1851 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 1852 info_v11->extdispconninfo.path[i].auxddclut_index; 1853 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 1854 info_v11->extdispconninfo.path[i].hpdlut_index; 1855 info->ext_disp_conn_info.path[i].channel_mapping.raw = 1856 info_v11->extdispconninfo.path[i].channelmapping; 1857 info->ext_disp_conn_info.path[i].caps = 1858 le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 1859 } 1860 info->ext_disp_conn_info.checksum = 1861 info_v11->extdispconninfo.checksum; 1862 1863 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 1864 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum; 1865 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 1866 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 1867 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1868 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 1869 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1870 } 1871 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum; 1872 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 1873 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1874 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1875 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1876 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1877 } 1878 1879 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 1880 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum; 1881 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 1882 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 1883 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1884 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 1885 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1886 } 1887 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum; 1888 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 1889 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1890 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1891 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1892 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1893 } 1894 1895 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 1896 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum; 1897 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 1898 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 1899 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1900 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 1901 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1902 } 1903 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum; 1904 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 1905 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1906 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1907 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1908 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1909 } 1910 1911 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 1912 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum; 1913 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 1914 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 1915 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1916 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 1917 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1918 } 1919 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum; 1920 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 1921 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1922 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1923 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1924 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1925 } 1926 1927 1928 /** TODO - review **/ 1929 #if 0 1930 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 1931 * 10; 1932 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 1933 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 1934 1935 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 1936 /* Convert [10KHz] into [KHz] */ 1937 info->disp_clk_voltage[i].max_supported_clk = 1938 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 1939 ulMaximumSupportedCLK) * 10; 1940 info->disp_clk_voltage[i].voltage_index = 1941 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 1942 } 1943 1944 info->boot_up_req_display_vector = 1945 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 1946 info->boot_up_nb_voltage = 1947 le16_to_cpu(info_v11->usBootUpNBVoltage); 1948 info->ext_disp_conn_info_offset = 1949 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 1950 info->gmc_restore_reset_time = 1951 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 1952 info->minimum_n_clk = 1953 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 1954 for (i = 1; i < 4; ++i) 1955 info->minimum_n_clk = 1956 info->minimum_n_clk < 1957 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 1958 info->minimum_n_clk : le32_to_cpu( 1959 info_v11->ulNbpStateNClkFreq[i]); 1960 1961 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 1962 info->ddr_dll_power_up_time = 1963 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 1964 info->ddr_pll_power_up_time = 1965 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 1966 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 1967 info->max_lvds_pclk_freq_in_single_link = 1968 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1969 info->max_lvds_pclk_freq_in_single_link = 1970 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1971 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 1972 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 1973 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 1974 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 1975 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 1976 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 1977 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 1978 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 1979 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 1980 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 1981 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 1982 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 1983 info->lvds_off_to_on_delay_in_4ms = 1984 info_v11->ucLVDSOffToOnDelay_in4Ms; 1985 info->lvds_bit_depth_control_val = 1986 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 1987 1988 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 1989 /* Convert [10KHz] into [KHz] */ 1990 info->avail_s_clk[i].supported_s_clk = 1991 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 1992 * 10; 1993 info->avail_s_clk[i].voltage_index = 1994 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 1995 info->avail_s_clk[i].voltage_id = 1996 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 1997 } 1998 #endif /* TODO*/ 1999 2000 return BP_RESULT_OK; 2001 } 2002 2003 static enum bp_result get_integrated_info_v2_1( 2004 struct bios_parser *bp, 2005 struct integrated_info *info) 2006 { 2007 struct atom_integrated_system_info_v2_1 *info_v2_1; 2008 uint32_t i; 2009 2010 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1, 2011 DATA_TABLES(integratedsysteminfo)); 2012 2013 if (info_v2_1 == NULL) 2014 return BP_RESULT_BADBIOSTABLE; 2015 2016 info->gpu_cap_info = 2017 le32_to_cpu(info_v2_1->gpucapinfo); 2018 /* 2019 * system_config: Bit[0] = 0 : PCIE power gating disabled 2020 * = 1 : PCIE power gating enabled 2021 * Bit[1] = 0 : DDR-PLL shut down disabled 2022 * = 1 : DDR-PLL shut down enabled 2023 * Bit[2] = 0 : DDR-PLL power down disabled 2024 * = 1 : DDR-PLL power down enabled 2025 */ 2026 info->system_config = le32_to_cpu(info_v2_1->system_config); 2027 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo); 2028 info->memory_type = info_v2_1->memorytype; 2029 info->ma_channel_number = info_v2_1->umachannelnumber; 2030 info->dp_ss_control = 2031 le16_to_cpu(info_v2_1->reserved1); 2032 2033 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2034 info->ext_disp_conn_info.gu_id[i] = 2035 info_v2_1->extdispconninfo.guid[i]; 2036 } 2037 2038 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2039 info->ext_disp_conn_info.path[i].device_connector_id = 2040 object_id_from_bios_object_id( 2041 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid)); 2042 2043 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2044 object_id_from_bios_object_id( 2045 le16_to_cpu( 2046 info_v2_1->extdispconninfo.path[i].ext_encoder_objid)); 2047 2048 info->ext_disp_conn_info.path[i].device_tag = 2049 le16_to_cpu( 2050 info_v2_1->extdispconninfo.path[i].device_tag); 2051 info->ext_disp_conn_info.path[i].device_acpi_enum = 2052 le16_to_cpu( 2053 info_v2_1->extdispconninfo.path[i].device_acpi_enum); 2054 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2055 info_v2_1->extdispconninfo.path[i].auxddclut_index; 2056 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2057 info_v2_1->extdispconninfo.path[i].hpdlut_index; 2058 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2059 info_v2_1->extdispconninfo.path[i].channelmapping; 2060 info->ext_disp_conn_info.path[i].caps = 2061 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); 2062 } 2063 2064 info->ext_disp_conn_info.checksum = 2065 info_v2_1->extdispconninfo.checksum; 2066 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr; 2067 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum; 2068 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2069 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2070 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2071 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2072 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2073 } 2074 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum; 2075 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2076 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2077 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2078 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2079 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2080 } 2081 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr; 2082 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum; 2083 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2084 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2085 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2086 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2087 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2088 } 2089 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum; 2090 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2091 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2092 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2093 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2094 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2095 } 2096 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr; 2097 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum; 2098 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2099 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2100 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2101 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2102 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2103 } 2104 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum; 2105 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2106 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2107 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2108 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2109 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2110 } 2111 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr; 2112 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum; 2113 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2114 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2115 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2116 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2117 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2118 } 2119 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum; 2120 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2121 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2122 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2123 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2124 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2125 } 2126 2127 info->edp1_info.edp_backlight_pwm_hz = 2128 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz); 2129 info->edp1_info.edp_ss_percentage = 2130 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage); 2131 info->edp1_info.edp_ss_rate_10hz = 2132 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz); 2133 info->edp1_info.edp_pwr_on_off_delay = 2134 info_v2_1->edp1_info.edp_pwr_on_off_delay; 2135 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2136 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon; 2137 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2138 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2139 info->edp1_info.edp_panel_bpc = 2140 info_v2_1->edp1_info.edp_panel_bpc; 2141 info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level; 2142 2143 info->edp2_info.edp_backlight_pwm_hz = 2144 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); 2145 info->edp2_info.edp_ss_percentage = 2146 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage); 2147 info->edp2_info.edp_ss_rate_10hz = 2148 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz); 2149 info->edp2_info.edp_pwr_on_off_delay = 2150 info_v2_1->edp2_info.edp_pwr_on_off_delay; 2151 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2152 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon; 2153 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2154 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2155 info->edp2_info.edp_panel_bpc = 2156 info_v2_1->edp2_info.edp_panel_bpc; 2157 info->edp2_info.edp_bootup_bl_level = 2158 info_v2_1->edp2_info.edp_bootup_bl_level; 2159 2160 return BP_RESULT_OK; 2161 } 2162 2163 static enum bp_result get_integrated_info_v2_2( 2164 struct bios_parser *bp, 2165 struct integrated_info *info) 2166 { 2167 struct atom_integrated_system_info_v2_2 *info_v2_2; 2168 uint32_t i; 2169 2170 info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2, 2171 DATA_TABLES(integratedsysteminfo)); 2172 2173 if (info_v2_2 == NULL) 2174 return BP_RESULT_BADBIOSTABLE; 2175 2176 info->gpu_cap_info = 2177 le32_to_cpu(info_v2_2->gpucapinfo); 2178 /* 2179 * system_config: Bit[0] = 0 : PCIE power gating disabled 2180 * = 1 : PCIE power gating enabled 2181 * Bit[1] = 0 : DDR-PLL shut down disabled 2182 * = 1 : DDR-PLL shut down enabled 2183 * Bit[2] = 0 : DDR-PLL power down disabled 2184 * = 1 : DDR-PLL power down enabled 2185 */ 2186 info->system_config = le32_to_cpu(info_v2_2->system_config); 2187 info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo); 2188 info->memory_type = info_v2_2->memorytype; 2189 info->ma_channel_number = info_v2_2->umachannelnumber; 2190 info->dp_ss_control = 2191 le16_to_cpu(info_v2_2->reserved1); 2192 2193 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2194 info->ext_disp_conn_info.gu_id[i] = 2195 info_v2_2->extdispconninfo.guid[i]; 2196 } 2197 2198 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2199 info->ext_disp_conn_info.path[i].device_connector_id = 2200 object_id_from_bios_object_id( 2201 le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid)); 2202 2203 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2204 object_id_from_bios_object_id( 2205 le16_to_cpu( 2206 info_v2_2->extdispconninfo.path[i].ext_encoder_objid)); 2207 2208 info->ext_disp_conn_info.path[i].device_tag = 2209 le16_to_cpu( 2210 info_v2_2->extdispconninfo.path[i].device_tag); 2211 info->ext_disp_conn_info.path[i].device_acpi_enum = 2212 le16_to_cpu( 2213 info_v2_2->extdispconninfo.path[i].device_acpi_enum); 2214 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2215 info_v2_2->extdispconninfo.path[i].auxddclut_index; 2216 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2217 info_v2_2->extdispconninfo.path[i].hpdlut_index; 2218 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2219 info_v2_2->extdispconninfo.path[i].channelmapping; 2220 info->ext_disp_conn_info.path[i].caps = 2221 le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps); 2222 } 2223 2224 info->ext_disp_conn_info.checksum = 2225 info_v2_2->extdispconninfo.checksum; 2226 2227 info->edp1_info.edp_backlight_pwm_hz = 2228 le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz); 2229 info->edp1_info.edp_ss_percentage = 2230 le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage); 2231 info->edp1_info.edp_ss_rate_10hz = 2232 le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz); 2233 info->edp1_info.edp_pwr_on_off_delay = 2234 info_v2_2->edp1_info.edp_pwr_on_off_delay; 2235 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2236 info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon; 2237 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2238 info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2239 info->edp1_info.edp_panel_bpc = 2240 info_v2_2->edp1_info.edp_panel_bpc; 2241 info->edp1_info.edp_bootup_bl_level = 2242 2243 info->edp2_info.edp_backlight_pwm_hz = 2244 le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz); 2245 info->edp2_info.edp_ss_percentage = 2246 le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage); 2247 info->edp2_info.edp_ss_rate_10hz = 2248 le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz); 2249 info->edp2_info.edp_pwr_on_off_delay = 2250 info_v2_2->edp2_info.edp_pwr_on_off_delay; 2251 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2252 info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon; 2253 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2254 info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2255 info->edp2_info.edp_panel_bpc = 2256 info_v2_2->edp2_info.edp_panel_bpc; 2257 info->edp2_info.edp_bootup_bl_level = 2258 info_v2_2->edp2_info.edp_bootup_bl_level; 2259 2260 return BP_RESULT_OK; 2261 } 2262 2263 /* 2264 * construct_integrated_info 2265 * 2266 * @brief 2267 * Get integrated BIOS information based on table revision 2268 * 2269 * @param 2270 * bios_parser *bp - [in]BIOS parser handler to get master data table 2271 * integrated_info *info - [out] store and output integrated info 2272 * 2273 * @return 2274 * enum bp_result - BP_RESULT_OK if information is available, 2275 * BP_RESULT_BADBIOSTABLE otherwise. 2276 */ 2277 static enum bp_result construct_integrated_info( 2278 struct bios_parser *bp, 2279 struct integrated_info *info) 2280 { 2281 enum bp_result result = BP_RESULT_BADBIOSTABLE; 2282 2283 struct atom_common_table_header *header; 2284 struct atom_data_revision revision; 2285 uint32_t i; 2286 uint32_t j; 2287 2288 if (info && DATA_TABLES(integratedsysteminfo)) { 2289 header = GET_IMAGE(struct atom_common_table_header, 2290 DATA_TABLES(integratedsysteminfo)); 2291 2292 get_atom_data_table_revision(header, &revision); 2293 2294 switch (revision.major) { 2295 case 1: 2296 switch (revision.minor) { 2297 case 11: 2298 case 12: 2299 result = get_integrated_info_v11(bp, info); 2300 break; 2301 default: 2302 return result; 2303 } 2304 break; 2305 case 2: 2306 switch (revision.minor) { 2307 case 1: 2308 result = get_integrated_info_v2_1(bp, info); 2309 break; 2310 case 2: 2311 result = get_integrated_info_v2_2(bp, info); 2312 break; 2313 default: 2314 return result; 2315 } 2316 break; 2317 default: 2318 return result; 2319 } 2320 } 2321 2322 if (result != BP_RESULT_OK) 2323 return result; 2324 2325 /* Sort voltage table from low to high*/ 2326 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2327 for (j = i; j > 0; --j) { 2328 if (info->disp_clk_voltage[j].max_supported_clk < 2329 info->disp_clk_voltage[j-1].max_supported_clk 2330 ) { 2331 /* swap j and j - 1*/ 2332 swap(info->disp_clk_voltage[j - 1], 2333 info->disp_clk_voltage[j]); 2334 } 2335 } 2336 } 2337 2338 return result; 2339 } 2340 2341 static enum bp_result bios_parser_get_vram_info( 2342 struct dc_bios *dcb, 2343 struct dc_vram_info *info) 2344 { 2345 struct bios_parser *bp = BP_FROM_DCB(dcb); 2346 enum bp_result result = BP_RESULT_BADBIOSTABLE; 2347 struct atom_common_table_header *header; 2348 struct atom_data_revision revision; 2349 2350 if (info && DATA_TABLES(vram_info)) { 2351 header = GET_IMAGE(struct atom_common_table_header, 2352 DATA_TABLES(vram_info)); 2353 2354 get_atom_data_table_revision(header, &revision); 2355 2356 switch (revision.major) { 2357 case 2: 2358 switch (revision.minor) { 2359 case 3: 2360 result = get_vram_info_v23(bp, info); 2361 break; 2362 case 4: 2363 result = get_vram_info_v24(bp, info); 2364 break; 2365 case 5: 2366 result = get_vram_info_v25(bp, info); 2367 break; 2368 default: 2369 break; 2370 } 2371 break; 2372 2373 default: 2374 return result; 2375 } 2376 2377 } 2378 return result; 2379 } 2380 2381 static struct integrated_info *bios_parser_create_integrated_info( 2382 struct dc_bios *dcb) 2383 { 2384 struct bios_parser *bp = BP_FROM_DCB(dcb); 2385 struct integrated_info *info = NULL; 2386 2387 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); 2388 2389 if (info == NULL) { 2390 ASSERT_CRITICAL(0); 2391 return NULL; 2392 } 2393 2394 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 2395 return info; 2396 2397 kfree(info); 2398 2399 return NULL; 2400 } 2401 2402 static enum bp_result update_slot_layout_info( 2403 struct dc_bios *dcb, 2404 unsigned int i, 2405 struct slot_layout_info *slot_layout_info) 2406 { 2407 unsigned int record_offset; 2408 unsigned int j; 2409 struct atom_display_object_path_v2 *object; 2410 struct atom_bracket_layout_record *record; 2411 struct atom_common_record_header *record_header; 2412 enum bp_result result; 2413 struct bios_parser *bp; 2414 struct object_info_table *tbl; 2415 struct display_object_info_table_v1_4 *v1_4; 2416 2417 record = NULL; 2418 record_header = NULL; 2419 result = BP_RESULT_NORECORD; 2420 2421 bp = BP_FROM_DCB(dcb); 2422 tbl = &bp->object_info_tbl; 2423 v1_4 = tbl->v1_4; 2424 2425 object = &v1_4->display_path[i]; 2426 record_offset = (unsigned int) 2427 (object->disp_recordoffset) + 2428 (unsigned int)(bp->object_info_tbl_offset); 2429 2430 for (;;) { 2431 2432 record_header = (struct atom_common_record_header *) 2433 GET_IMAGE(struct atom_common_record_header, 2434 record_offset); 2435 if (record_header == NULL) { 2436 result = BP_RESULT_BADBIOSTABLE; 2437 break; 2438 } 2439 2440 /* the end of the list */ 2441 if (record_header->record_type == 0xff || 2442 record_header->record_size == 0) { 2443 break; 2444 } 2445 2446 if (record_header->record_type == 2447 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 2448 sizeof(struct atom_bracket_layout_record) 2449 <= record_header->record_size) { 2450 record = (struct atom_bracket_layout_record *) 2451 (record_header); 2452 result = BP_RESULT_OK; 2453 break; 2454 } 2455 2456 record_offset += record_header->record_size; 2457 } 2458 2459 /* return if the record not found */ 2460 if (result != BP_RESULT_OK) 2461 return result; 2462 2463 /* get slot sizes */ 2464 slot_layout_info->length = record->bracketlen; 2465 slot_layout_info->width = record->bracketwidth; 2466 2467 /* get info for each connector in the slot */ 2468 slot_layout_info->num_of_connectors = record->conn_num; 2469 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 2470 slot_layout_info->connectors[j].connector_type = 2471 (enum connector_layout_type) 2472 (record->conn_info[j].connector_type); 2473 switch (record->conn_info[j].connector_type) { 2474 case CONNECTOR_TYPE_DVI_D: 2475 slot_layout_info->connectors[j].connector_type = 2476 CONNECTOR_LAYOUT_TYPE_DVI_D; 2477 slot_layout_info->connectors[j].length = 2478 CONNECTOR_SIZE_DVI; 2479 break; 2480 2481 case CONNECTOR_TYPE_HDMI: 2482 slot_layout_info->connectors[j].connector_type = 2483 CONNECTOR_LAYOUT_TYPE_HDMI; 2484 slot_layout_info->connectors[j].length = 2485 CONNECTOR_SIZE_HDMI; 2486 break; 2487 2488 case CONNECTOR_TYPE_DISPLAY_PORT: 2489 slot_layout_info->connectors[j].connector_type = 2490 CONNECTOR_LAYOUT_TYPE_DP; 2491 slot_layout_info->connectors[j].length = 2492 CONNECTOR_SIZE_DP; 2493 break; 2494 2495 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 2496 slot_layout_info->connectors[j].connector_type = 2497 CONNECTOR_LAYOUT_TYPE_MINI_DP; 2498 slot_layout_info->connectors[j].length = 2499 CONNECTOR_SIZE_MINI_DP; 2500 break; 2501 2502 default: 2503 slot_layout_info->connectors[j].connector_type = 2504 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 2505 slot_layout_info->connectors[j].length = 2506 CONNECTOR_SIZE_UNKNOWN; 2507 } 2508 2509 slot_layout_info->connectors[j].position = 2510 record->conn_info[j].position; 2511 slot_layout_info->connectors[j].connector_id = 2512 object_id_from_bios_object_id( 2513 record->conn_info[j].connectorobjid); 2514 } 2515 return result; 2516 } 2517 2518 2519 static enum bp_result get_bracket_layout_record( 2520 struct dc_bios *dcb, 2521 unsigned int bracket_layout_id, 2522 struct slot_layout_info *slot_layout_info) 2523 { 2524 unsigned int i; 2525 struct bios_parser *bp = BP_FROM_DCB(dcb); 2526 enum bp_result result; 2527 struct object_info_table *tbl; 2528 struct display_object_info_table_v1_4 *v1_4; 2529 2530 if (slot_layout_info == NULL) { 2531 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 2532 return BP_RESULT_BADINPUT; 2533 } 2534 tbl = &bp->object_info_tbl; 2535 v1_4 = tbl->v1_4; 2536 2537 result = BP_RESULT_NORECORD; 2538 for (i = 0; i < v1_4->number_of_path; ++i) { 2539 2540 if (bracket_layout_id == 2541 v1_4->display_path[i].display_objid) { 2542 result = update_slot_layout_info(dcb, i, 2543 slot_layout_info); 2544 break; 2545 } 2546 } 2547 return result; 2548 } 2549 2550 static enum bp_result bios_get_board_layout_info( 2551 struct dc_bios *dcb, 2552 struct board_layout_info *board_layout_info) 2553 { 2554 unsigned int i; 2555 enum bp_result record_result; 2556 2557 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 2558 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 2559 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 2560 0, 0 2561 }; 2562 2563 if (board_layout_info == NULL) { 2564 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 2565 return BP_RESULT_BADINPUT; 2566 } 2567 2568 board_layout_info->num_of_slots = 0; 2569 2570 for (i = 0; i < MAX_BOARD_SLOTS; ++i) { 2571 record_result = get_bracket_layout_record(dcb, 2572 slot_index_to_vbios_id[i], 2573 &board_layout_info->slots[i]); 2574 2575 if (record_result == BP_RESULT_NORECORD && i > 0) 2576 break; /* no more slots present in bios */ 2577 else if (record_result != BP_RESULT_OK) 2578 return record_result; /* fail */ 2579 2580 ++board_layout_info->num_of_slots; 2581 } 2582 2583 /* all data is valid */ 2584 board_layout_info->is_number_of_slots_valid = 1; 2585 board_layout_info->is_slots_size_valid = 1; 2586 board_layout_info->is_connector_offsets_valid = 1; 2587 board_layout_info->is_connector_lengths_valid = 1; 2588 2589 return BP_RESULT_OK; 2590 } 2591 2592 2593 static uint16_t bios_parser_pack_data_tables( 2594 struct dc_bios *dcb, 2595 void *dst) 2596 { 2597 #ifdef PACK_BIOS_DATA 2598 struct bios_parser *bp = BP_FROM_DCB(dcb); 2599 struct atom_rom_header_v2_2 *rom_header = NULL; 2600 struct atom_rom_header_v2_2 *packed_rom_header = NULL; 2601 struct atom_common_table_header *data_tbl_header = NULL; 2602 struct atom_master_list_of_data_tables_v2_1 *data_tbl_list = NULL; 2603 struct atom_master_data_table_v2_1 *packed_master_data_tbl = NULL; 2604 struct atom_data_revision tbl_rev = {0}; 2605 uint16_t *rom_header_offset = NULL; 2606 const uint8_t *bios = bp->base.bios; 2607 uint8_t *bios_dst = (uint8_t *)dst; 2608 uint16_t packed_rom_header_offset; 2609 uint16_t packed_masterdatatable_offset; 2610 uint16_t packed_data_tbl_offset; 2611 uint16_t data_tbl_offset; 2612 unsigned int i; 2613 2614 rom_header_offset = 2615 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2616 2617 if (!rom_header_offset) 2618 return 0; 2619 2620 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 2621 2622 if (!rom_header) 2623 return 0; 2624 2625 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 2626 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 2627 return 0; 2628 2629 get_atom_data_table_revision(&bp->master_data_tbl->table_header, &tbl_rev); 2630 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 1)) 2631 return 0; 2632 2633 packed_rom_header_offset = 2634 OFFSET_TO_ATOM_ROM_HEADER_POINTER + sizeof(*rom_header_offset); 2635 2636 packed_masterdatatable_offset = 2637 packed_rom_header_offset + rom_header->table_header.structuresize; 2638 2639 packed_data_tbl_offset = 2640 packed_masterdatatable_offset + 2641 bp->master_data_tbl->table_header.structuresize; 2642 2643 packed_rom_header = 2644 (struct atom_rom_header_v2_2 *)(bios_dst + packed_rom_header_offset); 2645 2646 packed_master_data_tbl = 2647 (struct atom_master_data_table_v2_1 *)(bios_dst + 2648 packed_masterdatatable_offset); 2649 2650 memcpy(bios_dst, bios, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2651 2652 *((uint16_t *)(bios_dst + OFFSET_TO_ATOM_ROM_HEADER_POINTER)) = 2653 packed_rom_header_offset; 2654 2655 memcpy(bios_dst + packed_rom_header_offset, rom_header, 2656 rom_header->table_header.structuresize); 2657 2658 packed_rom_header->masterdatatable_offset = packed_masterdatatable_offset; 2659 2660 memcpy(&packed_master_data_tbl->table_header, 2661 &bp->master_data_tbl->table_header, 2662 sizeof(bp->master_data_tbl->table_header)); 2663 2664 data_tbl_list = &bp->master_data_tbl->listOfdatatables; 2665 2666 /* Each data table offset in data table list is 2 bytes, 2667 * we can use that to iterate through listOfdatatables 2668 * without knowing the name of each member. 2669 */ 2670 for (i = 0; i < sizeof(*data_tbl_list)/sizeof(uint16_t); i++) { 2671 data_tbl_offset = *((uint16_t *)data_tbl_list + i); 2672 2673 if (data_tbl_offset) { 2674 data_tbl_header = 2675 (struct atom_common_table_header *)(bios + data_tbl_offset); 2676 2677 memcpy(bios_dst + packed_data_tbl_offset, data_tbl_header, 2678 data_tbl_header->structuresize); 2679 2680 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 2681 packed_data_tbl_offset; 2682 2683 packed_data_tbl_offset += data_tbl_header->structuresize; 2684 } else { 2685 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 0; 2686 } 2687 } 2688 return packed_data_tbl_offset; 2689 #endif 2690 // TODO: There is data bytes alignment issue, disable it for now. 2691 return 0; 2692 } 2693 2694 static struct atom_dc_golden_table_v1 *bios_get_golden_table( 2695 struct bios_parser *bp, 2696 uint32_t rev_major, 2697 uint32_t rev_minor, 2698 uint16_t *dc_golden_table_ver) 2699 { 2700 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL; 2701 uint32_t dc_golden_offset = 0; 2702 *dc_golden_table_ver = 0; 2703 2704 if (!DATA_TABLES(dce_info)) 2705 return NULL; 2706 2707 /* ver.4.4 or higher */ 2708 switch (rev_major) { 2709 case 4: 2710 switch (rev_minor) { 2711 case 4: 2712 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 2713 DATA_TABLES(dce_info)); 2714 if (!disp_cntl_tbl_4_4) 2715 return NULL; 2716 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset; 2717 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; 2718 break; 2719 } 2720 break; 2721 } 2722 2723 if (!dc_golden_offset) 2724 return NULL; 2725 2726 if (*dc_golden_table_ver != 1) 2727 return NULL; 2728 2729 return GET_IMAGE(struct atom_dc_golden_table_v1, 2730 dc_golden_offset); 2731 } 2732 2733 static enum bp_result bios_get_atom_dc_golden_table( 2734 struct dc_bios *dcb) 2735 { 2736 struct bios_parser *bp = BP_FROM_DCB(dcb); 2737 enum bp_result result = BP_RESULT_OK; 2738 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL; 2739 struct atom_common_table_header *header; 2740 struct atom_data_revision tbl_revision; 2741 uint16_t dc_golden_table_ver = 0; 2742 2743 header = GET_IMAGE(struct atom_common_table_header, 2744 DATA_TABLES(dce_info)); 2745 if (!header) 2746 return BP_RESULT_UNSUPPORTED; 2747 2748 get_atom_data_table_revision(header, &tbl_revision); 2749 2750 atom_dc_golden_table = bios_get_golden_table(bp, 2751 tbl_revision.major, 2752 tbl_revision.minor, 2753 &dc_golden_table_ver); 2754 2755 if (!atom_dc_golden_table) 2756 return BP_RESULT_UNSUPPORTED; 2757 2758 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver; 2759 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val; 2760 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val; 2761 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val; 2762 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val; 2763 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val; 2764 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val; 2765 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val; 2766 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val; 2767 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val; 2768 2769 return result; 2770 } 2771 2772 2773 static const struct dc_vbios_funcs vbios_funcs = { 2774 .get_connectors_number = bios_parser_get_connectors_number, 2775 2776 .get_connector_id = bios_parser_get_connector_id, 2777 2778 .get_src_obj = bios_parser_get_src_obj, 2779 2780 .get_i2c_info = bios_parser_get_i2c_info, 2781 2782 .get_hpd_info = bios_parser_get_hpd_info, 2783 2784 .get_device_tag = bios_parser_get_device_tag, 2785 2786 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 2787 2788 .get_ss_entry_number = bios_parser_get_ss_entry_number, 2789 2790 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 2791 2792 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 2793 2794 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 2795 2796 .is_device_id_supported = bios_parser_is_device_id_supported, 2797 2798 .is_accelerated_mode = bios_parser_is_accelerated_mode, 2799 2800 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 2801 2802 2803 /* COMMANDS */ 2804 .encoder_control = bios_parser_encoder_control, 2805 2806 .transmitter_control = bios_parser_transmitter_control, 2807 2808 .enable_crtc = bios_parser_enable_crtc, 2809 2810 .set_pixel_clock = bios_parser_set_pixel_clock, 2811 2812 .set_dce_clock = bios_parser_set_dce_clock, 2813 2814 .program_crtc_timing = bios_parser_program_crtc_timing, 2815 2816 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 2817 2818 .bios_parser_destroy = firmware_parser_destroy, 2819 2820 .get_board_layout_info = bios_get_board_layout_info, 2821 .pack_data_tables = bios_parser_pack_data_tables, 2822 2823 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table, 2824 2825 .enable_lvtma_control = bios_parser_enable_lvtma_control, 2826 2827 .get_soc_bb_info = bios_parser_get_soc_bb_info, 2828 2829 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info, 2830 2831 .get_lttpr_caps = bios_parser_get_lttpr_caps, 2832 2833 .get_lttpr_interop = bios_parser_get_lttpr_interop, 2834 }; 2835 2836 static bool bios_parser2_construct( 2837 struct bios_parser *bp, 2838 struct bp_init_data *init, 2839 enum dce_version dce_version) 2840 { 2841 uint16_t *rom_header_offset = NULL; 2842 struct atom_rom_header_v2_2 *rom_header = NULL; 2843 struct display_object_info_table_v1_4 *object_info_tbl; 2844 struct atom_data_revision tbl_rev = {0}; 2845 2846 if (!init) 2847 return false; 2848 2849 if (!init->bios) 2850 return false; 2851 2852 bp->base.funcs = &vbios_funcs; 2853 bp->base.bios = init->bios; 2854 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 2855 2856 bp->base.ctx = init->ctx; 2857 2858 bp->base.bios_local_image = NULL; 2859 2860 rom_header_offset = 2861 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2862 2863 if (!rom_header_offset) 2864 return false; 2865 2866 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 2867 2868 if (!rom_header) 2869 return false; 2870 2871 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 2872 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 2873 return false; 2874 2875 bp->master_data_tbl = 2876 GET_IMAGE(struct atom_master_data_table_v2_1, 2877 rom_header->masterdatatable_offset); 2878 2879 if (!bp->master_data_tbl) 2880 return false; 2881 2882 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 2883 2884 if (!bp->object_info_tbl_offset) 2885 return false; 2886 2887 object_info_tbl = 2888 GET_IMAGE(struct display_object_info_table_v1_4, 2889 bp->object_info_tbl_offset); 2890 2891 if (!object_info_tbl) 2892 return false; 2893 2894 get_atom_data_table_revision(&object_info_tbl->table_header, 2895 &bp->object_info_tbl.revision); 2896 2897 if (bp->object_info_tbl.revision.major == 1 2898 && bp->object_info_tbl.revision.minor >= 4) { 2899 struct display_object_info_table_v1_4 *tbl_v1_4; 2900 2901 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 2902 bp->object_info_tbl_offset); 2903 if (!tbl_v1_4) 2904 return false; 2905 2906 bp->object_info_tbl.v1_4 = tbl_v1_4; 2907 } else 2908 return false; 2909 2910 dal_firmware_parser_init_cmd_tbl(bp); 2911 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 2912 2913 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 2914 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; 2915 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info); 2916 2917 return true; 2918 } 2919 2920 struct dc_bios *firmware_parser_create( 2921 struct bp_init_data *init, 2922 enum dce_version dce_version) 2923 { 2924 struct bios_parser *bp = NULL; 2925 2926 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); 2927 if (!bp) 2928 return NULL; 2929 2930 if (bios_parser2_construct(bp, init, dce_version)) 2931 return &bp->base; 2932 2933 kfree(bp); 2934 return NULL; 2935 } 2936 2937 2938