1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 /* This header file defines the Admin Queue commands, error codes and 8 * descriptor format. It is shared between Firmware and Software. 9 */ 10 11 #define ICE_MAX_VSI 768 12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 14 15 struct ice_aqc_generic { 16 __le32 param0; 17 __le32 param1; 18 __le32 addr_high; 19 __le32 addr_low; 20 }; 21 22 /* Get version (direct 0x0001) */ 23 struct ice_aqc_get_ver { 24 __le32 rom_ver; 25 __le32 fw_build; 26 u8 fw_branch; 27 u8 fw_major; 28 u8 fw_minor; 29 u8 fw_patch; 30 u8 api_branch; 31 u8 api_major; 32 u8 api_minor; 33 u8 api_patch; 34 }; 35 36 /* Send driver version (indirect 0x0002) */ 37 struct ice_aqc_driver_ver { 38 u8 major_ver; 39 u8 minor_ver; 40 u8 build_ver; 41 u8 subbuild_ver; 42 u8 reserved[4]; 43 __le32 addr_high; 44 __le32 addr_low; 45 }; 46 47 /* Queue Shutdown (direct 0x0003) */ 48 struct ice_aqc_q_shutdown { 49 u8 driver_unloading; 50 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 51 u8 reserved[15]; 52 }; 53 54 /* Request resource ownership (direct 0x0008) 55 * Release resource ownership (direct 0x0009) 56 */ 57 struct ice_aqc_req_res { 58 __le16 res_id; 59 #define ICE_AQC_RES_ID_NVM 1 60 #define ICE_AQC_RES_ID_SDP 2 61 #define ICE_AQC_RES_ID_CHNG_LOCK 3 62 #define ICE_AQC_RES_ID_GLBL_LOCK 4 63 __le16 access_type; 64 #define ICE_AQC_RES_ACCESS_READ 1 65 #define ICE_AQC_RES_ACCESS_WRITE 2 66 67 /* Upon successful completion, FW writes this value and driver is 68 * expected to release resource before timeout. This value is provided 69 * in milliseconds. 70 */ 71 __le32 timeout; 72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 76 /* For SDP: pin ID of the SDP */ 77 __le32 res_number; 78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 79 __le16 status; 80 #define ICE_AQ_RES_GLBL_SUCCESS 0 81 #define ICE_AQ_RES_GLBL_IN_PROG 1 82 #define ICE_AQ_RES_GLBL_DONE 2 83 u8 reserved[2]; 84 }; 85 86 /* Get function capabilities (indirect 0x000A) 87 * Get device capabilities (indirect 0x000B) 88 */ 89 struct ice_aqc_list_caps { 90 u8 cmd_flags; 91 u8 pf_index; 92 u8 reserved[2]; 93 __le32 count; 94 __le32 addr_high; 95 __le32 addr_low; 96 }; 97 98 /* Device/Function buffer entry, repeated per reported capability */ 99 struct ice_aqc_list_caps_elem { 100 __le16 cap; 101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 102 #define ICE_AQC_CAPS_SRIOV 0x0012 103 #define ICE_AQC_CAPS_VF 0x0013 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_1588 0x0046 112 #define ICE_AQC_CAPS_MAX_MTU 0x0047 113 #define ICE_AQC_CAPS_NVM_VER 0x0048 114 #define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049 115 #define ICE_AQC_CAPS_OROM_VER 0x004A 116 #define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B 117 #define ICE_AQC_CAPS_NET_VER 0x004C 118 #define ICE_AQC_CAPS_PENDING_NET_VER 0x004D 119 #define ICE_AQC_CAPS_RDMA 0x0051 120 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 121 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 122 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 123 124 u8 major_ver; 125 u8 minor_ver; 126 /* Number of resources described by this capability */ 127 __le32 number; 128 /* Only meaningful for some types of resources */ 129 __le32 logical_id; 130 /* Only meaningful for some types of resources */ 131 __le32 phys_id; 132 __le64 rsvd1; 133 __le64 rsvd2; 134 }; 135 136 /* Manage MAC address, read command - indirect (0x0107) 137 * This struct is also used for the response 138 */ 139 struct ice_aqc_manage_mac_read { 140 __le16 flags; /* Zeroed by device driver */ 141 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 142 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 143 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 144 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 145 #define ICE_AQC_MAN_MAC_READ_S 4 146 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 147 u8 rsvd[2]; 148 u8 num_addr; /* Used in response */ 149 u8 rsvd1[3]; 150 __le32 addr_high; 151 __le32 addr_low; 152 }; 153 154 /* Response buffer format for manage MAC read command */ 155 struct ice_aqc_manage_mac_read_resp { 156 u8 lport_num; 157 u8 addr_type; 158 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 159 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 160 u8 mac_addr[ETH_ALEN]; 161 }; 162 163 /* Manage MAC address, write command - direct (0x0108) */ 164 struct ice_aqc_manage_mac_write { 165 u8 rsvd; 166 u8 flags; 167 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 168 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 169 #define ICE_AQC_MAN_MAC_WR_S 6 170 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S) 171 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 172 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 173 /* byte stream in network order */ 174 u8 mac_addr[ETH_ALEN]; 175 __le32 addr_high; 176 __le32 addr_low; 177 }; 178 179 /* Clear PXE Command and response (direct 0x0110) */ 180 struct ice_aqc_clear_pxe { 181 u8 rx_cnt; 182 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 183 u8 reserved[15]; 184 }; 185 186 /* Get switch configuration (0x0200) */ 187 struct ice_aqc_get_sw_cfg { 188 /* Reserved for command and copy of request flags for response */ 189 __le16 flags; 190 /* First desc in case of command and next_elem in case of response 191 * In case of response, if it is not zero, means all the configuration 192 * was not returned and new command shall be sent with this value in 193 * the 'first desc' field 194 */ 195 __le16 element; 196 /* Reserved for command, only used for response */ 197 __le16 num_elems; 198 __le16 rsvd; 199 __le32 addr_high; 200 __le32 addr_low; 201 }; 202 203 /* Each entry in the response buffer is of the following type: */ 204 struct ice_aqc_get_sw_cfg_resp_elem { 205 /* VSI/Port Number */ 206 __le16 vsi_port_num; 207 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 208 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 209 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 210 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 211 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 212 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 213 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 214 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 215 216 /* SWID VSI/Port belongs to */ 217 __le16 swid; 218 219 /* Bit 14..0 : PF/VF number VSI belongs to 220 * Bit 15 : VF indication bit 221 */ 222 __le16 pf_vf_num; 223 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 224 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 225 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 226 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 227 }; 228 229 /* These resource type defines are used for all switch resource 230 * commands where a resource type is required, such as: 231 * Get Resource Allocation command (indirect 0x0204) 232 * Allocate Resources command (indirect 0x0208) 233 * Free Resources command (indirect 0x0209) 234 * Get Allocated Resource Descriptors Command (indirect 0x020A) 235 */ 236 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 237 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 238 #define ICE_AQC_RES_TYPE_RECIPE 0x05 239 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 240 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 241 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 242 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 243 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 244 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 245 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 246 247 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 248 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 249 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 250 251 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 252 253 #define ICE_AQC_RES_TYPE_S 0 254 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 255 256 /* Allocate Resources command (indirect 0x0208) 257 * Free Resources command (indirect 0x0209) 258 */ 259 struct ice_aqc_alloc_free_res_cmd { 260 __le16 num_entries; /* Number of Resource entries */ 261 u8 reserved[6]; 262 __le32 addr_high; 263 __le32 addr_low; 264 }; 265 266 /* Resource descriptor */ 267 struct ice_aqc_res_elem { 268 union { 269 __le16 sw_resp; 270 __le16 flu_resp; 271 } e; 272 }; 273 274 /* Buffer for Allocate/Free Resources commands */ 275 struct ice_aqc_alloc_free_res_elem { 276 __le16 res_type; /* Types defined above cmd 0x0204 */ 277 #define ICE_AQC_RES_TYPE_SHARED_S 7 278 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 279 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 280 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 281 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 282 __le16 num_elems; 283 struct ice_aqc_res_elem elem[]; 284 }; 285 286 /* Add VSI (indirect 0x0210) 287 * Update VSI (indirect 0x0211) 288 * Get VSI (indirect 0x0212) 289 * Free VSI (indirect 0x0213) 290 */ 291 struct ice_aqc_add_get_update_free_vsi { 292 __le16 vsi_num; 293 #define ICE_AQ_VSI_NUM_S 0 294 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 295 #define ICE_AQ_VSI_IS_VALID BIT(15) 296 __le16 cmd_flags; 297 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 298 u8 vf_id; 299 u8 reserved; 300 __le16 vsi_flags; 301 #define ICE_AQ_VSI_TYPE_S 0 302 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 303 #define ICE_AQ_VSI_TYPE_VF 0x0 304 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 305 #define ICE_AQ_VSI_TYPE_PF 0x2 306 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 307 __le32 addr_high; 308 __le32 addr_low; 309 }; 310 311 /* Response descriptor for: 312 * Add VSI (indirect 0x0210) 313 * Update VSI (indirect 0x0211) 314 * Free VSI (indirect 0x0213) 315 */ 316 struct ice_aqc_add_update_free_vsi_resp { 317 __le16 vsi_num; 318 __le16 ext_status; 319 __le16 vsi_used; 320 __le16 vsi_free; 321 __le32 addr_high; 322 __le32 addr_low; 323 }; 324 325 struct ice_aqc_vsi_props { 326 __le16 valid_sections; 327 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 328 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 329 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 330 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 331 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 332 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 333 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 334 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 335 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 336 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 337 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 338 /* switch section */ 339 u8 sw_id; 340 u8 sw_flags; 341 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 342 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 343 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 344 u8 sw_flags2; 345 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 346 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 347 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 348 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 349 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 350 u8 veb_stat_id; 351 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 352 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 353 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 354 /* security section */ 355 u8 sec_flags; 356 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 357 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 358 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 359 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 360 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 361 u8 sec_reserved; 362 /* VLAN section */ 363 __le16 pvid; /* VLANS include priority bits */ 364 u8 pvlan_reserved[2]; 365 u8 vlan_flags; 366 #define ICE_AQ_VSI_VLAN_MODE_S 0 367 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 368 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 369 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 370 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 371 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 372 #define ICE_AQ_VSI_VLAN_EMOD_S 3 373 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 374 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 375 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 376 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 377 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 378 u8 pvlan_reserved2[3]; 379 /* ingress egress up sections */ 380 __le32 ingress_table; /* bitmap, 3 bits per up */ 381 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 382 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 383 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 384 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 385 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 386 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 387 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 388 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 389 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 390 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 391 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 392 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 393 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 394 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 395 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 396 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 397 __le32 egress_table; /* same defines as for ingress table */ 398 /* outer tags section */ 399 __le16 outer_tag; 400 u8 outer_tag_flags; 401 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 402 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 403 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 404 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 405 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 406 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 407 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 408 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 409 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 410 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 411 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 412 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 413 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 414 u8 outer_tag_reserved; 415 /* queue mapping section */ 416 __le16 mapping_flags; 417 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 418 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 419 __le16 q_mapping[16]; 420 #define ICE_AQ_VSI_Q_S 0 421 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 422 __le16 tc_mapping[8]; 423 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 424 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 425 #define ICE_AQ_VSI_TC_Q_NUM_S 11 426 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 427 /* queueing option section */ 428 u8 q_opt_rss; 429 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 430 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 431 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 432 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 433 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 434 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 435 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 436 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 437 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 438 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 439 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 440 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 441 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 442 u8 q_opt_tc; 443 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 444 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 445 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 446 u8 q_opt_flags; 447 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 448 u8 q_opt_reserved[3]; 449 /* outer up section */ 450 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 451 /* section 10 */ 452 __le16 sect_10_reserved; 453 /* flow director section */ 454 __le16 fd_options; 455 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 456 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 457 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 458 __le16 max_fd_fltr_dedicated; 459 __le16 max_fd_fltr_shared; 460 __le16 fd_def_q; 461 #define ICE_AQ_VSI_FD_DEF_Q_S 0 462 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 463 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 464 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 465 __le16 fd_report_opt; 466 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 467 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 468 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 469 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 470 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 471 /* PASID section */ 472 __le32 pasid_id; 473 #define ICE_AQ_VSI_PASID_ID_S 0 474 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 475 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 476 u8 reserved[24]; 477 }; 478 479 #define ICE_MAX_NUM_RECIPES 64 480 481 /* Add/Get Recipe (indirect 0x0290/0x0292) */ 482 struct ice_aqc_add_get_recipe { 483 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 484 __le16 return_index; /* Input, used for Get cmd only */ 485 u8 reserved[4]; 486 __le32 addr_high; 487 __le32 addr_low; 488 }; 489 490 struct ice_aqc_recipe_content { 491 u8 rid; 492 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 493 #define ICE_AQ_SW_ID_LKUP_IDX 0 494 u8 lkup_indx[5]; 495 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 496 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 497 __le16 mask[5]; 498 u8 result_indx; 499 #define ICE_AQ_RECIPE_RESULT_DATA_S 0 500 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 501 #define ICE_AQ_RECIPE_RESULT_EN BIT(7) 502 u8 rsvd0[3]; 503 u8 act_ctrl_join_priority; 504 u8 act_ctrl_fwd_priority; 505 u8 act_ctrl; 506 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 507 u8 rsvd1; 508 __le32 dflt_act; 509 }; 510 511 struct ice_aqc_recipe_data_elem { 512 u8 recipe_indx; 513 u8 resp_bits; 514 u8 rsvd0[2]; 515 u8 recipe_bitmap[8]; 516 u8 rsvd1[4]; 517 struct ice_aqc_recipe_content content; 518 u8 rsvd2[20]; 519 }; 520 521 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 522 struct ice_aqc_recipe_to_profile { 523 __le16 profile_id; 524 u8 rsvd[6]; 525 DECLARE_BITMAP(recipe_assoc, ICE_MAX_NUM_RECIPES); 526 }; 527 528 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 529 */ 530 struct ice_aqc_sw_rules { 531 /* ops: add switch rules, referring the number of rules. 532 * ops: update switch rules, referring the number of filters 533 * ops: remove switch rules, referring the entry index. 534 * ops: get switch rules, referring to the number of filters. 535 */ 536 __le16 num_rules_fltr_entry_index; 537 u8 reserved[6]; 538 __le32 addr_high; 539 __le32 addr_low; 540 }; 541 542 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 543 * This structures describes the lookup rules and associated actions. "index" 544 * is returned as part of a response to a successful Add command, and can be 545 * used to identify the rule for Update/Get/Remove commands. 546 */ 547 struct ice_sw_rule_lkup_rx_tx { 548 __le16 recipe_id; 549 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 550 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 551 __le16 src; 552 __le32 act; 553 554 /* Bit 0:1 - Action type */ 555 #define ICE_SINGLE_ACT_TYPE_S 0x00 556 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 557 558 /* Bit 2 - Loop back enable 559 * Bit 3 - LAN enable 560 */ 561 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 562 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 563 564 /* Action type = 0 - Forward to VSI or VSI list */ 565 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 566 567 #define ICE_SINGLE_ACT_VSI_ID_S 4 568 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 569 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 570 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 571 /* This bit needs to be set if action is forward to VSI list */ 572 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 573 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 574 #define ICE_SINGLE_ACT_DROP BIT(18) 575 576 /* Action type = 1 - Forward to Queue of Queue group */ 577 #define ICE_SINGLE_ACT_TO_Q 0x1 578 #define ICE_SINGLE_ACT_Q_INDEX_S 4 579 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 580 #define ICE_SINGLE_ACT_Q_REGION_S 15 581 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 582 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 583 584 /* Action type = 2 - Prune */ 585 #define ICE_SINGLE_ACT_PRUNE 0x2 586 #define ICE_SINGLE_ACT_EGRESS BIT(15) 587 #define ICE_SINGLE_ACT_INGRESS BIT(16) 588 #define ICE_SINGLE_ACT_PRUNET BIT(17) 589 /* Bit 18 should be set to 0 for this action */ 590 591 /* Action type = 2 - Pointer */ 592 #define ICE_SINGLE_ACT_PTR 0x2 593 #define ICE_SINGLE_ACT_PTR_VAL_S 4 594 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 595 /* Bit 18 should be set to 1 */ 596 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 597 598 /* Action type = 3 - Other actions. Last two bits 599 * are other action identifier 600 */ 601 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 602 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 603 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 604 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 605 606 /* Bit 17:18 - Defines other actions */ 607 /* Other action = 0 - Mirror VSI */ 608 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 609 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 610 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 611 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 612 613 /* Other action = 3 - Set Stat count */ 614 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 615 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 616 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 617 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 618 619 __le16 index; /* The index of the rule in the lookup table */ 620 /* Length and values of the header to be matched per recipe or 621 * lookup-type 622 */ 623 __le16 hdr_len; 624 u8 hdr[]; 625 }; 626 627 /* Add/Update/Remove large action command/response entry 628 * "index" is returned as part of a response to a successful Add command, and 629 * can be used to identify the action for Update/Get/Remove commands. 630 */ 631 struct ice_sw_rule_lg_act { 632 __le16 index; /* Index in large action table */ 633 __le16 size; 634 /* Max number of large actions */ 635 #define ICE_MAX_LG_ACT 4 636 /* Bit 0:1 - Action type */ 637 #define ICE_LG_ACT_TYPE_S 0 638 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 639 640 /* Action type = 0 - Forward to VSI or VSI list */ 641 #define ICE_LG_ACT_VSI_FORWARDING 0 642 #define ICE_LG_ACT_VSI_ID_S 3 643 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 644 #define ICE_LG_ACT_VSI_LIST_ID_S 3 645 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 646 /* This bit needs to be set if action is forward to VSI list */ 647 #define ICE_LG_ACT_VSI_LIST BIT(13) 648 649 #define ICE_LG_ACT_VALID_BIT BIT(16) 650 651 /* Action type = 1 - Forward to Queue of Queue group */ 652 #define ICE_LG_ACT_TO_Q 0x1 653 #define ICE_LG_ACT_Q_INDEX_S 3 654 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 655 #define ICE_LG_ACT_Q_REGION_S 14 656 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 657 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 658 659 /* Action type = 2 - Prune */ 660 #define ICE_LG_ACT_PRUNE 0x2 661 #define ICE_LG_ACT_EGRESS BIT(14) 662 #define ICE_LG_ACT_INGRESS BIT(15) 663 #define ICE_LG_ACT_PRUNET BIT(16) 664 665 /* Action type = 3 - Mirror VSI */ 666 #define ICE_LG_OTHER_ACT_MIRROR 0x3 667 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 668 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 669 670 /* Action type = 5 - Generic Value */ 671 #define ICE_LG_ACT_GENERIC 0x5 672 #define ICE_LG_ACT_GENERIC_VALUE_S 3 673 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 674 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 675 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 676 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 677 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 678 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 679 680 /* Action = 7 - Set Stat count */ 681 #define ICE_LG_ACT_STAT_COUNT 0x7 682 #define ICE_LG_ACT_STAT_COUNT_S 3 683 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 684 __le32 act[]; /* array of size for actions */ 685 }; 686 687 /* Add/Update/Remove VSI list command/response entry 688 * "index" is returned as part of a response to a successful Add command, and 689 * can be used to identify the VSI list for Update/Get/Remove commands. 690 */ 691 struct ice_sw_rule_vsi_list { 692 __le16 index; /* Index of VSI/Prune list */ 693 __le16 number_vsi; 694 __le16 vsi[]; /* Array of number_vsi VSI numbers */ 695 }; 696 697 /* Query VSI list command/response entry */ 698 struct ice_sw_rule_vsi_list_query { 699 __le16 index; 700 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI); 701 } __packed; 702 703 /* Add switch rule response: 704 * Content of return buffer is same as the input buffer. The status field and 705 * LUT index are updated as part of the response 706 */ 707 struct ice_aqc_sw_rules_elem { 708 __le16 type; /* Switch rule type, one of T_... */ 709 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 710 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 711 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 712 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 713 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 714 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 715 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 716 __le16 status; 717 union { 718 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 719 struct ice_sw_rule_lg_act lg_act; 720 struct ice_sw_rule_vsi_list vsi_list; 721 struct ice_sw_rule_vsi_list_query vsi_list_query; 722 } __packed pdata; 723 }; 724 725 /* Query PFC Mode (direct 0x0302) 726 * Set PFC Mode (direct 0x0303) 727 */ 728 struct ice_aqc_set_query_pfc_mode { 729 u8 pfc_mode; 730 /* For Query Command response, reserved in all other cases */ 731 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 732 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 733 u8 rsvd[15]; 734 }; 735 /* Get Default Topology (indirect 0x0400) */ 736 struct ice_aqc_get_topo { 737 u8 port_num; 738 u8 num_branches; 739 __le16 reserved1; 740 __le32 reserved2; 741 __le32 addr_high; 742 __le32 addr_low; 743 }; 744 745 /* Update TSE (indirect 0x0403) 746 * Get TSE (indirect 0x0404) 747 * Add TSE (indirect 0x0401) 748 * Delete TSE (indirect 0x040F) 749 * Move TSE (indirect 0x0408) 750 * Suspend Nodes (indirect 0x0409) 751 * Resume Nodes (indirect 0x040A) 752 */ 753 struct ice_aqc_sched_elem_cmd { 754 __le16 num_elem_req; /* Used by commands */ 755 __le16 num_elem_resp; /* Used by responses */ 756 __le32 reserved; 757 __le32 addr_high; 758 __le32 addr_low; 759 }; 760 761 struct ice_aqc_txsched_move_grp_info_hdr { 762 __le32 src_parent_teid; 763 __le32 dest_parent_teid; 764 __le16 num_elems; 765 __le16 reserved; 766 }; 767 768 struct ice_aqc_move_elem { 769 struct ice_aqc_txsched_move_grp_info_hdr hdr; 770 __le32 teid[]; 771 }; 772 773 struct ice_aqc_elem_info_bw { 774 __le16 bw_profile_idx; 775 __le16 bw_alloc; 776 }; 777 778 struct ice_aqc_txsched_elem { 779 u8 elem_type; /* Special field, reserved for some aq calls */ 780 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 781 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 782 #define ICE_AQC_ELEM_TYPE_TC 0x2 783 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 784 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 785 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 786 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 787 u8 valid_sections; 788 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 789 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 790 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 791 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 792 u8 generic; 793 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 794 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 795 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 796 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 797 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 798 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 799 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 800 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 801 u8 flags; /* Special field, reserved for some aq calls */ 802 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 803 struct ice_aqc_elem_info_bw cir_bw; 804 struct ice_aqc_elem_info_bw eir_bw; 805 __le16 srl_id; 806 __le16 reserved2; 807 }; 808 809 struct ice_aqc_txsched_elem_data { 810 __le32 parent_teid; 811 __le32 node_teid; 812 struct ice_aqc_txsched_elem data; 813 }; 814 815 struct ice_aqc_txsched_topo_grp_info_hdr { 816 __le32 parent_teid; 817 __le16 num_elems; 818 __le16 reserved2; 819 }; 820 821 struct ice_aqc_add_elem { 822 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 823 struct ice_aqc_txsched_elem_data generic[]; 824 }; 825 826 struct ice_aqc_get_topo_elem { 827 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 828 struct ice_aqc_txsched_elem_data 829 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 830 }; 831 832 struct ice_aqc_delete_elem { 833 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 834 __le32 teid[]; 835 }; 836 837 /* Query Port ETS (indirect 0x040E) 838 * 839 * This indirect command is used to query port TC node configuration. 840 */ 841 struct ice_aqc_query_port_ets { 842 __le32 port_teid; 843 __le32 reserved; 844 __le32 addr_high; 845 __le32 addr_low; 846 }; 847 848 struct ice_aqc_port_ets_elem { 849 u8 tc_valid_bits; 850 u8 reserved[3]; 851 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 852 __le32 up2tc; 853 u8 tc_bw_share[8]; 854 __le32 port_eir_prof_id; 855 __le32 port_cir_prof_id; 856 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 857 __le32 tc_node_prio; 858 #define ICE_TC_NODE_PRIO_S 0x4 859 u8 reserved1[4]; 860 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 861 }; 862 863 /* Rate limiting profile for 864 * Add RL profile (indirect 0x0410) 865 * Query RL profile (indirect 0x0411) 866 * Remove RL profile (indirect 0x0415) 867 * These indirect commands acts on single or multiple 868 * RL profiles with specified data. 869 */ 870 struct ice_aqc_rl_profile { 871 __le16 num_profiles; 872 __le16 num_processed; /* Only for response. Reserved in Command. */ 873 u8 reserved[4]; 874 __le32 addr_high; 875 __le32 addr_low; 876 }; 877 878 struct ice_aqc_rl_profile_elem { 879 u8 level; 880 u8 flags; 881 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 882 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 883 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 884 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 885 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 886 /* The following flag is used for Query RL Profile Data */ 887 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 888 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 889 890 __le16 profile_id; 891 __le16 max_burst_size; 892 __le16 rl_multiply; 893 __le16 wake_up_calc; 894 __le16 rl_encode; 895 }; 896 897 /* Query Scheduler Resource Allocation (indirect 0x0412) 898 * This indirect command retrieves the scheduler resources allocated by 899 * EMP Firmware to the given PF. 900 */ 901 struct ice_aqc_query_txsched_res { 902 u8 reserved[8]; 903 __le32 addr_high; 904 __le32 addr_low; 905 }; 906 907 struct ice_aqc_generic_sched_props { 908 __le16 phys_levels; 909 __le16 logical_levels; 910 u8 flattening_bitmap; 911 u8 max_device_cgds; 912 u8 max_pf_cgds; 913 u8 rsvd0; 914 __le16 rdma_qsets; 915 u8 rsvd1[22]; 916 }; 917 918 struct ice_aqc_layer_props { 919 u8 logical_layer; 920 u8 chunk_size; 921 __le16 max_device_nodes; 922 __le16 max_pf_nodes; 923 u8 rsvd0[4]; 924 __le16 max_sibl_grp_sz; 925 __le16 max_cir_rl_profiles; 926 __le16 max_eir_rl_profiles; 927 __le16 max_srl_profiles; 928 u8 rsvd1[14]; 929 }; 930 931 struct ice_aqc_query_txsched_res_resp { 932 struct ice_aqc_generic_sched_props sched_props; 933 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 934 }; 935 936 /* Get PHY capabilities (indirect 0x0600) */ 937 struct ice_aqc_get_phy_caps { 938 u8 lport_num; 939 u8 reserved; 940 __le16 param0; 941 /* 18.0 - Report qualified modules */ 942 #define ICE_AQC_GET_PHY_RQM BIT(0) 943 /* 18.1 - 18.3 : Report mode 944 * 000b - Report NVM capabilities 945 * 001b - Report topology capabilities 946 * 010b - Report SW configured 947 * 100b - Report default capabilities 948 */ 949 #define ICE_AQC_REPORT_MODE_S 1 950 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 951 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 952 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 953 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 954 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 955 __le32 reserved1; 956 __le32 addr_high; 957 __le32 addr_low; 958 }; 959 960 /* This is #define of PHY type (Extended): 961 * The first set of defines is for phy_type_low. 962 */ 963 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 964 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 965 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 966 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 967 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 968 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 969 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 970 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 971 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 972 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 973 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 974 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 975 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 976 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 977 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 978 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 979 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 980 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 981 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 982 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 983 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 984 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 985 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 986 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 987 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 988 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 989 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 990 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 991 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 992 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 993 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 994 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 995 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 996 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 997 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 998 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 999 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1000 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1001 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1002 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1003 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1004 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1005 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1006 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1007 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1008 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1009 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1010 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1011 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1012 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1013 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1014 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1015 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1016 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1017 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1018 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1019 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1020 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1021 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1022 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1023 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1024 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1025 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1026 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1027 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1028 /* The second set of defines is for phy_type_high. */ 1029 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1030 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1031 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1032 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1033 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1034 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 1035 1036 struct ice_aqc_get_phy_caps_data { 1037 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1038 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1039 u8 caps; 1040 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1041 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1042 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1043 #define ICE_AQC_PHY_EN_LINK BIT(3) 1044 #define ICE_AQC_PHY_AN_MODE BIT(4) 1045 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 1046 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1047 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 1048 u8 low_power_ctrl_an; 1049 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1050 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1051 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1052 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1053 __le16 eee_cap; 1054 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1055 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1056 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1057 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1058 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1059 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1060 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1061 __le16 eeer_value; 1062 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1063 u8 phy_fw_ver[8]; 1064 u8 link_fec_options; 1065 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1066 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1067 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1068 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1069 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1070 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1071 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1072 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 1073 u8 module_compliance_enforcement; 1074 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1075 u8 extended_compliance_code; 1076 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1077 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1078 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1079 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1080 #define ICE_AQC_MOD_TYPE_IDENT 1 1081 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1082 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1083 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1084 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1085 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1086 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1087 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1088 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1089 u8 qualified_module_count; 1090 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1091 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1092 struct { 1093 u8 v_oui[3]; 1094 u8 rsvd3; 1095 u8 v_part[16]; 1096 __le32 v_rev; 1097 __le64 rsvd4; 1098 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1099 }; 1100 1101 /* Set PHY capabilities (direct 0x0601) 1102 * NOTE: This command must be followed by setup link and restart auto-neg 1103 */ 1104 struct ice_aqc_set_phy_cfg { 1105 u8 lport_num; 1106 u8 reserved[7]; 1107 __le32 addr_high; 1108 __le32 addr_low; 1109 }; 1110 1111 /* Set PHY config command data structure */ 1112 struct ice_aqc_set_phy_cfg_data { 1113 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1114 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1115 u8 caps; 1116 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 1117 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1118 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1119 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1120 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1121 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1122 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1123 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1124 u8 low_power_ctrl_an; 1125 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1126 __le16 eeer_value; 1127 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1128 u8 module_compliance_enforcement; 1129 }; 1130 1131 /* Set MAC Config command data structure (direct 0x0603) */ 1132 struct ice_aqc_set_mac_cfg { 1133 __le16 max_frame_size; 1134 u8 params; 1135 #define ICE_AQ_SET_MAC_PACE_S 3 1136 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1137 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1138 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1139 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1140 u8 tx_tmr_priority; 1141 __le16 tx_tmr_value; 1142 __le16 fc_refresh_threshold; 1143 u8 drop_opts; 1144 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1145 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1146 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1147 u8 reserved[7]; 1148 }; 1149 1150 /* Restart AN command data structure (direct 0x0605) 1151 * Also used for response, with only the lport_num field present. 1152 */ 1153 struct ice_aqc_restart_an { 1154 u8 lport_num; 1155 u8 reserved; 1156 u8 cmd_flags; 1157 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1158 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1159 u8 reserved2[13]; 1160 }; 1161 1162 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1163 struct ice_aqc_get_link_status { 1164 u8 lport_num; 1165 u8 reserved; 1166 __le16 cmd_flags; 1167 #define ICE_AQ_LSE_M 0x3 1168 #define ICE_AQ_LSE_NOP 0x0 1169 #define ICE_AQ_LSE_DIS 0x2 1170 #define ICE_AQ_LSE_ENA 0x3 1171 /* only response uses this flag */ 1172 #define ICE_AQ_LSE_IS_ENABLED 0x1 1173 __le32 reserved2; 1174 __le32 addr_high; 1175 __le32 addr_low; 1176 }; 1177 1178 /* Get link status response data structure, also used for Link Status Event */ 1179 struct ice_aqc_get_link_status_data { 1180 u8 topo_media_conflict; 1181 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1182 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1183 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1184 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1185 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1186 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1187 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1188 u8 link_cfg_err; 1189 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1190 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1191 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1192 u8 link_info; 1193 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1194 #define ICE_AQ_LINK_FAULT BIT(1) 1195 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1196 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1197 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1198 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1199 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1200 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1201 u8 an_info; 1202 #define ICE_AQ_AN_COMPLETED BIT(0) 1203 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1204 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1205 #define ICE_AQ_FEC_EN BIT(3) 1206 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1207 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1208 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1209 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1210 u8 ext_info; 1211 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1212 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1213 /* Port Tx Suspended */ 1214 #define ICE_AQ_LINK_TX_S 2 1215 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1216 #define ICE_AQ_LINK_TX_ACTIVE 0 1217 #define ICE_AQ_LINK_TX_DRAINED 1 1218 #define ICE_AQ_LINK_TX_FLUSHED 3 1219 u8 reserved2; 1220 __le16 max_frame_size; 1221 u8 cfg; 1222 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1223 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1224 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1225 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1226 /* Pacing Config */ 1227 #define ICE_AQ_CFG_PACING_S 3 1228 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1229 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1230 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1231 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1232 /* External Device Power Ability */ 1233 u8 power_desc; 1234 #define ICE_AQ_PWR_CLASS_M 0x3F 1235 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1236 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1237 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1238 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1239 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1240 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1241 __le16 link_speed; 1242 #define ICE_AQ_LINK_SPEED_M 0x7FF 1243 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1244 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1245 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1246 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1247 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1248 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1249 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1250 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1251 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1252 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1253 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1254 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1255 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1256 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1257 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1258 }; 1259 1260 /* Set event mask command (direct 0x0613) */ 1261 struct ice_aqc_set_event_mask { 1262 u8 lport_num; 1263 u8 reserved[7]; 1264 __le16 event_mask; 1265 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1266 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1267 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1268 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1269 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1270 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1271 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1272 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1273 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1274 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 1275 u8 reserved1[6]; 1276 }; 1277 1278 /* Set MAC Loopback command (direct 0x0620) */ 1279 struct ice_aqc_set_mac_lb { 1280 u8 lb_mode; 1281 #define ICE_AQ_MAC_LB_EN BIT(0) 1282 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1283 u8 reserved[15]; 1284 }; 1285 1286 struct ice_aqc_link_topo_params { 1287 u8 lport_num; 1288 u8 lport_num_valid; 1289 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1290 u8 node_type_ctx; 1291 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1292 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1293 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1294 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1295 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1296 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1297 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1298 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1299 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1300 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1301 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1302 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1303 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1304 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1305 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1306 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1307 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1308 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1309 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1310 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1311 u8 index; 1312 }; 1313 1314 struct ice_aqc_link_topo_addr { 1315 struct ice_aqc_link_topo_params topo_params; 1316 __le16 handle; 1317 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1318 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1319 /* Used to decode the handle field */ 1320 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1321 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1322 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1323 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1324 /* In case of a Mezzanine type */ 1325 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1326 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1327 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1328 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1329 /* In case of a LOM type */ 1330 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1331 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1332 }; 1333 1334 /* Get Link Topology Handle (direct, 0x06E0) */ 1335 struct ice_aqc_get_link_topo { 1336 struct ice_aqc_link_topo_addr addr; 1337 u8 node_part_num; 1338 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 1339 u8 rsvd[9]; 1340 }; 1341 1342 /* Set Port Identification LED (direct, 0x06E9) */ 1343 struct ice_aqc_set_port_id_led { 1344 u8 lport_num; 1345 u8 lport_num_valid; 1346 u8 ident_mode; 1347 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1348 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1349 u8 rsvd[13]; 1350 }; 1351 1352 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 1353 struct ice_aqc_gpio { 1354 __le16 gpio_ctrl_handle; 1355 #define ICE_AQC_GPIO_HANDLE_S 0 1356 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 1357 u8 gpio_num; 1358 u8 gpio_val; 1359 u8 rsvd[12]; 1360 }; 1361 1362 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1363 struct ice_aqc_sff_eeprom { 1364 u8 lport_num; 1365 u8 lport_num_valid; 1366 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1367 __le16 i2c_bus_addr; 1368 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1369 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1370 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1371 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1372 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1373 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1374 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1375 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1376 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1377 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1378 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1379 __le16 i2c_mem_addr; 1380 __le16 eeprom_page; 1381 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1382 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1383 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1384 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1385 __le32 addr_high; 1386 __le32 addr_low; 1387 }; 1388 1389 /* NVM Read command (indirect 0x0701) 1390 * NVM Erase commands (direct 0x0702) 1391 * NVM Update commands (indirect 0x0703) 1392 */ 1393 struct ice_aqc_nvm { 1394 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1395 __le16 offset_low; 1396 u8 offset_high; 1397 u8 cmd_flags; 1398 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1399 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1400 #define ICE_AQC_NVM_PRESERVATION_S 1 1401 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1402 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1403 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1404 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1405 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1406 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1407 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1408 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1409 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1410 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1411 #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3) 1412 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1413 #define ICE_AQC_NVM_RESET_LVL_M ICE_M(0x3, 0) /* Write reply only */ 1414 #define ICE_AQC_NVM_POR_FLAG 0 1415 #define ICE_AQC_NVM_PERST_FLAG 1 1416 #define ICE_AQC_NVM_EMPR_FLAG 2 1417 #define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 1418 __le16 module_typeid; 1419 __le16 length; 1420 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1421 __le32 addr_high; 1422 __le32 addr_low; 1423 }; 1424 1425 #define ICE_AQC_NVM_START_POINT 0 1426 1427 /* NVM Checksum Command (direct, 0x0706) */ 1428 struct ice_aqc_nvm_checksum { 1429 u8 flags; 1430 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1431 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1432 u8 rsvd; 1433 __le16 checksum; /* Used only by response */ 1434 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1435 u8 rsvd2[12]; 1436 }; 1437 1438 /* Used for NVM Set Package Data command - 0x070A */ 1439 struct ice_aqc_nvm_pkg_data { 1440 u8 reserved[3]; 1441 u8 cmd_flags; 1442 #define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */ 1443 #define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */ 1444 1445 u32 reserved1; 1446 __le32 addr_high; 1447 __le32 addr_low; 1448 }; 1449 1450 /* Used for Pass Component Table command - 0x070B */ 1451 struct ice_aqc_nvm_pass_comp_tbl { 1452 u8 component_response; /* Response only */ 1453 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0 1454 #define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1 1455 #define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2 1456 u8 component_response_code; /* Response only */ 1457 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0 1458 #define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1 1459 #define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2 1460 #define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3 1461 #define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4 1462 #define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5 1463 #define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6 1464 #define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7 1465 #define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8 1466 #define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA 1467 #define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB 1468 u8 reserved; 1469 u8 transfer_flag; 1470 #define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1 1471 #define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2 1472 #define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4 1473 #define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5 1474 __le32 reserved1; 1475 __le32 addr_high; 1476 __le32 addr_low; 1477 }; 1478 1479 struct ice_aqc_nvm_comp_tbl { 1480 __le16 comp_class; 1481 #define NVM_COMP_CLASS_ALL_FW 0x000A 1482 1483 __le16 comp_id; 1484 #define NVM_COMP_ID_OROM 0x5 1485 #define NVM_COMP_ID_NVM 0x6 1486 #define NVM_COMP_ID_NETLIST 0x8 1487 1488 u8 comp_class_idx; 1489 #define FWU_COMP_CLASS_IDX_NOT_USE 0x0 1490 1491 __le32 comp_cmp_stamp; 1492 u8 cvs_type; 1493 #define NVM_CVS_TYPE_ASCII 0x1 1494 1495 u8 cvs_len; 1496 u8 cvs[]; /* Component Version String */ 1497 } __packed; 1498 1499 /* Send to PF command (indirect 0x0801) ID is only used by PF 1500 * 1501 * Send to VF command (indirect 0x0802) ID is only used by PF 1502 * 1503 */ 1504 struct ice_aqc_pf_vf_msg { 1505 __le32 id; 1506 u32 reserved; 1507 __le32 addr_high; 1508 __le32 addr_low; 1509 }; 1510 1511 /* Get LLDP MIB (indirect 0x0A00) 1512 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1513 * as the format is the same. 1514 */ 1515 struct ice_aqc_lldp_get_mib { 1516 u8 type; 1517 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1518 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1519 #define ICE_AQ_LLDP_MIB_LOCAL 0 1520 #define ICE_AQ_LLDP_MIB_REMOTE 1 1521 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1522 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1523 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1524 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1525 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1526 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1527 #define ICE_AQ_LLDP_TX_S 0x4 1528 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1529 #define ICE_AQ_LLDP_TX_ACTIVE 0 1530 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1531 #define ICE_AQ_LLDP_TX_FLUSHED 3 1532 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1533 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1534 * Get LLDP MIB (0x0A00) response only. 1535 */ 1536 u8 reserved1; 1537 __le16 local_len; 1538 __le16 remote_len; 1539 u8 reserved2[2]; 1540 __le32 addr_high; 1541 __le32 addr_low; 1542 }; 1543 1544 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1545 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1546 struct ice_aqc_lldp_set_mib_change { 1547 u8 command; 1548 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1549 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1550 u8 reserved[15]; 1551 }; 1552 1553 /* Stop LLDP (direct 0x0A05) */ 1554 struct ice_aqc_lldp_stop { 1555 u8 command; 1556 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1557 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1558 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1559 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1560 u8 reserved[15]; 1561 }; 1562 1563 /* Start LLDP (direct 0x0A06) */ 1564 struct ice_aqc_lldp_start { 1565 u8 command; 1566 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1567 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1568 u8 reserved[15]; 1569 }; 1570 1571 /* Get CEE DCBX Oper Config (0x0A07) 1572 * The command uses the generic descriptor struct and 1573 * returns the struct below as an indirect response. 1574 */ 1575 struct ice_aqc_get_cee_dcb_cfg_resp { 1576 u8 oper_num_tc; 1577 u8 oper_prio_tc[4]; 1578 u8 oper_tc_bw[8]; 1579 u8 oper_pfc_en; 1580 __le16 oper_app_prio; 1581 #define ICE_AQC_CEE_APP_FCOE_S 0 1582 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1583 #define ICE_AQC_CEE_APP_ISCSI_S 3 1584 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1585 #define ICE_AQC_CEE_APP_FIP_S 8 1586 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1587 __le32 tlv_status; 1588 #define ICE_AQC_CEE_PG_STATUS_S 0 1589 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1590 #define ICE_AQC_CEE_PFC_STATUS_S 3 1591 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1592 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1593 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1594 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1595 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1596 #define ICE_AQC_CEE_FIP_STATUS_S 16 1597 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1598 u8 reserved[12]; 1599 }; 1600 1601 /* Set Local LLDP MIB (indirect 0x0A08) 1602 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1603 */ 1604 struct ice_aqc_lldp_set_local_mib { 1605 u8 type; 1606 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1607 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1608 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1609 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1610 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1611 u8 reserved0; 1612 __le16 length; 1613 u8 reserved1[4]; 1614 __le32 addr_high; 1615 __le32 addr_low; 1616 }; 1617 1618 /* Stop/Start LLDP Agent (direct 0x0A09) 1619 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1620 * The same structure is used for the response, with the command field 1621 * being used as the status field. 1622 */ 1623 struct ice_aqc_lldp_stop_start_specific_agent { 1624 u8 command; 1625 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1626 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1627 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1628 u8 reserved[15]; 1629 }; 1630 1631 /* LLDP Filter Control (direct 0x0A0A) */ 1632 struct ice_aqc_lldp_filter_ctrl { 1633 u8 cmd_flags; 1634 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 1635 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 1636 u8 reserved1; 1637 __le16 vsi_num; 1638 u8 reserved2[12]; 1639 }; 1640 1641 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1642 struct ice_aqc_get_set_rss_key { 1643 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1644 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1645 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1646 __le16 vsi_id; 1647 u8 reserved[6]; 1648 __le32 addr_high; 1649 __le32 addr_low; 1650 }; 1651 1652 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1653 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1654 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1655 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1656 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1657 1658 struct ice_aqc_get_set_rss_keys { 1659 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1660 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1661 }; 1662 1663 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1664 struct ice_aqc_get_set_rss_lut { 1665 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1666 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1667 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1668 __le16 vsi_id; 1669 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1670 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1671 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1672 1673 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1674 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1675 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1676 1677 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1678 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1679 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1680 1681 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1682 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1683 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1684 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1685 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1686 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1687 1688 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1689 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1690 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1691 1692 __le16 flags; 1693 __le32 reserved; 1694 __le32 addr_high; 1695 __le32 addr_low; 1696 }; 1697 1698 /* Sideband Control Interface Commands */ 1699 /* Neighbor Device Request (indirect 0x0C00); also used for the response. */ 1700 struct ice_aqc_neigh_dev_req { 1701 __le16 sb_data_len; 1702 u8 reserved[6]; 1703 __le32 addr_high; 1704 __le32 addr_low; 1705 }; 1706 1707 /* Add Tx LAN Queues (indirect 0x0C30) */ 1708 struct ice_aqc_add_txqs { 1709 u8 num_qgrps; 1710 u8 reserved[3]; 1711 __le32 reserved1; 1712 __le32 addr_high; 1713 __le32 addr_low; 1714 }; 1715 1716 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1717 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1718 */ 1719 struct ice_aqc_add_txqs_perq { 1720 __le16 txq_id; 1721 u8 rsvd[2]; 1722 __le32 q_teid; 1723 u8 txq_ctx[22]; 1724 u8 rsvd2[2]; 1725 struct ice_aqc_txsched_elem info; 1726 }; 1727 1728 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 1729 * is an array of the following structs. Please note that the length of 1730 * each struct ice_aqc_add_tx_qgrp is variable due 1731 * to the variable number of queues in each group! 1732 */ 1733 struct ice_aqc_add_tx_qgrp { 1734 __le32 parent_teid; 1735 u8 num_txqs; 1736 u8 rsvd[3]; 1737 struct ice_aqc_add_txqs_perq txqs[]; 1738 }; 1739 1740 /* Disable Tx LAN Queues (indirect 0x0C31) */ 1741 struct ice_aqc_dis_txqs { 1742 u8 cmd_type; 1743 #define ICE_AQC_Q_DIS_CMD_S 0 1744 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1745 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1746 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1747 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1748 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1749 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1750 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1751 u8 num_entries; 1752 __le16 vmvf_and_timeout; 1753 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 1754 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 1755 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 1756 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 1757 __le32 blocked_cgds; 1758 __le32 addr_high; 1759 __le32 addr_low; 1760 }; 1761 1762 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 1763 * contains the following structures, arrayed one after the 1764 * other. 1765 * Note: Since the q_id is 16 bits wide, if the 1766 * number of queues is even, then 2 bytes of alignment MUST be 1767 * added before the start of the next group, to allow correct 1768 * alignment of the parent_teid field. 1769 */ 1770 struct ice_aqc_dis_txq_item { 1771 __le32 parent_teid; 1772 u8 num_qs; 1773 u8 rsvd; 1774 /* The length of the q_id array varies according to num_qs */ 1775 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 1776 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 1777 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1778 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 1779 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1780 __le16 q_id[]; 1781 } __packed; 1782 1783 /* Add Tx RDMA Queue Set (indirect 0x0C33) */ 1784 struct ice_aqc_add_rdma_qset { 1785 u8 num_qset_grps; 1786 u8 reserved[7]; 1787 __le32 addr_high; 1788 __le32 addr_low; 1789 }; 1790 1791 /* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set 1792 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset. 1793 */ 1794 struct ice_aqc_add_tx_rdma_qset_entry { 1795 __le16 tx_qset_id; 1796 u8 rsvd[2]; 1797 __le32 qset_teid; 1798 struct ice_aqc_txsched_elem info; 1799 }; 1800 1801 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33) 1802 * is an array of the following structs. Please note that the length of 1803 * each struct ice_aqc_add_rdma_qset is variable due to the variable 1804 * number of queues in each group! 1805 */ 1806 struct ice_aqc_add_rdma_qset_data { 1807 __le32 parent_teid; 1808 __le16 num_qsets; 1809 u8 rsvd[2]; 1810 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[]; 1811 }; 1812 1813 /* Configure Firmware Logging Command (indirect 0xFF09) 1814 * Logging Information Read Response (indirect 0xFF10) 1815 * Note: The 0xFF10 command has no input parameters. 1816 */ 1817 struct ice_aqc_fw_logging { 1818 u8 log_ctrl; 1819 #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 1820 #define ICE_AQC_FW_LOG_UART_EN BIT(1) 1821 u8 rsvd0; 1822 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 1823 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 1824 #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 1825 u8 rsvd1[5]; 1826 __le32 addr_high; 1827 __le32 addr_low; 1828 }; 1829 1830 enum ice_aqc_fw_logging_mod { 1831 ICE_AQC_FW_LOG_ID_GENERAL = 0, 1832 ICE_AQC_FW_LOG_ID_CTRL, 1833 ICE_AQC_FW_LOG_ID_LINK, 1834 ICE_AQC_FW_LOG_ID_LINK_TOPO, 1835 ICE_AQC_FW_LOG_ID_DNL, 1836 ICE_AQC_FW_LOG_ID_I2C, 1837 ICE_AQC_FW_LOG_ID_SDP, 1838 ICE_AQC_FW_LOG_ID_MDIO, 1839 ICE_AQC_FW_LOG_ID_ADMINQ, 1840 ICE_AQC_FW_LOG_ID_HDMA, 1841 ICE_AQC_FW_LOG_ID_LLDP, 1842 ICE_AQC_FW_LOG_ID_DCBX, 1843 ICE_AQC_FW_LOG_ID_DCB, 1844 ICE_AQC_FW_LOG_ID_NETPROXY, 1845 ICE_AQC_FW_LOG_ID_NVM, 1846 ICE_AQC_FW_LOG_ID_AUTH, 1847 ICE_AQC_FW_LOG_ID_VPD, 1848 ICE_AQC_FW_LOG_ID_IOSF, 1849 ICE_AQC_FW_LOG_ID_PARSER, 1850 ICE_AQC_FW_LOG_ID_SW, 1851 ICE_AQC_FW_LOG_ID_SCHEDULER, 1852 ICE_AQC_FW_LOG_ID_TXQ, 1853 ICE_AQC_FW_LOG_ID_RSVD, 1854 ICE_AQC_FW_LOG_ID_POST, 1855 ICE_AQC_FW_LOG_ID_WATCHDOG, 1856 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 1857 ICE_AQC_FW_LOG_ID_MNG, 1858 ICE_AQC_FW_LOG_ID_MAX, 1859 }; 1860 1861 /* Defines for both above FW logging command/response buffers */ 1862 #define ICE_AQC_FW_LOG_ID_S 0 1863 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 1864 1865 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 1866 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 1867 1868 #define ICE_AQC_FW_LOG_EN_S 12 1869 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 1870 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 1871 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 1872 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 1873 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 1874 1875 /* Get/Clear FW Log (indirect 0xFF11) */ 1876 struct ice_aqc_get_clear_fw_log { 1877 u8 flags; 1878 #define ICE_AQC_FW_LOG_CLEAR BIT(0) 1879 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 1880 u8 rsvd1[7]; 1881 __le32 addr_high; 1882 __le32 addr_low; 1883 }; 1884 1885 /* Download Package (indirect 0x0C40) */ 1886 /* Also used for Update Package (indirect 0x0C42) */ 1887 struct ice_aqc_download_pkg { 1888 u8 flags; 1889 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 1890 u8 reserved[3]; 1891 __le32 reserved1; 1892 __le32 addr_high; 1893 __le32 addr_low; 1894 }; 1895 1896 struct ice_aqc_download_pkg_resp { 1897 __le32 error_offset; 1898 __le32 error_info; 1899 __le32 addr_high; 1900 __le32 addr_low; 1901 }; 1902 1903 /* Get Package Info List (indirect 0x0C43) */ 1904 struct ice_aqc_get_pkg_info_list { 1905 __le32 reserved1; 1906 __le32 reserved2; 1907 __le32 addr_high; 1908 __le32 addr_low; 1909 }; 1910 1911 /* Version format for packages */ 1912 struct ice_pkg_ver { 1913 u8 major; 1914 u8 minor; 1915 u8 update; 1916 u8 draft; 1917 }; 1918 1919 #define ICE_PKG_NAME_SIZE 32 1920 #define ICE_SEG_ID_SIZE 28 1921 #define ICE_SEG_NAME_SIZE 28 1922 1923 struct ice_aqc_get_pkg_info { 1924 struct ice_pkg_ver ver; 1925 char name[ICE_SEG_NAME_SIZE]; 1926 __le32 track_id; 1927 u8 is_in_nvm; 1928 u8 is_active; 1929 u8 is_active_at_boot; 1930 u8 is_modified; 1931 }; 1932 1933 /* Get Package Info List response buffer format (0x0C43) */ 1934 struct ice_aqc_get_pkg_info_resp { 1935 __le32 count; 1936 struct ice_aqc_get_pkg_info pkg_info[]; 1937 }; 1938 1939 /* Driver Shared Parameters (direct, 0x0C90) */ 1940 struct ice_aqc_driver_shared_params { 1941 u8 set_or_get_op; 1942 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 1943 #define ICE_AQC_DRIVER_PARAM_SET 0 1944 #define ICE_AQC_DRIVER_PARAM_GET 1 1945 u8 param_indx; 1946 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 1947 u8 rsvd[2]; 1948 __le32 param_val; 1949 __le32 addr_high; 1950 __le32 addr_low; 1951 }; 1952 1953 enum ice_aqc_driver_params { 1954 /* OS clock index for PTP timer Domain 0 */ 1955 ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0 = 0, 1956 /* OS clock index for PTP timer Domain 1 */ 1957 ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1, 1958 1959 /* Add new parameters above */ 1960 ICE_AQC_DRIVER_PARAM_MAX = 16, 1961 }; 1962 1963 /* Lan Queue Overflow Event (direct, 0x1001) */ 1964 struct ice_aqc_event_lan_overflow { 1965 __le32 prtdcb_ruptq; 1966 __le32 qtx_ctl; 1967 u8 reserved[8]; 1968 }; 1969 1970 /** 1971 * struct ice_aq_desc - Admin Queue (AQ) descriptor 1972 * @flags: ICE_AQ_FLAG_* flags 1973 * @opcode: AQ command opcode 1974 * @datalen: length in bytes of indirect/external data buffer 1975 * @retval: return value from firmware 1976 * @cookie_high: opaque data high-half 1977 * @cookie_low: opaque data low-half 1978 * @params: command-specific parameters 1979 * 1980 * Descriptor format for commands the driver posts on the Admin Transmit Queue 1981 * (ATQ). The firmware writes back onto the command descriptor and returns 1982 * the result of the command. Asynchronous events that are not an immediate 1983 * result of the command are written to the Admin Receive Queue (ARQ) using 1984 * the same descriptor format. Descriptors are in little-endian notation with 1985 * 32-bit words. 1986 */ 1987 struct ice_aq_desc { 1988 __le16 flags; 1989 __le16 opcode; 1990 __le16 datalen; 1991 __le16 retval; 1992 __le32 cookie_high; 1993 __le32 cookie_low; 1994 union { 1995 u8 raw[16]; 1996 struct ice_aqc_generic generic; 1997 struct ice_aqc_get_ver get_ver; 1998 struct ice_aqc_driver_ver driver_ver; 1999 struct ice_aqc_q_shutdown q_shutdown; 2000 struct ice_aqc_req_res res_owner; 2001 struct ice_aqc_manage_mac_read mac_read; 2002 struct ice_aqc_manage_mac_write mac_write; 2003 struct ice_aqc_clear_pxe clear_pxe; 2004 struct ice_aqc_list_caps get_cap; 2005 struct ice_aqc_get_phy_caps get_phy; 2006 struct ice_aqc_set_phy_cfg set_phy; 2007 struct ice_aqc_restart_an restart_an; 2008 struct ice_aqc_gpio read_write_gpio; 2009 struct ice_aqc_sff_eeprom read_write_sff_param; 2010 struct ice_aqc_set_port_id_led set_port_id_led; 2011 struct ice_aqc_get_sw_cfg get_sw_conf; 2012 struct ice_aqc_sw_rules sw_rules; 2013 struct ice_aqc_add_get_recipe add_get_recipe; 2014 struct ice_aqc_recipe_to_profile recipe_to_profile; 2015 struct ice_aqc_get_topo get_topo; 2016 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2017 struct ice_aqc_query_txsched_res query_sched_res; 2018 struct ice_aqc_query_port_ets port_ets; 2019 struct ice_aqc_rl_profile rl_profile; 2020 struct ice_aqc_nvm nvm; 2021 struct ice_aqc_nvm_checksum nvm_checksum; 2022 struct ice_aqc_nvm_pkg_data pkg_data; 2023 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl; 2024 struct ice_aqc_pf_vf_msg virt; 2025 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2026 struct ice_aqc_lldp_get_mib lldp_get_mib; 2027 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2028 struct ice_aqc_lldp_stop lldp_stop; 2029 struct ice_aqc_lldp_start lldp_start; 2030 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2031 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2032 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2033 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2034 struct ice_aqc_get_set_rss_key get_set_rss_key; 2035 struct ice_aqc_neigh_dev_req neigh_dev; 2036 struct ice_aqc_add_txqs add_txqs; 2037 struct ice_aqc_dis_txqs dis_txqs; 2038 struct ice_aqc_add_rdma_qset add_rdma_qset; 2039 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2040 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2041 struct ice_aqc_fw_logging fw_logging; 2042 struct ice_aqc_get_clear_fw_log get_clear_fw_log; 2043 struct ice_aqc_download_pkg download_pkg; 2044 struct ice_aqc_driver_shared_params drv_shared_params; 2045 struct ice_aqc_set_mac_lb set_mac_lb; 2046 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2047 struct ice_aqc_set_mac_cfg set_mac_cfg; 2048 struct ice_aqc_set_event_mask set_event_mask; 2049 struct ice_aqc_get_link_status get_link_status; 2050 struct ice_aqc_event_lan_overflow lan_overflow; 2051 struct ice_aqc_get_link_topo get_link_topo; 2052 } params; 2053 }; 2054 2055 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2056 #define ICE_AQ_LG_BUF 512 2057 2058 #define ICE_AQ_FLAG_ERR_S 2 2059 #define ICE_AQ_FLAG_LB_S 9 2060 #define ICE_AQ_FLAG_RD_S 10 2061 #define ICE_AQ_FLAG_BUF_S 12 2062 #define ICE_AQ_FLAG_SI_S 13 2063 2064 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2065 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2066 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2067 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2068 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2069 2070 /* error codes */ 2071 enum ice_aq_err { 2072 ICE_AQ_RC_OK = 0, /* Success */ 2073 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2074 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2075 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2076 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2077 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2078 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2079 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2080 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2081 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2082 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2083 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2084 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2085 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2086 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2087 }; 2088 2089 /* Admin Queue command opcodes */ 2090 enum ice_adminq_opc { 2091 /* AQ commands */ 2092 ice_aqc_opc_get_ver = 0x0001, 2093 ice_aqc_opc_driver_ver = 0x0002, 2094 ice_aqc_opc_q_shutdown = 0x0003, 2095 2096 /* resource ownership */ 2097 ice_aqc_opc_req_res = 0x0008, 2098 ice_aqc_opc_release_res = 0x0009, 2099 2100 /* device/function capabilities */ 2101 ice_aqc_opc_list_func_caps = 0x000A, 2102 ice_aqc_opc_list_dev_caps = 0x000B, 2103 2104 /* manage MAC address */ 2105 ice_aqc_opc_manage_mac_read = 0x0107, 2106 ice_aqc_opc_manage_mac_write = 0x0108, 2107 2108 /* PXE */ 2109 ice_aqc_opc_clear_pxe_mode = 0x0110, 2110 2111 /* internal switch commands */ 2112 ice_aqc_opc_get_sw_cfg = 0x0200, 2113 2114 /* Alloc/Free/Get Resources */ 2115 ice_aqc_opc_alloc_res = 0x0208, 2116 ice_aqc_opc_free_res = 0x0209, 2117 2118 /* VSI commands */ 2119 ice_aqc_opc_add_vsi = 0x0210, 2120 ice_aqc_opc_update_vsi = 0x0211, 2121 ice_aqc_opc_free_vsi = 0x0213, 2122 2123 /* recipe commands */ 2124 ice_aqc_opc_add_recipe = 0x0290, 2125 ice_aqc_opc_recipe_to_profile = 0x0291, 2126 ice_aqc_opc_get_recipe = 0x0292, 2127 ice_aqc_opc_get_recipe_to_profile = 0x0293, 2128 2129 /* switch rules population commands */ 2130 ice_aqc_opc_add_sw_rules = 0x02A0, 2131 ice_aqc_opc_update_sw_rules = 0x02A1, 2132 ice_aqc_opc_remove_sw_rules = 0x02A2, 2133 2134 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2135 2136 /* DCB commands */ 2137 ice_aqc_opc_query_pfc_mode = 0x0302, 2138 ice_aqc_opc_set_pfc_mode = 0x0303, 2139 2140 /* transmit scheduler commands */ 2141 ice_aqc_opc_get_dflt_topo = 0x0400, 2142 ice_aqc_opc_add_sched_elems = 0x0401, 2143 ice_aqc_opc_cfg_sched_elems = 0x0403, 2144 ice_aqc_opc_get_sched_elems = 0x0404, 2145 ice_aqc_opc_move_sched_elems = 0x0408, 2146 ice_aqc_opc_suspend_sched_elems = 0x0409, 2147 ice_aqc_opc_resume_sched_elems = 0x040A, 2148 ice_aqc_opc_query_port_ets = 0x040E, 2149 ice_aqc_opc_delete_sched_elems = 0x040F, 2150 ice_aqc_opc_add_rl_profiles = 0x0410, 2151 ice_aqc_opc_query_sched_res = 0x0412, 2152 ice_aqc_opc_remove_rl_profiles = 0x0415, 2153 2154 /* PHY commands */ 2155 ice_aqc_opc_get_phy_caps = 0x0600, 2156 ice_aqc_opc_set_phy_cfg = 0x0601, 2157 ice_aqc_opc_set_mac_cfg = 0x0603, 2158 ice_aqc_opc_restart_an = 0x0605, 2159 ice_aqc_opc_get_link_status = 0x0607, 2160 ice_aqc_opc_set_event_mask = 0x0613, 2161 ice_aqc_opc_set_mac_lb = 0x0620, 2162 ice_aqc_opc_get_link_topo = 0x06E0, 2163 ice_aqc_opc_set_port_id_led = 0x06E9, 2164 ice_aqc_opc_set_gpio = 0x06EC, 2165 ice_aqc_opc_get_gpio = 0x06ED, 2166 ice_aqc_opc_sff_eeprom = 0x06EE, 2167 2168 /* NVM commands */ 2169 ice_aqc_opc_nvm_read = 0x0701, 2170 ice_aqc_opc_nvm_erase = 0x0702, 2171 ice_aqc_opc_nvm_write = 0x0703, 2172 ice_aqc_opc_nvm_checksum = 0x0706, 2173 ice_aqc_opc_nvm_write_activate = 0x0707, 2174 ice_aqc_opc_nvm_update_empr = 0x0709, 2175 ice_aqc_opc_nvm_pkg_data = 0x070A, 2176 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 2177 2178 /* PF/VF mailbox commands */ 2179 ice_mbx_opc_send_msg_to_pf = 0x0801, 2180 ice_mbx_opc_send_msg_to_vf = 0x0802, 2181 /* LLDP commands */ 2182 ice_aqc_opc_lldp_get_mib = 0x0A00, 2183 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2184 ice_aqc_opc_lldp_stop = 0x0A05, 2185 ice_aqc_opc_lldp_start = 0x0A06, 2186 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2187 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 2188 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 2189 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 2190 2191 /* RSS commands */ 2192 ice_aqc_opc_set_rss_key = 0x0B02, 2193 ice_aqc_opc_set_rss_lut = 0x0B03, 2194 ice_aqc_opc_get_rss_key = 0x0B04, 2195 ice_aqc_opc_get_rss_lut = 0x0B05, 2196 2197 /* Sideband Control Interface commands */ 2198 ice_aqc_opc_neighbour_device_request = 0x0C00, 2199 2200 /* Tx queue handling commands/events */ 2201 ice_aqc_opc_add_txqs = 0x0C30, 2202 ice_aqc_opc_dis_txqs = 0x0C31, 2203 ice_aqc_opc_add_rdma_qset = 0x0C33, 2204 2205 /* package commands */ 2206 ice_aqc_opc_download_pkg = 0x0C40, 2207 ice_aqc_opc_update_pkg = 0x0C42, 2208 ice_aqc_opc_get_pkg_info_list = 0x0C43, 2209 2210 ice_aqc_opc_driver_shared_params = 0x0C90, 2211 2212 /* Standalone Commands/Events */ 2213 ice_aqc_opc_event_lan_overflow = 0x1001, 2214 2215 /* debug commands */ 2216 ice_aqc_opc_fw_logging = 0xFF09, 2217 ice_aqc_opc_fw_logging_info = 0xFF10, 2218 }; 2219 2220 #endif /* _ICE_ADMINQ_CMD_H_ */ 2221