1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copied from arch/arm64/include/asm/hwcap.h 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Copyright (C) 2017 SiFive 7 */ 8 #ifndef _ASM_RISCV_HWCAP_H 9 #define _ASM_RISCV_HWCAP_H 10 11 #include <linux/bits.h> 12 #include <uapi/asm/hwcap.h> 13 14 #ifndef __ASSEMBLY__ 15 /* 16 * This yields a mask that user programs can use to figure out what 17 * instruction set this cpu supports. 18 */ 19 #define ELF_HWCAP (elf_hwcap) 20 21 enum { 22 CAP_HWCAP = 1, 23 }; 24 25 extern unsigned long elf_hwcap; 26 27 #define RISCV_ISA_EXT_a ('a' - 'a') 28 #define RISCV_ISA_EXT_c ('c' - 'a') 29 #define RISCV_ISA_EXT_d ('d' - 'a') 30 #define RISCV_ISA_EXT_f ('f' - 'a') 31 #define RISCV_ISA_EXT_h ('h' - 'a') 32 #define RISCV_ISA_EXT_i ('i' - 'a') 33 #define RISCV_ISA_EXT_m ('m' - 'a') 34 #define RISCV_ISA_EXT_s ('s' - 'a') 35 #define RISCV_ISA_EXT_u ('u' - 'a') 36 37 /* 38 * Increse this to higher value as kernel support more ISA extensions. 39 */ 40 #define RISCV_ISA_EXT_MAX 64 41 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 42 43 /* The base ID for multi-letter ISA extensions */ 44 #define RISCV_ISA_EXT_BASE 26 45 46 /* 47 * This enum represent the logical ID for each multi-letter RISC-V ISA extension. 48 * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed 49 * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter 50 * extensions while all the multi-letter extensions should define the next 51 * available logical extension id. 52 */ 53 enum riscv_isa_ext_id { 54 RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, 55 RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, 56 }; 57 58 struct riscv_isa_ext_data { 59 /* Name of the extension displayed to userspace via /proc/cpuinfo */ 60 char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; 61 /* The logical ISA extension ID */ 62 unsigned int isa_ext_id; 63 }; 64 65 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); 66 67 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) 68 69 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit); 70 #define riscv_isa_extension_available(isa_bitmap, ext) \ 71 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) 72 73 #endif 74 75 #endif /* _ASM_RISCV_HWCAP_H */ 76