1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * linux/sound/soc/codecs/tlv320aic32x4.c 4 * 5 * Copyright 2011 Vista Silicon S.L. 6 * 7 * Author: Javier Martin <javier.martin@vista-silicon.com> 8 * 9 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/gpio.h> 18 #include <linux/of_gpio.h> 19 #include <linux/cdev.h> 20 #include <linux/slab.h> 21 #include <linux/clk.h> 22 #include <linux/of_clk.h> 23 #include <linux/regulator/consumer.h> 24 25 #include <sound/tlv320aic32x4.h> 26 #include <sound/core.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 #include <sound/soc-dapm.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 34 #include "tlv320aic32x4.h" 35 36 struct aic32x4_priv { 37 struct regmap *regmap; 38 u32 power_cfg; 39 u32 micpga_routing; 40 bool swapdacs; 41 int rstn_gpio; 42 const char *mclk_name; 43 44 struct regulator *supply_ldo; 45 struct regulator *supply_iov; 46 struct regulator *supply_dv; 47 struct regulator *supply_av; 48 49 struct aic32x4_setup_data *setup; 50 struct device *dev; 51 enum aic32x4_type type; 52 }; 53 54 static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w, 55 struct snd_kcontrol *kcontrol, int event) 56 { 57 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 58 u32 adc_reg; 59 60 /* 61 * Workaround: the datasheet does not mention a required programming 62 * sequence but experiments show the ADC needs to be reset after each 63 * capture to avoid audible artifacts. 64 */ 65 switch (event) { 66 case SND_SOC_DAPM_POST_PMD: 67 adc_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP); 68 snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg | 69 AIC32X4_LADC_EN | AIC32X4_RADC_EN); 70 snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg); 71 break; 72 } 73 return 0; 74 }; 75 76 static int mic_bias_event(struct snd_soc_dapm_widget *w, 77 struct snd_kcontrol *kcontrol, int event) 78 { 79 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 80 81 switch (event) { 82 case SND_SOC_DAPM_POST_PMU: 83 /* Change Mic Bias Registor */ 84 snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 85 AIC32x4_MICBIAS_MASK, 86 AIC32X4_MICBIAS_LDOIN | 87 AIC32X4_MICBIAS_2075V); 88 printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__); 89 break; 90 case SND_SOC_DAPM_PRE_PMD: 91 snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 92 AIC32x4_MICBIAS_MASK, 0); 93 printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n", 94 __func__); 95 break; 96 } 97 98 return 0; 99 } 100 101 102 static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol, 103 struct snd_ctl_elem_value *ucontrol) 104 { 105 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 106 u8 val; 107 108 val = snd_soc_component_read(component, AIC32X4_DINCTL); 109 110 ucontrol->value.integer.value[0] = (val & 0x01); 111 112 return 0; 113 }; 114 115 static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol, 116 struct snd_ctl_elem_value *ucontrol) 117 { 118 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 119 u8 val; 120 u8 gpio_check; 121 122 val = snd_soc_component_read(component, AIC32X4_DOUTCTL); 123 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 124 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 125 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n", 126 __func__); 127 return -EINVAL; 128 } 129 130 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH)) 131 return 0; 132 133 if (ucontrol->value.integer.value[0]) 134 val |= ucontrol->value.integer.value[0]; 135 else 136 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH; 137 138 snd_soc_component_write(component, AIC32X4_DOUTCTL, val); 139 140 return 0; 141 }; 142 143 static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol, 144 struct snd_ctl_elem_value *ucontrol) 145 { 146 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 147 u8 val; 148 149 val = snd_soc_component_read(component, AIC32X4_SCLKCTL); 150 151 ucontrol->value.integer.value[0] = (val & 0x01); 152 153 return 0; 154 }; 155 156 static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol, 157 struct snd_ctl_elem_value *ucontrol) 158 { 159 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 160 u8 val; 161 u8 gpio_check; 162 163 val = snd_soc_component_read(component, AIC32X4_MISOCTL); 164 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 165 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 166 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n", 167 __func__); 168 return -EINVAL; 169 } 170 171 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH)) 172 return 0; 173 174 if (ucontrol->value.integer.value[0]) 175 val |= ucontrol->value.integer.value[0]; 176 else 177 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH; 178 179 snd_soc_component_write(component, AIC32X4_MISOCTL, val); 180 181 return 0; 182 }; 183 184 static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol, 185 struct snd_ctl_elem_value *ucontrol) 186 { 187 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 188 u8 val; 189 190 val = snd_soc_component_read(component, AIC32X4_GPIOCTL); 191 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1); 192 193 return 0; 194 }; 195 196 static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol, 197 struct snd_ctl_elem_value *ucontrol) 198 { 199 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 200 u8 val; 201 u8 gpio_check; 202 203 val = snd_soc_component_read(component, AIC32X4_GPIOCTL); 204 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT); 205 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) { 206 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n", 207 __func__); 208 return -EINVAL; 209 } 210 211 if (ucontrol->value.integer.value[0] == (val & 0x1)) 212 return 0; 213 214 if (ucontrol->value.integer.value[0]) 215 val |= ucontrol->value.integer.value[0]; 216 else 217 val &= 0xfe; 218 219 snd_soc_component_write(component, AIC32X4_GPIOCTL, val); 220 221 return 0; 222 }; 223 224 static const struct snd_kcontrol_new aic32x4_mfp1[] = { 225 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL), 226 }; 227 228 static const struct snd_kcontrol_new aic32x4_mfp2[] = { 229 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio), 230 }; 231 232 static const struct snd_kcontrol_new aic32x4_mfp3[] = { 233 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL), 234 }; 235 236 static const struct snd_kcontrol_new aic32x4_mfp4[] = { 237 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio), 238 }; 239 240 static const struct snd_kcontrol_new aic32x4_mfp5[] = { 241 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio, 242 aic32x4_set_mfp5_gpio), 243 }; 244 245 /* 0dB min, 0.5dB steps */ 246 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0); 247 /* -63.5dB min, 0.5dB steps */ 248 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0); 249 /* -6dB min, 1dB steps */ 250 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0); 251 /* -12dB min, 0.5dB steps */ 252 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0); 253 /* -6dB min, 1dB steps */ 254 static DECLARE_TLV_DB_SCALE(tlv_tas_driver_gain, -5850, 50, 0); 255 static DECLARE_TLV_DB_SCALE(tlv_amp_vol, 0, 600, 1); 256 257 static const char * const lo_cm_text[] = { 258 "Full Chip", "1.65V", 259 }; 260 261 static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text); 262 263 static const char * const ptm_text[] = { 264 "P3", "P2", "P1", 265 }; 266 267 static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text); 268 static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text); 269 270 static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 271 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL, 272 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm), 273 SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum), 274 SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum), 275 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN, 276 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0, 277 tlv_driver_gain), 278 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN, 279 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0, 280 tlv_driver_gain), 281 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN, 282 AIC32X4_HPRGAIN, 6, 0x01, 1), 283 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN, 284 AIC32X4_LORGAIN, 6, 0x01, 1), 285 SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum), 286 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL, 287 AIC32X4_RMICPGAVOL, 7, 0x01, 1), 288 289 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0), 290 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0), 291 292 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL, 293 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol), 294 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL, 295 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5), 296 297 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 298 299 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0), 300 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0), 301 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 302 4, 0x07, 0), 303 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 304 0, 0x03, 0), 305 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 306 6, 0x03, 0), 307 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 308 1, 0x1F, 0), 309 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 310 0, 0x7F, 0), 311 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 312 3, 0x1F, 0), 313 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 314 3, 0x1F, 0), 315 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 316 0, 0x1F, 0), 317 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 318 0, 0x0F, 0), 319 }; 320 321 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { 322 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 323 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), 324 }; 325 326 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = { 327 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0), 328 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0), 329 }; 330 331 static const struct snd_kcontrol_new lol_output_mixer_controls[] = { 332 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0), 333 }; 334 335 static const struct snd_kcontrol_new lor_output_mixer_controls[] = { 336 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0), 337 }; 338 339 static const char * const resistor_text[] = { 340 "Off", "10 kOhm", "20 kOhm", "40 kOhm", 341 }; 342 343 /* Left mixer pins */ 344 static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text); 345 static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text); 346 static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text); 347 static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text); 348 349 static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text); 350 static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text); 351 static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text); 352 353 static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = { 354 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum), 355 }; 356 static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = { 357 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum), 358 }; 359 static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = { 360 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum), 361 }; 362 static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = { 363 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum), 364 }; 365 static const struct snd_kcontrol_new cml_to_lmixer_controls[] = { 366 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum), 367 }; 368 static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = { 369 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum), 370 }; 371 static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = { 372 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum), 373 }; 374 375 /* Right mixer pins */ 376 static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text); 377 static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text); 378 static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text); 379 static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text); 380 static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text); 381 static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text); 382 static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text); 383 384 static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = { 385 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum), 386 }; 387 static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = { 388 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum), 389 }; 390 static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = { 391 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum), 392 }; 393 static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = { 394 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum), 395 }; 396 static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = { 397 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum), 398 }; 399 static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = { 400 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum), 401 }; 402 static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = { 403 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum), 404 }; 405 406 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { 407 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0), 408 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0, 409 &hpl_output_mixer_controls[0], 410 ARRAY_SIZE(hpl_output_mixer_controls)), 411 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 412 413 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0, 414 &lol_output_mixer_controls[0], 415 ARRAY_SIZE(lol_output_mixer_controls)), 416 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0), 417 418 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0), 419 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0, 420 &hpr_output_mixer_controls[0], 421 ARRAY_SIZE(hpr_output_mixer_controls)), 422 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0), 423 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0, 424 &lor_output_mixer_controls[0], 425 ARRAY_SIZE(lor_output_mixer_controls)), 426 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0), 427 428 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0), 429 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 430 in1r_to_rmixer_controls), 431 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 432 in2r_to_rmixer_controls), 433 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 434 in3r_to_rmixer_controls), 435 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 436 in2l_to_rmixer_controls), 437 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 438 cmr_to_rmixer_controls), 439 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 440 in1l_to_rmixer_controls), 441 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 442 in3l_to_rmixer_controls), 443 444 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0), 445 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 446 in1l_to_lmixer_controls), 447 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 448 in2l_to_lmixer_controls), 449 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 450 in3l_to_lmixer_controls), 451 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 452 in1r_to_lmixer_controls), 453 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 454 cml_to_lmixer_controls), 455 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 456 in2r_to_lmixer_controls), 457 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 458 in3r_to_lmixer_controls), 459 460 SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event, 461 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 462 463 SND_SOC_DAPM_POST("ADC Reset", aic32x4_reset_adc), 464 465 SND_SOC_DAPM_OUTPUT("HPL"), 466 SND_SOC_DAPM_OUTPUT("HPR"), 467 SND_SOC_DAPM_OUTPUT("LOL"), 468 SND_SOC_DAPM_OUTPUT("LOR"), 469 SND_SOC_DAPM_INPUT("IN1_L"), 470 SND_SOC_DAPM_INPUT("IN1_R"), 471 SND_SOC_DAPM_INPUT("IN2_L"), 472 SND_SOC_DAPM_INPUT("IN2_R"), 473 SND_SOC_DAPM_INPUT("IN3_L"), 474 SND_SOC_DAPM_INPUT("IN3_R"), 475 SND_SOC_DAPM_INPUT("CM_L"), 476 SND_SOC_DAPM_INPUT("CM_R"), 477 }; 478 479 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { 480 /* Left Output */ 481 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"}, 482 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"}, 483 484 {"HPL Power", NULL, "HPL Output Mixer"}, 485 {"HPL", NULL, "HPL Power"}, 486 487 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"}, 488 489 {"LOL Power", NULL, "LOL Output Mixer"}, 490 {"LOL", NULL, "LOL Power"}, 491 492 /* Right Output */ 493 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"}, 494 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"}, 495 496 {"HPR Power", NULL, "HPR Output Mixer"}, 497 {"HPR", NULL, "HPR Power"}, 498 499 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"}, 500 501 {"LOR Power", NULL, "LOR Output Mixer"}, 502 {"LOR", NULL, "LOR Power"}, 503 504 /* Right Input */ 505 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"}, 506 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 507 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 508 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 509 510 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"}, 511 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"}, 512 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"}, 513 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"}, 514 515 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"}, 516 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"}, 517 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"}, 518 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"}, 519 520 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"}, 521 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 522 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 523 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 524 525 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"}, 526 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"}, 527 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"}, 528 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"}, 529 530 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"}, 531 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"}, 532 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"}, 533 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"}, 534 535 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"}, 536 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"}, 537 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"}, 538 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"}, 539 540 /* Left Input */ 541 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"}, 542 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"}, 543 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"}, 544 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"}, 545 546 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"}, 547 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 548 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 549 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 550 551 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"}, 552 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"}, 553 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"}, 554 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"}, 555 556 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"}, 557 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 558 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 559 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 560 561 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"}, 562 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"}, 563 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"}, 564 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"}, 565 566 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"}, 567 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"}, 568 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"}, 569 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"}, 570 571 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"}, 572 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"}, 573 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"}, 574 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"}, 575 }; 576 577 static const struct regmap_range_cfg aic32x4_regmap_pages[] = { 578 { 579 .selector_reg = 0, 580 .selector_mask = 0xff, 581 .window_start = 0, 582 .window_len = 128, 583 .range_min = 0, 584 .range_max = AIC32X4_REFPOWERUP, 585 }, 586 }; 587 588 const struct regmap_config aic32x4_regmap_config = { 589 .max_register = AIC32X4_REFPOWERUP, 590 .ranges = aic32x4_regmap_pages, 591 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages), 592 }; 593 EXPORT_SYMBOL(aic32x4_regmap_config); 594 595 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, 596 int clk_id, unsigned int freq, int dir) 597 { 598 struct snd_soc_component *component = codec_dai->component; 599 struct clk *mclk; 600 struct clk *pll; 601 602 pll = devm_clk_get(component->dev, "pll"); 603 if (IS_ERR(pll)) 604 return PTR_ERR(pll); 605 606 mclk = clk_get_parent(pll); 607 608 return clk_set_rate(mclk, freq); 609 } 610 611 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 612 { 613 struct snd_soc_component *component = codec_dai->component; 614 u8 iface_reg_1 = 0; 615 u8 iface_reg_2 = 0; 616 u8 iface_reg_3 = 0; 617 618 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 619 case SND_SOC_DAIFMT_CBP_CFP: 620 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 621 break; 622 case SND_SOC_DAIFMT_CBC_CFC: 623 break; 624 default: 625 printk(KERN_ERR "aic32x4: invalid clock provider\n"); 626 return -EINVAL; 627 } 628 629 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 630 case SND_SOC_DAIFMT_I2S: 631 break; 632 case SND_SOC_DAIFMT_DSP_A: 633 iface_reg_1 |= (AIC32X4_DSP_MODE << 634 AIC32X4_IFACE1_DATATYPE_SHIFT); 635 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 636 iface_reg_2 = 0x01; /* add offset 1 */ 637 break; 638 case SND_SOC_DAIFMT_DSP_B: 639 iface_reg_1 |= (AIC32X4_DSP_MODE << 640 AIC32X4_IFACE1_DATATYPE_SHIFT); 641 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 642 break; 643 case SND_SOC_DAIFMT_RIGHT_J: 644 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE << 645 AIC32X4_IFACE1_DATATYPE_SHIFT); 646 break; 647 case SND_SOC_DAIFMT_LEFT_J: 648 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE << 649 AIC32X4_IFACE1_DATATYPE_SHIFT); 650 break; 651 default: 652 printk(KERN_ERR "aic32x4: invalid DAI interface format\n"); 653 return -EINVAL; 654 } 655 656 snd_soc_component_update_bits(component, AIC32X4_IFACE1, 657 AIC32X4_IFACE1_DATATYPE_MASK | 658 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1); 659 snd_soc_component_update_bits(component, AIC32X4_IFACE2, 660 AIC32X4_DATA_OFFSET_MASK, iface_reg_2); 661 snd_soc_component_update_bits(component, AIC32X4_IFACE3, 662 AIC32X4_BCLKINV_MASK, iface_reg_3); 663 664 return 0; 665 } 666 667 static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr) 668 { 669 return snd_soc_component_write(component, AIC32X4_AOSR, aosr); 670 } 671 672 static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr) 673 { 674 snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8); 675 snd_soc_component_write(component, AIC32X4_DOSRLSB, 676 (dosr & 0xff)); 677 678 return 0; 679 } 680 681 static int aic32x4_set_processing_blocks(struct snd_soc_component *component, 682 u8 r_block, u8 p_block) 683 { 684 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 685 686 if (aic32x4->type == AIC32X4_TYPE_TAS2505) { 687 if (r_block || p_block > 3) 688 return -EINVAL; 689 690 snd_soc_component_write(component, AIC32X4_DACSPB, p_block); 691 } else { /* AIC32x4 */ 692 if (r_block > 18 || p_block > 25) 693 return -EINVAL; 694 695 snd_soc_component_write(component, AIC32X4_ADCSPB, r_block); 696 snd_soc_component_write(component, AIC32X4_DACSPB, p_block); 697 } 698 699 return 0; 700 } 701 702 static int aic32x4_setup_clocks(struct snd_soc_component *component, 703 unsigned int sample_rate, unsigned int channels, 704 unsigned int bit_depth) 705 { 706 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 707 u8 aosr; 708 u16 dosr; 709 u8 adc_resource_class, dac_resource_class; 710 u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac; 711 u8 dosr_increment; 712 u16 max_dosr, min_dosr; 713 unsigned long adc_clock_rate, dac_clock_rate; 714 int ret; 715 716 static struct clk_bulk_data clocks[] = { 717 { .id = "pll" }, 718 { .id = "nadc" }, 719 { .id = "madc" }, 720 { .id = "ndac" }, 721 { .id = "mdac" }, 722 { .id = "bdiv" }, 723 }; 724 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 725 if (ret) 726 return ret; 727 728 if (sample_rate <= 48000) { 729 aosr = 128; 730 adc_resource_class = 6; 731 dac_resource_class = 8; 732 dosr_increment = 8; 733 if (aic32x4->type == AIC32X4_TYPE_TAS2505) 734 aic32x4_set_processing_blocks(component, 0, 1); 735 else 736 aic32x4_set_processing_blocks(component, 1, 1); 737 } else if (sample_rate <= 96000) { 738 aosr = 64; 739 adc_resource_class = 6; 740 dac_resource_class = 8; 741 dosr_increment = 4; 742 if (aic32x4->type == AIC32X4_TYPE_TAS2505) 743 aic32x4_set_processing_blocks(component, 0, 1); 744 else 745 aic32x4_set_processing_blocks(component, 1, 9); 746 } else if (sample_rate == 192000) { 747 aosr = 32; 748 adc_resource_class = 3; 749 dac_resource_class = 4; 750 dosr_increment = 2; 751 if (aic32x4->type == AIC32X4_TYPE_TAS2505) 752 aic32x4_set_processing_blocks(component, 0, 1); 753 else 754 aic32x4_set_processing_blocks(component, 13, 19); 755 } else { 756 dev_err(component->dev, "Sampling rate not supported\n"); 757 return -EINVAL; 758 } 759 760 madc = DIV_ROUND_UP((32 * adc_resource_class), aosr); 761 max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) * 762 dosr_increment; 763 min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) * 764 dosr_increment; 765 max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate); 766 767 for (nadc = max_nadc; nadc > 0; --nadc) { 768 adc_clock_rate = nadc * madc * aosr * sample_rate; 769 for (dosr = max_dosr; dosr >= min_dosr; 770 dosr -= dosr_increment) { 771 min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr); 772 max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ / 773 (min_mdac * dosr * sample_rate); 774 for (mdac = min_mdac; mdac <= 128; ++mdac) { 775 for (ndac = max_ndac; ndac > 0; --ndac) { 776 dac_clock_rate = ndac * mdac * dosr * 777 sample_rate; 778 if (dac_clock_rate == adc_clock_rate) { 779 if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0) 780 continue; 781 782 clk_set_rate(clocks[0].clk, 783 dac_clock_rate); 784 785 clk_set_rate(clocks[1].clk, 786 sample_rate * aosr * 787 madc); 788 clk_set_rate(clocks[2].clk, 789 sample_rate * aosr); 790 aic32x4_set_aosr(component, 791 aosr); 792 793 clk_set_rate(clocks[3].clk, 794 sample_rate * dosr * 795 mdac); 796 clk_set_rate(clocks[4].clk, 797 sample_rate * dosr); 798 aic32x4_set_dosr(component, 799 dosr); 800 801 clk_set_rate(clocks[5].clk, 802 sample_rate * channels * 803 bit_depth); 804 805 return 0; 806 } 807 } 808 } 809 } 810 } 811 812 dev_err(component->dev, 813 "Could not set clocks to support sample rate.\n"); 814 return -EINVAL; 815 } 816 817 static int aic32x4_hw_params(struct snd_pcm_substream *substream, 818 struct snd_pcm_hw_params *params, 819 struct snd_soc_dai *dai) 820 { 821 struct snd_soc_component *component = dai->component; 822 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 823 u8 iface1_reg = 0; 824 u8 dacsetup_reg = 0; 825 826 aic32x4_setup_clocks(component, params_rate(params), 827 params_channels(params), 828 params_physical_width(params)); 829 830 switch (params_physical_width(params)) { 831 case 16: 832 iface1_reg |= (AIC32X4_WORD_LEN_16BITS << 833 AIC32X4_IFACE1_DATALEN_SHIFT); 834 break; 835 case 20: 836 iface1_reg |= (AIC32X4_WORD_LEN_20BITS << 837 AIC32X4_IFACE1_DATALEN_SHIFT); 838 break; 839 case 24: 840 iface1_reg |= (AIC32X4_WORD_LEN_24BITS << 841 AIC32X4_IFACE1_DATALEN_SHIFT); 842 break; 843 case 32: 844 iface1_reg |= (AIC32X4_WORD_LEN_32BITS << 845 AIC32X4_IFACE1_DATALEN_SHIFT); 846 break; 847 } 848 snd_soc_component_update_bits(component, AIC32X4_IFACE1, 849 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg); 850 851 if (params_channels(params) == 1) { 852 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN; 853 } else { 854 if (aic32x4->swapdacs) 855 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN; 856 else 857 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN; 858 } 859 snd_soc_component_update_bits(component, AIC32X4_DACSETUP, 860 AIC32X4_DAC_CHAN_MASK, dacsetup_reg); 861 862 return 0; 863 } 864 865 static int aic32x4_mute(struct snd_soc_dai *dai, int mute, int direction) 866 { 867 struct snd_soc_component *component = dai->component; 868 869 snd_soc_component_update_bits(component, AIC32X4_DACMUTE, 870 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0); 871 872 return 0; 873 } 874 875 static int aic32x4_set_bias_level(struct snd_soc_component *component, 876 enum snd_soc_bias_level level) 877 { 878 int ret; 879 880 static struct clk_bulk_data clocks[] = { 881 { .id = "madc" }, 882 { .id = "mdac" }, 883 { .id = "bdiv" }, 884 }; 885 886 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 887 if (ret) 888 return ret; 889 890 switch (level) { 891 case SND_SOC_BIAS_ON: 892 ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks); 893 if (ret) { 894 dev_err(component->dev, "Failed to enable clocks\n"); 895 return ret; 896 } 897 break; 898 case SND_SOC_BIAS_PREPARE: 899 break; 900 case SND_SOC_BIAS_STANDBY: 901 /* Initial cold start */ 902 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 903 break; 904 905 clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); 906 break; 907 case SND_SOC_BIAS_OFF: 908 break; 909 } 910 return 0; 911 } 912 913 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000 914 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 915 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE \ 916 | SNDRV_PCM_FMTBIT_S32_LE) 917 918 static const struct snd_soc_dai_ops aic32x4_ops = { 919 .hw_params = aic32x4_hw_params, 920 .mute_stream = aic32x4_mute, 921 .set_fmt = aic32x4_set_dai_fmt, 922 .set_sysclk = aic32x4_set_dai_sysclk, 923 .no_capture_mute = 1, 924 }; 925 926 static struct snd_soc_dai_driver aic32x4_dai = { 927 .name = "tlv320aic32x4-hifi", 928 .playback = { 929 .stream_name = "Playback", 930 .channels_min = 1, 931 .channels_max = 2, 932 .rates = AIC32X4_RATES, 933 .formats = AIC32X4_FORMATS,}, 934 .capture = { 935 .stream_name = "Capture", 936 .channels_min = 1, 937 .channels_max = 8, 938 .rates = AIC32X4_RATES, 939 .formats = AIC32X4_FORMATS,}, 940 .ops = &aic32x4_ops, 941 .symmetric_rate = 1, 942 }; 943 944 static void aic32x4_setup_gpios(struct snd_soc_component *component) 945 { 946 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 947 948 /* setup GPIO functions */ 949 /* MFP1 */ 950 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) { 951 snd_soc_component_write(component, AIC32X4_DINCTL, 952 aic32x4->setup->gpio_func[0]); 953 snd_soc_add_component_controls(component, aic32x4_mfp1, 954 ARRAY_SIZE(aic32x4_mfp1)); 955 } 956 957 /* MFP2 */ 958 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) { 959 snd_soc_component_write(component, AIC32X4_DOUTCTL, 960 aic32x4->setup->gpio_func[1]); 961 snd_soc_add_component_controls(component, aic32x4_mfp2, 962 ARRAY_SIZE(aic32x4_mfp2)); 963 } 964 965 /* MFP3 */ 966 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) { 967 snd_soc_component_write(component, AIC32X4_SCLKCTL, 968 aic32x4->setup->gpio_func[2]); 969 snd_soc_add_component_controls(component, aic32x4_mfp3, 970 ARRAY_SIZE(aic32x4_mfp3)); 971 } 972 973 /* MFP4 */ 974 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) { 975 snd_soc_component_write(component, AIC32X4_MISOCTL, 976 aic32x4->setup->gpio_func[3]); 977 snd_soc_add_component_controls(component, aic32x4_mfp4, 978 ARRAY_SIZE(aic32x4_mfp4)); 979 } 980 981 /* MFP5 */ 982 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) { 983 snd_soc_component_write(component, AIC32X4_GPIOCTL, 984 aic32x4->setup->gpio_func[4]); 985 snd_soc_add_component_controls(component, aic32x4_mfp5, 986 ARRAY_SIZE(aic32x4_mfp5)); 987 } 988 } 989 990 static int aic32x4_component_probe(struct snd_soc_component *component) 991 { 992 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 993 u32 tmp_reg; 994 int ret; 995 996 static struct clk_bulk_data clocks[] = { 997 { .id = "codec_clkin" }, 998 { .id = "pll" }, 999 { .id = "bdiv" }, 1000 { .id = "mdac" }, 1001 }; 1002 1003 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 1004 if (ret) 1005 return ret; 1006 1007 if (aic32x4->setup) 1008 aic32x4_setup_gpios(component); 1009 1010 clk_set_parent(clocks[0].clk, clocks[1].clk); 1011 clk_set_parent(clocks[2].clk, clocks[3].clk); 1012 1013 /* Power platform configuration */ 1014 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { 1015 snd_soc_component_write(component, AIC32X4_MICBIAS, 1016 AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V); 1017 } 1018 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) 1019 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 1020 1021 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ? 1022 AIC32X4_LDOCTLEN : 0; 1023 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg); 1024 1025 tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE); 1026 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) 1027 tmp_reg |= AIC32X4_LDOIN_18_36; 1028 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) 1029 tmp_reg |= AIC32X4_LDOIN2HP; 1030 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg); 1031 1032 /* Mic PGA routing */ 1033 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) 1034 snd_soc_component_write(component, AIC32X4_LMICPGANIN, 1035 AIC32X4_LMICPGANIN_IN2R_10K); 1036 else 1037 snd_soc_component_write(component, AIC32X4_LMICPGANIN, 1038 AIC32X4_LMICPGANIN_CM1L_10K); 1039 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) 1040 snd_soc_component_write(component, AIC32X4_RMICPGANIN, 1041 AIC32X4_RMICPGANIN_IN1L_10K); 1042 else 1043 snd_soc_component_write(component, AIC32X4_RMICPGANIN, 1044 AIC32X4_RMICPGANIN_CM1R_10K); 1045 1046 /* 1047 * Workaround: for an unknown reason, the ADC needs to be powered up 1048 * and down for the first capture to work properly. It seems related to 1049 * a HW BUG or some kind of behavior not documented in the datasheet. 1050 */ 1051 tmp_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP); 1052 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg | 1053 AIC32X4_LADC_EN | AIC32X4_RADC_EN); 1054 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg); 1055 1056 /* 1057 * Enable the fast charging feature and ensure the needed 40ms ellapsed 1058 * before using the analog circuits. 1059 */ 1060 snd_soc_component_write(component, AIC32X4_REFPOWERUP, 1061 AIC32X4_REFPOWERUP_40MS); 1062 msleep(40); 1063 1064 return 0; 1065 } 1066 1067 static const struct snd_soc_component_driver soc_component_dev_aic32x4 = { 1068 .probe = aic32x4_component_probe, 1069 .set_bias_level = aic32x4_set_bias_level, 1070 .controls = aic32x4_snd_controls, 1071 .num_controls = ARRAY_SIZE(aic32x4_snd_controls), 1072 .dapm_widgets = aic32x4_dapm_widgets, 1073 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets), 1074 .dapm_routes = aic32x4_dapm_routes, 1075 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes), 1076 .suspend_bias_off = 1, 1077 .idle_bias_on = 1, 1078 .use_pmdown_time = 1, 1079 .endianness = 1, 1080 }; 1081 1082 static const struct snd_kcontrol_new aic32x4_tas2505_snd_controls[] = { 1083 SOC_SINGLE_S8_TLV("PCM Playback Volume", 1084 AIC32X4_LDACVOL, -0x7f, 0x30, tlv_pcm), 1085 SOC_ENUM("DAC Playback PowerTune Switch", l_ptm_enum), 1086 1087 SOC_SINGLE_TLV("HP Driver Gain Volume", 1088 AIC32X4_HPLGAIN, 0, 0x74, 1, tlv_tas_driver_gain), 1089 SOC_SINGLE("HP DAC Playback Switch", AIC32X4_HPLGAIN, 6, 1, 1), 1090 1091 SOC_SINGLE_TLV("Speaker Driver Playback Volume", 1092 TAS2505_SPKVOL1, 0, 0x74, 1, tlv_tas_driver_gain), 1093 SOC_SINGLE_TLV("Speaker Amplifier Playback Volume", 1094 TAS2505_SPKVOL2, 4, 5, 0, tlv_amp_vol), 1095 1096 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 1097 }; 1098 1099 static const struct snd_kcontrol_new hp_output_mixer_controls[] = { 1100 SOC_DAPM_SINGLE("DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 1101 }; 1102 1103 static const struct snd_soc_dapm_widget aic32x4_tas2505_dapm_widgets[] = { 1104 SND_SOC_DAPM_DAC("DAC", "Playback", AIC32X4_DACSETUP, 7, 0), 1105 SND_SOC_DAPM_MIXER("HP Output Mixer", SND_SOC_NOPM, 0, 0, 1106 &hp_output_mixer_controls[0], 1107 ARRAY_SIZE(hp_output_mixer_controls)), 1108 SND_SOC_DAPM_PGA("HP Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 1109 1110 SND_SOC_DAPM_PGA("Speaker Driver", TAS2505_SPK, 1, 0, NULL, 0), 1111 1112 SND_SOC_DAPM_OUTPUT("HP"), 1113 SND_SOC_DAPM_OUTPUT("Speaker"), 1114 }; 1115 1116 static const struct snd_soc_dapm_route aic32x4_tas2505_dapm_routes[] = { 1117 /* Left Output */ 1118 {"HP Output Mixer", "DAC Switch", "DAC"}, 1119 1120 {"HP Power", NULL, "HP Output Mixer"}, 1121 {"HP", NULL, "HP Power"}, 1122 1123 {"Speaker Driver", NULL, "DAC"}, 1124 {"Speaker", NULL, "Speaker Driver"}, 1125 }; 1126 1127 static struct snd_soc_dai_driver aic32x4_tas2505_dai = { 1128 .name = "tas2505-hifi", 1129 .playback = { 1130 .stream_name = "Playback", 1131 .channels_min = 1, 1132 .channels_max = 2, 1133 .rates = SNDRV_PCM_RATE_8000_96000, 1134 .formats = AIC32X4_FORMATS,}, 1135 .ops = &aic32x4_ops, 1136 .symmetric_rate = 1, 1137 }; 1138 1139 static int aic32x4_tas2505_component_probe(struct snd_soc_component *component) 1140 { 1141 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 1142 u32 tmp_reg; 1143 int ret; 1144 1145 static struct clk_bulk_data clocks[] = { 1146 { .id = "codec_clkin" }, 1147 { .id = "pll" }, 1148 { .id = "bdiv" }, 1149 { .id = "mdac" }, 1150 }; 1151 1152 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 1153 if (ret) 1154 return ret; 1155 1156 if (aic32x4->setup) 1157 aic32x4_setup_gpios(component); 1158 1159 clk_set_parent(clocks[0].clk, clocks[1].clk); 1160 clk_set_parent(clocks[2].clk, clocks[3].clk); 1161 1162 /* Power platform configuration */ 1163 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) 1164 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 1165 1166 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ? 1167 AIC32X4_LDOCTLEN : 0; 1168 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg); 1169 1170 tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE); 1171 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) 1172 tmp_reg |= AIC32X4_LDOIN_18_36; 1173 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) 1174 tmp_reg |= AIC32X4_LDOIN2HP; 1175 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg); 1176 1177 /* 1178 * Enable the fast charging feature and ensure the needed 40ms ellapsed 1179 * before using the analog circuits. 1180 */ 1181 snd_soc_component_write(component, TAS2505_REFPOWERUP, 1182 AIC32X4_REFPOWERUP_40MS); 1183 msleep(40); 1184 1185 return 0; 1186 } 1187 1188 static const struct snd_soc_component_driver soc_component_dev_aic32x4_tas2505 = { 1189 .probe = aic32x4_tas2505_component_probe, 1190 .set_bias_level = aic32x4_set_bias_level, 1191 .controls = aic32x4_tas2505_snd_controls, 1192 .num_controls = ARRAY_SIZE(aic32x4_tas2505_snd_controls), 1193 .dapm_widgets = aic32x4_tas2505_dapm_widgets, 1194 .num_dapm_widgets = ARRAY_SIZE(aic32x4_tas2505_dapm_widgets), 1195 .dapm_routes = aic32x4_tas2505_dapm_routes, 1196 .num_dapm_routes = ARRAY_SIZE(aic32x4_tas2505_dapm_routes), 1197 .suspend_bias_off = 1, 1198 .idle_bias_on = 1, 1199 .use_pmdown_time = 1, 1200 .endianness = 1, 1201 }; 1202 1203 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4, 1204 struct device_node *np) 1205 { 1206 struct aic32x4_setup_data *aic32x4_setup; 1207 int ret; 1208 1209 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup), 1210 GFP_KERNEL); 1211 if (!aic32x4_setup) 1212 return -ENOMEM; 1213 1214 ret = of_property_match_string(np, "clock-names", "mclk"); 1215 if (ret < 0) 1216 return -EINVAL; 1217 aic32x4->mclk_name = of_clk_get_parent_name(np, ret); 1218 1219 aic32x4->swapdacs = false; 1220 aic32x4->micpga_routing = 0; 1221 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0); 1222 1223 if (of_property_read_u32_array(np, "aic32x4-gpio-func", 1224 aic32x4_setup->gpio_func, 5) >= 0) 1225 aic32x4->setup = aic32x4_setup; 1226 return 0; 1227 } 1228 1229 static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4) 1230 { 1231 regulator_disable(aic32x4->supply_iov); 1232 1233 if (!IS_ERR(aic32x4->supply_ldo)) 1234 regulator_disable(aic32x4->supply_ldo); 1235 1236 if (!IS_ERR(aic32x4->supply_dv)) 1237 regulator_disable(aic32x4->supply_dv); 1238 1239 if (!IS_ERR(aic32x4->supply_av)) 1240 regulator_disable(aic32x4->supply_av); 1241 } 1242 1243 static int aic32x4_setup_regulators(struct device *dev, 1244 struct aic32x4_priv *aic32x4) 1245 { 1246 int ret = 0; 1247 1248 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin"); 1249 aic32x4->supply_iov = devm_regulator_get(dev, "iov"); 1250 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv"); 1251 aic32x4->supply_av = devm_regulator_get_optional(dev, "av"); 1252 1253 /* Check if the regulator requirements are fulfilled */ 1254 1255 if (IS_ERR(aic32x4->supply_iov)) { 1256 dev_err(dev, "Missing supply 'iov'\n"); 1257 return PTR_ERR(aic32x4->supply_iov); 1258 } 1259 1260 if (IS_ERR(aic32x4->supply_ldo)) { 1261 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER) 1262 return -EPROBE_DEFER; 1263 1264 if (IS_ERR(aic32x4->supply_dv)) { 1265 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n"); 1266 return PTR_ERR(aic32x4->supply_dv); 1267 } 1268 if (IS_ERR(aic32x4->supply_av)) { 1269 dev_err(dev, "Missing supply 'av' or 'ldoin'\n"); 1270 return PTR_ERR(aic32x4->supply_av); 1271 } 1272 } else { 1273 if (PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER) 1274 return -EPROBE_DEFER; 1275 if (PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER) 1276 return -EPROBE_DEFER; 1277 } 1278 1279 ret = regulator_enable(aic32x4->supply_iov); 1280 if (ret) { 1281 dev_err(dev, "Failed to enable regulator iov\n"); 1282 return ret; 1283 } 1284 1285 if (!IS_ERR(aic32x4->supply_ldo)) { 1286 ret = regulator_enable(aic32x4->supply_ldo); 1287 if (ret) { 1288 dev_err(dev, "Failed to enable regulator ldo\n"); 1289 goto error_ldo; 1290 } 1291 } 1292 1293 if (!IS_ERR(aic32x4->supply_dv)) { 1294 ret = regulator_enable(aic32x4->supply_dv); 1295 if (ret) { 1296 dev_err(dev, "Failed to enable regulator dv\n"); 1297 goto error_dv; 1298 } 1299 } 1300 1301 if (!IS_ERR(aic32x4->supply_av)) { 1302 ret = regulator_enable(aic32x4->supply_av); 1303 if (ret) { 1304 dev_err(dev, "Failed to enable regulator av\n"); 1305 goto error_av; 1306 } 1307 } 1308 1309 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av)) 1310 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE; 1311 1312 return 0; 1313 1314 error_av: 1315 if (!IS_ERR(aic32x4->supply_dv)) 1316 regulator_disable(aic32x4->supply_dv); 1317 1318 error_dv: 1319 if (!IS_ERR(aic32x4->supply_ldo)) 1320 regulator_disable(aic32x4->supply_ldo); 1321 1322 error_ldo: 1323 regulator_disable(aic32x4->supply_iov); 1324 return ret; 1325 } 1326 1327 int aic32x4_probe(struct device *dev, struct regmap *regmap) 1328 { 1329 struct aic32x4_priv *aic32x4; 1330 struct aic32x4_pdata *pdata = dev->platform_data; 1331 struct device_node *np = dev->of_node; 1332 int ret; 1333 1334 if (IS_ERR(regmap)) 1335 return PTR_ERR(regmap); 1336 1337 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv), 1338 GFP_KERNEL); 1339 if (aic32x4 == NULL) 1340 return -ENOMEM; 1341 1342 aic32x4->dev = dev; 1343 aic32x4->type = (enum aic32x4_type)dev_get_drvdata(dev); 1344 1345 dev_set_drvdata(dev, aic32x4); 1346 1347 if (pdata) { 1348 aic32x4->power_cfg = pdata->power_cfg; 1349 aic32x4->swapdacs = pdata->swapdacs; 1350 aic32x4->micpga_routing = pdata->micpga_routing; 1351 aic32x4->rstn_gpio = pdata->rstn_gpio; 1352 aic32x4->mclk_name = "mclk"; 1353 } else if (np) { 1354 ret = aic32x4_parse_dt(aic32x4, np); 1355 if (ret) { 1356 dev_err(dev, "Failed to parse DT node\n"); 1357 return ret; 1358 } 1359 } else { 1360 aic32x4->power_cfg = 0; 1361 aic32x4->swapdacs = false; 1362 aic32x4->micpga_routing = 0; 1363 aic32x4->rstn_gpio = -1; 1364 aic32x4->mclk_name = "mclk"; 1365 } 1366 1367 if (gpio_is_valid(aic32x4->rstn_gpio)) { 1368 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio, 1369 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); 1370 if (ret != 0) 1371 return ret; 1372 } 1373 1374 ret = aic32x4_setup_regulators(dev, aic32x4); 1375 if (ret) { 1376 dev_err(dev, "Failed to setup regulators\n"); 1377 return ret; 1378 } 1379 1380 if (gpio_is_valid(aic32x4->rstn_gpio)) { 1381 ndelay(10); 1382 gpio_set_value_cansleep(aic32x4->rstn_gpio, 1); 1383 mdelay(1); 1384 } 1385 1386 ret = regmap_write(regmap, AIC32X4_RESET, 0x01); 1387 if (ret) 1388 goto err_disable_regulators; 1389 1390 ret = aic32x4_register_clocks(dev, aic32x4->mclk_name); 1391 if (ret) 1392 goto err_disable_regulators; 1393 1394 switch (aic32x4->type) { 1395 case AIC32X4_TYPE_TAS2505: 1396 ret = devm_snd_soc_register_component(dev, 1397 &soc_component_dev_aic32x4_tas2505, &aic32x4_tas2505_dai, 1); 1398 break; 1399 default: 1400 ret = devm_snd_soc_register_component(dev, 1401 &soc_component_dev_aic32x4, &aic32x4_dai, 1); 1402 } 1403 1404 if (ret) { 1405 dev_err(dev, "Failed to register component\n"); 1406 goto err_disable_regulators; 1407 } 1408 1409 return 0; 1410 1411 err_disable_regulators: 1412 aic32x4_disable_regulators(aic32x4); 1413 1414 return ret; 1415 } 1416 EXPORT_SYMBOL(aic32x4_probe); 1417 1418 void aic32x4_remove(struct device *dev) 1419 { 1420 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev); 1421 1422 aic32x4_disable_regulators(aic32x4); 1423 } 1424 EXPORT_SYMBOL(aic32x4_remove); 1425 1426 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver"); 1427 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>"); 1428 MODULE_LICENSE("GPL"); 1429