1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/ptp_classify.h> 10 #include <soc/mscc/ocelot_vcap.h> 11 #include "ocelot.h" 12 #include "ocelot_vcap.h" 13 14 #define TABLE_UPDATE_SLEEP_US 10 15 #define TABLE_UPDATE_TIMEOUT_US 100000 16 17 struct ocelot_mact_entry { 18 u8 mac[ETH_ALEN]; 19 u16 vid; 20 enum macaccess_entry_type type; 21 }; 22 23 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 24 { 25 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 26 } 27 28 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 29 { 30 u32 val; 31 32 return readx_poll_timeout(ocelot_mact_read_macaccess, 33 ocelot, val, 34 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 35 MACACCESS_CMD_IDLE, 36 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 37 } 38 39 static void ocelot_mact_select(struct ocelot *ocelot, 40 const unsigned char mac[ETH_ALEN], 41 unsigned int vid) 42 { 43 u32 macl = 0, mach = 0; 44 45 /* Set the MAC address to handle and the vlan associated in a format 46 * understood by the hardware. 47 */ 48 mach |= vid << 16; 49 mach |= mac[0] << 8; 50 mach |= mac[1] << 0; 51 macl |= mac[2] << 24; 52 macl |= mac[3] << 16; 53 macl |= mac[4] << 8; 54 macl |= mac[5] << 0; 55 56 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 57 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 58 59 } 60 61 int ocelot_mact_learn(struct ocelot *ocelot, int port, 62 const unsigned char mac[ETH_ALEN], 63 unsigned int vid, enum macaccess_entry_type type) 64 { 65 u32 cmd = ANA_TABLES_MACACCESS_VALID | 66 ANA_TABLES_MACACCESS_DEST_IDX(port) | 67 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 68 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 69 unsigned int mc_ports; 70 71 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 72 if (type == ENTRYTYPE_MACv4) 73 mc_ports = (mac[1] << 8) | mac[2]; 74 else if (type == ENTRYTYPE_MACv6) 75 mc_ports = (mac[0] << 8) | mac[1]; 76 else 77 mc_ports = 0; 78 79 if (mc_ports & BIT(ocelot->num_phys_ports)) 80 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 81 82 ocelot_mact_select(ocelot, mac, vid); 83 84 /* Issue a write command */ 85 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 86 87 return ocelot_mact_wait_for_completion(ocelot); 88 } 89 EXPORT_SYMBOL(ocelot_mact_learn); 90 91 int ocelot_mact_forget(struct ocelot *ocelot, 92 const unsigned char mac[ETH_ALEN], unsigned int vid) 93 { 94 ocelot_mact_select(ocelot, mac, vid); 95 96 /* Issue a forget command */ 97 ocelot_write(ocelot, 98 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 99 ANA_TABLES_MACACCESS); 100 101 return ocelot_mact_wait_for_completion(ocelot); 102 } 103 EXPORT_SYMBOL(ocelot_mact_forget); 104 105 static void ocelot_mact_init(struct ocelot *ocelot) 106 { 107 /* Configure the learning mode entries attributes: 108 * - Do not copy the frame to the CPU extraction queues. 109 * - Use the vlan and mac_cpoy for dmac lookup. 110 */ 111 ocelot_rmw(ocelot, 0, 112 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 113 | ANA_AGENCTRL_LEARN_FWD_KILL 114 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 115 ANA_AGENCTRL); 116 117 /* Clear the MAC table */ 118 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 119 } 120 121 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 122 { 123 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 124 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 125 ANA_PORT_VCAP_S2_CFG, port); 126 127 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 128 ANA_PORT_VCAP_CFG, port); 129 130 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 131 REW_PORT_CFG_ES0_EN, 132 REW_PORT_CFG, port); 133 } 134 135 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 136 { 137 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 138 } 139 140 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 141 { 142 u32 val; 143 144 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 145 ocelot, 146 val, 147 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 148 ANA_TABLES_VLANACCESS_CMD_IDLE, 149 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 150 } 151 152 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 153 { 154 /* Select the VID to configure */ 155 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 156 ANA_TABLES_VLANTIDX); 157 /* Set the vlan port members mask and issue a write command */ 158 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 159 ANA_TABLES_VLANACCESS_CMD_WRITE, 160 ANA_TABLES_VLANACCESS); 161 162 return ocelot_vlant_wait_for_completion(ocelot); 163 } 164 165 static void ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 166 struct ocelot_vlan native_vlan) 167 { 168 struct ocelot_port *ocelot_port = ocelot->ports[port]; 169 u32 val = 0; 170 171 ocelot_port->native_vlan = native_vlan; 172 173 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(native_vlan.vid), 174 REW_PORT_VLAN_CFG_PORT_VID_M, 175 REW_PORT_VLAN_CFG, port); 176 177 if (ocelot_port->vlan_aware) { 178 if (native_vlan.valid) 179 /* Tag all frames except when VID == DEFAULT_VLAN */ 180 val = REW_TAG_CFG_TAG_CFG(1); 181 else 182 /* Tag all frames */ 183 val = REW_TAG_CFG_TAG_CFG(3); 184 } else { 185 /* Port tagging disabled. */ 186 val = REW_TAG_CFG_TAG_CFG(0); 187 } 188 ocelot_rmw_gix(ocelot, val, 189 REW_TAG_CFG_TAG_CFG_M, 190 REW_TAG_CFG, port); 191 } 192 193 /* Default vlan to clasify for untagged frames (may be zero) */ 194 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 195 struct ocelot_vlan pvid_vlan) 196 { 197 struct ocelot_port *ocelot_port = ocelot->ports[port]; 198 u32 val = 0; 199 200 ocelot_port->pvid_vlan = pvid_vlan; 201 202 if (!ocelot_port->vlan_aware) 203 pvid_vlan.vid = 0; 204 205 ocelot_rmw_gix(ocelot, 206 ANA_PORT_VLAN_CFG_VLAN_VID(pvid_vlan.vid), 207 ANA_PORT_VLAN_CFG_VLAN_VID_M, 208 ANA_PORT_VLAN_CFG, port); 209 210 /* If there's no pvid, we should drop not only untagged traffic (which 211 * happens automatically), but also 802.1p traffic which gets 212 * classified to VLAN 0, but that is always in our RX filter, so it 213 * would get accepted were it not for this setting. 214 */ 215 if (!pvid_vlan.valid && ocelot_port->vlan_aware) 216 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 217 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 218 219 ocelot_rmw_gix(ocelot, val, 220 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 221 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 222 ANA_PORT_DROP_CFG, port); 223 } 224 225 static int ocelot_vlan_member_set(struct ocelot *ocelot, u32 vlan_mask, u16 vid) 226 { 227 int err; 228 229 err = ocelot_vlant_set_mask(ocelot, vid, vlan_mask); 230 if (err) 231 return err; 232 233 ocelot->vlan_mask[vid] = vlan_mask; 234 235 return 0; 236 } 237 238 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid) 239 { 240 return ocelot_vlan_member_set(ocelot, 241 ocelot->vlan_mask[vid] | BIT(port), 242 vid); 243 } 244 245 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid) 246 { 247 return ocelot_vlan_member_set(ocelot, 248 ocelot->vlan_mask[vid] & ~BIT(port), 249 vid); 250 } 251 252 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 253 bool vlan_aware, struct netlink_ext_ack *extack) 254 { 255 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 256 struct ocelot_port *ocelot_port = ocelot->ports[port]; 257 struct ocelot_vcap_filter *filter; 258 u32 val; 259 260 list_for_each_entry(filter, &block->rules, list) { 261 if (filter->ingress_port_mask & BIT(port) && 262 filter->action.vid_replace_ena) { 263 NL_SET_ERR_MSG_MOD(extack, 264 "Cannot change VLAN state with vlan modify rules active"); 265 return -EBUSY; 266 } 267 } 268 269 ocelot_port->vlan_aware = vlan_aware; 270 271 if (vlan_aware) 272 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 273 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 274 else 275 val = 0; 276 ocelot_rmw_gix(ocelot, val, 277 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 278 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 279 ANA_PORT_VLAN_CFG, port); 280 281 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 282 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->native_vlan); 283 284 return 0; 285 } 286 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 287 288 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 289 bool untagged, struct netlink_ext_ack *extack) 290 { 291 struct ocelot_port *ocelot_port = ocelot->ports[port]; 292 293 /* Deny changing the native VLAN, but always permit deleting it */ 294 if (untagged && ocelot_port->native_vlan.vid != vid && 295 ocelot_port->native_vlan.valid) { 296 NL_SET_ERR_MSG_MOD(extack, 297 "Port already has a native VLAN"); 298 return -EBUSY; 299 } 300 301 return 0; 302 } 303 EXPORT_SYMBOL(ocelot_vlan_prepare); 304 305 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 306 bool untagged) 307 { 308 int err; 309 310 err = ocelot_vlan_member_add(ocelot, port, vid); 311 if (err) 312 return err; 313 314 /* Default ingress vlan classification */ 315 if (pvid) { 316 struct ocelot_vlan pvid_vlan; 317 318 pvid_vlan.vid = vid; 319 pvid_vlan.valid = true; 320 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 321 } 322 323 /* Untagged egress vlan clasification */ 324 if (untagged) { 325 struct ocelot_vlan native_vlan; 326 327 native_vlan.vid = vid; 328 native_vlan.valid = true; 329 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 330 } 331 332 return 0; 333 } 334 EXPORT_SYMBOL(ocelot_vlan_add); 335 336 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 337 { 338 struct ocelot_port *ocelot_port = ocelot->ports[port]; 339 int err; 340 341 err = ocelot_vlan_member_del(ocelot, port, vid); 342 if (err) 343 return err; 344 345 /* Ingress */ 346 if (ocelot_port->pvid_vlan.vid == vid) { 347 struct ocelot_vlan pvid_vlan = {0}; 348 349 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 350 } 351 352 /* Egress */ 353 if (ocelot_port->native_vlan.vid == vid) { 354 struct ocelot_vlan native_vlan = {0}; 355 356 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 357 } 358 359 return 0; 360 } 361 EXPORT_SYMBOL(ocelot_vlan_del); 362 363 static void ocelot_vlan_init(struct ocelot *ocelot) 364 { 365 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0); 366 u16 port, vid; 367 368 /* Clear VLAN table, by default all ports are members of all VLANs */ 369 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 370 ANA_TABLES_VLANACCESS); 371 ocelot_vlant_wait_for_completion(ocelot); 372 373 /* Configure the port VLAN memberships */ 374 for (vid = 1; vid < VLAN_N_VID; vid++) 375 ocelot_vlan_member_set(ocelot, 0, vid); 376 377 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 378 * traffic. It is added automatically if 8021q module is loaded, but 379 * we can't rely on it since module may be not loaded. 380 */ 381 ocelot_vlan_member_set(ocelot, all_ports, 0); 382 383 /* Set vlan ingress filter mask to all ports but the CPU port by 384 * default. 385 */ 386 ocelot_write(ocelot, all_ports, ANA_VLANMASK); 387 388 for (port = 0; port < ocelot->num_phys_ports; port++) { 389 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 390 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 391 } 392 } 393 394 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 395 { 396 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 397 } 398 399 static int ocelot_port_flush(struct ocelot *ocelot, int port) 400 { 401 unsigned int pause_ena; 402 int err, val; 403 404 /* Disable dequeuing from the egress queues */ 405 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 406 QSYS_PORT_MODE_DEQUEUE_DIS, 407 QSYS_PORT_MODE, port); 408 409 /* Disable flow control */ 410 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 411 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 412 413 /* Disable priority flow control */ 414 ocelot_fields_write(ocelot, port, 415 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 416 417 /* Wait at least the time it takes to receive a frame of maximum length 418 * at the port. 419 * Worst-case delays for 10 kilobyte jumbo frames are: 420 * 8 ms on a 10M port 421 * 800 μs on a 100M port 422 * 80 μs on a 1G port 423 * 32 μs on a 2.5G port 424 */ 425 usleep_range(8000, 10000); 426 427 /* Disable half duplex backpressure. */ 428 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 429 SYS_FRONT_PORT_MODE, port); 430 431 /* Flush the queues associated with the port. */ 432 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 433 REW_PORT_CFG, port); 434 435 /* Enable dequeuing from the egress queues. */ 436 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 437 port); 438 439 /* Wait until flushing is complete. */ 440 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 441 100, 2000000, false, ocelot, port); 442 443 /* Clear flushing again. */ 444 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 445 446 /* Re-enable flow control */ 447 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 448 449 return err; 450 } 451 452 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 453 unsigned int link_an_mode, 454 phy_interface_t interface, 455 unsigned long quirks) 456 { 457 struct ocelot_port *ocelot_port = ocelot->ports[port]; 458 int err; 459 460 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 461 DEV_MAC_ENA_CFG); 462 463 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 464 465 err = ocelot_port_flush(ocelot, port); 466 if (err) 467 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 468 port, err); 469 470 /* Put the port in reset. */ 471 if (interface != PHY_INTERFACE_MODE_QSGMII || 472 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 473 ocelot_port_rmwl(ocelot_port, 474 DEV_CLOCK_CFG_MAC_TX_RST | 475 DEV_CLOCK_CFG_MAC_TX_RST, 476 DEV_CLOCK_CFG_MAC_TX_RST | 477 DEV_CLOCK_CFG_MAC_TX_RST, 478 DEV_CLOCK_CFG); 479 } 480 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 481 482 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 483 struct phy_device *phydev, 484 unsigned int link_an_mode, 485 phy_interface_t interface, 486 int speed, int duplex, 487 bool tx_pause, bool rx_pause, 488 unsigned long quirks) 489 { 490 struct ocelot_port *ocelot_port = ocelot->ports[port]; 491 int mac_speed, mode = 0; 492 u32 mac_fc_cfg; 493 494 /* The MAC might be integrated in systems where the MAC speed is fixed 495 * and it's the PCS who is performing the rate adaptation, so we have 496 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 497 * (which is also its default value). 498 */ 499 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 500 speed == SPEED_1000) { 501 mac_speed = OCELOT_SPEED_1000; 502 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 503 } else if (speed == SPEED_2500) { 504 mac_speed = OCELOT_SPEED_2500; 505 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 506 } else if (speed == SPEED_100) { 507 mac_speed = OCELOT_SPEED_100; 508 } else { 509 mac_speed = OCELOT_SPEED_10; 510 } 511 512 if (duplex == DUPLEX_FULL) 513 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 514 515 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 516 517 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 518 * PORT_RST bits in DEV_CLOCK_CFG. 519 */ 520 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 521 DEV_CLOCK_CFG); 522 523 switch (speed) { 524 case SPEED_10: 525 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 526 break; 527 case SPEED_100: 528 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 529 break; 530 case SPEED_1000: 531 case SPEED_2500: 532 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 533 break; 534 default: 535 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 536 port, speed); 537 return; 538 } 539 540 /* Handle RX pause in all cases, with 2500base-X this is used for rate 541 * adaptation. 542 */ 543 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 544 545 if (tx_pause) 546 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 547 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 548 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 549 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 550 551 /* Flow control. Link speed is only used here to evaluate the time 552 * specification in incoming pause frames. 553 */ 554 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 555 556 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 557 558 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, tx_pause); 559 560 /* Undo the effects of ocelot_phylink_mac_link_down: 561 * enable MAC module 562 */ 563 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 564 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 565 566 /* Core: Enable port for frame transfer */ 567 ocelot_fields_write(ocelot, port, 568 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 569 } 570 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 571 572 static void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 573 struct sk_buff *clone) 574 { 575 struct ocelot_port *ocelot_port = ocelot->ports[port]; 576 577 spin_lock(&ocelot_port->ts_id_lock); 578 579 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 580 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */ 581 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id; 582 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4; 583 skb_queue_tail(&ocelot_port->tx_skbs, clone); 584 585 spin_unlock(&ocelot_port->ts_id_lock); 586 } 587 588 u32 ocelot_ptp_rew_op(struct sk_buff *skb) 589 { 590 struct sk_buff *clone = OCELOT_SKB_CB(skb)->clone; 591 u8 ptp_cmd = OCELOT_SKB_CB(skb)->ptp_cmd; 592 u32 rew_op = 0; 593 594 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP && clone) { 595 rew_op = ptp_cmd; 596 rew_op |= OCELOT_SKB_CB(clone)->ts_id << 3; 597 } else if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 598 rew_op = ptp_cmd; 599 } 600 601 return rew_op; 602 } 603 EXPORT_SYMBOL(ocelot_ptp_rew_op); 604 605 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb) 606 { 607 struct ptp_header *hdr; 608 unsigned int ptp_class; 609 u8 msgtype, twostep; 610 611 ptp_class = ptp_classify_raw(skb); 612 if (ptp_class == PTP_CLASS_NONE) 613 return false; 614 615 hdr = ptp_parse_header(skb, ptp_class); 616 if (!hdr) 617 return false; 618 619 msgtype = ptp_get_msgtype(hdr, ptp_class); 620 twostep = hdr->flag_field[0] & 0x2; 621 622 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0) 623 return true; 624 625 return false; 626 } 627 628 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 629 struct sk_buff *skb, 630 struct sk_buff **clone) 631 { 632 struct ocelot_port *ocelot_port = ocelot->ports[port]; 633 u8 ptp_cmd = ocelot_port->ptp_cmd; 634 635 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */ 636 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 637 if (ocelot_ptp_is_onestep_sync(skb)) { 638 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 639 return 0; 640 } 641 642 /* Fall back to two-step timestamping */ 643 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 644 } 645 646 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 647 *clone = skb_clone_sk(skb); 648 if (!(*clone)) 649 return -ENOMEM; 650 651 ocelot_port_add_txtstamp_skb(ocelot, port, *clone); 652 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 653 } 654 655 return 0; 656 } 657 EXPORT_SYMBOL(ocelot_port_txtstamp_request); 658 659 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 660 struct timespec64 *ts) 661 { 662 unsigned long flags; 663 u32 val; 664 665 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 666 667 /* Read current PTP time to get seconds */ 668 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 669 670 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 671 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 672 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 673 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 674 675 /* Read packet HW timestamp from FIFO */ 676 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 677 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 678 679 /* Sec has incremented since the ts was registered */ 680 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 681 ts->tv_sec--; 682 683 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 684 } 685 686 void ocelot_get_txtstamp(struct ocelot *ocelot) 687 { 688 int budget = OCELOT_PTP_QUEUE_SZ; 689 690 while (budget--) { 691 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 692 struct skb_shared_hwtstamps shhwtstamps; 693 struct ocelot_port *port; 694 struct timespec64 ts; 695 unsigned long flags; 696 u32 val, id, txport; 697 698 val = ocelot_read(ocelot, SYS_PTP_STATUS); 699 700 /* Check if a timestamp can be retrieved */ 701 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 702 break; 703 704 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 705 706 /* Retrieve the ts ID and Tx port */ 707 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 708 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 709 710 /* Retrieve its associated skb */ 711 port = ocelot->ports[txport]; 712 713 spin_lock_irqsave(&port->tx_skbs.lock, flags); 714 715 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 716 if (OCELOT_SKB_CB(skb)->ts_id != id) 717 continue; 718 __skb_unlink(skb, &port->tx_skbs); 719 skb_match = skb; 720 break; 721 } 722 723 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 724 725 /* Get the h/w timestamp */ 726 ocelot_get_hwtimestamp(ocelot, &ts); 727 728 if (unlikely(!skb_match)) 729 continue; 730 731 /* Set the timestamp into the skb */ 732 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 733 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 734 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 735 736 /* Next ts */ 737 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 738 } 739 } 740 EXPORT_SYMBOL(ocelot_get_txtstamp); 741 742 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 743 u32 *rval) 744 { 745 u32 bytes_valid, val; 746 747 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 748 if (val == XTR_NOT_READY) { 749 if (ifh) 750 return -EIO; 751 752 do { 753 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 754 } while (val == XTR_NOT_READY); 755 } 756 757 switch (val) { 758 case XTR_ABORT: 759 return -EIO; 760 case XTR_EOF_0: 761 case XTR_EOF_1: 762 case XTR_EOF_2: 763 case XTR_EOF_3: 764 case XTR_PRUNED: 765 bytes_valid = XTR_VALID_BYTES(val); 766 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 767 if (val == XTR_ESCAPE) 768 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 769 else 770 *rval = val; 771 772 return bytes_valid; 773 case XTR_ESCAPE: 774 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 775 776 return 4; 777 default: 778 *rval = val; 779 780 return 4; 781 } 782 } 783 784 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 785 { 786 int i, err = 0; 787 788 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 789 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 790 if (err != 4) 791 return (err < 0) ? err : -EIO; 792 } 793 794 return 0; 795 } 796 797 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 798 { 799 struct skb_shared_hwtstamps *shhwtstamps; 800 u64 tod_in_ns, full_ts_in_ns; 801 u64 timestamp, src_port, len; 802 u32 xfh[OCELOT_TAG_LEN / 4]; 803 struct net_device *dev; 804 struct timespec64 ts; 805 struct sk_buff *skb; 806 int sz, buf_len; 807 u32 val, *buf; 808 int err; 809 810 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 811 if (err) 812 return err; 813 814 ocelot_xfh_get_src_port(xfh, &src_port); 815 ocelot_xfh_get_len(xfh, &len); 816 ocelot_xfh_get_rew_val(xfh, ×tamp); 817 818 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 819 return -EINVAL; 820 821 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 822 if (!dev) 823 return -EINVAL; 824 825 skb = netdev_alloc_skb(dev, len); 826 if (unlikely(!skb)) { 827 netdev_err(dev, "Unable to allocate sk_buff\n"); 828 return -ENOMEM; 829 } 830 831 buf_len = len - ETH_FCS_LEN; 832 buf = (u32 *)skb_put(skb, buf_len); 833 834 len = 0; 835 do { 836 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 837 if (sz < 0) { 838 err = sz; 839 goto out_free_skb; 840 } 841 *buf++ = val; 842 len += sz; 843 } while (len < buf_len); 844 845 /* Read the FCS */ 846 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 847 if (sz < 0) { 848 err = sz; 849 goto out_free_skb; 850 } 851 852 /* Update the statistics if part of the FCS was read before */ 853 len -= ETH_FCS_LEN - sz; 854 855 if (unlikely(dev->features & NETIF_F_RXFCS)) { 856 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 857 *buf = val; 858 } 859 860 if (ocelot->ptp) { 861 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 862 863 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 864 if ((tod_in_ns & 0xffffffff) < timestamp) 865 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 866 timestamp; 867 else 868 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 869 timestamp; 870 871 shhwtstamps = skb_hwtstamps(skb); 872 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 873 shhwtstamps->hwtstamp = full_ts_in_ns; 874 } 875 876 /* Everything we see on an interface that is in the HW bridge 877 * has already been forwarded. 878 */ 879 if (ocelot->ports[src_port]->bridge) 880 skb->offload_fwd_mark = 1; 881 882 skb->protocol = eth_type_trans(skb, dev); 883 884 *nskb = skb; 885 886 return 0; 887 888 out_free_skb: 889 kfree_skb(skb); 890 return err; 891 } 892 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 893 894 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 895 { 896 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 897 898 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 899 return false; 900 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 901 return false; 902 903 return true; 904 } 905 EXPORT_SYMBOL(ocelot_can_inject); 906 907 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 908 u32 rew_op, struct sk_buff *skb) 909 { 910 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 911 unsigned int i, count, last; 912 913 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 914 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 915 916 ocelot_ifh_set_bypass(ifh, 1); 917 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 918 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 919 ocelot_ifh_set_vid(ifh, skb_vlan_tag_get(skb)); 920 ocelot_ifh_set_rew_op(ifh, rew_op); 921 922 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 923 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 924 925 count = DIV_ROUND_UP(skb->len, 4); 926 last = skb->len % 4; 927 for (i = 0; i < count; i++) 928 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 929 930 /* Add padding */ 931 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 932 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 933 i++; 934 } 935 936 /* Indicate EOF and valid bytes in last word */ 937 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 938 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 939 QS_INJ_CTRL_EOF, 940 QS_INJ_CTRL, grp); 941 942 /* Add dummy CRC */ 943 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 944 skb_tx_timestamp(skb); 945 946 skb->dev->stats.tx_packets++; 947 skb->dev->stats.tx_bytes += skb->len; 948 } 949 EXPORT_SYMBOL(ocelot_port_inject_frame); 950 951 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 952 { 953 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 954 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 955 } 956 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 957 958 int ocelot_fdb_add(struct ocelot *ocelot, int port, 959 const unsigned char *addr, u16 vid) 960 { 961 int pgid = port; 962 963 if (port == ocelot->npi) 964 pgid = PGID_CPU; 965 966 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 967 } 968 EXPORT_SYMBOL(ocelot_fdb_add); 969 970 int ocelot_fdb_del(struct ocelot *ocelot, int port, 971 const unsigned char *addr, u16 vid) 972 { 973 return ocelot_mact_forget(ocelot, addr, vid); 974 } 975 EXPORT_SYMBOL(ocelot_fdb_del); 976 977 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 978 bool is_static, void *data) 979 { 980 struct ocelot_dump_ctx *dump = data; 981 u32 portid = NETLINK_CB(dump->cb->skb).portid; 982 u32 seq = dump->cb->nlh->nlmsg_seq; 983 struct nlmsghdr *nlh; 984 struct ndmsg *ndm; 985 986 if (dump->idx < dump->cb->args[2]) 987 goto skip; 988 989 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 990 sizeof(*ndm), NLM_F_MULTI); 991 if (!nlh) 992 return -EMSGSIZE; 993 994 ndm = nlmsg_data(nlh); 995 ndm->ndm_family = AF_BRIDGE; 996 ndm->ndm_pad1 = 0; 997 ndm->ndm_pad2 = 0; 998 ndm->ndm_flags = NTF_SELF; 999 ndm->ndm_type = 0; 1000 ndm->ndm_ifindex = dump->dev->ifindex; 1001 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 1002 1003 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 1004 goto nla_put_failure; 1005 1006 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 1007 goto nla_put_failure; 1008 1009 nlmsg_end(dump->skb, nlh); 1010 1011 skip: 1012 dump->idx++; 1013 return 0; 1014 1015 nla_put_failure: 1016 nlmsg_cancel(dump->skb, nlh); 1017 return -EMSGSIZE; 1018 } 1019 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 1020 1021 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1022 struct ocelot_mact_entry *entry) 1023 { 1024 u32 val, dst, macl, mach; 1025 char mac[ETH_ALEN]; 1026 1027 /* Set row and column to read from */ 1028 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1029 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1030 1031 /* Issue a read command */ 1032 ocelot_write(ocelot, 1033 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1034 ANA_TABLES_MACACCESS); 1035 1036 if (ocelot_mact_wait_for_completion(ocelot)) 1037 return -ETIMEDOUT; 1038 1039 /* Read the entry flags */ 1040 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1041 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1042 return -EINVAL; 1043 1044 /* If the entry read has another port configured as its destination, 1045 * do not report it. 1046 */ 1047 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1048 if (dst != port) 1049 return -EINVAL; 1050 1051 /* Get the entry's MAC address and VLAN id */ 1052 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1053 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1054 1055 mac[0] = (mach >> 8) & 0xff; 1056 mac[1] = (mach >> 0) & 0xff; 1057 mac[2] = (macl >> 24) & 0xff; 1058 mac[3] = (macl >> 16) & 0xff; 1059 mac[4] = (macl >> 8) & 0xff; 1060 mac[5] = (macl >> 0) & 0xff; 1061 1062 entry->vid = (mach >> 16) & 0xfff; 1063 ether_addr_copy(entry->mac, mac); 1064 1065 return 0; 1066 } 1067 1068 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1069 dsa_fdb_dump_cb_t *cb, void *data) 1070 { 1071 int i, j; 1072 1073 /* Loop through all the mac tables entries. */ 1074 for (i = 0; i < ocelot->num_mact_rows; i++) { 1075 for (j = 0; j < 4; j++) { 1076 struct ocelot_mact_entry entry; 1077 bool is_static; 1078 int ret; 1079 1080 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 1081 /* If the entry is invalid (wrong port, invalid...), 1082 * skip it. 1083 */ 1084 if (ret == -EINVAL) 1085 continue; 1086 else if (ret) 1087 return ret; 1088 1089 is_static = (entry.type == ENTRYTYPE_LOCKED); 1090 1091 ret = cb(entry.mac, entry.vid, is_static, data); 1092 if (ret) 1093 return ret; 1094 } 1095 } 1096 1097 return 0; 1098 } 1099 EXPORT_SYMBOL(ocelot_fdb_dump); 1100 1101 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 1102 { 1103 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1104 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1105 } 1106 EXPORT_SYMBOL(ocelot_hwstamp_get); 1107 1108 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 1109 { 1110 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1111 struct hwtstamp_config cfg; 1112 1113 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1114 return -EFAULT; 1115 1116 /* reserved for future extensions */ 1117 if (cfg.flags) 1118 return -EINVAL; 1119 1120 /* Tx type sanity check */ 1121 switch (cfg.tx_type) { 1122 case HWTSTAMP_TX_ON: 1123 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1124 break; 1125 case HWTSTAMP_TX_ONESTEP_SYNC: 1126 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1127 * need to update the origin time. 1128 */ 1129 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1130 break; 1131 case HWTSTAMP_TX_OFF: 1132 ocelot_port->ptp_cmd = 0; 1133 break; 1134 default: 1135 return -ERANGE; 1136 } 1137 1138 mutex_lock(&ocelot->ptp_lock); 1139 1140 switch (cfg.rx_filter) { 1141 case HWTSTAMP_FILTER_NONE: 1142 break; 1143 case HWTSTAMP_FILTER_ALL: 1144 case HWTSTAMP_FILTER_SOME: 1145 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1146 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1147 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1148 case HWTSTAMP_FILTER_NTP_ALL: 1149 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1150 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1151 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1152 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1153 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1154 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1155 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1156 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1157 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1158 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1159 break; 1160 default: 1161 mutex_unlock(&ocelot->ptp_lock); 1162 return -ERANGE; 1163 } 1164 1165 /* Commit back the result & save it */ 1166 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1167 mutex_unlock(&ocelot->ptp_lock); 1168 1169 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1170 } 1171 EXPORT_SYMBOL(ocelot_hwstamp_set); 1172 1173 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1174 { 1175 int i; 1176 1177 if (sset != ETH_SS_STATS) 1178 return; 1179 1180 for (i = 0; i < ocelot->num_stats; i++) 1181 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1182 ETH_GSTRING_LEN); 1183 } 1184 EXPORT_SYMBOL(ocelot_get_strings); 1185 1186 static void ocelot_update_stats(struct ocelot *ocelot) 1187 { 1188 int i, j; 1189 1190 mutex_lock(&ocelot->stats_lock); 1191 1192 for (i = 0; i < ocelot->num_phys_ports; i++) { 1193 /* Configure the port to read the stats from */ 1194 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1195 1196 for (j = 0; j < ocelot->num_stats; j++) { 1197 u32 val; 1198 unsigned int idx = i * ocelot->num_stats + j; 1199 1200 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1201 ocelot->stats_layout[j].offset); 1202 1203 if (val < (ocelot->stats[idx] & U32_MAX)) 1204 ocelot->stats[idx] += (u64)1 << 32; 1205 1206 ocelot->stats[idx] = (ocelot->stats[idx] & 1207 ~(u64)U32_MAX) + val; 1208 } 1209 } 1210 1211 mutex_unlock(&ocelot->stats_lock); 1212 } 1213 1214 static void ocelot_check_stats_work(struct work_struct *work) 1215 { 1216 struct delayed_work *del_work = to_delayed_work(work); 1217 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1218 stats_work); 1219 1220 ocelot_update_stats(ocelot); 1221 1222 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1223 OCELOT_STATS_CHECK_DELAY); 1224 } 1225 1226 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1227 { 1228 int i; 1229 1230 /* check and update now */ 1231 ocelot_update_stats(ocelot); 1232 1233 /* Copy all counters */ 1234 for (i = 0; i < ocelot->num_stats; i++) 1235 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1236 } 1237 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1238 1239 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1240 { 1241 if (sset != ETH_SS_STATS) 1242 return -EOPNOTSUPP; 1243 1244 return ocelot->num_stats; 1245 } 1246 EXPORT_SYMBOL(ocelot_get_sset_count); 1247 1248 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1249 struct ethtool_ts_info *info) 1250 { 1251 info->phc_index = ocelot->ptp_clock ? 1252 ptp_clock_index(ocelot->ptp_clock) : -1; 1253 if (info->phc_index == -1) { 1254 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1255 SOF_TIMESTAMPING_RX_SOFTWARE | 1256 SOF_TIMESTAMPING_SOFTWARE; 1257 return 0; 1258 } 1259 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1260 SOF_TIMESTAMPING_RX_SOFTWARE | 1261 SOF_TIMESTAMPING_SOFTWARE | 1262 SOF_TIMESTAMPING_TX_HARDWARE | 1263 SOF_TIMESTAMPING_RX_HARDWARE | 1264 SOF_TIMESTAMPING_RAW_HARDWARE; 1265 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1266 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1267 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1268 1269 return 0; 1270 } 1271 EXPORT_SYMBOL(ocelot_get_ts_info); 1272 1273 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond, 1274 bool only_active_ports) 1275 { 1276 u32 mask = 0; 1277 int port; 1278 1279 for (port = 0; port < ocelot->num_phys_ports; port++) { 1280 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1281 1282 if (!ocelot_port) 1283 continue; 1284 1285 if (ocelot_port->bond == bond) { 1286 if (only_active_ports && !ocelot_port->lag_tx_active) 1287 continue; 1288 1289 mask |= BIT(port); 1290 } 1291 } 1292 1293 return mask; 1294 } 1295 1296 static u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port, 1297 struct net_device *bridge) 1298 { 1299 struct ocelot_port *ocelot_port = ocelot->ports[src_port]; 1300 u32 mask = 0; 1301 int port; 1302 1303 if (!ocelot_port || ocelot_port->bridge != bridge || 1304 ocelot_port->stp_state != BR_STATE_FORWARDING) 1305 return 0; 1306 1307 for (port = 0; port < ocelot->num_phys_ports; port++) { 1308 ocelot_port = ocelot->ports[port]; 1309 1310 if (!ocelot_port) 1311 continue; 1312 1313 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1314 ocelot_port->bridge == bridge) 1315 mask |= BIT(port); 1316 } 1317 1318 return mask; 1319 } 1320 1321 static u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot) 1322 { 1323 u32 mask = 0; 1324 int port; 1325 1326 for (port = 0; port < ocelot->num_phys_ports; port++) { 1327 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1328 1329 if (!ocelot_port) 1330 continue; 1331 1332 if (ocelot_port->is_dsa_8021q_cpu) 1333 mask |= BIT(port); 1334 } 1335 1336 return mask; 1337 } 1338 1339 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot) 1340 { 1341 unsigned long cpu_fwd_mask; 1342 int port; 1343 1344 /* If a DSA tag_8021q CPU exists, it needs to be included in the 1345 * regular forwarding path of the front ports regardless of whether 1346 * those are bridged or standalone. 1347 * If DSA tag_8021q is not used, this returns 0, which is fine because 1348 * the hardware-based CPU port module can be a destination for packets 1349 * even if it isn't part of PGID_SRC. 1350 */ 1351 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot); 1352 1353 /* Apply FWD mask. The loop is needed to add/remove the current port as 1354 * a source for the other ports. 1355 */ 1356 for (port = 0; port < ocelot->num_phys_ports; port++) { 1357 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1358 unsigned long mask; 1359 1360 if (!ocelot_port) { 1361 /* Unused ports can't send anywhere */ 1362 mask = 0; 1363 } else if (ocelot_port->is_dsa_8021q_cpu) { 1364 /* The DSA tag_8021q CPU ports need to be able to 1365 * forward packets to all other ports except for 1366 * themselves 1367 */ 1368 mask = GENMASK(ocelot->num_phys_ports - 1, 0); 1369 mask &= ~cpu_fwd_mask; 1370 } else if (ocelot_port->bridge) { 1371 struct net_device *bridge = ocelot_port->bridge; 1372 struct net_device *bond = ocelot_port->bond; 1373 1374 mask = ocelot_get_bridge_fwd_mask(ocelot, port, bridge); 1375 mask |= cpu_fwd_mask; 1376 mask &= ~BIT(port); 1377 if (bond) { 1378 mask &= ~ocelot_get_bond_mask(ocelot, bond, 1379 false); 1380 } 1381 } else { 1382 /* Standalone ports forward only to DSA tag_8021q CPU 1383 * ports (if those exist), or to the hardware CPU port 1384 * module otherwise. 1385 */ 1386 mask = cpu_fwd_mask; 1387 } 1388 1389 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1390 } 1391 } 1392 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask); 1393 1394 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1395 { 1396 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1397 u32 learn_ena = 0; 1398 1399 ocelot_port->stp_state = state; 1400 1401 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1402 ocelot_port->learn_ena) 1403 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1404 1405 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1406 ANA_PORT_PORT_CFG, port); 1407 1408 ocelot_apply_bridge_fwd_mask(ocelot); 1409 } 1410 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1411 1412 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1413 { 1414 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 1415 1416 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1417 * which is clearly not what our intention is. So avoid that. 1418 */ 1419 if (!age_period) 1420 age_period = 1; 1421 1422 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1423 } 1424 EXPORT_SYMBOL(ocelot_set_ageing_time); 1425 1426 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1427 const unsigned char *addr, 1428 u16 vid) 1429 { 1430 struct ocelot_multicast *mc; 1431 1432 list_for_each_entry(mc, &ocelot->multicast, list) { 1433 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1434 return mc; 1435 } 1436 1437 return NULL; 1438 } 1439 1440 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 1441 { 1442 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 1443 return ENTRYTYPE_MACv4; 1444 if (addr[0] == 0x33 && addr[1] == 0x33) 1445 return ENTRYTYPE_MACv6; 1446 return ENTRYTYPE_LOCKED; 1447 } 1448 1449 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 1450 unsigned long ports) 1451 { 1452 struct ocelot_pgid *pgid; 1453 1454 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 1455 if (!pgid) 1456 return ERR_PTR(-ENOMEM); 1457 1458 pgid->ports = ports; 1459 pgid->index = index; 1460 refcount_set(&pgid->refcount, 1); 1461 list_add_tail(&pgid->list, &ocelot->pgids); 1462 1463 return pgid; 1464 } 1465 1466 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 1467 { 1468 if (!refcount_dec_and_test(&pgid->refcount)) 1469 return; 1470 1471 list_del(&pgid->list); 1472 kfree(pgid); 1473 } 1474 1475 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 1476 const struct ocelot_multicast *mc) 1477 { 1478 struct ocelot_pgid *pgid; 1479 int index; 1480 1481 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 1482 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 1483 * destination mask table (PGID), the destination set is programmed as 1484 * part of the entry MAC address.", and the DEST_IDX is set to 0. 1485 */ 1486 if (mc->entry_type == ENTRYTYPE_MACv4 || 1487 mc->entry_type == ENTRYTYPE_MACv6) 1488 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 1489 1490 list_for_each_entry(pgid, &ocelot->pgids, list) { 1491 /* When searching for a nonreserved multicast PGID, ignore the 1492 * dummy PGID of zero that we have for MACv4/MACv6 entries 1493 */ 1494 if (pgid->index && pgid->ports == mc->ports) { 1495 refcount_inc(&pgid->refcount); 1496 return pgid; 1497 } 1498 } 1499 1500 /* Search for a free index in the nonreserved multicast PGID area */ 1501 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 1502 bool used = false; 1503 1504 list_for_each_entry(pgid, &ocelot->pgids, list) { 1505 if (pgid->index == index) { 1506 used = true; 1507 break; 1508 } 1509 } 1510 1511 if (!used) 1512 return ocelot_pgid_alloc(ocelot, index, mc->ports); 1513 } 1514 1515 return ERR_PTR(-ENOSPC); 1516 } 1517 1518 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1519 struct ocelot_multicast *mc) 1520 { 1521 ether_addr_copy(addr, mc->addr); 1522 1523 if (mc->entry_type == ENTRYTYPE_MACv4) { 1524 addr[0] = 0; 1525 addr[1] = mc->ports >> 8; 1526 addr[2] = mc->ports & 0xff; 1527 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 1528 addr[0] = mc->ports >> 8; 1529 addr[1] = mc->ports & 0xff; 1530 } 1531 } 1532 1533 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1534 const struct switchdev_obj_port_mdb *mdb) 1535 { 1536 unsigned char addr[ETH_ALEN]; 1537 struct ocelot_multicast *mc; 1538 struct ocelot_pgid *pgid; 1539 u16 vid = mdb->vid; 1540 1541 if (port == ocelot->npi) 1542 port = ocelot->num_phys_ports; 1543 1544 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1545 if (!mc) { 1546 /* New entry */ 1547 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1548 if (!mc) 1549 return -ENOMEM; 1550 1551 mc->entry_type = ocelot_classify_mdb(mdb->addr); 1552 ether_addr_copy(mc->addr, mdb->addr); 1553 mc->vid = vid; 1554 1555 list_add_tail(&mc->list, &ocelot->multicast); 1556 } else { 1557 /* Existing entry. Clean up the current port mask from 1558 * hardware now, because we'll be modifying it. 1559 */ 1560 ocelot_pgid_free(ocelot, mc->pgid); 1561 ocelot_encode_ports_to_mdb(addr, mc); 1562 ocelot_mact_forget(ocelot, addr, vid); 1563 } 1564 1565 mc->ports |= BIT(port); 1566 1567 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1568 if (IS_ERR(pgid)) { 1569 dev_err(ocelot->dev, 1570 "Cannot allocate PGID for mdb %pM vid %d\n", 1571 mc->addr, mc->vid); 1572 devm_kfree(ocelot->dev, mc); 1573 return PTR_ERR(pgid); 1574 } 1575 mc->pgid = pgid; 1576 1577 ocelot_encode_ports_to_mdb(addr, mc); 1578 1579 if (mc->entry_type != ENTRYTYPE_MACv4 && 1580 mc->entry_type != ENTRYTYPE_MACv6) 1581 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1582 pgid->index); 1583 1584 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1585 mc->entry_type); 1586 } 1587 EXPORT_SYMBOL(ocelot_port_mdb_add); 1588 1589 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1590 const struct switchdev_obj_port_mdb *mdb) 1591 { 1592 unsigned char addr[ETH_ALEN]; 1593 struct ocelot_multicast *mc; 1594 struct ocelot_pgid *pgid; 1595 u16 vid = mdb->vid; 1596 1597 if (port == ocelot->npi) 1598 port = ocelot->num_phys_ports; 1599 1600 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1601 if (!mc) 1602 return -ENOENT; 1603 1604 ocelot_encode_ports_to_mdb(addr, mc); 1605 ocelot_mact_forget(ocelot, addr, vid); 1606 1607 ocelot_pgid_free(ocelot, mc->pgid); 1608 mc->ports &= ~BIT(port); 1609 if (!mc->ports) { 1610 list_del(&mc->list); 1611 devm_kfree(ocelot->dev, mc); 1612 return 0; 1613 } 1614 1615 /* We have a PGID with fewer ports now */ 1616 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1617 if (IS_ERR(pgid)) 1618 return PTR_ERR(pgid); 1619 mc->pgid = pgid; 1620 1621 ocelot_encode_ports_to_mdb(addr, mc); 1622 1623 if (mc->entry_type != ENTRYTYPE_MACv4 && 1624 mc->entry_type != ENTRYTYPE_MACv6) 1625 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1626 pgid->index); 1627 1628 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1629 mc->entry_type); 1630 } 1631 EXPORT_SYMBOL(ocelot_port_mdb_del); 1632 1633 void ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1634 struct net_device *bridge) 1635 { 1636 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1637 1638 ocelot_port->bridge = bridge; 1639 1640 ocelot_apply_bridge_fwd_mask(ocelot); 1641 } 1642 EXPORT_SYMBOL(ocelot_port_bridge_join); 1643 1644 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1645 struct net_device *bridge) 1646 { 1647 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1648 struct ocelot_vlan pvid = {0}, native_vlan = {0}; 1649 1650 ocelot_port->bridge = NULL; 1651 1652 ocelot_port_set_pvid(ocelot, port, pvid); 1653 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 1654 ocelot_apply_bridge_fwd_mask(ocelot); 1655 } 1656 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1657 1658 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1659 { 1660 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 1661 int i, port, lag; 1662 1663 /* Reset destination and aggregation PGIDS */ 1664 for_each_unicast_dest_pgid(ocelot, port) 1665 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1666 1667 for_each_aggr_pgid(ocelot, i) 1668 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1669 ANA_PGID_PGID, i); 1670 1671 /* The visited ports bitmask holds the list of ports offloading any 1672 * bonding interface. Initially we mark all these ports as unvisited, 1673 * then every time we visit a port in this bitmask, we know that it is 1674 * the lowest numbered port, i.e. the one whose logical ID == physical 1675 * port ID == LAG ID. So we mark as visited all further ports in the 1676 * bitmask that are offloading the same bonding interface. This way, 1677 * we set up the aggregation PGIDs only once per bonding interface. 1678 */ 1679 for (port = 0; port < ocelot->num_phys_ports; port++) { 1680 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1681 1682 if (!ocelot_port || !ocelot_port->bond) 1683 continue; 1684 1685 visited &= ~BIT(port); 1686 } 1687 1688 /* Now, set PGIDs for each active LAG */ 1689 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1690 struct net_device *bond = ocelot->ports[lag]->bond; 1691 int num_active_ports = 0; 1692 unsigned long bond_mask; 1693 u8 aggr_idx[16]; 1694 1695 if (!bond || (visited & BIT(lag))) 1696 continue; 1697 1698 bond_mask = ocelot_get_bond_mask(ocelot, bond, true); 1699 1700 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1701 // Destination mask 1702 ocelot_write_rix(ocelot, bond_mask, 1703 ANA_PGID_PGID, port); 1704 aggr_idx[num_active_ports++] = port; 1705 } 1706 1707 for_each_aggr_pgid(ocelot, i) { 1708 u32 ac; 1709 1710 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1711 ac &= ~bond_mask; 1712 /* Don't do division by zero if there was no active 1713 * port. Just make all aggregation codes zero. 1714 */ 1715 if (num_active_ports) 1716 ac |= BIT(aggr_idx[i % num_active_ports]); 1717 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1718 } 1719 1720 /* Mark all ports in the same LAG as visited to avoid applying 1721 * the same config again. 1722 */ 1723 for (port = lag; port < ocelot->num_phys_ports; port++) { 1724 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1725 1726 if (!ocelot_port) 1727 continue; 1728 1729 if (ocelot_port->bond == bond) 1730 visited |= BIT(port); 1731 } 1732 } 1733 } 1734 1735 /* When offloading a bonding interface, the switch ports configured under the 1736 * same bond must have the same logical port ID, equal to the physical port ID 1737 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 1738 * bridged mode, each port has a logical port ID equal to its physical port ID. 1739 */ 1740 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 1741 { 1742 int port; 1743 1744 for (port = 0; port < ocelot->num_phys_ports; port++) { 1745 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1746 struct net_device *bond; 1747 1748 if (!ocelot_port) 1749 continue; 1750 1751 bond = ocelot_port->bond; 1752 if (bond) { 1753 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond, 1754 false)); 1755 1756 ocelot_rmw_gix(ocelot, 1757 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1758 ANA_PORT_PORT_CFG_PORTID_VAL_M, 1759 ANA_PORT_PORT_CFG, port); 1760 } else { 1761 ocelot_rmw_gix(ocelot, 1762 ANA_PORT_PORT_CFG_PORTID_VAL(port), 1763 ANA_PORT_PORT_CFG_PORTID_VAL_M, 1764 ANA_PORT_PORT_CFG, port); 1765 } 1766 } 1767 } 1768 1769 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1770 struct net_device *bond, 1771 struct netdev_lag_upper_info *info) 1772 { 1773 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 1774 return -EOPNOTSUPP; 1775 1776 ocelot->ports[port]->bond = bond; 1777 1778 ocelot_setup_logical_port_ids(ocelot); 1779 ocelot_apply_bridge_fwd_mask(ocelot); 1780 ocelot_set_aggr_pgids(ocelot); 1781 1782 return 0; 1783 } 1784 EXPORT_SYMBOL(ocelot_port_lag_join); 1785 1786 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1787 struct net_device *bond) 1788 { 1789 ocelot->ports[port]->bond = NULL; 1790 1791 ocelot_setup_logical_port_ids(ocelot); 1792 ocelot_apply_bridge_fwd_mask(ocelot); 1793 ocelot_set_aggr_pgids(ocelot); 1794 } 1795 EXPORT_SYMBOL(ocelot_port_lag_leave); 1796 1797 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 1798 { 1799 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1800 1801 ocelot_port->lag_tx_active = lag_tx_active; 1802 1803 /* Rebalance the LAGs */ 1804 ocelot_set_aggr_pgids(ocelot); 1805 } 1806 EXPORT_SYMBOL(ocelot_port_lag_change); 1807 1808 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 1809 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 1810 * In the special case that it's the NPI port that we're configuring, the 1811 * length of the tag and optional prefix needs to be accounted for privately, 1812 * in order to be able to sustain communication at the requested @sdu. 1813 */ 1814 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 1815 { 1816 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1817 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 1818 int pause_start, pause_stop; 1819 int atop, atop_tot; 1820 1821 if (port == ocelot->npi) { 1822 maxlen += OCELOT_TAG_LEN; 1823 1824 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1825 maxlen += OCELOT_SHORT_PREFIX_LEN; 1826 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 1827 maxlen += OCELOT_LONG_PREFIX_LEN; 1828 } 1829 1830 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 1831 1832 /* Set Pause watermark hysteresis */ 1833 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 1834 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 1835 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 1836 pause_start); 1837 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 1838 pause_stop); 1839 1840 /* Tail dropping watermarks */ 1841 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 1842 OCELOT_BUFFER_CELL_SZ; 1843 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 1844 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 1845 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 1846 } 1847 EXPORT_SYMBOL(ocelot_port_set_maxlen); 1848 1849 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 1850 { 1851 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 1852 1853 if (port == ocelot->npi) { 1854 max_mtu -= OCELOT_TAG_LEN; 1855 1856 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1857 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 1858 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 1859 max_mtu -= OCELOT_LONG_PREFIX_LEN; 1860 } 1861 1862 return max_mtu; 1863 } 1864 EXPORT_SYMBOL(ocelot_get_max_mtu); 1865 1866 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 1867 bool enabled) 1868 { 1869 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1870 u32 val = 0; 1871 1872 if (enabled) 1873 val = ANA_PORT_PORT_CFG_LEARN_ENA; 1874 1875 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 1876 ANA_PORT_PORT_CFG, port); 1877 1878 ocelot_port->learn_ena = enabled; 1879 } 1880 1881 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 1882 bool enabled) 1883 { 1884 u32 val = 0; 1885 1886 if (enabled) 1887 val = BIT(port); 1888 1889 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 1890 } 1891 1892 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 1893 bool enabled) 1894 { 1895 u32 val = 0; 1896 1897 if (enabled) 1898 val = BIT(port); 1899 1900 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 1901 } 1902 1903 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 1904 bool enabled) 1905 { 1906 u32 val = 0; 1907 1908 if (enabled) 1909 val = BIT(port); 1910 1911 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 1912 } 1913 1914 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 1915 struct switchdev_brport_flags flags) 1916 { 1917 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1918 BR_BCAST_FLOOD)) 1919 return -EINVAL; 1920 1921 return 0; 1922 } 1923 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 1924 1925 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 1926 struct switchdev_brport_flags flags) 1927 { 1928 if (flags.mask & BR_LEARNING) 1929 ocelot_port_set_learning(ocelot, port, 1930 !!(flags.val & BR_LEARNING)); 1931 1932 if (flags.mask & BR_FLOOD) 1933 ocelot_port_set_ucast_flood(ocelot, port, 1934 !!(flags.val & BR_FLOOD)); 1935 1936 if (flags.mask & BR_MCAST_FLOOD) 1937 ocelot_port_set_mcast_flood(ocelot, port, 1938 !!(flags.val & BR_MCAST_FLOOD)); 1939 1940 if (flags.mask & BR_BCAST_FLOOD) 1941 ocelot_port_set_bcast_flood(ocelot, port, 1942 !!(flags.val & BR_BCAST_FLOOD)); 1943 } 1944 EXPORT_SYMBOL(ocelot_port_bridge_flags); 1945 1946 void ocelot_init_port(struct ocelot *ocelot, int port) 1947 { 1948 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1949 1950 skb_queue_head_init(&ocelot_port->tx_skbs); 1951 spin_lock_init(&ocelot_port->ts_id_lock); 1952 1953 /* Basic L2 initialization */ 1954 1955 /* Set MAC IFG Gaps 1956 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 1957 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 1958 */ 1959 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 1960 DEV_MAC_IFG_CFG); 1961 1962 /* Load seed (0) and set MAC HDX late collision */ 1963 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 1964 DEV_MAC_HDX_CFG_SEED_LOAD, 1965 DEV_MAC_HDX_CFG); 1966 mdelay(1); 1967 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 1968 DEV_MAC_HDX_CFG); 1969 1970 /* Set Max Length and maximum tags allowed */ 1971 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 1972 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 1973 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 1974 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 1975 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 1976 DEV_MAC_TAGS_CFG); 1977 1978 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 1979 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 1980 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 1981 1982 /* Enable transmission of pause frames */ 1983 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 1984 1985 /* Drop frames with multicast source address */ 1986 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1987 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1988 ANA_PORT_DROP_CFG, port); 1989 1990 /* Set default VLAN and tag type to 8021Q. */ 1991 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 1992 REW_PORT_VLAN_CFG_PORT_TPID_M, 1993 REW_PORT_VLAN_CFG, port); 1994 1995 /* Disable source address learning for standalone mode */ 1996 ocelot_port_set_learning(ocelot, port, false); 1997 1998 /* Set the port's initial logical port ID value, enable receiving 1999 * frames on it, and configure the MAC address learning type to 2000 * automatic. 2001 */ 2002 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 2003 ANA_PORT_PORT_CFG_RECV_ENA | 2004 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2005 ANA_PORT_PORT_CFG, port); 2006 2007 /* Enable vcap lookups */ 2008 ocelot_vcap_enable(ocelot, port); 2009 } 2010 EXPORT_SYMBOL(ocelot_init_port); 2011 2012 /* Configure and enable the CPU port module, which is a set of queues 2013 * accessible through register MMIO, frame DMA or Ethernet (in case 2014 * NPI mode is used). 2015 */ 2016 static void ocelot_cpu_port_init(struct ocelot *ocelot) 2017 { 2018 int cpu = ocelot->num_phys_ports; 2019 2020 /* The unicast destination PGID for the CPU port module is unused */ 2021 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2022 /* Instead set up a multicast destination PGID for traffic copied to 2023 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2024 * addresses will be copied to the CPU via this PGID. 2025 */ 2026 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2027 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2028 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2029 ANA_PORT_PORT_CFG, cpu); 2030 2031 /* Enable CPU port module */ 2032 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 2033 /* CPU port Injection/Extraction configuration */ 2034 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 2035 OCELOT_TAG_PREFIX_NONE); 2036 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 2037 OCELOT_TAG_PREFIX_NONE); 2038 2039 /* Configure the CPU port to be VLAN aware */ 2040 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 2041 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2042 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2043 ANA_PORT_VLAN_CFG, cpu); 2044 } 2045 2046 static void ocelot_detect_features(struct ocelot *ocelot) 2047 { 2048 int mmgt, eq_ctrl; 2049 2050 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 2051 * the number of 240-byte free memory words (aka 4-cell chunks) and not 2052 * 192 bytes as the documentation incorrectly says. 2053 */ 2054 mmgt = ocelot_read(ocelot, SYS_MMGT); 2055 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 2056 2057 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 2058 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 2059 } 2060 2061 int ocelot_init(struct ocelot *ocelot) 2062 { 2063 char queue_name[32]; 2064 int i, ret; 2065 u32 port; 2066 2067 if (ocelot->ops->reset) { 2068 ret = ocelot->ops->reset(ocelot); 2069 if (ret) { 2070 dev_err(ocelot->dev, "Switch reset failed\n"); 2071 return ret; 2072 } 2073 } 2074 2075 ocelot->stats = devm_kcalloc(ocelot->dev, 2076 ocelot->num_phys_ports * ocelot->num_stats, 2077 sizeof(u64), GFP_KERNEL); 2078 if (!ocelot->stats) 2079 return -ENOMEM; 2080 2081 mutex_init(&ocelot->stats_lock); 2082 mutex_init(&ocelot->ptp_lock); 2083 spin_lock_init(&ocelot->ptp_clock_lock); 2084 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2085 dev_name(ocelot->dev)); 2086 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2087 if (!ocelot->stats_queue) 2088 return -ENOMEM; 2089 2090 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 2091 if (!ocelot->owq) { 2092 destroy_workqueue(ocelot->stats_queue); 2093 return -ENOMEM; 2094 } 2095 2096 INIT_LIST_HEAD(&ocelot->multicast); 2097 INIT_LIST_HEAD(&ocelot->pgids); 2098 ocelot_detect_features(ocelot); 2099 ocelot_mact_init(ocelot); 2100 ocelot_vlan_init(ocelot); 2101 ocelot_vcap_init(ocelot); 2102 ocelot_cpu_port_init(ocelot); 2103 2104 for (port = 0; port < ocelot->num_phys_ports; port++) { 2105 /* Clear all counters (5 groups) */ 2106 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2107 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2108 SYS_STAT_CFG); 2109 } 2110 2111 /* Only use S-Tag */ 2112 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2113 2114 /* Aggregation mode */ 2115 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2116 ANA_AGGR_CFG_AC_DMAC_ENA | 2117 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2118 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 2119 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 2120 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 2121 ANA_AGGR_CFG); 2122 2123 /* Set MAC age time to default value. The entry is aged after 2124 * 2*AGE_PERIOD 2125 */ 2126 ocelot_write(ocelot, 2127 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2128 ANA_AUTOAGE); 2129 2130 /* Disable learning for frames discarded by VLAN ingress filtering */ 2131 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2132 2133 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2134 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2135 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2136 2137 /* Setup flooding PGIDs */ 2138 for (i = 0; i < ocelot->num_flooding_pgids; i++) 2139 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2140 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 2141 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2142 ANA_FLOODING, i); 2143 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2144 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2145 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2146 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2147 ANA_FLOODING_IPMC); 2148 2149 for (port = 0; port < ocelot->num_phys_ports; port++) { 2150 /* Transmit the frame to the local port. */ 2151 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2152 /* Do not forward BPDU frames to the front ports. */ 2153 ocelot_write_gix(ocelot, 2154 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2155 ANA_PORT_CPU_FWD_BPDU_CFG, 2156 port); 2157 /* Ensure bridging is disabled */ 2158 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2159 } 2160 2161 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 2162 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2163 2164 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2165 } 2166 2167 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 2168 2169 /* Allow broadcast and unknown L2 multicast to the CPU. */ 2170 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2171 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2172 ANA_PGID_PGID, PGID_MC); 2173 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2174 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2175 ANA_PGID_PGID, PGID_BC); 2176 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2177 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2178 2179 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2180 * registers endianness. 2181 */ 2182 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2183 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2184 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2185 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2186 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2187 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2188 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2189 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2190 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2191 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2192 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2193 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2194 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2195 for (i = 0; i < 16; i++) 2196 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2197 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2198 ANA_CPUQ_8021_CFG, i); 2199 2200 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2201 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2202 OCELOT_STATS_CHECK_DELAY); 2203 2204 return 0; 2205 } 2206 EXPORT_SYMBOL(ocelot_init); 2207 2208 void ocelot_deinit(struct ocelot *ocelot) 2209 { 2210 cancel_delayed_work(&ocelot->stats_work); 2211 destroy_workqueue(ocelot->stats_queue); 2212 destroy_workqueue(ocelot->owq); 2213 mutex_destroy(&ocelot->stats_lock); 2214 } 2215 EXPORT_SYMBOL(ocelot_deinit); 2216 2217 void ocelot_deinit_port(struct ocelot *ocelot, int port) 2218 { 2219 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2220 2221 skb_queue_purge(&ocelot_port->tx_skbs); 2222 } 2223 EXPORT_SYMBOL(ocelot_deinit_port); 2224 2225 MODULE_LICENSE("Dual MIT/GPL"); 2226