1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2015 Atmel Corporation, 4 * Nicolas Ferre <nicolas.ferre@atmel.com> 5 * 6 * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk-provider.h> 11 #include <linux/clkdev.h> 12 #include <linux/clk/at91_pmc.h> 13 #include <linux/of.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/regmap.h> 16 17 #include "pmc.h" 18 19 #define GENERATED_MAX_DIV 255 20 21 struct clk_generated { 22 struct clk_hw hw; 23 struct regmap *regmap; 24 struct clk_range range; 25 spinlock_t *lock; 26 u32 *mux_table; 27 u32 id; 28 u32 gckdiv; 29 const struct clk_pcr_layout *layout; 30 struct at91_clk_pms pms; 31 u8 parent_id; 32 int chg_pid; 33 }; 34 35 #define to_clk_generated(hw) \ 36 container_of(hw, struct clk_generated, hw) 37 38 static int clk_generated_set(struct clk_generated *gck, int status) 39 { 40 unsigned long flags; 41 unsigned int enable = status ? AT91_PMC_PCR_GCKEN : 0; 42 43 spin_lock_irqsave(gck->lock, flags); 44 regmap_write(gck->regmap, gck->layout->offset, 45 (gck->id & gck->layout->pid_mask)); 46 regmap_update_bits(gck->regmap, gck->layout->offset, 47 AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask | 48 gck->layout->cmd | enable, 49 field_prep(gck->layout->gckcss_mask, gck->parent_id) | 50 gck->layout->cmd | 51 FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) | 52 enable); 53 spin_unlock_irqrestore(gck->lock, flags); 54 55 return 0; 56 } 57 58 static int clk_generated_enable(struct clk_hw *hw) 59 { 60 struct clk_generated *gck = to_clk_generated(hw); 61 62 pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", 63 __func__, gck->gckdiv, gck->parent_id); 64 65 clk_generated_set(gck, 1); 66 67 return 0; 68 } 69 70 static void clk_generated_disable(struct clk_hw *hw) 71 { 72 struct clk_generated *gck = to_clk_generated(hw); 73 unsigned long flags; 74 75 spin_lock_irqsave(gck->lock, flags); 76 regmap_write(gck->regmap, gck->layout->offset, 77 (gck->id & gck->layout->pid_mask)); 78 regmap_update_bits(gck->regmap, gck->layout->offset, 79 gck->layout->cmd | AT91_PMC_PCR_GCKEN, 80 gck->layout->cmd); 81 spin_unlock_irqrestore(gck->lock, flags); 82 } 83 84 static int clk_generated_is_enabled(struct clk_hw *hw) 85 { 86 struct clk_generated *gck = to_clk_generated(hw); 87 unsigned long flags; 88 unsigned int status; 89 90 spin_lock_irqsave(gck->lock, flags); 91 regmap_write(gck->regmap, gck->layout->offset, 92 (gck->id & gck->layout->pid_mask)); 93 regmap_read(gck->regmap, gck->layout->offset, &status); 94 spin_unlock_irqrestore(gck->lock, flags); 95 96 return !!(status & AT91_PMC_PCR_GCKEN); 97 } 98 99 static unsigned long 100 clk_generated_recalc_rate(struct clk_hw *hw, 101 unsigned long parent_rate) 102 { 103 struct clk_generated *gck = to_clk_generated(hw); 104 105 return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1); 106 } 107 108 static void clk_generated_best_diff(struct clk_rate_request *req, 109 struct clk_hw *parent, 110 unsigned long parent_rate, u32 div, 111 int *best_diff, long *best_rate) 112 { 113 unsigned long tmp_rate; 114 int tmp_diff; 115 116 if (!div) 117 tmp_rate = parent_rate; 118 else 119 tmp_rate = parent_rate / div; 120 121 if (tmp_rate < req->min_rate || tmp_rate > req->max_rate) 122 return; 123 124 tmp_diff = abs(req->rate - tmp_rate); 125 126 if (*best_diff < 0 || *best_diff >= tmp_diff) { 127 *best_rate = tmp_rate; 128 *best_diff = tmp_diff; 129 req->best_parent_rate = parent_rate; 130 req->best_parent_hw = parent; 131 } 132 } 133 134 static int clk_generated_determine_rate(struct clk_hw *hw, 135 struct clk_rate_request *req) 136 { 137 struct clk_generated *gck = to_clk_generated(hw); 138 struct clk_hw *parent = NULL; 139 struct clk_rate_request req_parent = *req; 140 long best_rate = -EINVAL; 141 unsigned long min_rate, parent_rate; 142 int best_diff = -1; 143 int i; 144 u32 div; 145 146 /* do not look for a rate that is outside of our range */ 147 if (gck->range.max && req->rate > gck->range.max) 148 req->rate = gck->range.max; 149 if (gck->range.min && req->rate < gck->range.min) 150 req->rate = gck->range.min; 151 152 for (i = 0; i < clk_hw_get_num_parents(hw); i++) { 153 if (gck->chg_pid == i) 154 continue; 155 156 parent = clk_hw_get_parent_by_index(hw, i); 157 if (!parent) 158 continue; 159 160 parent_rate = clk_hw_get_rate(parent); 161 min_rate = DIV_ROUND_CLOSEST(parent_rate, GENERATED_MAX_DIV + 1); 162 if (!parent_rate || 163 (gck->range.max && min_rate > gck->range.max)) 164 continue; 165 166 div = DIV_ROUND_CLOSEST(parent_rate, req->rate); 167 if (div > GENERATED_MAX_DIV + 1) 168 div = GENERATED_MAX_DIV + 1; 169 170 clk_generated_best_diff(req, parent, parent_rate, div, 171 &best_diff, &best_rate); 172 173 if (!best_diff) 174 break; 175 } 176 177 /* 178 * The audio_pll rate can be modified, unlike the five others clocks 179 * that should never be altered. 180 * The audio_pll can technically be used by multiple consumers. However, 181 * with the rate locking, the first consumer to enable to clock will be 182 * the one definitely setting the rate of the clock. 183 * Since audio IPs are most likely to request the same rate, we enforce 184 * that the only clks able to modify gck rate are those of audio IPs. 185 */ 186 187 if (gck->chg_pid < 0) 188 goto end; 189 190 parent = clk_hw_get_parent_by_index(hw, gck->chg_pid); 191 if (!parent) 192 goto end; 193 194 for (div = 1; div < GENERATED_MAX_DIV + 2; div++) { 195 req_parent.rate = req->rate * div; 196 if (__clk_determine_rate(parent, &req_parent)) 197 continue; 198 clk_generated_best_diff(req, parent, req_parent.rate, div, 199 &best_diff, &best_rate); 200 201 if (!best_diff) 202 break; 203 } 204 205 end: 206 pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n", 207 __func__, best_rate, 208 __clk_get_name((req->best_parent_hw)->clk), 209 req->best_parent_rate); 210 211 if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max)) 212 return -EINVAL; 213 214 req->rate = best_rate; 215 return 0; 216 } 217 218 /* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */ 219 static int clk_generated_set_parent(struct clk_hw *hw, u8 index) 220 { 221 struct clk_generated *gck = to_clk_generated(hw); 222 223 if (index >= clk_hw_get_num_parents(hw)) 224 return -EINVAL; 225 226 if (gck->mux_table) 227 gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index); 228 else 229 gck->parent_id = index; 230 231 return 0; 232 } 233 234 static u8 clk_generated_get_parent(struct clk_hw *hw) 235 { 236 struct clk_generated *gck = to_clk_generated(hw); 237 238 return gck->parent_id; 239 } 240 241 /* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */ 242 static int clk_generated_set_rate(struct clk_hw *hw, 243 unsigned long rate, 244 unsigned long parent_rate) 245 { 246 struct clk_generated *gck = to_clk_generated(hw); 247 u32 div; 248 249 if (!rate) 250 return -EINVAL; 251 252 if (gck->range.max && rate > gck->range.max) 253 return -EINVAL; 254 255 div = DIV_ROUND_CLOSEST(parent_rate, rate); 256 if (div > GENERATED_MAX_DIV + 1 || !div) 257 return -EINVAL; 258 259 gck->gckdiv = div - 1; 260 return 0; 261 } 262 263 static int clk_generated_save_context(struct clk_hw *hw) 264 { 265 struct clk_generated *gck = to_clk_generated(hw); 266 267 gck->pms.status = clk_generated_is_enabled(&gck->hw); 268 269 return 0; 270 } 271 272 static void clk_generated_restore_context(struct clk_hw *hw) 273 { 274 struct clk_generated *gck = to_clk_generated(hw); 275 276 if (gck->pms.status) 277 clk_generated_set(gck, gck->pms.status); 278 } 279 280 static const struct clk_ops generated_ops = { 281 .enable = clk_generated_enable, 282 .disable = clk_generated_disable, 283 .is_enabled = clk_generated_is_enabled, 284 .recalc_rate = clk_generated_recalc_rate, 285 .determine_rate = clk_generated_determine_rate, 286 .get_parent = clk_generated_get_parent, 287 .set_parent = clk_generated_set_parent, 288 .set_rate = clk_generated_set_rate, 289 .save_context = clk_generated_save_context, 290 .restore_context = clk_generated_restore_context, 291 }; 292 293 /** 294 * clk_generated_startup - Initialize a given clock to its default parent and 295 * divisor parameter. 296 * 297 * @gck: Generated clock to set the startup parameters for. 298 * 299 * Take parameters from the hardware and update local clock configuration 300 * accordingly. 301 */ 302 static void clk_generated_startup(struct clk_generated *gck) 303 { 304 u32 tmp; 305 unsigned long flags; 306 307 spin_lock_irqsave(gck->lock, flags); 308 regmap_write(gck->regmap, gck->layout->offset, 309 (gck->id & gck->layout->pid_mask)); 310 regmap_read(gck->regmap, gck->layout->offset, &tmp); 311 spin_unlock_irqrestore(gck->lock, flags); 312 313 gck->parent_id = field_get(gck->layout->gckcss_mask, tmp); 314 gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp); 315 } 316 317 struct clk_hw * __init 318 at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, 319 const struct clk_pcr_layout *layout, 320 const char *name, const char **parent_names, 321 u32 *mux_table, u8 num_parents, u8 id, 322 const struct clk_range *range, 323 int chg_pid) 324 { 325 struct clk_generated *gck; 326 struct clk_init_data init; 327 struct clk_hw *hw; 328 int ret; 329 330 gck = kzalloc(sizeof(*gck), GFP_KERNEL); 331 if (!gck) 332 return ERR_PTR(-ENOMEM); 333 334 init.name = name; 335 init.ops = &generated_ops; 336 init.parent_names = parent_names; 337 init.num_parents = num_parents; 338 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; 339 if (chg_pid >= 0) 340 init.flags |= CLK_SET_RATE_PARENT; 341 342 gck->id = id; 343 gck->hw.init = &init; 344 gck->regmap = regmap; 345 gck->lock = lock; 346 gck->range = *range; 347 gck->chg_pid = chg_pid; 348 gck->layout = layout; 349 gck->mux_table = mux_table; 350 351 clk_generated_startup(gck); 352 hw = &gck->hw; 353 ret = clk_hw_register(NULL, &gck->hw); 354 if (ret) { 355 kfree(gck); 356 hw = ERR_PTR(ret); 357 } 358 359 return hw; 360 } 361