1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __QCOM_TSENS_H__ 7 #define __QCOM_TSENS_H__ 8 9 #define NO_PT_CALIB 0x0 10 #define ONE_PT_CALIB 0x1 11 #define ONE_PT_CALIB2 0x2 12 #define TWO_PT_CALIB 0x3 13 #define CAL_DEGC_PT1 30 14 #define CAL_DEGC_PT2 120 15 #define SLOPE_FACTOR 1000 16 #define SLOPE_DEFAULT 3200 17 #define TIMEOUT_US 100 18 #define THRESHOLD_MAX_ADC_CODE 0x3ff 19 #define THRESHOLD_MIN_ADC_CODE 0x0 20 21 #define MAX_SENSORS 16 22 23 #include <linux/interrupt.h> 24 #include <linux/thermal.h> 25 #include <linux/regmap.h> 26 #include <linux/slab.h> 27 28 struct tsens_priv; 29 30 /* IP version numbers in ascending order */ 31 enum tsens_ver { 32 VER_0 = 0, 33 VER_0_1, 34 VER_1_X, 35 VER_2_X, 36 }; 37 38 enum tsens_irq_type { 39 LOWER, 40 UPPER, 41 CRITICAL, 42 }; 43 44 /** 45 * struct tsens_sensor - data for each sensor connected to the tsens device 46 * @priv: tsens device instance that this sensor is connected to 47 * @tzd: pointer to the thermal zone that this sensor is in 48 * @offset: offset of temperature adjustment curve 49 * @hw_id: HW ID can be used in case of platform-specific IDs 50 * @slope: slope of temperature adjustment curve 51 * @status: 8960-specific variable to track 8960 and 8660 status register offset 52 */ 53 struct tsens_sensor { 54 struct tsens_priv *priv; 55 struct thermal_zone_device *tzd; 56 int offset; 57 unsigned int hw_id; 58 int slope; 59 u32 status; 60 }; 61 62 /** 63 * struct tsens_ops - operations as supported by the tsens device 64 * @init: Function to initialize the tsens device 65 * @calibrate: Function to calibrate the tsens device 66 * @get_temp: Function which returns the temp in millidegC 67 * @enable: Function to enable (clocks/power) tsens device 68 * @disable: Function to disable the tsens device 69 * @suspend: Function to suspend the tsens device 70 * @resume: Function to resume the tsens device 71 */ 72 struct tsens_ops { 73 /* mandatory callbacks */ 74 int (*init)(struct tsens_priv *priv); 75 int (*calibrate)(struct tsens_priv *priv); 76 int (*get_temp)(const struct tsens_sensor *s, int *temp); 77 /* optional callbacks */ 78 int (*enable)(struct tsens_priv *priv, int i); 79 void (*disable)(struct tsens_priv *priv); 80 int (*suspend)(struct tsens_priv *priv); 81 int (*resume)(struct tsens_priv *priv); 82 }; 83 84 #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ 85 [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \ 86 [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \ 87 [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \ 88 [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \ 89 [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \ 90 [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \ 91 [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \ 92 [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \ 93 [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \ 94 [_name##_##9] = REG_FIELD(_offset + 36, _startbit, _stopbit), \ 95 [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit) 96 97 #define REG_FIELD_FOR_EACH_SENSOR16(_name, _offset, _startbit, _stopbit) \ 98 [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \ 99 [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \ 100 [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \ 101 [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \ 102 [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \ 103 [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \ 104 [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \ 105 [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \ 106 [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \ 107 [_name##_##9] = REG_FIELD(_offset + 36, _startbit, _stopbit), \ 108 [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit), \ 109 [_name##_##11] = REG_FIELD(_offset + 44, _startbit, _stopbit), \ 110 [_name##_##12] = REG_FIELD(_offset + 48, _startbit, _stopbit), \ 111 [_name##_##13] = REG_FIELD(_offset + 52, _startbit, _stopbit), \ 112 [_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \ 113 [_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit) 114 115 #define REG_FIELD_SPLIT_BITS_0_15(_name, _offset) \ 116 [_name##_##0] = REG_FIELD(_offset, 0, 0), \ 117 [_name##_##1] = REG_FIELD(_offset, 1, 1), \ 118 [_name##_##2] = REG_FIELD(_offset, 2, 2), \ 119 [_name##_##3] = REG_FIELD(_offset, 3, 3), \ 120 [_name##_##4] = REG_FIELD(_offset, 4, 4), \ 121 [_name##_##5] = REG_FIELD(_offset, 5, 5), \ 122 [_name##_##6] = REG_FIELD(_offset, 6, 6), \ 123 [_name##_##7] = REG_FIELD(_offset, 7, 7), \ 124 [_name##_##8] = REG_FIELD(_offset, 8, 8), \ 125 [_name##_##9] = REG_FIELD(_offset, 9, 9), \ 126 [_name##_##10] = REG_FIELD(_offset, 10, 10), \ 127 [_name##_##11] = REG_FIELD(_offset, 11, 11), \ 128 [_name##_##12] = REG_FIELD(_offset, 12, 12), \ 129 [_name##_##13] = REG_FIELD(_offset, 13, 13), \ 130 [_name##_##14] = REG_FIELD(_offset, 14, 14), \ 131 [_name##_##15] = REG_FIELD(_offset, 15, 15) 132 133 #define REG_FIELD_SPLIT_BITS_16_31(_name, _offset) \ 134 [_name##_##0] = REG_FIELD(_offset, 16, 16), \ 135 [_name##_##1] = REG_FIELD(_offset, 17, 17), \ 136 [_name##_##2] = REG_FIELD(_offset, 18, 18), \ 137 [_name##_##3] = REG_FIELD(_offset, 19, 19), \ 138 [_name##_##4] = REG_FIELD(_offset, 20, 20), \ 139 [_name##_##5] = REG_FIELD(_offset, 21, 21), \ 140 [_name##_##6] = REG_FIELD(_offset, 22, 22), \ 141 [_name##_##7] = REG_FIELD(_offset, 23, 23), \ 142 [_name##_##8] = REG_FIELD(_offset, 24, 24), \ 143 [_name##_##9] = REG_FIELD(_offset, 25, 25), \ 144 [_name##_##10] = REG_FIELD(_offset, 26, 26), \ 145 [_name##_##11] = REG_FIELD(_offset, 27, 27), \ 146 [_name##_##12] = REG_FIELD(_offset, 28, 28), \ 147 [_name##_##13] = REG_FIELD(_offset, 29, 29), \ 148 [_name##_##14] = REG_FIELD(_offset, 30, 30), \ 149 [_name##_##15] = REG_FIELD(_offset, 31, 31) 150 151 /* 152 * reg_field IDs to use as an index into an array 153 * If you change the order of the entries, check the devm_regmap_field_alloc() 154 * calls in init_common() 155 */ 156 enum regfield_ids { 157 /* ----- SROT ------ */ 158 /* HW_VER */ 159 VER_MAJOR, 160 VER_MINOR, 161 VER_STEP, 162 /* CTRL_OFFSET */ 163 TSENS_EN, 164 TSENS_SW_RST, 165 SENSOR_EN, 166 CODE_OR_TEMP, 167 168 /* ----- TM ------ */ 169 /* TRDY */ 170 TRDY, 171 /* INTERRUPT ENABLE */ 172 INT_EN, /* v2+ has separate enables for crit, upper and lower irq */ 173 /* STATUS */ 174 LAST_TEMP_0, /* Last temperature reading */ 175 LAST_TEMP_1, 176 LAST_TEMP_2, 177 LAST_TEMP_3, 178 LAST_TEMP_4, 179 LAST_TEMP_5, 180 LAST_TEMP_6, 181 LAST_TEMP_7, 182 LAST_TEMP_8, 183 LAST_TEMP_9, 184 LAST_TEMP_10, 185 LAST_TEMP_11, 186 LAST_TEMP_12, 187 LAST_TEMP_13, 188 LAST_TEMP_14, 189 LAST_TEMP_15, 190 VALID_0, /* VALID reading or not */ 191 VALID_1, 192 VALID_2, 193 VALID_3, 194 VALID_4, 195 VALID_5, 196 VALID_6, 197 VALID_7, 198 VALID_8, 199 VALID_9, 200 VALID_10, 201 VALID_11, 202 VALID_12, 203 VALID_13, 204 VALID_14, 205 VALID_15, 206 LOWER_STATUS_0, /* LOWER threshold violated */ 207 LOWER_STATUS_1, 208 LOWER_STATUS_2, 209 LOWER_STATUS_3, 210 LOWER_STATUS_4, 211 LOWER_STATUS_5, 212 LOWER_STATUS_6, 213 LOWER_STATUS_7, 214 LOWER_STATUS_8, 215 LOWER_STATUS_9, 216 LOWER_STATUS_10, 217 LOWER_STATUS_11, 218 LOWER_STATUS_12, 219 LOWER_STATUS_13, 220 LOWER_STATUS_14, 221 LOWER_STATUS_15, 222 LOW_INT_STATUS_0, /* LOWER interrupt status */ 223 LOW_INT_STATUS_1, 224 LOW_INT_STATUS_2, 225 LOW_INT_STATUS_3, 226 LOW_INT_STATUS_4, 227 LOW_INT_STATUS_5, 228 LOW_INT_STATUS_6, 229 LOW_INT_STATUS_7, 230 LOW_INT_STATUS_8, 231 LOW_INT_STATUS_9, 232 LOW_INT_STATUS_10, 233 LOW_INT_STATUS_11, 234 LOW_INT_STATUS_12, 235 LOW_INT_STATUS_13, 236 LOW_INT_STATUS_14, 237 LOW_INT_STATUS_15, 238 LOW_INT_CLEAR_0, /* LOWER interrupt clear */ 239 LOW_INT_CLEAR_1, 240 LOW_INT_CLEAR_2, 241 LOW_INT_CLEAR_3, 242 LOW_INT_CLEAR_4, 243 LOW_INT_CLEAR_5, 244 LOW_INT_CLEAR_6, 245 LOW_INT_CLEAR_7, 246 LOW_INT_CLEAR_8, 247 LOW_INT_CLEAR_9, 248 LOW_INT_CLEAR_10, 249 LOW_INT_CLEAR_11, 250 LOW_INT_CLEAR_12, 251 LOW_INT_CLEAR_13, 252 LOW_INT_CLEAR_14, 253 LOW_INT_CLEAR_15, 254 LOW_INT_MASK_0, /* LOWER interrupt mask */ 255 LOW_INT_MASK_1, 256 LOW_INT_MASK_2, 257 LOW_INT_MASK_3, 258 LOW_INT_MASK_4, 259 LOW_INT_MASK_5, 260 LOW_INT_MASK_6, 261 LOW_INT_MASK_7, 262 LOW_INT_MASK_8, 263 LOW_INT_MASK_9, 264 LOW_INT_MASK_10, 265 LOW_INT_MASK_11, 266 LOW_INT_MASK_12, 267 LOW_INT_MASK_13, 268 LOW_INT_MASK_14, 269 LOW_INT_MASK_15, 270 LOW_THRESH_0, /* LOWER threshold values */ 271 LOW_THRESH_1, 272 LOW_THRESH_2, 273 LOW_THRESH_3, 274 LOW_THRESH_4, 275 LOW_THRESH_5, 276 LOW_THRESH_6, 277 LOW_THRESH_7, 278 LOW_THRESH_8, 279 LOW_THRESH_9, 280 LOW_THRESH_10, 281 LOW_THRESH_11, 282 LOW_THRESH_12, 283 LOW_THRESH_13, 284 LOW_THRESH_14, 285 LOW_THRESH_15, 286 UPPER_STATUS_0, /* UPPER threshold violated */ 287 UPPER_STATUS_1, 288 UPPER_STATUS_2, 289 UPPER_STATUS_3, 290 UPPER_STATUS_4, 291 UPPER_STATUS_5, 292 UPPER_STATUS_6, 293 UPPER_STATUS_7, 294 UPPER_STATUS_8, 295 UPPER_STATUS_9, 296 UPPER_STATUS_10, 297 UPPER_STATUS_11, 298 UPPER_STATUS_12, 299 UPPER_STATUS_13, 300 UPPER_STATUS_14, 301 UPPER_STATUS_15, 302 UP_INT_STATUS_0, /* UPPER interrupt status */ 303 UP_INT_STATUS_1, 304 UP_INT_STATUS_2, 305 UP_INT_STATUS_3, 306 UP_INT_STATUS_4, 307 UP_INT_STATUS_5, 308 UP_INT_STATUS_6, 309 UP_INT_STATUS_7, 310 UP_INT_STATUS_8, 311 UP_INT_STATUS_9, 312 UP_INT_STATUS_10, 313 UP_INT_STATUS_11, 314 UP_INT_STATUS_12, 315 UP_INT_STATUS_13, 316 UP_INT_STATUS_14, 317 UP_INT_STATUS_15, 318 UP_INT_CLEAR_0, /* UPPER interrupt clear */ 319 UP_INT_CLEAR_1, 320 UP_INT_CLEAR_2, 321 UP_INT_CLEAR_3, 322 UP_INT_CLEAR_4, 323 UP_INT_CLEAR_5, 324 UP_INT_CLEAR_6, 325 UP_INT_CLEAR_7, 326 UP_INT_CLEAR_8, 327 UP_INT_CLEAR_9, 328 UP_INT_CLEAR_10, 329 UP_INT_CLEAR_11, 330 UP_INT_CLEAR_12, 331 UP_INT_CLEAR_13, 332 UP_INT_CLEAR_14, 333 UP_INT_CLEAR_15, 334 UP_INT_MASK_0, /* UPPER interrupt mask */ 335 UP_INT_MASK_1, 336 UP_INT_MASK_2, 337 UP_INT_MASK_3, 338 UP_INT_MASK_4, 339 UP_INT_MASK_5, 340 UP_INT_MASK_6, 341 UP_INT_MASK_7, 342 UP_INT_MASK_8, 343 UP_INT_MASK_9, 344 UP_INT_MASK_10, 345 UP_INT_MASK_11, 346 UP_INT_MASK_12, 347 UP_INT_MASK_13, 348 UP_INT_MASK_14, 349 UP_INT_MASK_15, 350 UP_THRESH_0, /* UPPER threshold values */ 351 UP_THRESH_1, 352 UP_THRESH_2, 353 UP_THRESH_3, 354 UP_THRESH_4, 355 UP_THRESH_5, 356 UP_THRESH_6, 357 UP_THRESH_7, 358 UP_THRESH_8, 359 UP_THRESH_9, 360 UP_THRESH_10, 361 UP_THRESH_11, 362 UP_THRESH_12, 363 UP_THRESH_13, 364 UP_THRESH_14, 365 UP_THRESH_15, 366 CRITICAL_STATUS_0, /* CRITICAL threshold violated */ 367 CRITICAL_STATUS_1, 368 CRITICAL_STATUS_2, 369 CRITICAL_STATUS_3, 370 CRITICAL_STATUS_4, 371 CRITICAL_STATUS_5, 372 CRITICAL_STATUS_6, 373 CRITICAL_STATUS_7, 374 CRITICAL_STATUS_8, 375 CRITICAL_STATUS_9, 376 CRITICAL_STATUS_10, 377 CRITICAL_STATUS_11, 378 CRITICAL_STATUS_12, 379 CRITICAL_STATUS_13, 380 CRITICAL_STATUS_14, 381 CRITICAL_STATUS_15, 382 CRIT_INT_STATUS_0, /* CRITICAL interrupt status */ 383 CRIT_INT_STATUS_1, 384 CRIT_INT_STATUS_2, 385 CRIT_INT_STATUS_3, 386 CRIT_INT_STATUS_4, 387 CRIT_INT_STATUS_5, 388 CRIT_INT_STATUS_6, 389 CRIT_INT_STATUS_7, 390 CRIT_INT_STATUS_8, 391 CRIT_INT_STATUS_9, 392 CRIT_INT_STATUS_10, 393 CRIT_INT_STATUS_11, 394 CRIT_INT_STATUS_12, 395 CRIT_INT_STATUS_13, 396 CRIT_INT_STATUS_14, 397 CRIT_INT_STATUS_15, 398 CRIT_INT_CLEAR_0, /* CRITICAL interrupt clear */ 399 CRIT_INT_CLEAR_1, 400 CRIT_INT_CLEAR_2, 401 CRIT_INT_CLEAR_3, 402 CRIT_INT_CLEAR_4, 403 CRIT_INT_CLEAR_5, 404 CRIT_INT_CLEAR_6, 405 CRIT_INT_CLEAR_7, 406 CRIT_INT_CLEAR_8, 407 CRIT_INT_CLEAR_9, 408 CRIT_INT_CLEAR_10, 409 CRIT_INT_CLEAR_11, 410 CRIT_INT_CLEAR_12, 411 CRIT_INT_CLEAR_13, 412 CRIT_INT_CLEAR_14, 413 CRIT_INT_CLEAR_15, 414 CRIT_INT_MASK_0, /* CRITICAL interrupt mask */ 415 CRIT_INT_MASK_1, 416 CRIT_INT_MASK_2, 417 CRIT_INT_MASK_3, 418 CRIT_INT_MASK_4, 419 CRIT_INT_MASK_5, 420 CRIT_INT_MASK_6, 421 CRIT_INT_MASK_7, 422 CRIT_INT_MASK_8, 423 CRIT_INT_MASK_9, 424 CRIT_INT_MASK_10, 425 CRIT_INT_MASK_11, 426 CRIT_INT_MASK_12, 427 CRIT_INT_MASK_13, 428 CRIT_INT_MASK_14, 429 CRIT_INT_MASK_15, 430 CRIT_THRESH_0, /* CRITICAL threshold values */ 431 CRIT_THRESH_1, 432 CRIT_THRESH_2, 433 CRIT_THRESH_3, 434 CRIT_THRESH_4, 435 CRIT_THRESH_5, 436 CRIT_THRESH_6, 437 CRIT_THRESH_7, 438 CRIT_THRESH_8, 439 CRIT_THRESH_9, 440 CRIT_THRESH_10, 441 CRIT_THRESH_11, 442 CRIT_THRESH_12, 443 CRIT_THRESH_13, 444 CRIT_THRESH_14, 445 CRIT_THRESH_15, 446 447 /* WATCHDOG */ 448 WDOG_BARK_STATUS, 449 WDOG_BARK_CLEAR, 450 WDOG_BARK_MASK, 451 WDOG_BARK_COUNT, 452 453 /* CYCLE COMPLETION MONITOR */ 454 CC_MON_STATUS, 455 CC_MON_CLEAR, 456 CC_MON_MASK, 457 458 MIN_STATUS_0, /* MIN threshold violated */ 459 MIN_STATUS_1, 460 MIN_STATUS_2, 461 MIN_STATUS_3, 462 MIN_STATUS_4, 463 MIN_STATUS_5, 464 MIN_STATUS_6, 465 MIN_STATUS_7, 466 MIN_STATUS_8, 467 MIN_STATUS_9, 468 MIN_STATUS_10, 469 MIN_STATUS_11, 470 MIN_STATUS_12, 471 MIN_STATUS_13, 472 MIN_STATUS_14, 473 MIN_STATUS_15, 474 MAX_STATUS_0, /* MAX threshold violated */ 475 MAX_STATUS_1, 476 MAX_STATUS_2, 477 MAX_STATUS_3, 478 MAX_STATUS_4, 479 MAX_STATUS_5, 480 MAX_STATUS_6, 481 MAX_STATUS_7, 482 MAX_STATUS_8, 483 MAX_STATUS_9, 484 MAX_STATUS_10, 485 MAX_STATUS_11, 486 MAX_STATUS_12, 487 MAX_STATUS_13, 488 MAX_STATUS_14, 489 MAX_STATUS_15, 490 491 /* Keep last */ 492 MAX_REGFIELDS 493 }; 494 495 /** 496 * struct tsens_features - Features supported by the IP 497 * @ver_major: Major number of IP version 498 * @crit_int: does the IP support critical interrupts? 499 * @combo_int: does the IP use one IRQ for up, low and critical thresholds? 500 * @adc: do the sensors only output adc code (instead of temperature)? 501 * @srot_split: does the IP neatly splits the register space into SROT and TM, 502 * with SROT only being available to secure boot firmware? 503 * @has_watchdog: does this IP support watchdog functionality? 504 * @max_sensors: maximum sensors supported by this version of the IP 505 * @trip_min_temp: minimum trip temperature supported by this version of the IP 506 * @trip_max_temp: maximum trip temperature supported by this version of the IP 507 */ 508 struct tsens_features { 509 unsigned int ver_major; 510 unsigned int crit_int:1; 511 unsigned int combo_int:1; 512 unsigned int adc:1; 513 unsigned int srot_split:1; 514 unsigned int has_watchdog:1; 515 unsigned int max_sensors; 516 int trip_min_temp; 517 int trip_max_temp; 518 }; 519 520 /** 521 * struct tsens_plat_data - tsens compile-time platform data 522 * @num_sensors: Number of sensors supported by platform 523 * @ops: operations the tsens instance supports 524 * @hw_ids: Subset of sensors ids supported by platform, if not the first n 525 * @feat: features of the IP 526 * @fields: bitfield locations 527 */ 528 struct tsens_plat_data { 529 const u32 num_sensors; 530 const struct tsens_ops *ops; 531 unsigned int *hw_ids; 532 struct tsens_features *feat; 533 const struct reg_field *fields; 534 }; 535 536 /** 537 * struct tsens_context - Registers to be saved/restored across a context loss 538 * @threshold: Threshold register value 539 * @control: Control register value 540 */ 541 struct tsens_context { 542 int threshold; 543 int control; 544 }; 545 546 /** 547 * struct tsens_priv - private data for each instance of the tsens IP 548 * @dev: pointer to struct device 549 * @num_sensors: number of sensors enabled on this device 550 * @tm_map: pointer to TM register address space 551 * @srot_map: pointer to SROT register address space 552 * @tm_offset: deal with old device trees that don't address TM and SROT 553 * address space separately 554 * @ul_lock: lock while processing upper/lower threshold interrupts 555 * @crit_lock: lock while processing critical threshold interrupts 556 * @rf: array of regmap_fields used to store value of the field 557 * @ctx: registers to be saved and restored during suspend/resume 558 * @feat: features of the IP 559 * @fields: bitfield locations 560 * @ops: pointer to list of callbacks supported by this device 561 * @debug_root: pointer to debugfs dentry for all tsens 562 * @debug: pointer to debugfs dentry for tsens controller 563 * @sensor: list of sensors attached to this device 564 */ 565 struct tsens_priv { 566 struct device *dev; 567 u32 num_sensors; 568 struct regmap *tm_map; 569 struct regmap *srot_map; 570 u32 tm_offset; 571 572 /* lock for upper/lower threshold interrupts */ 573 spinlock_t ul_lock; 574 575 struct regmap_field *rf[MAX_REGFIELDS]; 576 struct tsens_context ctx; 577 struct tsens_features *feat; 578 const struct reg_field *fields; 579 const struct tsens_ops *ops; 580 581 struct dentry *debug_root; 582 struct dentry *debug; 583 584 struct tsens_sensor sensor[]; 585 }; 586 587 /** 588 * struct tsens_single_value - internal representation of a single field inside nvmem calibration data 589 * @idx: index into the u32 data array 590 * @shift: the shift of the first bit in the value 591 * @blob: index of the data blob to use for this cell 592 */ 593 struct tsens_single_value { 594 u8 idx; 595 u8 shift; 596 u8 blob; 597 }; 598 599 /** 600 * struct tsens_legacy_calibration_format - description of calibration data used when parsing the legacy nvmem blob 601 * @base_len: the length of the base fields inside calibration data 602 * @base_shift: the shift to be applied to base data 603 * @sp_len: the length of the sN_pM fields inside calibration data 604 * @mode: descriptor of the calibration mode field 605 * @invalid: descriptor of the calibration mode invalid field 606 * @base: descriptors of the base0 and base1 fields 607 * @sp: descriptors of the sN_pM fields 608 */ 609 struct tsens_legacy_calibration_format { 610 unsigned int base_len; 611 unsigned int base_shift; 612 unsigned int sp_len; 613 /* just two bits */ 614 struct tsens_single_value mode; 615 /* on all platforms except 8974 invalid is the third bit of what downstream calls 'mode' */ 616 struct tsens_single_value invalid; 617 struct tsens_single_value base[2]; 618 struct tsens_single_value sp[][2]; 619 }; 620 621 char *qfprom_read(struct device *dev, const char *cname); 622 int tsens_read_calibration_legacy(struct tsens_priv *priv, 623 const struct tsens_legacy_calibration_format *format, 624 u32 *p1, u32 *p2, 625 u32 *cdata, u32 *csel); 626 int tsens_read_calibration(struct tsens_priv *priv, int shift, u32 *p1, u32 *p2, bool backup); 627 int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift); 628 int tsens_calibrate_common(struct tsens_priv *priv); 629 void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode); 630 int init_common(struct tsens_priv *priv); 631 int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp); 632 int get_temp_common(const struct tsens_sensor *s, int *temp); 633 634 /* TSENS target */ 635 extern struct tsens_plat_data data_8960; 636 637 /* TSENS v0.1 targets */ 638 extern struct tsens_plat_data data_8916, data_8939, data_8974, data_9607; 639 640 /* TSENS v1 targets */ 641 extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956; 642 643 /* TSENS v2 targets */ 644 extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; 645 646 #endif /* __QCOM_TSENS_H__ */ 647