1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <net/mac80211.h> 17 #include "util.h" 18 #include "testmode.h" 19 20 #define MT_MCU_RING_SIZE 32 21 #define MT_RX_BUF_SIZE 2048 22 #define MT_SKB_HEAD_LEN 128 23 24 #define MT_MAX_NON_AQL_PKT 16 25 #define MT_TXQ_FREE_THR 32 26 27 #define MT76_TOKEN_FREE_THR 64 28 29 struct mt76_dev; 30 struct mt76_phy; 31 struct mt76_wcid; 32 struct mt76s_intr; 33 34 struct mt76_reg_pair { 35 u32 reg; 36 u32 value; 37 }; 38 39 enum mt76_bus_type { 40 MT76_BUS_MMIO, 41 MT76_BUS_USB, 42 MT76_BUS_SDIO, 43 }; 44 45 struct mt76_bus_ops { 46 u32 (*rr)(struct mt76_dev *dev, u32 offset); 47 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 48 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 49 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 50 int len); 51 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 52 int len); 53 int (*wr_rp)(struct mt76_dev *dev, u32 base, 54 const struct mt76_reg_pair *rp, int len); 55 int (*rd_rp)(struct mt76_dev *dev, u32 base, 56 struct mt76_reg_pair *rp, int len); 57 enum mt76_bus_type type; 58 }; 59 60 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 61 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 62 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 63 64 enum mt76_txq_id { 65 MT_TXQ_VO = IEEE80211_AC_VO, 66 MT_TXQ_VI = IEEE80211_AC_VI, 67 MT_TXQ_BE = IEEE80211_AC_BE, 68 MT_TXQ_BK = IEEE80211_AC_BK, 69 MT_TXQ_PSD, 70 MT_TXQ_BEACON, 71 MT_TXQ_CAB, 72 __MT_TXQ_MAX 73 }; 74 75 enum mt76_mcuq_id { 76 MT_MCUQ_WM, 77 MT_MCUQ_WA, 78 MT_MCUQ_FWDL, 79 __MT_MCUQ_MAX 80 }; 81 82 enum mt76_rxq_id { 83 MT_RXQ_MAIN, 84 MT_RXQ_MCU, 85 MT_RXQ_MCU_WA, 86 MT_RXQ_EXT, 87 MT_RXQ_EXT_WA, 88 __MT_RXQ_MAX 89 }; 90 91 enum mt76_cipher_type { 92 MT_CIPHER_NONE, 93 MT_CIPHER_WEP40, 94 MT_CIPHER_TKIP, 95 MT_CIPHER_TKIP_NO_MIC, 96 MT_CIPHER_AES_CCMP, 97 MT_CIPHER_WEP104, 98 MT_CIPHER_BIP_CMAC_128, 99 MT_CIPHER_WEP128, 100 MT_CIPHER_WAPI, 101 MT_CIPHER_CCMP_CCX, 102 MT_CIPHER_CCMP_256, 103 MT_CIPHER_GCMP, 104 MT_CIPHER_GCMP_256, 105 }; 106 107 struct mt76_queue_buf { 108 dma_addr_t addr; 109 u16 len; 110 bool skip_unmap; 111 }; 112 113 struct mt76_tx_info { 114 struct mt76_queue_buf buf[32]; 115 struct sk_buff *skb; 116 int nbuf; 117 u32 info; 118 }; 119 120 struct mt76_queue_entry { 121 union { 122 void *buf; 123 struct sk_buff *skb; 124 }; 125 union { 126 struct mt76_txwi_cache *txwi; 127 struct urb *urb; 128 int buf_sz; 129 }; 130 u32 dma_addr[2]; 131 u16 dma_len[2]; 132 u16 wcid; 133 bool skip_buf0:1; 134 bool skip_buf1:1; 135 bool done:1; 136 }; 137 138 struct mt76_queue_regs { 139 u32 desc_base; 140 u32 ring_size; 141 u32 cpu_idx; 142 u32 dma_idx; 143 } __packed __aligned(4); 144 145 struct mt76_queue { 146 struct mt76_queue_regs __iomem *regs; 147 148 spinlock_t lock; 149 spinlock_t cleanup_lock; 150 struct mt76_queue_entry *entry; 151 struct mt76_desc *desc; 152 153 u16 first; 154 u16 head; 155 u16 tail; 156 int ndesc; 157 int queued; 158 int buf_size; 159 bool stopped; 160 bool blocked; 161 162 u8 buf_offset; 163 u8 hw_idx; 164 u8 qid; 165 166 dma_addr_t desc_dma; 167 struct sk_buff *rx_head; 168 struct page_frag_cache rx_page; 169 }; 170 171 struct mt76_mcu_ops { 172 u32 headroom; 173 u32 tailroom; 174 175 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 176 int len, bool wait_resp); 177 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 178 int cmd, int *seq); 179 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 180 struct sk_buff *skb, int seq); 181 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 182 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 183 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 184 const struct mt76_reg_pair *rp, int len); 185 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 186 struct mt76_reg_pair *rp, int len); 187 int (*mcu_restart)(struct mt76_dev *dev); 188 }; 189 190 struct mt76_queue_ops { 191 int (*init)(struct mt76_dev *dev, 192 int (*poll)(struct napi_struct *napi, int budget)); 193 194 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 195 int idx, int n_desc, int bufsize, 196 u32 ring_base); 197 198 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 199 struct sk_buff *skb, struct mt76_wcid *wcid, 200 struct ieee80211_sta *sta); 201 202 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 203 struct sk_buff *skb, u32 tx_info); 204 205 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 206 int *len, u32 *info, bool *more); 207 208 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 209 210 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 211 bool flush); 212 213 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 214 215 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 216 217 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 218 }; 219 220 enum mt76_wcid_flags { 221 MT_WCID_FLAG_CHECK_PS, 222 MT_WCID_FLAG_PS, 223 MT_WCID_FLAG_4ADDR, 224 MT_WCID_FLAG_HDR_TRANS, 225 }; 226 227 #define MT76_N_WCIDS 288 228 229 /* stored in ieee80211_tx_info::hw_queue */ 230 #define MT_TX_HW_QUEUE_EXT_PHY BIT(3) 231 232 DECLARE_EWMA(signal, 10, 8); 233 234 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 235 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 236 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 237 #define MT_WCID_TX_INFO_SET BIT(31) 238 239 struct mt76_wcid { 240 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 241 242 atomic_t non_aql_packets; 243 unsigned long flags; 244 245 struct ewma_signal rssi; 246 int inactive_count; 247 248 struct rate_info rate; 249 250 u16 idx; 251 u8 hw_key_idx; 252 u8 hw_key_idx2; 253 254 u8 sta:1; 255 u8 ext_phy:1; 256 u8 amsdu:1; 257 258 u8 rx_check_pn; 259 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 260 u16 cipher; 261 262 u32 tx_info; 263 bool sw_iv; 264 265 struct list_head list; 266 struct idr pktid; 267 }; 268 269 struct mt76_txq { 270 struct mt76_wcid *wcid; 271 272 u16 agg_ssn; 273 bool send_bar; 274 bool aggr; 275 }; 276 277 struct mt76_txwi_cache { 278 struct list_head list; 279 dma_addr_t dma_addr; 280 281 struct sk_buff *skb; 282 }; 283 284 struct mt76_rx_tid { 285 struct rcu_head rcu_head; 286 287 struct mt76_dev *dev; 288 289 spinlock_t lock; 290 struct delayed_work reorder_work; 291 292 u16 head; 293 u16 size; 294 u16 nframes; 295 296 u8 num; 297 298 u8 started:1, stopped:1, timer_pending:1; 299 300 struct sk_buff *reorder_buf[]; 301 }; 302 303 #define MT_TX_CB_DMA_DONE BIT(0) 304 #define MT_TX_CB_TXS_DONE BIT(1) 305 #define MT_TX_CB_TXS_FAILED BIT(2) 306 307 #define MT_PACKET_ID_MASK GENMASK(6, 0) 308 #define MT_PACKET_ID_NO_ACK 0 309 #define MT_PACKET_ID_NO_SKB 1 310 #define MT_PACKET_ID_FIRST 2 311 #define MT_PACKET_ID_HAS_RATE BIT(7) 312 /* This is timer for when to give up when waiting for TXS callback, 313 * with starting time being the time at which the DMA_DONE callback 314 * was seen (so, we know packet was processed then, it should not take 315 * long after that for firmware to send the TXS callback if it is going 316 * to do so.) 317 */ 318 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 319 320 struct mt76_tx_cb { 321 unsigned long jiffies; 322 u16 wcid; 323 u8 pktid; 324 u8 flags; 325 }; 326 327 enum { 328 MT76_STATE_INITIALIZED, 329 MT76_STATE_RUNNING, 330 MT76_STATE_MCU_RUNNING, 331 MT76_SCANNING, 332 MT76_HW_SCANNING, 333 MT76_HW_SCHED_SCANNING, 334 MT76_RESTART, 335 MT76_RESET, 336 MT76_MCU_RESET, 337 MT76_REMOVED, 338 MT76_READING_STATS, 339 MT76_STATE_POWER_OFF, 340 MT76_STATE_SUSPEND, 341 MT76_STATE_ROC, 342 MT76_STATE_PM, 343 }; 344 345 struct mt76_hw_cap { 346 bool has_2ghz; 347 bool has_5ghz; 348 bool has_6ghz; 349 }; 350 351 #define MT_DRV_TXWI_NO_FREE BIT(0) 352 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 353 #define MT_DRV_SW_RX_AIRTIME BIT(2) 354 #define MT_DRV_RX_DMA_HDR BIT(3) 355 #define MT_DRV_HW_MGMT_TXQ BIT(4) 356 357 struct mt76_driver_ops { 358 u32 drv_flags; 359 u32 survey_flags; 360 u16 txwi_size; 361 u16 token_size; 362 u8 mcs_rates; 363 364 void (*update_survey)(struct mt76_phy *phy); 365 366 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 367 enum mt76_txq_id qid, struct mt76_wcid *wcid, 368 struct ieee80211_sta *sta, 369 struct mt76_tx_info *tx_info); 370 371 void (*tx_complete_skb)(struct mt76_dev *dev, 372 struct mt76_queue_entry *e); 373 374 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 375 376 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 377 378 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 379 struct sk_buff *skb); 380 381 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 382 383 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 384 bool ps); 385 386 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 387 struct ieee80211_sta *sta); 388 389 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 390 struct ieee80211_sta *sta); 391 392 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 393 struct ieee80211_sta *sta); 394 }; 395 396 struct mt76_channel_state { 397 u64 cc_active; 398 u64 cc_busy; 399 u64 cc_rx; 400 u64 cc_bss_rx; 401 u64 cc_tx; 402 403 s8 noise; 404 }; 405 406 struct mt76_sband { 407 struct ieee80211_supported_band sband; 408 struct mt76_channel_state *chan; 409 }; 410 411 struct mt76_rate_power { 412 union { 413 struct { 414 s8 cck[4]; 415 s8 ofdm[8]; 416 s8 stbc[10]; 417 s8 ht[16]; 418 s8 vht[10]; 419 }; 420 s8 all[48]; 421 }; 422 }; 423 424 /* addr req mask */ 425 #define MT_VEND_TYPE_EEPROM BIT(31) 426 #define MT_VEND_TYPE_CFG BIT(30) 427 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 428 429 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 430 enum mt_vendor_req { 431 MT_VEND_DEV_MODE = 0x1, 432 MT_VEND_WRITE = 0x2, 433 MT_VEND_POWER_ON = 0x4, 434 MT_VEND_MULTI_WRITE = 0x6, 435 MT_VEND_MULTI_READ = 0x7, 436 MT_VEND_READ_EEPROM = 0x9, 437 MT_VEND_WRITE_FCE = 0x42, 438 MT_VEND_WRITE_CFG = 0x46, 439 MT_VEND_READ_CFG = 0x47, 440 MT_VEND_READ_EXT = 0x63, 441 MT_VEND_WRITE_EXT = 0x66, 442 MT_VEND_FEATURE_SET = 0x91, 443 }; 444 445 enum mt76u_in_ep { 446 MT_EP_IN_PKT_RX, 447 MT_EP_IN_CMD_RESP, 448 __MT_EP_IN_MAX, 449 }; 450 451 enum mt76u_out_ep { 452 MT_EP_OUT_INBAND_CMD, 453 MT_EP_OUT_AC_BE, 454 MT_EP_OUT_AC_BK, 455 MT_EP_OUT_AC_VI, 456 MT_EP_OUT_AC_VO, 457 MT_EP_OUT_HCCA, 458 __MT_EP_OUT_MAX, 459 }; 460 461 struct mt76_mcu { 462 struct mutex mutex; 463 u32 msg_seq; 464 int timeout; 465 466 struct sk_buff_head res_q; 467 wait_queue_head_t wait; 468 }; 469 470 #define MT_TX_SG_MAX_SIZE 8 471 #define MT_RX_SG_MAX_SIZE 4 472 #define MT_NUM_TX_ENTRIES 256 473 #define MT_NUM_RX_ENTRIES 128 474 #define MCU_RESP_URB_SIZE 1024 475 struct mt76_usb { 476 struct mutex usb_ctrl_mtx; 477 u8 *data; 478 u16 data_len; 479 480 struct mt76_worker status_worker; 481 struct mt76_worker rx_worker; 482 483 struct work_struct stat_work; 484 485 u8 out_ep[__MT_EP_OUT_MAX]; 486 u8 in_ep[__MT_EP_IN_MAX]; 487 bool sg_en; 488 489 struct mt76u_mcu { 490 u8 *data; 491 /* multiple reads */ 492 struct mt76_reg_pair *rp; 493 int rp_len; 494 u32 base; 495 bool burst; 496 } mcu; 497 }; 498 499 #define MT76S_XMIT_BUF_SZ (16 * PAGE_SIZE) 500 #define MT76S_NUM_TX_ENTRIES 256 501 #define MT76S_NUM_RX_ENTRIES 512 502 struct mt76_sdio { 503 struct mt76_worker txrx_worker; 504 struct mt76_worker status_worker; 505 struct mt76_worker net_worker; 506 507 struct work_struct stat_work; 508 509 u8 *xmit_buf[IEEE80211_NUM_ACS + 2]; 510 511 struct sdio_func *func; 512 void *intr_data; 513 u8 hw_ver; 514 wait_queue_head_t wait; 515 516 struct { 517 int pse_data_quota; 518 int ple_data_quota; 519 int pse_mcu_quota; 520 int pse_page_size; 521 int deficit; 522 } sched; 523 524 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 525 }; 526 527 struct mt76_mmio { 528 void __iomem *regs; 529 spinlock_t irq_lock; 530 u32 irqmask; 531 }; 532 533 struct mt76_rx_status { 534 union { 535 struct mt76_wcid *wcid; 536 u16 wcid_idx; 537 }; 538 539 u32 reorder_time; 540 541 u32 ampdu_ref; 542 u32 timestamp; 543 544 u8 iv[6]; 545 546 u8 ext_phy:1; 547 u8 aggr:1; 548 u8 qos_ctl; 549 u16 seqno; 550 551 u16 freq; 552 u32 flag; 553 u8 enc_flags; 554 u8 encoding:2, bw:3, he_ru:3; 555 u8 he_gi:2, he_dcm:1; 556 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 557 u8 rate_idx; 558 u8 nss; 559 u8 band; 560 s8 signal; 561 u8 chains; 562 s8 chain_signal[IEEE80211_MAX_CHAINS]; 563 }; 564 565 struct mt76_freq_range_power { 566 const struct cfg80211_sar_freq_ranges *range; 567 s8 power; 568 }; 569 570 struct mt76_testmode_ops { 571 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 572 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 573 enum mt76_testmode_state new_state); 574 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 575 }; 576 577 struct mt76_testmode_data { 578 enum mt76_testmode_state state; 579 580 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 581 struct sk_buff *tx_skb; 582 583 u32 tx_count; 584 u16 tx_mpdu_len; 585 586 u8 tx_rate_mode; 587 u8 tx_rate_idx; 588 u8 tx_rate_nss; 589 u8 tx_rate_sgi; 590 u8 tx_rate_ldpc; 591 u8 tx_rate_stbc; 592 u8 tx_ltf; 593 594 u8 tx_antenna_mask; 595 u8 tx_spe_idx; 596 597 u8 tx_duty_cycle; 598 u32 tx_time; 599 u32 tx_ipg; 600 601 u32 freq_offset; 602 603 u8 tx_power[4]; 604 u8 tx_power_control; 605 606 u8 addr[3][ETH_ALEN]; 607 608 u32 tx_pending; 609 u32 tx_queued; 610 u16 tx_queued_limit; 611 u32 tx_done; 612 struct { 613 u64 packets[__MT_RXQ_MAX]; 614 u64 fcs_error[__MT_RXQ_MAX]; 615 } rx_stats; 616 }; 617 618 struct mt76_vif { 619 u8 idx; 620 u8 omac_idx; 621 u8 band_idx; 622 u8 wmm_idx; 623 u8 scan_seq_num; 624 }; 625 626 struct mt76_phy { 627 struct ieee80211_hw *hw; 628 struct mt76_dev *dev; 629 void *priv; 630 631 unsigned long state; 632 633 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 634 635 struct cfg80211_chan_def chandef; 636 struct ieee80211_channel *main_chan; 637 638 struct mt76_channel_state *chan_state; 639 ktime_t survey_time; 640 641 struct mt76_hw_cap cap; 642 struct mt76_sband sband_2g; 643 struct mt76_sband sband_5g; 644 struct mt76_sband sband_6g; 645 646 u8 macaddr[ETH_ALEN]; 647 648 int txpower_cur; 649 u8 antenna_mask; 650 u16 chainmask; 651 652 #ifdef CONFIG_NL80211_TESTMODE 653 struct mt76_testmode_data test; 654 #endif 655 656 struct delayed_work mac_work; 657 u8 mac_work_count; 658 659 struct { 660 struct sk_buff *head; 661 struct sk_buff **tail; 662 u16 seqno; 663 } rx_amsdu[__MT_RXQ_MAX]; 664 665 struct mt76_freq_range_power *frp; 666 }; 667 668 struct mt76_dev { 669 struct mt76_phy phy; /* must be first */ 670 671 struct mt76_phy *phy2; 672 673 struct ieee80211_hw *hw; 674 675 spinlock_t lock; 676 spinlock_t cc_lock; 677 678 u32 cur_cc_bss_rx; 679 680 struct mt76_rx_status rx_ampdu_status; 681 u32 rx_ampdu_len; 682 u32 rx_ampdu_ref; 683 684 struct mutex mutex; 685 686 const struct mt76_bus_ops *bus; 687 const struct mt76_driver_ops *drv; 688 const struct mt76_mcu_ops *mcu_ops; 689 struct device *dev; 690 691 struct mt76_mcu mcu; 692 693 struct net_device napi_dev; 694 struct net_device tx_napi_dev; 695 spinlock_t rx_lock; 696 struct napi_struct napi[__MT_RXQ_MAX]; 697 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 698 699 struct list_head txwi_cache; 700 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 701 struct mt76_queue q_rx[__MT_RXQ_MAX]; 702 const struct mt76_queue_ops *queue_ops; 703 int tx_dma_idx[4]; 704 705 struct mt76_worker tx_worker; 706 struct napi_struct tx_napi; 707 708 spinlock_t token_lock; 709 struct idr token; 710 int token_count; 711 712 wait_queue_head_t tx_wait; 713 /* spinclock used to protect wcid pktid linked list */ 714 spinlock_t status_lock; 715 716 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 717 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 718 719 u32 vif_mask; 720 721 struct mt76_wcid global_wcid; 722 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 723 struct list_head wcid_list; 724 725 u32 rev; 726 727 u32 aggr_stats[32]; 728 729 struct tasklet_struct pre_tbtt_tasklet; 730 int beacon_int; 731 u8 beacon_mask; 732 733 struct debugfs_blob_wrapper eeprom; 734 struct debugfs_blob_wrapper otp; 735 736 struct mt76_rate_power rate_power; 737 738 char alpha2[3]; 739 enum nl80211_dfs_regions region; 740 741 u32 debugfs_reg; 742 743 struct led_classdev led_cdev; 744 char led_name[32]; 745 bool led_al; 746 u8 led_pin; 747 748 u8 csa_complete; 749 750 u32 rxfilter; 751 752 #ifdef CONFIG_NL80211_TESTMODE 753 const struct mt76_testmode_ops *test_ops; 754 struct { 755 const char *name; 756 u32 offset; 757 } test_mtd; 758 #endif 759 struct workqueue_struct *wq; 760 761 union { 762 struct mt76_mmio mmio; 763 struct mt76_usb usb; 764 struct mt76_sdio sdio; 765 }; 766 }; 767 768 struct mt76_power_limits { 769 s8 cck[4]; 770 s8 ofdm[8]; 771 s8 mcs[4][10]; 772 s8 ru[7][12]; 773 }; 774 775 enum mt76_phy_type { 776 MT_PHY_TYPE_CCK, 777 MT_PHY_TYPE_OFDM, 778 MT_PHY_TYPE_HT, 779 MT_PHY_TYPE_HT_GF, 780 MT_PHY_TYPE_VHT, 781 MT_PHY_TYPE_HE_SU = 8, 782 MT_PHY_TYPE_HE_EXT_SU, 783 MT_PHY_TYPE_HE_TB, 784 MT_PHY_TYPE_HE_MU, 785 __MT_PHY_TYPE_HE_MAX, 786 }; 787 788 struct mt76_sta_stats { 789 u64 tx_mode[__MT_PHY_TYPE_HE_MAX]; 790 u64 tx_bw[4]; /* 20, 40, 80, 160 */ 791 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 792 u64 tx_mcs[16]; /* mcs idx */ 793 }; 794 795 struct mt76_ethtool_worker_info { 796 u64 *data; 797 int idx; 798 int initial_stat_idx; 799 int worker_stat_count; 800 int sta_count; 801 }; 802 803 #define CCK_RATE(_idx, _rate) { \ 804 .bitrate = _rate, \ 805 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 806 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 807 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 808 } 809 810 #define OFDM_RATE(_idx, _rate) { \ 811 .bitrate = _rate, \ 812 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 813 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 814 } 815 816 extern struct ieee80211_rate mt76_rates[12]; 817 818 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 819 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 820 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 821 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 822 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 823 824 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 825 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 826 827 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 828 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 829 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 830 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 831 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 832 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 833 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 834 835 836 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 837 #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev)) 838 839 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 840 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 841 842 #define mt76_get_field(_dev, _reg, _field) \ 843 FIELD_GET(_field, mt76_rr(dev, _reg)) 844 845 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 846 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 847 848 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 849 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 850 851 #define mt76_hw(dev) (dev)->mphy.hw 852 853 static inline struct ieee80211_hw * 854 mt76_wcid_hw(struct mt76_dev *dev, u16 wcid) 855 { 856 if (wcid <= MT76_N_WCIDS && 857 mt76_wcid_mask_test(dev->wcid_phy_mask, wcid)) 858 return dev->phy2->hw; 859 860 return dev->phy.hw; 861 } 862 863 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 864 int timeout); 865 866 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 867 868 bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 869 int timeout); 870 871 #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 872 873 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 874 void mt76_pci_disable_aspm(struct pci_dev *pdev); 875 876 static inline u16 mt76_chip(struct mt76_dev *dev) 877 { 878 return dev->rev >> 16; 879 } 880 881 static inline u16 mt76_rev(struct mt76_dev *dev) 882 { 883 return dev->rev & 0xffff; 884 } 885 886 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 887 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 888 889 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 890 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 891 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 892 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 893 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 894 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 895 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 896 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 897 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 898 899 #define mt76_for_each_q_rx(dev, i) \ 900 for (i = 0; i < ARRAY_SIZE((dev)->q_rx) && \ 901 (dev)->q_rx[i].ndesc; i++) 902 903 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 904 const struct ieee80211_ops *ops, 905 const struct mt76_driver_ops *drv_ops); 906 int mt76_register_device(struct mt76_dev *dev, bool vht, 907 struct ieee80211_rate *rates, int n_rates); 908 void mt76_unregister_device(struct mt76_dev *dev); 909 void mt76_free_device(struct mt76_dev *dev); 910 void mt76_unregister_phy(struct mt76_phy *phy); 911 912 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 913 const struct ieee80211_ops *ops); 914 int mt76_register_phy(struct mt76_phy *phy, bool vht, 915 struct ieee80211_rate *rates, int n_rates); 916 917 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 918 const struct file_operations *ops); 919 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 920 { 921 return mt76_register_debugfs_fops(&dev->phy, NULL); 922 } 923 924 int mt76_queues_read(struct seq_file *s, void *data); 925 void mt76_seq_puts_array(struct seq_file *file, const char *str, 926 s8 *val, int len); 927 928 int mt76_eeprom_init(struct mt76_dev *dev, int len); 929 void mt76_eeprom_override(struct mt76_phy *phy); 930 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); 931 932 struct mt76_queue * 933 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 934 int ring_base); 935 u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx); 936 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 937 int n_desc, int ring_base) 938 { 939 struct mt76_queue *q; 940 941 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base); 942 if (IS_ERR(q)) 943 return PTR_ERR(q); 944 945 q->qid = qid; 946 phy->q_tx[qid] = q; 947 948 return 0; 949 } 950 951 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 952 int n_desc, int ring_base) 953 { 954 struct mt76_queue *q; 955 956 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base); 957 if (IS_ERR(q)) 958 return PTR_ERR(q); 959 960 q->qid = __MT_TXQ_MAX + qid; 961 dev->q_mcu[qid] = q; 962 963 return 0; 964 } 965 966 static inline struct mt76_phy * 967 mt76_dev_phy(struct mt76_dev *dev, bool phy_ext) 968 { 969 if (phy_ext && dev->phy2) 970 return dev->phy2; 971 return &dev->phy; 972 } 973 974 static inline struct ieee80211_hw * 975 mt76_phy_hw(struct mt76_dev *dev, bool phy_ext) 976 { 977 return mt76_dev_phy(dev, phy_ext)->hw; 978 } 979 980 static inline u8 * 981 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 982 { 983 return (u8 *)t - dev->drv->txwi_size; 984 } 985 986 /* increment with wrap-around */ 987 static inline int mt76_incr(int val, int size) 988 { 989 return (val + 1) & (size - 1); 990 } 991 992 /* decrement with wrap-around */ 993 static inline int mt76_decr(int val, int size) 994 { 995 return (val - 1) & (size - 1); 996 } 997 998 u8 mt76_ac_to_hwq(u8 ac); 999 1000 static inline struct ieee80211_txq * 1001 mtxq_to_txq(struct mt76_txq *mtxq) 1002 { 1003 void *ptr = mtxq; 1004 1005 return container_of(ptr, struct ieee80211_txq, drv_priv); 1006 } 1007 1008 static inline struct ieee80211_sta * 1009 wcid_to_sta(struct mt76_wcid *wcid) 1010 { 1011 void *ptr = wcid; 1012 1013 if (!wcid || !wcid->sta) 1014 return NULL; 1015 1016 return container_of(ptr, struct ieee80211_sta, drv_priv); 1017 } 1018 1019 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1020 { 1021 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1022 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1023 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1024 } 1025 1026 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1027 { 1028 struct mt76_rx_status mstat; 1029 u8 *data = skb->data; 1030 1031 /* Alignment concerns */ 1032 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1033 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1034 1035 mstat = *((struct mt76_rx_status *)skb->cb); 1036 1037 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1038 data += sizeof(struct ieee80211_radiotap_he); 1039 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1040 data += sizeof(struct ieee80211_radiotap_he_mu); 1041 1042 return data; 1043 } 1044 1045 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1046 { 1047 int len = ieee80211_get_hdrlen_from_skb(skb); 1048 1049 if (len % 4 == 0) 1050 return; 1051 1052 skb_push(skb, 2); 1053 memmove(skb->data, skb->data + 2, len); 1054 1055 skb->data[len] = 0; 1056 skb->data[len + 1] = 0; 1057 } 1058 1059 static inline bool mt76_is_skb_pktid(u8 pktid) 1060 { 1061 if (pktid & MT_PACKET_ID_HAS_RATE) 1062 return false; 1063 1064 return pktid >= MT_PACKET_ID_FIRST; 1065 } 1066 1067 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1068 { 1069 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1070 1071 return nss_delta[nss - 1]; 1072 } 1073 1074 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1075 { 1076 #ifdef CONFIG_NL80211_TESTMODE 1077 return phy->test.state != MT76_TM_STATE_OFF; 1078 #else 1079 return false; 1080 #endif 1081 } 1082 1083 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1084 struct sk_buff *skb, 1085 struct ieee80211_hw **hw) 1086 { 1087 #ifdef CONFIG_NL80211_TESTMODE 1088 if (skb == dev->phy.test.tx_skb) 1089 *hw = dev->phy.hw; 1090 else if (dev->phy2 && skb == dev->phy2->test.tx_skb) 1091 *hw = dev->phy2->hw; 1092 else 1093 return false; 1094 return true; 1095 #else 1096 return false; 1097 #endif 1098 } 1099 1100 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1101 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1102 struct mt76_wcid *wcid, struct sk_buff *skb); 1103 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1104 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1105 bool send_bar); 1106 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1107 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1108 void mt76_txq_schedule_all(struct mt76_phy *phy); 1109 void mt76_tx_worker_run(struct mt76_dev *dev); 1110 void mt76_tx_worker(struct mt76_worker *w); 1111 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1112 struct ieee80211_sta *sta, 1113 u16 tids, int nframes, 1114 enum ieee80211_frame_release_type reason, 1115 bool more_data); 1116 bool mt76_has_tx_pending(struct mt76_phy *phy); 1117 void mt76_set_channel(struct mt76_phy *phy); 1118 void mt76_update_survey(struct mt76_phy *phy); 1119 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1120 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1121 struct survey_info *survey); 1122 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1123 1124 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1125 u16 ssn, u16 size); 1126 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1127 1128 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1129 struct ieee80211_key_conf *key); 1130 1131 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1132 __acquires(&dev->status_lock); 1133 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1134 __releases(&dev->status_lock); 1135 1136 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1137 struct sk_buff *skb); 1138 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1139 struct mt76_wcid *wcid, int pktid, 1140 struct sk_buff_head *list); 1141 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1142 struct sk_buff_head *list); 1143 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1144 struct list_head *free_list); 1145 static inline void 1146 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1147 { 1148 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1149 } 1150 1151 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1152 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1153 struct ieee80211_sta *sta, 1154 enum ieee80211_sta_state old_state, 1155 enum ieee80211_sta_state new_state); 1156 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1157 struct ieee80211_sta *sta); 1158 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1159 struct ieee80211_sta *sta); 1160 1161 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1162 1163 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1164 int *dbm); 1165 int mt76_init_sar_power(struct ieee80211_hw *hw, 1166 const struct cfg80211_sar_specs *sar); 1167 int mt76_get_sar_power(struct mt76_phy *phy, 1168 struct ieee80211_channel *chan, 1169 int power); 1170 1171 void mt76_csa_check(struct mt76_dev *dev); 1172 void mt76_csa_finish(struct mt76_dev *dev); 1173 1174 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1175 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1176 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1177 int mt76_get_rate(struct mt76_dev *dev, 1178 struct ieee80211_supported_band *sband, 1179 int idx, bool cck); 1180 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1181 const u8 *mac); 1182 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1183 struct ieee80211_vif *vif); 1184 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1185 void *data, int len); 1186 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1187 struct netlink_callback *cb, void *data, int len); 1188 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1189 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1190 1191 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1192 { 1193 #ifdef CONFIG_NL80211_TESTMODE 1194 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1195 1196 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1197 state = MT76_TM_STATE_OFF; 1198 1199 mt76_testmode_set_state(phy, state); 1200 #endif 1201 } 1202 1203 1204 /* internal */ 1205 static inline struct ieee80211_hw * 1206 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1207 { 1208 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1209 struct ieee80211_hw *hw = dev->phy.hw; 1210 1211 if ((info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY) && dev->phy2) 1212 hw = dev->phy2->hw; 1213 1214 info->hw_queue &= ~MT_TX_HW_QUEUE_EXT_PHY; 1215 1216 return hw; 1217 } 1218 1219 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1220 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1221 struct napi_struct *napi); 1222 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1223 struct napi_struct *napi); 1224 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1225 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1226 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1227 struct mt76_queue_entry *e); 1228 1229 /* usb */ 1230 static inline bool mt76u_urb_error(struct urb *urb) 1231 { 1232 return urb->status && 1233 urb->status != -ECONNRESET && 1234 urb->status != -ESHUTDOWN && 1235 urb->status != -ENOENT; 1236 } 1237 1238 /* Map hardware queues to usb endpoints */ 1239 static inline u8 q2ep(u8 qid) 1240 { 1241 /* TODO: take management packets to queue 5 */ 1242 return qid + 1; 1243 } 1244 1245 static inline int 1246 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1247 int timeout, int ep) 1248 { 1249 struct usb_interface *uintf = to_usb_interface(dev->dev); 1250 struct usb_device *udev = interface_to_usbdev(uintf); 1251 struct mt76_usb *usb = &dev->usb; 1252 unsigned int pipe; 1253 1254 if (actual_len) 1255 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1256 else 1257 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1258 1259 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1260 } 1261 1262 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1263 struct mt76_sta_stats *stats); 1264 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1265 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1266 u8 req_type, u16 val, u16 offset, 1267 void *buf, size_t len); 1268 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1269 const u16 offset, const u32 val); 1270 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1271 bool ext); 1272 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1273 int mt76u_alloc_queues(struct mt76_dev *dev); 1274 void mt76u_stop_tx(struct mt76_dev *dev); 1275 void mt76u_stop_rx(struct mt76_dev *dev); 1276 int mt76u_resume_rx(struct mt76_dev *dev); 1277 void mt76u_queues_deinit(struct mt76_dev *dev); 1278 1279 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1280 const struct mt76_bus_ops *bus_ops); 1281 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1282 int mt76s_alloc_tx(struct mt76_dev *dev); 1283 void mt76s_deinit(struct mt76_dev *dev); 1284 void mt76s_sdio_irq(struct sdio_func *func); 1285 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1286 bool mt76s_txqs_empty(struct mt76_dev *dev); 1287 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1288 int hw_ver); 1289 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1290 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1291 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1292 u32 mt76s_read_pcr(struct mt76_dev *dev); 1293 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1294 const void *data, int len); 1295 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1296 void *data, int len); 1297 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1298 const struct mt76_reg_pair *data, 1299 int len); 1300 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1301 struct mt76_reg_pair *data, int len); 1302 1303 struct sk_buff * 1304 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1305 int data_len); 1306 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1307 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1308 unsigned long expires); 1309 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1310 int len, bool wait_resp, struct sk_buff **ret); 1311 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1312 int cmd, bool wait_resp, struct sk_buff **ret); 1313 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1314 int len, int max_len); 1315 static inline int 1316 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1317 int len) 1318 { 1319 int max_len = 4096 - dev->mcu_ops->headroom; 1320 1321 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1322 } 1323 1324 static inline int 1325 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1326 bool wait_resp) 1327 { 1328 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1329 } 1330 1331 static inline int 1332 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1333 bool wait_resp) 1334 { 1335 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1336 } 1337 1338 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1339 1340 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1341 struct ieee80211_channel *chan, 1342 struct mt76_power_limits *dest, 1343 s8 target_power); 1344 1345 struct mt76_txwi_cache * 1346 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1347 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1348 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1349 1350 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1351 { 1352 spin_lock_bh(&dev->token_lock); 1353 __mt76_set_tx_blocked(dev, blocked); 1354 spin_unlock_bh(&dev->token_lock); 1355 } 1356 1357 static inline int 1358 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1359 { 1360 int token; 1361 1362 spin_lock_bh(&dev->token_lock); 1363 token = idr_alloc(&dev->token, *ptxwi, 0, dev->drv->token_size, 1364 GFP_ATOMIC); 1365 spin_unlock_bh(&dev->token_lock); 1366 1367 return token; 1368 } 1369 1370 static inline struct mt76_txwi_cache * 1371 mt76_token_put(struct mt76_dev *dev, int token) 1372 { 1373 struct mt76_txwi_cache *txwi; 1374 1375 spin_lock_bh(&dev->token_lock); 1376 txwi = idr_remove(&dev->token, token); 1377 spin_unlock_bh(&dev->token_lock); 1378 1379 return txwi; 1380 } 1381 1382 static inline void mt76_packet_id_init(struct mt76_wcid *wcid) 1383 { 1384 INIT_LIST_HEAD(&wcid->list); 1385 idr_init(&wcid->pktid); 1386 } 1387 1388 static inline void 1389 mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid) 1390 { 1391 struct sk_buff_head list; 1392 1393 mt76_tx_status_lock(dev, &list); 1394 mt76_tx_status_skb_get(dev, wcid, -1, &list); 1395 mt76_tx_status_unlock(dev, &list); 1396 1397 idr_destroy(&wcid->pktid); 1398 } 1399 1400 #endif 1401