1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 model = "Qualcomm Technologies, Inc. IPQ8074"; 14 compatible = "qcom,ipq8074"; 15 interrupt-parent = <&intc>; 16 17 clocks { 18 sleep_clk: sleep_clk { 19 compatible = "fixed-clock"; 20 clock-frequency = <32768>; 21 #clock-cells = <0>; 22 }; 23 24 xo: xo { 25 compatible = "fixed-clock"; 26 clock-frequency = <19200000>; 27 #clock-cells = <0>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 CPU0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a53"; 38 reg = <0x0>; 39 next-level-cache = <&L2_0>; 40 enable-method = "psci"; 41 }; 42 43 CPU1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 enable-method = "psci"; 47 reg = <0x1>; 48 next-level-cache = <&L2_0>; 49 }; 50 51 CPU2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 enable-method = "psci"; 55 reg = <0x2>; 56 next-level-cache = <&L2_0>; 57 }; 58 59 CPU3: cpu@3 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 enable-method = "psci"; 63 reg = <0x3>; 64 next-level-cache = <&L2_0>; 65 }; 66 67 L2_0: l2-cache { 68 compatible = "cache"; 69 cache-level = <0x2>; 70 }; 71 }; 72 73 pmu { 74 compatible = "arm,cortex-a53-pmu"; 75 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 76 }; 77 78 psci { 79 compatible = "arm,psci-1.0"; 80 method = "smc"; 81 }; 82 83 reserved-memory { 84 #address-cells = <2>; 85 #size-cells = <2>; 86 ranges; 87 88 bootloader@4a600000 { 89 reg = <0x0 0x4a600000 0x0 0x400000>; 90 no-map; 91 }; 92 93 sbl@4aa00000 { 94 reg = <0x0 0x4aa00000 0x0 0x100000>; 95 no-map; 96 }; 97 98 smem@4ab00000 { 99 compatible = "qcom,smem"; 100 reg = <0x0 0x4ab00000 0x0 0x100000>; 101 no-map; 102 103 hwlocks = <&tcsr_mutex 0>; 104 }; 105 106 memory@4ac00000 { 107 reg = <0x0 0x4ac00000 0x0 0x400000>; 108 no-map; 109 }; 110 }; 111 112 firmware { 113 scm { 114 compatible = "qcom,scm-ipq8074", "qcom,scm"; 115 qcom,dload-mode = <&tcsr 0x6100>; 116 }; 117 }; 118 119 soc: soc@0 { 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges = <0 0 0 0xffffffff>; 123 compatible = "simple-bus"; 124 125 ssphy_1: phy@58000 { 126 compatible = "qcom,ipq8074-qmp-usb3-phy"; 127 reg = <0x00058000 0x1c4>; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 ranges; 131 132 clocks = <&gcc GCC_USB1_AUX_CLK>, 133 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 134 <&xo>; 135 clock-names = "aux", "cfg_ahb", "ref"; 136 137 resets = <&gcc GCC_USB1_PHY_BCR>, 138 <&gcc GCC_USB3PHY_1_PHY_BCR>; 139 reset-names = "phy","common"; 140 status = "disabled"; 141 142 usb1_ssphy: phy@58200 { 143 reg = <0x00058200 0x130>, /* Tx */ 144 <0x00058400 0x200>, /* Rx */ 145 <0x00058800 0x1f8>, /* PCS */ 146 <0x00058600 0x044>; /* PCS misc */ 147 #phy-cells = <0>; 148 #clock-cells = <0>; 149 clocks = <&gcc GCC_USB1_PIPE_CLK>; 150 clock-names = "pipe0"; 151 clock-output-names = "usb3phy_1_cc_pipe_clk"; 152 }; 153 }; 154 155 qusb_phy_1: phy@59000 { 156 compatible = "qcom,ipq8074-qusb2-phy"; 157 reg = <0x00059000 0x180>; 158 #phy-cells = <0>; 159 160 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 161 <&xo>; 162 clock-names = "cfg_ahb", "ref"; 163 164 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 165 status = "disabled"; 166 }; 167 168 ssphy_0: phy@78000 { 169 compatible = "qcom,ipq8074-qmp-usb3-phy"; 170 reg = <0x00078000 0x1c4>; 171 #address-cells = <1>; 172 #size-cells = <1>; 173 ranges; 174 175 clocks = <&gcc GCC_USB0_AUX_CLK>, 176 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 177 <&xo>; 178 clock-names = "aux", "cfg_ahb", "ref"; 179 180 resets = <&gcc GCC_USB0_PHY_BCR>, 181 <&gcc GCC_USB3PHY_0_PHY_BCR>; 182 reset-names = "phy","common"; 183 status = "disabled"; 184 185 usb0_ssphy: phy@78200 { 186 reg = <0x00078200 0x130>, /* Tx */ 187 <0x00078400 0x200>, /* Rx */ 188 <0x00078800 0x1f8>, /* PCS */ 189 <0x00078600 0x044>; /* PCS misc */ 190 #phy-cells = <0>; 191 #clock-cells = <0>; 192 clocks = <&gcc GCC_USB0_PIPE_CLK>; 193 clock-names = "pipe0"; 194 clock-output-names = "usb3phy_0_cc_pipe_clk"; 195 }; 196 }; 197 198 qusb_phy_0: phy@79000 { 199 compatible = "qcom,ipq8074-qusb2-phy"; 200 reg = <0x00079000 0x180>; 201 #phy-cells = <0>; 202 203 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 204 <&xo>; 205 clock-names = "cfg_ahb", "ref"; 206 207 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 208 status = "disabled"; 209 }; 210 211 pcie_qmp0: phy@84000 { 212 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; 213 reg = <0x00084000 0x1bc>; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 ranges; 217 218 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 219 <&gcc GCC_PCIE0_AHB_CLK>; 220 clock-names = "aux", "cfg_ahb"; 221 resets = <&gcc GCC_PCIE0_PHY_BCR>, 222 <&gcc GCC_PCIE0PHY_PHY_BCR>; 223 reset-names = "phy", 224 "common"; 225 status = "disabled"; 226 227 pcie_phy0: phy@84200 { 228 reg = <0x84200 0x16c>, 229 <0x84400 0x200>, 230 <0x84800 0x1f0>, 231 <0x84c00 0xf4>; 232 #phy-cells = <0>; 233 #clock-cells = <0>; 234 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 235 clock-names = "pipe0"; 236 clock-output-names = "pcie20_phy0_pipe_clk"; 237 }; 238 }; 239 240 pcie_qmp1: phy@8e000 { 241 compatible = "qcom,ipq8074-qmp-pcie-phy"; 242 reg = <0x0008e000 0x1c4>; 243 #address-cells = <1>; 244 #size-cells = <1>; 245 ranges; 246 247 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 248 <&gcc GCC_PCIE1_AHB_CLK>; 249 clock-names = "aux", "cfg_ahb"; 250 resets = <&gcc GCC_PCIE1_PHY_BCR>, 251 <&gcc GCC_PCIE1PHY_PHY_BCR>; 252 reset-names = "phy", 253 "common"; 254 status = "disabled"; 255 256 pcie_phy1: phy@8e200 { 257 reg = <0x8e200 0x130>, 258 <0x8e400 0x200>, 259 <0x8e800 0x1f8>; 260 #phy-cells = <0>; 261 #clock-cells = <0>; 262 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 263 clock-names = "pipe0"; 264 clock-output-names = "pcie20_phy1_pipe_clk"; 265 }; 266 }; 267 268 mdio: mdio@90000 { 269 compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio"; 270 reg = <0x00090000 0x64>; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 274 clocks = <&gcc GCC_MDIO_AHB_CLK>; 275 clock-names = "gcc_mdio_ahb_clk"; 276 277 status = "disabled"; 278 }; 279 280 qfprom: efuse@a4000 { 281 compatible = "qcom,ipq8074-qfprom", "qcom,qfprom"; 282 reg = <0x000a4000 0x2000>; 283 #address-cells = <1>; 284 #size-cells = <1>; 285 }; 286 287 prng: rng@e3000 { 288 compatible = "qcom,prng-ee"; 289 reg = <0x000e3000 0x1000>; 290 clocks = <&gcc GCC_PRNG_AHB_CLK>; 291 clock-names = "core"; 292 status = "disabled"; 293 }; 294 295 tsens: thermal-sensor@4a9000 { 296 compatible = "qcom,ipq8074-tsens"; 297 reg = <0x4a9000 0x1000>, /* TM */ 298 <0x4a8000 0x1000>; /* SROT */ 299 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 300 interrupt-names = "combined"; 301 #qcom,sensors = <16>; 302 #thermal-sensor-cells = <1>; 303 }; 304 305 cryptobam: dma-controller@704000 { 306 compatible = "qcom,bam-v1.7.0"; 307 reg = <0x00704000 0x20000>; 308 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 310 clock-names = "bam_clk"; 311 #dma-cells = <1>; 312 qcom,ee = <1>; 313 qcom,controlled-remotely; 314 status = "disabled"; 315 }; 316 317 crypto: crypto@73a000 { 318 compatible = "qcom,crypto-v5.1"; 319 reg = <0x0073a000 0x6000>; 320 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 321 <&gcc GCC_CRYPTO_AXI_CLK>, 322 <&gcc GCC_CRYPTO_CLK>; 323 clock-names = "iface", "bus", "core"; 324 dmas = <&cryptobam 2>, <&cryptobam 3>; 325 dma-names = "rx", "tx"; 326 status = "disabled"; 327 }; 328 329 tlmm: pinctrl@1000000 { 330 compatible = "qcom,ipq8074-pinctrl"; 331 reg = <0x01000000 0x300000>; 332 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 333 gpio-controller; 334 gpio-ranges = <&tlmm 0 0 70>; 335 #gpio-cells = <2>; 336 interrupt-controller; 337 #interrupt-cells = <2>; 338 339 serial_4_pins: serial4-state { 340 pins = "gpio23", "gpio24"; 341 function = "blsp4_uart1"; 342 drive-strength = <8>; 343 bias-disable; 344 }; 345 346 i2c_0_pins: i2c-0-state { 347 pins = "gpio42", "gpio43"; 348 function = "blsp1_i2c"; 349 drive-strength = <8>; 350 bias-disable; 351 }; 352 353 spi_0_pins: spi-0-state { 354 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 355 function = "blsp0_spi"; 356 drive-strength = <8>; 357 bias-disable; 358 }; 359 360 hsuart_pins: hsuart-state { 361 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 362 function = "blsp2_uart"; 363 drive-strength = <8>; 364 bias-disable; 365 }; 366 367 qpic_pins: qpic-state { 368 pins = "gpio1", "gpio3", "gpio4", 369 "gpio5", "gpio6", "gpio7", 370 "gpio8", "gpio10", "gpio11", 371 "gpio12", "gpio13", "gpio14", 372 "gpio15", "gpio16", "gpio17"; 373 function = "qpic"; 374 drive-strength = <8>; 375 bias-disable; 376 }; 377 }; 378 379 gcc: gcc@1800000 { 380 compatible = "qcom,gcc-ipq8074"; 381 reg = <0x01800000 0x80000>; 382 clocks = <&xo>, <&sleep_clk>; 383 clock-names = "xo", "sleep_clk"; 384 #clock-cells = <1>; 385 #power-domain-cells = <1>; 386 #reset-cells = <1>; 387 }; 388 389 tcsr_mutex: hwlock@1905000 { 390 compatible = "qcom,tcsr-mutex"; 391 reg = <0x01905000 0x20000>; 392 #hwlock-cells = <1>; 393 }; 394 395 tcsr: syscon@1937000 { 396 compatible = "qcom,tcsr-ipq8074", "syscon"; 397 reg = <0x01937000 0x21000>; 398 }; 399 400 spmi_bus: spmi@200f000 { 401 compatible = "qcom,spmi-pmic-arb"; 402 reg = <0x0200f000 0x001000>, 403 <0x02400000 0x800000>, 404 <0x02c00000 0x800000>, 405 <0x03800000 0x200000>, 406 <0x0200a000 0x000700>; 407 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 408 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 409 interrupt-names = "periph_irq"; 410 qcom,ee = <0>; 411 qcom,channel = <0>; 412 #address-cells = <2>; 413 #size-cells = <0>; 414 interrupt-controller; 415 #interrupt-cells = <4>; 416 }; 417 418 sdhc_1: mmc@7824900 { 419 compatible = "qcom,sdhci-msm-v4"; 420 reg = <0x7824900 0x500>, <0x7824000 0x800>; 421 reg-names = "hc", "core"; 422 423 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 425 interrupt-names = "hc_irq", "pwr_irq"; 426 427 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 428 <&gcc GCC_SDCC1_APPS_CLK>, 429 <&xo>; 430 clock-names = "iface", "core", "xo"; 431 resets = <&gcc GCC_SDCC1_BCR>; 432 max-frequency = <384000000>; 433 mmc-ddr-1_8v; 434 mmc-hs200-1_8v; 435 mmc-hs400-1_8v; 436 bus-width = <8>; 437 438 status = "disabled"; 439 }; 440 441 blsp_dma: dma-controller@7884000 { 442 compatible = "qcom,bam-v1.7.0"; 443 reg = <0x07884000 0x2b000>; 444 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 446 clock-names = "bam_clk"; 447 #dma-cells = <1>; 448 qcom,ee = <0>; 449 }; 450 451 blsp1_uart1: serial@78af000 { 452 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 453 reg = <0x078af000 0x200>; 454 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 456 <&gcc GCC_BLSP1_AHB_CLK>; 457 clock-names = "core", "iface"; 458 status = "disabled"; 459 }; 460 461 blsp1_uart3: serial@78b1000 { 462 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 463 reg = <0x078b1000 0x200>; 464 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 466 <&gcc GCC_BLSP1_AHB_CLK>; 467 clock-names = "core", "iface"; 468 dmas = <&blsp_dma 4>, 469 <&blsp_dma 5>; 470 dma-names = "tx", "rx"; 471 pinctrl-0 = <&hsuart_pins>; 472 pinctrl-names = "default"; 473 status = "disabled"; 474 }; 475 476 blsp1_uart5: serial@78b3000 { 477 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 478 reg = <0x078b3000 0x200>; 479 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 481 <&gcc GCC_BLSP1_AHB_CLK>; 482 clock-names = "core", "iface"; 483 pinctrl-0 = <&serial_4_pins>; 484 pinctrl-names = "default"; 485 status = "disabled"; 486 }; 487 488 blsp1_spi1: spi@78b5000 { 489 compatible = "qcom,spi-qup-v2.2.1"; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 reg = <0x078b5000 0x600>; 493 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 495 <&gcc GCC_BLSP1_AHB_CLK>; 496 clock-names = "core", "iface"; 497 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 498 dma-names = "tx", "rx"; 499 pinctrl-0 = <&spi_0_pins>; 500 pinctrl-names = "default"; 501 status = "disabled"; 502 }; 503 504 blsp1_i2c2: i2c@78b6000 { 505 compatible = "qcom,i2c-qup-v2.2.1"; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 reg = <0x078b6000 0x600>; 509 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 511 <&gcc GCC_BLSP1_AHB_CLK>; 512 clock-names = "core", "iface"; 513 clock-frequency = <400000>; 514 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 515 dma-names = "tx", "rx"; 516 pinctrl-0 = <&i2c_0_pins>; 517 pinctrl-names = "default"; 518 status = "disabled"; 519 }; 520 521 blsp1_i2c3: i2c@78b7000 { 522 compatible = "qcom,i2c-qup-v2.2.1"; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 reg = <0x078b7000 0x600>; 526 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 528 <&gcc GCC_BLSP1_AHB_CLK>; 529 clock-names = "core", "iface"; 530 clock-frequency = <100000>; 531 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 532 dma-names = "tx", "rx"; 533 status = "disabled"; 534 }; 535 536 blsp1_i2c5: i2c@78b9000 { 537 compatible = "qcom,i2c-qup-v2.2.1"; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 reg = <0x78b9000 0x600>; 541 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 543 <&gcc GCC_BLSP1_AHB_CLK>; 544 clock-names = "core", "iface"; 545 clock-frequency = <400000>; 546 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 547 dma-names = "tx", "rx"; 548 status = "disabled"; 549 }; 550 551 blsp1_spi5: spi@78b9000 { 552 compatible = "qcom,spi-qup-v2.2.1"; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 reg = <0x78b9000 0x600>; 556 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 558 <&gcc GCC_BLSP1_AHB_CLK>; 559 clock-names = "core", "iface"; 560 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 561 dma-names = "tx", "rx"; 562 status = "disabled"; 563 }; 564 565 blsp1_i2c6: i2c@78ba000 { 566 compatible = "qcom,i2c-qup-v2.2.1"; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 reg = <0x078ba000 0x600>; 570 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 572 <&gcc GCC_BLSP1_AHB_CLK>; 573 clock-names = "core", "iface"; 574 clock-frequency = <100000>; 575 dmas = <&blsp_dma 22>, <&blsp_dma 23>; 576 dma-names = "tx", "rx"; 577 status = "disabled"; 578 }; 579 580 qpic_bam: dma-controller@7984000 { 581 compatible = "qcom,bam-v1.7.0"; 582 reg = <0x07984000 0x1a000>; 583 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&gcc GCC_QPIC_AHB_CLK>; 585 clock-names = "bam_clk"; 586 #dma-cells = <1>; 587 qcom,ee = <0>; 588 status = "disabled"; 589 }; 590 591 qpic_nand: nand-controller@79b0000 { 592 compatible = "qcom,ipq8074-nand"; 593 reg = <0x079b0000 0x10000>; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 clocks = <&gcc GCC_QPIC_CLK>, 597 <&gcc GCC_QPIC_AHB_CLK>; 598 clock-names = "core", "aon"; 599 600 dmas = <&qpic_bam 0>, 601 <&qpic_bam 1>, 602 <&qpic_bam 2>; 603 dma-names = "tx", "rx", "cmd"; 604 pinctrl-0 = <&qpic_pins>; 605 pinctrl-names = "default"; 606 status = "disabled"; 607 }; 608 609 usb_0: usb@8af8800 { 610 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 611 reg = <0x08af8800 0x400>; 612 #address-cells = <1>; 613 #size-cells = <1>; 614 ranges; 615 616 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 617 <&gcc GCC_USB0_MASTER_CLK>, 618 <&gcc GCC_USB0_SLEEP_CLK>, 619 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 620 clock-names = "cfg_noc", 621 "core", 622 "sleep", 623 "mock_utmi"; 624 625 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 626 <&gcc GCC_USB0_MASTER_CLK>, 627 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 628 assigned-clock-rates = <133330000>, 629 <133330000>, 630 <19200000>; 631 632 power-domains = <&gcc USB0_GDSC>; 633 634 resets = <&gcc GCC_USB0_BCR>; 635 status = "disabled"; 636 637 dwc_0: usb@8a00000 { 638 compatible = "snps,dwc3"; 639 reg = <0x8a00000 0xcd00>; 640 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 641 phys = <&qusb_phy_0>, <&usb0_ssphy>; 642 phy-names = "usb2-phy", "usb3-phy"; 643 snps,is-utmi-l1-suspend; 644 snps,hird-threshold = /bits/ 8 <0x0>; 645 snps,dis_u2_susphy_quirk; 646 snps,dis_u3_susphy_quirk; 647 dr_mode = "host"; 648 }; 649 }; 650 651 usb_1: usb@8cf8800 { 652 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 653 reg = <0x08cf8800 0x400>; 654 #address-cells = <1>; 655 #size-cells = <1>; 656 ranges; 657 658 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 659 <&gcc GCC_USB1_MASTER_CLK>, 660 <&gcc GCC_USB1_SLEEP_CLK>, 661 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 662 clock-names = "cfg_noc", 663 "core", 664 "sleep", 665 "mock_utmi"; 666 667 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 668 <&gcc GCC_USB1_MASTER_CLK>, 669 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 670 assigned-clock-rates = <133330000>, 671 <133330000>, 672 <19200000>; 673 674 power-domains = <&gcc USB1_GDSC>; 675 676 resets = <&gcc GCC_USB1_BCR>; 677 status = "disabled"; 678 679 dwc_1: usb@8c00000 { 680 compatible = "snps,dwc3"; 681 reg = <0x8c00000 0xcd00>; 682 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 683 phys = <&qusb_phy_1>, <&usb1_ssphy>; 684 phy-names = "usb2-phy", "usb3-phy"; 685 snps,is-utmi-l1-suspend; 686 snps,hird-threshold = /bits/ 8 <0x0>; 687 snps,dis_u2_susphy_quirk; 688 snps,dis_u3_susphy_quirk; 689 dr_mode = "host"; 690 }; 691 }; 692 693 intc: interrupt-controller@b000000 { 694 compatible = "qcom,msm-qgic2"; 695 #address-cells = <1>; 696 #size-cells = <1>; 697 interrupt-controller; 698 #interrupt-cells = <3>; 699 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 700 ranges = <0 0xb00a000 0xffd>; 701 702 v2m@0 { 703 compatible = "arm,gic-v2m-frame"; 704 msi-controller; 705 reg = <0x0 0xffd>; 706 }; 707 }; 708 709 watchdog: watchdog@b017000 { 710 compatible = "qcom,kpss-wdt"; 711 reg = <0xb017000 0x1000>; 712 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 713 clocks = <&sleep_clk>; 714 timeout-sec = <30>; 715 }; 716 717 apcs_glb: mailbox@b111000 { 718 compatible = "qcom,ipq8074-apcs-apps-global", 719 "qcom,ipq6018-apcs-apps-global"; 720 reg = <0x0b111000 0x1000>; 721 clocks = <&a53pll>, <&xo>; 722 clock-names = "pll", "xo"; 723 724 #clock-cells = <1>; 725 #mbox-cells = <1>; 726 }; 727 728 a53pll: clock@b116000 { 729 compatible = "qcom,ipq8074-a53pll"; 730 reg = <0x0b116000 0x40>; 731 #clock-cells = <0>; 732 clocks = <&xo>; 733 clock-names = "xo"; 734 }; 735 736 timer@b120000 { 737 #address-cells = <1>; 738 #size-cells = <1>; 739 ranges; 740 compatible = "arm,armv7-timer-mem"; 741 reg = <0x0b120000 0x1000>; 742 743 frame@b120000 { 744 frame-number = <0>; 745 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 747 reg = <0x0b121000 0x1000>, 748 <0x0b122000 0x1000>; 749 }; 750 751 frame@b123000 { 752 frame-number = <1>; 753 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 754 reg = <0x0b123000 0x1000>; 755 status = "disabled"; 756 }; 757 758 frame@b124000 { 759 frame-number = <2>; 760 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 761 reg = <0x0b124000 0x1000>; 762 status = "disabled"; 763 }; 764 765 frame@b125000 { 766 frame-number = <3>; 767 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 768 reg = <0x0b125000 0x1000>; 769 status = "disabled"; 770 }; 771 772 frame@b126000 { 773 frame-number = <4>; 774 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 775 reg = <0x0b126000 0x1000>; 776 status = "disabled"; 777 }; 778 779 frame@b127000 { 780 frame-number = <5>; 781 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 782 reg = <0x0b127000 0x1000>; 783 status = "disabled"; 784 }; 785 786 frame@b128000 { 787 frame-number = <6>; 788 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 789 reg = <0x0b128000 0x1000>; 790 status = "disabled"; 791 }; 792 }; 793 794 pcie1: pci@10000000 { 795 compatible = "qcom,pcie-ipq8074"; 796 reg = <0x10000000 0xf1d>, 797 <0x10000f20 0xa8>, 798 <0x00088000 0x2000>, 799 <0x10100000 0x1000>; 800 reg-names = "dbi", "elbi", "parf", "config"; 801 device_type = "pci"; 802 linux,pci-domain = <1>; 803 bus-range = <0x00 0xff>; 804 num-lanes = <1>; 805 max-link-speed = <2>; 806 #address-cells = <3>; 807 #size-cells = <2>; 808 809 phys = <&pcie_phy1>; 810 phy-names = "pciephy"; 811 812 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ 813 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ 814 815 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 816 interrupt-names = "msi"; 817 #interrupt-cells = <1>; 818 interrupt-map-mask = <0 0 0 0x7>; 819 interrupt-map = <0 0 0 1 &intc 0 142 820 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 821 <0 0 0 2 &intc 0 143 822 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 823 <0 0 0 3 &intc 0 144 824 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 825 <0 0 0 4 &intc 0 145 826 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 827 828 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 829 <&gcc GCC_PCIE1_AXI_M_CLK>, 830 <&gcc GCC_PCIE1_AXI_S_CLK>, 831 <&gcc GCC_PCIE1_AHB_CLK>, 832 <&gcc GCC_PCIE1_AUX_CLK>; 833 clock-names = "iface", 834 "axi_m", 835 "axi_s", 836 "ahb", 837 "aux"; 838 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 839 <&gcc GCC_PCIE1_SLEEP_ARES>, 840 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 841 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 842 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 843 <&gcc GCC_PCIE1_AHB_ARES>, 844 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 845 reset-names = "pipe", 846 "sleep", 847 "sticky", 848 "axi_m", 849 "axi_s", 850 "ahb", 851 "axi_m_sticky"; 852 status = "disabled"; 853 }; 854 855 pcie0: pci@20000000 { 856 compatible = "qcom,pcie-ipq8074-gen3"; 857 reg = <0x20000000 0xf1d>, 858 <0x20000f20 0xa8>, 859 <0x20001000 0x1000>, 860 <0x00080000 0x4000>, 861 <0x20100000 0x1000>; 862 reg-names = "dbi", "elbi", "atu", "parf", "config"; 863 device_type = "pci"; 864 linux,pci-domain = <0>; 865 bus-range = <0x00 0xff>; 866 num-lanes = <1>; 867 max-link-speed = <3>; 868 #address-cells = <3>; 869 #size-cells = <2>; 870 871 phys = <&pcie_phy0>; 872 phy-names = "pciephy"; 873 874 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ 875 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ 876 877 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 878 interrupt-names = "msi"; 879 #interrupt-cells = <1>; 880 interrupt-map-mask = <0 0 0 0x7>; 881 interrupt-map = <0 0 0 1 &intc 0 75 882 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 883 <0 0 0 2 &intc 0 78 884 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 885 <0 0 0 3 &intc 0 79 886 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 887 <0 0 0 4 &intc 0 83 888 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 889 890 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 891 <&gcc GCC_PCIE0_AXI_M_CLK>, 892 <&gcc GCC_PCIE0_AXI_S_CLK>, 893 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 894 <&gcc GCC_PCIE0_RCHNG_CLK>; 895 clock-names = "iface", 896 "axi_m", 897 "axi_s", 898 "axi_bridge", 899 "rchng"; 900 901 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 902 <&gcc GCC_PCIE0_SLEEP_ARES>, 903 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 904 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 905 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 906 <&gcc GCC_PCIE0_AHB_ARES>, 907 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 908 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 909 reset-names = "pipe", 910 "sleep", 911 "sticky", 912 "axi_m", 913 "axi_s", 914 "ahb", 915 "axi_m_sticky", 916 "axi_s_sticky"; 917 status = "disabled"; 918 }; 919 }; 920 921 timer { 922 compatible = "arm,armv8-timer"; 923 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 924 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 925 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 926 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 927 }; 928 929 thermal-zones { 930 nss-top-thermal { 931 polling-delay-passive = <250>; 932 polling-delay = <1000>; 933 934 thermal-sensors = <&tsens 4>; 935 936 trips { 937 nss-top-crit { 938 temperature = <110000>; 939 hysteresis = <1000>; 940 type = "critical"; 941 }; 942 }; 943 }; 944 945 nss0-thermal { 946 polling-delay-passive = <250>; 947 polling-delay = <1000>; 948 949 thermal-sensors = <&tsens 5>; 950 951 trips { 952 nss-0-crit { 953 temperature = <110000>; 954 hysteresis = <1000>; 955 type = "critical"; 956 }; 957 }; 958 }; 959 960 nss1-thermal { 961 polling-delay-passive = <250>; 962 polling-delay = <1000>; 963 964 thermal-sensors = <&tsens 6>; 965 966 trips { 967 nss-1-crit { 968 temperature = <110000>; 969 hysteresis = <1000>; 970 type = "critical"; 971 }; 972 }; 973 }; 974 975 wcss-phya0-thermal { 976 polling-delay-passive = <250>; 977 polling-delay = <1000>; 978 979 thermal-sensors = <&tsens 7>; 980 981 trips { 982 wcss-phya0-crit { 983 temperature = <110000>; 984 hysteresis = <1000>; 985 type = "critical"; 986 }; 987 }; 988 }; 989 990 wcss-phya1-thermal { 991 polling-delay-passive = <250>; 992 polling-delay = <1000>; 993 994 thermal-sensors = <&tsens 8>; 995 996 trips { 997 wcss-phya1-crit { 998 temperature = <110000>; 999 hysteresis = <1000>; 1000 type = "critical"; 1001 }; 1002 }; 1003 }; 1004 1005 cpu0_thermal: cpu0-thermal { 1006 polling-delay-passive = <250>; 1007 polling-delay = <1000>; 1008 1009 thermal-sensors = <&tsens 9>; 1010 1011 trips { 1012 cpu0-crit { 1013 temperature = <110000>; 1014 hysteresis = <1000>; 1015 type = "critical"; 1016 }; 1017 }; 1018 }; 1019 1020 cpu1_thermal: cpu1-thermal { 1021 polling-delay-passive = <250>; 1022 polling-delay = <1000>; 1023 1024 thermal-sensors = <&tsens 10>; 1025 1026 trips { 1027 cpu1-crit { 1028 temperature = <110000>; 1029 hysteresis = <1000>; 1030 type = "critical"; 1031 }; 1032 }; 1033 }; 1034 1035 cpu2_thermal: cpu2-thermal { 1036 polling-delay-passive = <250>; 1037 polling-delay = <1000>; 1038 1039 thermal-sensors = <&tsens 11>; 1040 1041 trips { 1042 cpu2-crit { 1043 temperature = <110000>; 1044 hysteresis = <1000>; 1045 type = "critical"; 1046 }; 1047 }; 1048 }; 1049 1050 cpu3_thermal: cpu3-thermal { 1051 polling-delay-passive = <250>; 1052 polling-delay = <1000>; 1053 1054 thermal-sensors = <&tsens 12>; 1055 1056 trips { 1057 cpu3-crit { 1058 temperature = <110000>; 1059 hysteresis = <1000>; 1060 type = "critical"; 1061 }; 1062 }; 1063 }; 1064 1065 cluster_thermal: cluster-thermal { 1066 polling-delay-passive = <250>; 1067 polling-delay = <1000>; 1068 1069 thermal-sensors = <&tsens 13>; 1070 1071 trips { 1072 cluster-crit { 1073 temperature = <110000>; 1074 hysteresis = <1000>; 1075 type = "critical"; 1076 }; 1077 }; 1078 }; 1079 1080 wcss-phyb0-thermal { 1081 polling-delay-passive = <250>; 1082 polling-delay = <1000>; 1083 1084 thermal-sensors = <&tsens 14>; 1085 1086 trips { 1087 wcss-phyb0-crit { 1088 temperature = <110000>; 1089 hysteresis = <1000>; 1090 type = "critical"; 1091 }; 1092 }; 1093 }; 1094 1095 wcss-phyb1-thermal { 1096 polling-delay-passive = <250>; 1097 polling-delay = <1000>; 1098 1099 thermal-sensors = <&tsens 15>; 1100 1101 trips { 1102 wcss-phyb1-crit { 1103 temperature = <110000>; 1104 hysteresis = <1000>; 1105 type = "critical"; 1106 }; 1107 }; 1108 }; 1109 }; 1110}; 1111