1# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
2# Copyright (C) 2019 Texas Instruments Incorporated
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/sound/tlv320adcx140.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
9
10maintainers:
11  - Dan Murphy <dmurphy@ti.com>
12
13description: |
14  The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15  PDM microphones recording), high-performance audio, analog-to-digital
16  converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140
17  family supports line and  microphone Inputs, and offers a programmable
18  microphone bias or supply voltage generation.
19
20  Specifications can be found at:
21    https://www.ti.com/lit/ds/symlink/tlv320adc3140.pdf
22    https://www.ti.com/lit/ds/symlink/tlv320adc5140.pdf
23    https://www.ti.com/lit/ds/symlink/tlv320adc6140.pdf
24
25properties:
26  compatible:
27    enum:
28      - ti,tlv320adc3140
29      - ti,tlv320adc5140
30      - ti,tlv320adc6140
31
32  reg:
33    maxItems: 1
34    description: |
35      I2C addresss of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f
36
37  reset-gpios:
38    maxItems: 1
39    description: |
40      GPIO used for hardware reset.
41
42  areg-supply:
43    description: |
44      Regulator with AVDD at 3.3V.  If not defined then the internal regulator
45      is enabled.
46
47  ti,mic-bias-source:
48    description: |
49      Indicates the source for MIC Bias.
50      0 - Mic bias is set to VREF
51      1 - Mic bias is set to VREF × 1.096
52      6 - Mic bias is set to AVDD
53    $ref: /schemas/types.yaml#/definitions/uint32
54    enum: [0, 1, 6]
55
56  ti,vref-source:
57    description: |
58      Indicates the source for MIC Bias.
59      0 - Set VREF to 2.75V
60      1 - Set VREF to 2.5V
61      2 - Set VREF to 1.375V
62    $ref: /schemas/types.yaml#/definitions/uint32
63    enum: [0, 1, 2]
64
65  ti,pdm-edge-select:
66    description: |
67       Defines the PDMCLK sampling edge configuration for the PDM inputs.  This
68       array is defined as <PDMIN1 PDMIN2 PDMIN3 PDMIN4>.
69
70       0 - (default) Odd channel is latched on the negative edge and even
71       channel is latched on the the positive edge.
72       1 - Odd channel is latched on the positive edge and even channel is
73       latched on the the negative edge.
74
75       PDMIN1 - PDMCLK latching edge used for channel 1 and 2 data
76       PDMIN2 - PDMCLK latching edge used for channel 3 and 4 data
77       PDMIN3 - PDMCLK latching edge used for channel 5 and 6 data
78       PDMIN4 - PDMCLK latching edge used for channel 7 and 8 data
79
80    $ref: /schemas/types.yaml#/definitions/uint32-array
81    minItems: 1
82    maxItems: 4
83    items:
84      maximum: 1
85    default: [0, 0, 0, 0]
86
87  ti,gpi-config:
88    description: |
89       Defines the configuration for the general purpose input pins (GPI).
90       The array is defined as <GPI1 GPI2 GPI3 GPI4>.
91
92       0 - (default) disabled
93       1 - GPIX is configured as a general-purpose input (GPI)
94       2 - GPIX is configured as a master clock input (MCLK)
95       3 - GPIX is configured as an ASI input for daisy-chain (SDIN)
96       4 - GPIX is configured as a PDM data input for channel 1 and channel
97            (PDMDIN1)
98       5 - GPIX is configured as a PDM data input for channel 3 and channel
99            (PDMDIN2)
100       6 - GPIX is configured as a PDM data input for channel 5 and channel
101            (PDMDIN3)
102       7 - GPIX is configured as a PDM data input for channel 7 and channel
103            (PDMDIN4)
104
105    $ref: /schemas/types.yaml#/definitions/uint32-array
106    minItems: 1
107    maxItems: 4
108    items:
109      maximum: 7
110    default: [0, 0, 0, 0]
111
112  ti,asi-tx-drive:
113    type: boolean
114    description: |
115      When set the device will set the Tx ASI output to a Hi-Z state for unused
116      data cycles. Default is to drive the output low on unused ASI cycles.
117
118patternProperties:
119  '^ti,gpo-config-[1-4]$':
120    $ref: /schemas/types.yaml#/definitions/uint32-array
121    description: |
122       Defines the configuration and output driver for the general purpose
123       output pins (GPO).  These values are pairs, the first value is for the
124       configuration type and the second value is for the output drive type.
125       The array is defined as <GPO_CFG GPO_DRV>
126
127       GPO output configuration can be one of the following:
128
129       0 - (default) disabled
130       1 - GPOX is configured as a general-purpose output (GPO)
131       2 - GPOX is configured as a device interrupt output (IRQ)
132       3 - GPOX is configured as a secondary ASI output (SDOUT2)
133       4 - GPOX is configured as a PDM clock output (PDMCLK)
134
135       GPO output drive configuration for the GPO pins can be one of the following:
136
137       0d - (default) Hi-Z output
138       1d - Drive active low and active high
139       2d - Drive active low and weak high
140       3d - Drive active low and Hi-Z
141       4d - Drive weak low and active high
142       5d - Drive Hi-Z and active high
143
144  ti,gpio-config:
145    description: |
146       Defines the configuration and output drive for the General Purpose
147       Input and Output pin (GPIO1). Its value is a pair, the first value is for
148       the configuration type and the second value is for the output drive
149       type. The array is defined as <GPIO1_CFG GPIO1_DRV>
150
151       configuration for the GPIO pin can be one of the following:
152       0 - disabled
153       1 - GPIO1 is configured as a general-purpose output (GPO)
154       2 - (default) GPIO1 is configured as a device interrupt output (IRQ)
155       3 - GPIO1 is configured as a secondary ASI output (SDOUT2)
156       4 - GPIO1 is configured as a PDM clock output (PDMCLK)
157       8 - GPIO1 is configured as an input to control when MICBIAS turns on or
158           off (MICBIAS_EN)
159       9 - GPIO1 is configured as a general-purpose input (GPI)
160       10 - GPIO1 is configured as a master clock input (MCLK)
161       11 - GPIO1 is configured as an ASI input for daisy-chain (SDIN)
162       12 - GPIO1 is configured as a PDM data input for channel 1 and channel 2
163            (PDMDIN1)
164       13 - GPIO1 is configured as a PDM data input for channel 3 and channel 4
165            (PDMDIN2)
166       14 - GPIO1 is configured as a PDM data input for channel 5 and channel 6
167            (PDMDIN3)
168       15 - GPIO1 is configured as a PDM data input for channel 7 and channel 8
169            (PDMDIN4)
170
171       output drive type for the GPIO pin can be one of the following:
172       0 - Hi-Z output
173       1 - Drive active low and active high
174       2 - (default) Drive active low and weak high
175       3 - Drive active low and Hi-Z
176       4 - Drive weak low and active high
177       5 - Drive Hi-Z and active high
178
179    $ref: /schemas/types.yaml#/definitions/uint32-array
180    minItems: 2
181    maxItems: 2
182    items:
183      maximum: 15
184    default: [2, 2]
185
186required:
187  - compatible
188  - reg
189
190additionalProperties: false
191
192examples:
193  - |
194    #include <dt-bindings/gpio/gpio.h>
195    i2c0 {
196      #address-cells = <1>;
197      #size-cells = <0>;
198      codec: codec@4c {
199        compatible = "ti,tlv320adc5140";
200        reg = <0x4c>;
201        ti,mic-bias-source = <6>;
202        ti,pdm-edge-select = <0 1 0 1>;
203        ti,gpi-config = <4 5 6 7>;
204        ti,gpio-config = <10 2>;
205        ti,gpo-config-1 = <0 0>;
206        ti,gpo-config-2 = <0 0>;
207        reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
208      };
209    };
210