1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/clock/qcom,sm6375-gcc.h> 8#include <dt-bindings/clock/qcom,sm6375-gpucc.h> 9#include <dt-bindings/dma/qcom-gpi.h> 10#include <dt-bindings/firmware/qcom,scm.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/mailbox/qcom-ipcc.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 clocks { 24 xo_board_clk: xo-board-clk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 }; 28 29 sleep_clk: sleep-clk { 30 compatible = "fixed-clock"; 31 clock-frequency = <32000>; 32 #clock-cells = <0>; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo660"; 43 reg = <0x0 0x0>; 44 clocks = <&cpufreq_hw 0>; 45 enable-method = "psci"; 46 next-level-cache = <&L2_0>; 47 qcom,freq-domain = <&cpufreq_hw 0>; 48 power-domains = <&CPU_PD0>; 49 power-domain-names = "psci"; 50 #cooling-cells = <2>; 51 L2_0: l2-cache { 52 compatible = "cache"; 53 next-level-cache = <&L3_0>; 54 L3_0: l3-cache { 55 compatible = "cache"; 56 }; 57 }; 58 }; 59 60 CPU1: cpu@100 { 61 device_type = "cpu"; 62 compatible = "qcom,kryo660"; 63 reg = <0x0 0x100>; 64 clocks = <&cpufreq_hw 0>; 65 enable-method = "psci"; 66 next-level-cache = <&L2_100>; 67 qcom,freq-domain = <&cpufreq_hw 0>; 68 power-domains = <&CPU_PD1>; 69 power-domain-names = "psci"; 70 #cooling-cells = <2>; 71 L2_100: l2-cache { 72 compatible = "cache"; 73 next-level-cache = <&L3_0>; 74 }; 75 }; 76 77 CPU2: cpu@200 { 78 device_type = "cpu"; 79 compatible = "qcom,kryo660"; 80 reg = <0x0 0x200>; 81 clocks = <&cpufreq_hw 0>; 82 enable-method = "psci"; 83 next-level-cache = <&L2_200>; 84 qcom,freq-domain = <&cpufreq_hw 0>; 85 power-domains = <&CPU_PD2>; 86 power-domain-names = "psci"; 87 #cooling-cells = <2>; 88 L2_200: l2-cache { 89 compatible = "cache"; 90 next-level-cache = <&L3_0>; 91 }; 92 }; 93 94 CPU3: cpu@300 { 95 device_type = "cpu"; 96 compatible = "qcom,kryo660"; 97 reg = <0x0 0x300>; 98 clocks = <&cpufreq_hw 0>; 99 enable-method = "psci"; 100 next-level-cache = <&L2_300>; 101 qcom,freq-domain = <&cpufreq_hw 0>; 102 power-domains = <&CPU_PD3>; 103 power-domain-names = "psci"; 104 #cooling-cells = <2>; 105 L2_300: l2-cache { 106 compatible = "cache"; 107 next-level-cache = <&L3_0>; 108 }; 109 }; 110 111 CPU4: cpu@400 { 112 device_type = "cpu"; 113 compatible = "qcom,kryo660"; 114 reg = <0x0 0x400>; 115 clocks = <&cpufreq_hw 0>; 116 enable-method = "psci"; 117 next-level-cache = <&L2_400>; 118 qcom,freq-domain = <&cpufreq_hw 0>; 119 power-domains = <&CPU_PD4>; 120 power-domain-names = "psci"; 121 #cooling-cells = <2>; 122 L2_400: l2-cache { 123 compatible = "cache"; 124 next-level-cache = <&L3_0>; 125 }; 126 }; 127 128 CPU5: cpu@500 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo660"; 131 reg = <0x0 0x500>; 132 clocks = <&cpufreq_hw 0>; 133 enable-method = "psci"; 134 next-level-cache = <&L2_500>; 135 qcom,freq-domain = <&cpufreq_hw 0>; 136 power-domains = <&CPU_PD5>; 137 power-domain-names = "psci"; 138 #cooling-cells = <2>; 139 L2_500: l2-cache { 140 compatible = "cache"; 141 next-level-cache = <&L3_0>; 142 }; 143 }; 144 145 CPU6: cpu@600 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo660"; 148 reg = <0x0 0x600>; 149 clocks = <&cpufreq_hw 1>; 150 enable-method = "psci"; 151 next-level-cache = <&L2_600>; 152 qcom,freq-domain = <&cpufreq_hw 1>; 153 power-domains = <&CPU_PD6>; 154 power-domain-names = "psci"; 155 #cooling-cells = <2>; 156 L2_600: l2-cache { 157 compatible = "cache"; 158 next-level-cache = <&L3_0>; 159 }; 160 }; 161 162 CPU7: cpu@700 { 163 device_type = "cpu"; 164 compatible = "qcom,kryo660"; 165 reg = <0x0 0x700>; 166 clocks = <&cpufreq_hw 1>; 167 enable-method = "psci"; 168 next-level-cache = <&L2_700>; 169 qcom,freq-domain = <&cpufreq_hw 1>; 170 power-domains = <&CPU_PD7>; 171 power-domain-names = "psci"; 172 #cooling-cells = <2>; 173 L2_700: l2-cache { 174 compatible = "cache"; 175 next-level-cache = <&L3_0>; 176 }; 177 }; 178 179 cpu-map { 180 cluster0 { 181 core0 { 182 cpu = <&CPU0>; 183 }; 184 185 core1 { 186 cpu = <&CPU1>; 187 }; 188 189 core2 { 190 cpu = <&CPU2>; 191 }; 192 193 core3 { 194 cpu = <&CPU3>; 195 }; 196 197 core4 { 198 cpu = <&CPU4>; 199 }; 200 201 core5 { 202 cpu = <&CPU5>; 203 }; 204 205 core6 { 206 cpu = <&CPU6>; 207 }; 208 209 core7 { 210 cpu = <&CPU7>; 211 }; 212 }; 213 }; 214 215 idle-states { 216 entry-method = "psci"; 217 218 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 219 compatible = "arm,idle-state"; 220 idle-state-name = "silver-power-collapse"; 221 arm,psci-suspend-param = <0x40000003>; 222 entry-latency-us = <549>; 223 exit-latency-us = <901>; 224 min-residency-us = <1774>; 225 local-timer-stop; 226 }; 227 228 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 229 compatible = "arm,idle-state"; 230 idle-state-name = "silver-rail-power-collapse"; 231 arm,psci-suspend-param = <0x40000004>; 232 entry-latency-us = <702>; 233 exit-latency-us = <915>; 234 min-residency-us = <4001>; 235 local-timer-stop; 236 }; 237 238 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 239 compatible = "arm,idle-state"; 240 idle-state-name = "gold-power-collapse"; 241 arm,psci-suspend-param = <0x40000003>; 242 entry-latency-us = <523>; 243 exit-latency-us = <1244>; 244 min-residency-us = <2207>; 245 local-timer-stop; 246 }; 247 248 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 249 compatible = "arm,idle-state"; 250 idle-state-name = "gold-rail-power-collapse"; 251 arm,psci-suspend-param = <0x40000004>; 252 entry-latency-us = <526>; 253 exit-latency-us = <1854>; 254 min-residency-us = <5555>; 255 local-timer-stop; 256 }; 257 }; 258 259 domain-idle-states { 260 CLUSTER_SLEEP_0: cluster-sleep-0 { 261 compatible = "domain-idle-state"; 262 arm,psci-suspend-param = <0x41000044>; 263 entry-latency-us = <2752>; 264 exit-latency-us = <3048>; 265 min-residency-us = <6118>; 266 }; 267 }; 268 }; 269 270 firmware { 271 scm { 272 compatible = "qcom,scm-sm6375", "qcom,scm"; 273 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 274 clock-names = "core"; 275 #reset-cells = <1>; 276 }; 277 }; 278 279 memory@80000000 { 280 device_type = "memory"; 281 /* We expect the bootloader to fill in the size */ 282 reg = <0x0 0x80000000 0x0 0x0>; 283 }; 284 285 pmu { 286 compatible = "arm,armv8-pmuv3"; 287 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 288 }; 289 290 psci { 291 compatible = "arm,psci-1.0"; 292 method = "smc"; 293 294 CPU_PD0: power-domain-cpu0 { 295 #power-domain-cells = <0>; 296 power-domains = <&CLUSTER_PD>; 297 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 298 }; 299 300 CPU_PD1: power-domain-cpu1 { 301 #power-domain-cells = <0>; 302 power-domains = <&CLUSTER_PD>; 303 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 304 }; 305 306 CPU_PD2: power-domain-cpu2 { 307 #power-domain-cells = <0>; 308 power-domains = <&CLUSTER_PD>; 309 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 310 }; 311 312 CPU_PD3: power-domain-cpu3 { 313 #power-domain-cells = <0>; 314 power-domains = <&CLUSTER_PD>; 315 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 316 }; 317 318 CPU_PD4: power-domain-cpu4 { 319 #power-domain-cells = <0>; 320 power-domains = <&CLUSTER_PD>; 321 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 322 }; 323 324 CPU_PD5: power-domain-cpu5 { 325 #power-domain-cells = <0>; 326 power-domains = <&CLUSTER_PD>; 327 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 328 }; 329 330 CPU_PD6: power-domain-cpu6 { 331 #power-domain-cells = <0>; 332 power-domains = <&CLUSTER_PD>; 333 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 334 }; 335 336 CPU_PD7: power-domain-cpu7 { 337 #power-domain-cells = <0>; 338 power-domains = <&CLUSTER_PD>; 339 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 340 }; 341 342 CLUSTER_PD: power-domain-cpu-cluster0 { 343 #power-domain-cells = <0>; 344 domain-idle-states = <&CLUSTER_SLEEP_0>; 345 }; 346 }; 347 348 qup_opp_table: opp-table-qup { 349 compatible = "operating-points-v2"; 350 351 opp-75000000 { 352 opp-hz = /bits/ 64 <75000000>; 353 required-opps = <&rpmpd_opp_low_svs>; 354 }; 355 356 opp-100000000 { 357 opp-hz = /bits/ 64 <100000000>; 358 required-opps = <&rpmpd_opp_svs>; 359 }; 360 361 opp-128000000 { 362 opp-hz = /bits/ 64 <128000000>; 363 required-opps = <&rpmpd_opp_nom>; 364 }; 365 }; 366 367 reserved_memory: reserved-memory { 368 #address-cells = <2>; 369 #size-cells = <2>; 370 ranges; 371 372 hyp_mem: hypervisor@80000000 { 373 reg = <0 0x80000000 0 0x600000>; 374 no-map; 375 }; 376 377 xbl_aop_mem: xbl-aop@80700000 { 378 reg = <0 0x80700000 0 0x100000>; 379 no-map; 380 }; 381 382 reserved_xbl_uefi: xbl-uefi-res@80880000 { 383 reg = <0 0x80880000 0 0x14000>; 384 no-map; 385 }; 386 387 smem_mem: smem@80900000 { 388 compatible = "qcom,smem"; 389 reg = <0 0x80900000 0 0x200000>; 390 hwlocks = <&tcsr_mutex 3>; 391 no-map; 392 }; 393 394 fw_mem: fw@80b00000 { 395 reg = <0 0x80b00000 0 0x100000>; 396 no-map; 397 }; 398 399 cdsp_secure_heap_mem: cdsp-sec-heap@80c00000 { 400 reg = <0 0x80c00000 0 0x1e00000>; 401 no-map; 402 }; 403 404 dfps_data_mem: dpfs-data@85e00000 { 405 reg = <0 0x85e00000 0 0x100000>; 406 no-map; 407 }; 408 409 pil_wlan_mem: pil-wlan@86500000 { 410 reg = <0 0x86500000 0 0x200000>; 411 no-map; 412 }; 413 414 pil_adsp_mem: pil-adsp@86700000 { 415 reg = <0 0x86700000 0 0x2000000>; 416 no-map; 417 }; 418 419 pil_cdsp_mem: pil-cdsp@88700000 { 420 reg = <0 0x88700000 0 0x1e00000>; 421 no-map; 422 }; 423 424 pil_video_mem: pil-video@8a500000 { 425 reg = <0 0x8a500000 0 0x500000>; 426 no-map; 427 }; 428 429 pil_ipa_fw_mem: pil-ipa-fw@8aa00000 { 430 reg = <0 0x8aa00000 0 0x10000>; 431 no-map; 432 }; 433 434 pil_ipa_gsi_mem: pil-ipa-gsi@8aa10000 { 435 reg = <0 0x8aa10000 0 0xa000>; 436 no-map; 437 }; 438 439 pil_gpu_micro_code_mem: pil-gpu-ucode@8aa1a000 { 440 reg = <0 0x8aa1a000 0 0x2000>; 441 no-map; 442 }; 443 444 pil_mpss_wlan_mem: pil-mpss-wlan@8b800000 { 445 reg = <0 0x8b800000 0 0x10000000>; 446 no-map; 447 }; 448 449 removed_mem: removed@c0000000 { 450 reg = <0 0xc0000000 0 0x5100000>; 451 no-map; 452 }; 453 454 rmtfs_mem: rmtfs@f3900000 { 455 compatible = "qcom,rmtfs-mem"; 456 reg = <0 0xf3900000 0 0x280000>; 457 no-map; 458 459 qcom,client-id = <1>; 460 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 461 }; 462 463 debug_mem: debug@ffb00000 { 464 reg = <0 0xffb00000 0 0xc0000>; 465 no-map; 466 }; 467 468 last_log_mem: lastlog@ffbc0000 { 469 reg = <0 0xffbc0000 0 0x80000>; 470 no-map; 471 }; 472 473 cmdline_region: cmdline@ffd00000 { 474 reg = <0 0xffd00000 0 0x1000>; 475 no-map; 476 }; 477 }; 478 479 rpm-glink { 480 compatible = "qcom,glink-rpm"; 481 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 482 IPCC_MPROC_SIGNAL_GLINK_QMP 483 IRQ_TYPE_EDGE_RISING>; 484 qcom,rpm-msg-ram = <&rpm_msg_ram>; 485 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 486 487 rpm_requests: rpm-requests { 488 compatible = "qcom,rpm-sm6375"; 489 qcom,glink-channels = "rpm_requests"; 490 491 rpmcc: clock-controller { 492 compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; 493 clocks = <&xo_board_clk>; 494 clock-names = "xo"; 495 #clock-cells = <1>; 496 }; 497 498 rpmpd: power-controller { 499 compatible = "qcom,sm6375-rpmpd"; 500 #power-domain-cells = <1>; 501 operating-points-v2 = <&rpmpd_opp_table>; 502 503 rpmpd_opp_table: opp-table { 504 compatible = "operating-points-v2"; 505 506 rpmpd_opp_ret: opp1 { 507 opp-level = <RPM_SMD_LEVEL_RETENTION>; 508 }; 509 510 rpmpd_opp_min_svs: opp2 { 511 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 512 }; 513 514 rpmpd_opp_low_svs: opp3 { 515 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 516 }; 517 518 rpmpd_opp_svs: opp4 { 519 opp-level = <RPM_SMD_LEVEL_SVS>; 520 }; 521 522 rpmpd_opp_svs_plus: opp5 { 523 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 524 }; 525 526 rpmpd_opp_nom: opp6 { 527 opp-level = <RPM_SMD_LEVEL_NOM>; 528 }; 529 530 rpmpd_opp_nom_plus: opp7 { 531 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 532 }; 533 534 rpmpd_opp_turbo: opp8 { 535 opp-level = <RPM_SMD_LEVEL_TURBO>; 536 }; 537 538 rpmpd_opp_turbo_no_cpr: opp9 { 539 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 540 }; 541 }; 542 }; 543 }; 544 }; 545 546 smp2p-adsp { 547 compatible = "qcom,smp2p"; 548 qcom,smem = <443>, <429>; 549 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 550 IPCC_MPROC_SIGNAL_SMP2P 551 IRQ_TYPE_EDGE_RISING>; 552 mboxes = <&ipcc IPCC_CLIENT_LPASS 553 IPCC_MPROC_SIGNAL_SMP2P>; 554 555 qcom,local-pid = <0>; 556 qcom,remote-pid = <2>; 557 558 smp2p_adsp_out: master-kernel { 559 qcom,entry-name = "master-kernel"; 560 #qcom,smem-state-cells = <1>; 561 }; 562 563 smp2p_adsp_in: slave-kernel { 564 qcom,entry-name = "slave-kernel"; 565 interrupt-controller; 566 #interrupt-cells = <2>; 567 }; 568 }; 569 570 smp2p-cdsp { 571 compatible = "qcom,smp2p"; 572 qcom,smem = <94>, <432>; 573 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 574 IPCC_MPROC_SIGNAL_SMP2P 575 IRQ_TYPE_EDGE_RISING>; 576 mboxes = <&ipcc IPCC_CLIENT_CDSP 577 IPCC_MPROC_SIGNAL_SMP2P>; 578 579 qcom,local-pid = <0>; 580 qcom,remote-pid = <5>; 581 582 smp2p_cdsp_out: master-kernel { 583 qcom,entry-name = "master-kernel"; 584 #qcom,smem-state-cells = <1>; 585 }; 586 587 smp2p_cdsp_in: slave-kernel { 588 qcom,entry-name = "slave-kernel"; 589 interrupt-controller; 590 #interrupt-cells = <2>; 591 }; 592 }; 593 594 smp2p-modem { 595 compatible = "qcom,smp2p"; 596 qcom,smem = <435>, <428>; 597 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 598 IPCC_MPROC_SIGNAL_SMP2P 599 IRQ_TYPE_EDGE_RISING>; 600 mboxes = <&ipcc IPCC_CLIENT_MPSS 601 IPCC_MPROC_SIGNAL_SMP2P>; 602 603 qcom,local-pid = <0>; 604 qcom,remote-pid = <1>; 605 606 smp2p_modem_out: master-kernel { 607 qcom,entry-name = "master-kernel"; 608 #qcom,smem-state-cells = <1>; 609 }; 610 611 smp2p_modem_in: slave-kernel { 612 qcom,entry-name = "slave-kernel"; 613 interrupt-controller; 614 #interrupt-cells = <2>; 615 }; 616 617 ipa_smp2p_out: ipa-ap-to-modem { 618 qcom,entry-name = "ipa"; 619 #qcom,smem-state-cells = <1>; 620 }; 621 622 ipa_smp2p_in: ipa-modem-to-ap { 623 qcom,entry-name = "ipa"; 624 interrupt-controller; 625 #interrupt-cells = <2>; 626 }; 627 628 wlan_smp2p_in: wlan-wpss-to-ap { 629 qcom,entry-name = "wlan"; 630 interrupt-controller; 631 #interrupt-cells = <2>; 632 }; 633 }; 634 635 soc: soc@0 { 636 #address-cells = <2>; 637 #size-cells = <2>; 638 ranges = <0 0 0 0 0x10 0>; 639 dma-ranges = <0 0 0 0 0x10 0>; 640 compatible = "simple-bus"; 641 642 ipcc: mailbox@208000 { 643 compatible = "qcom,sm6375-ipcc", "qcom,ipcc"; 644 reg = <0 0x00208000 0 0x1000>; 645 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 646 interrupt-controller; 647 #interrupt-cells = <3>; 648 #mbox-cells = <2>; 649 }; 650 651 tcsr_mutex: hwlock@340000 { 652 compatible = "qcom,tcsr-mutex"; 653 reg = <0x0 0x00340000 0x0 0x40000>; 654 #hwlock-cells = <1>; 655 }; 656 657 tlmm: pinctrl@500000 { 658 compatible = "qcom,sm6375-tlmm"; 659 reg = <0 0x00500000 0 0x800000>; 660 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 661 gpio-ranges = <&tlmm 0 0 157>; 662 /* TODO: Hook up MPM as wakeup-parent when it's there */ 663 interrupt-controller; 664 gpio-controller; 665 #interrupt-cells = <2>; 666 #gpio-cells = <2>; 667 668 sdc2_off_state: sdc2-off-state { 669 clk-pins { 670 pins = "sdc2_clk"; 671 drive-strength = <2>; 672 bias-disable; 673 }; 674 675 cmd-pins { 676 pins = "sdc2_cmd"; 677 drive-strength = <2>; 678 bias-pull-up; 679 }; 680 681 data-pins { 682 pins = "sdc2_data"; 683 drive-strength = <2>; 684 bias-pull-up; 685 }; 686 }; 687 688 sdc2_on_state: sdc2-on-state { 689 clk-pins { 690 pins = "sdc2_clk"; 691 drive-strength = <16>; 692 bias-disable; 693 }; 694 695 cmd-pins { 696 pins = "sdc2_cmd"; 697 drive-strength = <10>; 698 bias-pull-up; 699 }; 700 701 data-pins { 702 pins = "sdc2_data"; 703 drive-strength = <10>; 704 bias-pull-up; 705 }; 706 }; 707 708 qup_i2c0_default: qup-i2c0-default-state { 709 pins = "gpio0", "gpio1"; 710 function = "qup00"; 711 drive-strength = <2>; 712 bias-pull-up; 713 }; 714 715 qup_i2c1_default: qup-i2c1-default-state { 716 pins = "gpio61", "gpio62"; 717 function = "qup01"; 718 drive-strength = <2>; 719 bias-pull-up; 720 }; 721 722 qup_i2c2_default: qup-i2c2-default-state { 723 pins = "gpio45", "gpio46"; 724 function = "qup02"; 725 drive-strength = <2>; 726 bias-pull-up; 727 }; 728 729 qup_i2c8_default: qup-i2c8-default-state { 730 pins = "gpio19", "gpio20"; 731 /* TLMM, GCC and vendor DT all have different indices.. */ 732 function = "qup12"; 733 drive-strength = <2>; 734 bias-pull-up; 735 }; 736 737 qup_i2c10_default: qup-i2c10-default-state { 738 pins = "gpio4", "gpio5"; 739 function = "qup10"; 740 drive-strength = <2>; 741 bias-pull-up; 742 }; 743 744 qup_spi0_default: qup-spi0-default-state { 745 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 746 function = "qup00"; 747 drive-strength = <6>; 748 bias-disable; 749 }; 750 }; 751 752 gcc: clock-controller@1400000 { 753 compatible = "qcom,sm6375-gcc"; 754 reg = <0 0x01400000 0 0x1f0000>; 755 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 756 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 757 <&sleep_clk>; 758 #power-domain-cells = <1>; 759 #clock-cells = <1>; 760 #reset-cells = <1>; 761 }; 762 763 usb_1_hsphy: phy@162b000 { 764 compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; 765 reg = <0 0x0162b000 0 0x400>; 766 767 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 768 clock-names = "ref"; 769 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 770 #phy-cells = <0>; 771 772 status = "disabled"; 773 }; 774 775 spmi_bus: spmi@1c40000 { 776 compatible = "qcom,spmi-pmic-arb"; 777 reg = <0 0x01c40000 0 0x1100>, 778 <0 0x01e00000 0 0x2000000>, 779 <0 0x03e00000 0 0x100000>, 780 <0 0x03f00000 0 0xa0000>, 781 <0 0x01c0a000 0 0x26000>; 782 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 783 interrupt-names = "periph_irq"; 784 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 785 qcom,ee = <0>; 786 qcom,channel = <0>; 787 #address-cells = <2>; 788 #size-cells = <0>; 789 interrupt-controller; 790 #interrupt-cells = <4>; 791 }; 792 793 tsens0: thermal-sensor@4411000 { 794 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; 795 reg = <0 0x04411000 0 0x140>, /* TM */ 796 <0 0x04410000 0 0x20>; /* SROT */ 797 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 799 interrupt-names = "uplow", "critical"; 800 #thermal-sensor-cells = <1>; 801 #qcom,sensors = <15>; 802 }; 803 804 tsens1: thermal-sensor@4413000 { 805 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; 806 reg = <0 0x04413000 0 0x140>, /* TM */ 807 <0 0x04412000 0 0x20>; /* SROT */ 808 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 810 interrupt-names = "uplow", "critical"; 811 #thermal-sensor-cells = <1>; 812 #qcom,sensors = <11>; 813 }; 814 815 rpm_msg_ram: sram@45f0000 { 816 compatible = "qcom,rpm-msg-ram"; 817 reg = <0 0x045f0000 0 0x7000>; 818 }; 819 820 sram@4690000 { 821 compatible = "qcom,rpm-stats"; 822 reg = <0 0x04690000 0 0x400>; 823 }; 824 825 sdhc_2: mmc@4784000 { 826 compatible = "qcom,sm6375-sdhci", "qcom,sdhci-msm-v5"; 827 reg = <0 0x04784000 0 0x1000>; 828 829 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 831 interrupt-names = "hc_irq", "pwr_irq"; 832 833 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 834 <&gcc GCC_SDCC2_APPS_CLK>, 835 <&rpmcc RPM_SMD_XO_CLK_SRC>; 836 clock-names = "iface", "core", "xo"; 837 resets = <&gcc GCC_SDCC2_BCR>; 838 iommus = <&apps_smmu 0x40 0x0>; 839 840 pinctrl-0 = <&sdc2_on_state>; 841 pinctrl-1 = <&sdc2_off_state>; 842 pinctrl-names = "default", "sleep"; 843 844 qcom,dll-config = <0x0007642c>; 845 qcom,ddr-config = <0x80040868>; 846 power-domains = <&rpmpd SM6375_VDDCX>; 847 operating-points-v2 = <&sdhc2_opp_table>; 848 bus-width = <4>; 849 850 status = "disabled"; 851 852 sdhc2_opp_table: opp-table { 853 compatible = "operating-points-v2"; 854 855 opp-100000000 { 856 opp-hz = /bits/ 64 <100000000>; 857 required-opps = <&rpmpd_opp_low_svs>; 858 }; 859 860 opp-202000000 { 861 opp-hz = /bits/ 64 <202000000>; 862 required-opps = <&rpmpd_opp_svs_plus>; 863 }; 864 }; 865 }; 866 867 gpi_dma0: dma-controller@4a00000 { 868 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 869 reg = <0 0x04a00000 0 0x60000>; 870 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 880 dma-channels = <10>; 881 dma-channel-mask = <0x1f>; 882 iommus = <&apps_smmu 0x16 0x0>; 883 #dma-cells = <3>; 884 status = "disabled"; 885 }; 886 887 qupv3_id_0: geniqup@4ac0000 { 888 compatible = "qcom,geni-se-qup"; 889 reg = <0x0 0x04ac0000 0x0 0x2000>; 890 clock-names = "m-ahb", "s-ahb"; 891 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 892 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 893 iommus = <&apps_smmu 0x3 0x0>; 894 #address-cells = <2>; 895 #size-cells = <2>; 896 ranges; 897 status = "disabled"; 898 899 i2c0: i2c@4a80000 { 900 compatible = "qcom,geni-i2c"; 901 reg = <0x0 0x04a80000 0x0 0x4000>; 902 clock-names = "se"; 903 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 904 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 905 pinctrl-names = "default"; 906 pinctrl-0 = <&qup_i2c0_default>; 907 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 908 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 909 dma-names = "tx", "rx"; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 status = "disabled"; 913 }; 914 915 spi0: spi@4a80000 { 916 compatible = "qcom,geni-spi"; 917 reg = <0x0 0x04a80000 0x0 0x4000>; 918 clock-names = "se"; 919 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 920 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 921 pinctrl-names = "default"; 922 pinctrl-0 = <&qup_spi0_default>; 923 power-domains = <&rpmpd SM6375_VDDCX>; 924 operating-points-v2 = <&qup_opp_table>; 925 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 926 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 927 dma-names = "tx", "rx"; 928 #address-cells = <1>; 929 #size-cells = <0>; 930 status = "disabled"; 931 }; 932 933 i2c1: i2c@4a84000 { 934 compatible = "qcom,geni-i2c"; 935 reg = <0x0 0x04a84000 0x0 0x4000>; 936 clock-names = "se"; 937 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 938 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 939 pinctrl-names = "default"; 940 pinctrl-0 = <&qup_i2c1_default>; 941 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 942 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 943 dma-names = "tx", "rx"; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 status = "disabled"; 947 }; 948 949 spi1: spi@4a84000 { 950 compatible = "qcom,geni-spi"; 951 reg = <0x0 0x04a84000 0x0 0x4000>; 952 clock-names = "se"; 953 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 954 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 955 power-domains = <&rpmpd SM6375_VDDCX>; 956 operating-points-v2 = <&qup_opp_table>; 957 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 958 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 959 dma-names = "tx", "rx"; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 status = "disabled"; 963 }; 964 965 i2c2: i2c@4a88000 { 966 compatible = "qcom,geni-i2c"; 967 reg = <0x0 0x04a88000 0x0 0x4000>; 968 clock-names = "se"; 969 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 970 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 971 pinctrl-names = "default"; 972 pinctrl-0 = <&qup_i2c2_default>; 973 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 974 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 975 dma-names = "tx", "rx"; 976 #address-cells = <1>; 977 #size-cells = <0>; 978 status = "disabled"; 979 }; 980 981 spi2: spi@4a88000 { 982 compatible = "qcom,geni-spi"; 983 reg = <0x0 0x04a88000 0x0 0x4000>; 984 clock-names = "se"; 985 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 986 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 987 power-domains = <&rpmpd SM6375_VDDCX>; 988 operating-points-v2 = <&qup_opp_table>; 989 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 990 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 991 dma-names = "tx", "rx"; 992 #address-cells = <1>; 993 #size-cells = <0>; 994 status = "disabled"; 995 }; 996 997 /* 998 * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream. 999 * There is a comment in the included DTSI of another SoC saying that they 1000 * are not "bolled out" (probably meaning not routed to solder balls) 1001 * TLMM driver however, suggests there are as many as 15 QUPs in total! 1002 * Most of which don't even have pin configurations for.. Sad stuff! 1003 */ 1004 }; 1005 1006 gpi_dma1: dma-controller@4c00000 { 1007 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 1008 reg = <0 0x04c00000 0 0x60000>; 1009 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 1019 dma-channels = <10>; 1020 dma-channel-mask = <0x1f>; 1021 iommus = <&apps_smmu 0xd6 0x0>; 1022 #dma-cells = <3>; 1023 status = "disabled"; 1024 }; 1025 1026 qupv3_id_1: geniqup@4cc0000 { 1027 compatible = "qcom,geni-se-qup"; 1028 reg = <0x0 0x04cc0000 0x0 0x2000>; 1029 clock-names = "m-ahb", "s-ahb"; 1030 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1031 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1032 iommus = <&apps_smmu 0xc3 0x0>; 1033 #address-cells = <2>; 1034 #size-cells = <2>; 1035 ranges; 1036 status = "disabled"; 1037 1038 i2c6: i2c@4c80000 { 1039 compatible = "qcom,geni-i2c"; 1040 reg = <0x0 0x04c80000 0x0 0x4000>; 1041 clock-names = "se"; 1042 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1043 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 1044 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1045 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1046 dma-names = "tx", "rx"; 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 status = "disabled"; 1050 }; 1051 1052 spi6: spi@4c80000 { 1053 compatible = "qcom,geni-spi"; 1054 reg = <0x0 0x04c80000 0x0 0x4000>; 1055 clock-names = "se"; 1056 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1057 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 1058 power-domains = <&rpmpd SM6375_VDDCX>; 1059 operating-points-v2 = <&qup_opp_table>; 1060 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1061 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1062 dma-names = "tx", "rx"; 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 status = "disabled"; 1066 }; 1067 1068 i2c7: i2c@4c84000 { 1069 compatible = "qcom,geni-i2c"; 1070 reg = <0x0 0x04c84000 0x0 0x4000>; 1071 clock-names = "se"; 1072 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1073 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1074 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1075 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1076 dma-names = "tx", "rx"; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 status = "disabled"; 1080 }; 1081 1082 spi7: spi@4c84000 { 1083 compatible = "qcom,geni-spi"; 1084 reg = <0x0 0x04c84000 0x0 0x4000>; 1085 clock-names = "se"; 1086 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1087 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1088 power-domains = <&rpmpd SM6375_VDDCX>; 1089 operating-points-v2 = <&qup_opp_table>; 1090 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1091 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1092 dma-names = "tx", "rx"; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 status = "disabled"; 1096 }; 1097 1098 i2c8: i2c@4c88000 { 1099 compatible = "qcom,geni-i2c"; 1100 reg = <0x0 0x04c88000 0x0 0x4000>; 1101 clock-names = "se"; 1102 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1103 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&qup_i2c8_default>; 1106 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1107 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1108 dma-names = "tx", "rx"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 status = "disabled"; 1112 }; 1113 1114 spi8: spi@4c88000 { 1115 compatible = "qcom,geni-spi"; 1116 reg = <0x0 0x04c88000 0x0 0x4000>; 1117 clock-names = "se"; 1118 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1119 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1120 power-domains = <&rpmpd SM6375_VDDCX>; 1121 operating-points-v2 = <&qup_opp_table>; 1122 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1123 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1124 dma-names = "tx", "rx"; 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 status = "disabled"; 1128 }; 1129 1130 i2c9: i2c@4c8c000 { 1131 compatible = "qcom,geni-i2c"; 1132 reg = <0x0 0x04c8c000 0x0 0x4000>; 1133 clock-names = "se"; 1134 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1135 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1136 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1137 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1138 dma-names = "tx", "rx"; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 status = "disabled"; 1142 }; 1143 1144 spi9: spi@4c8c000 { 1145 compatible = "qcom,geni-spi"; 1146 reg = <0x0 0x04c8c000 0x0 0x4000>; 1147 clock-names = "se"; 1148 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1149 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1150 power-domains = <&rpmpd SM6375_VDDCX>; 1151 operating-points-v2 = <&qup_opp_table>; 1152 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1153 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1154 dma-names = "tx", "rx"; 1155 #address-cells = <1>; 1156 #size-cells = <0>; 1157 status = "disabled"; 1158 }; 1159 1160 i2c10: i2c@4c90000 { 1161 compatible = "qcom,geni-i2c"; 1162 reg = <0x0 0x04c90000 0x0 0x4000>; 1163 clock-names = "se"; 1164 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1165 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&qup_i2c10_default>; 1168 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1169 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1170 dma-names = "tx", "rx"; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 status = "disabled"; 1174 }; 1175 1176 spi10: spi@4c90000 { 1177 compatible = "qcom,geni-spi"; 1178 reg = <0x0 0x04c90000 0x0 0x4000>; 1179 clock-names = "se"; 1180 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1181 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1182 power-domains = <&rpmpd SM6375_VDDCX>; 1183 operating-points-v2 = <&qup_opp_table>; 1184 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1185 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1186 dma-names = "tx", "rx"; 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 status = "disabled"; 1190 }; 1191 }; 1192 1193 usb_1: usb@4ef8800 { 1194 compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; 1195 reg = <0 0x04ef8800 0 0x400>; 1196 1197 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1198 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1199 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1200 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1201 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1202 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1203 clock-names = "cfg_noc", 1204 "core", 1205 "iface", 1206 "sleep", 1207 "mock_utmi", 1208 "xo"; 1209 1210 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1211 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1212 assigned-clock-rates = <19200000>, <133333333>; 1213 1214 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1218 interrupt-names = "hs_phy_irq", 1219 "ss_phy_irq", 1220 "dm_hs_phy_irq", 1221 "dp_hs_phy_irq"; 1222 1223 power-domains = <&gcc USB30_PRIM_GDSC>; 1224 1225 resets = <&gcc GCC_USB30_PRIM_BCR>; 1226 1227 /* 1228 * This property is there to allow USB2 to work, as 1229 * USB3 is not implemented yet - (re)move it when 1230 * proper support is in place. 1231 */ 1232 qcom,select-utmi-as-pipe-clk; 1233 1234 #address-cells = <2>; 1235 #size-cells = <2>; 1236 ranges; 1237 1238 status = "disabled"; 1239 1240 usb_1_dwc3: usb@4e00000 { 1241 compatible = "snps,dwc3"; 1242 reg = <0 0x04e00000 0 0xcd00>; 1243 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1244 maximum-speed = "high-speed"; 1245 phys = <&usb_1_hsphy>; 1246 phy-names = "usb2-phy"; 1247 iommus = <&apps_smmu 0xe0 0x0>; 1248 1249 /* Yes, this impl *does* have an unfunny number of quirks.. */ 1250 snps,hird-threshold = /bits/ 8 <0x10>; 1251 snps,usb2-gadget-lpm-disable; 1252 snps,dis_u2_susphy_quirk; 1253 snps,is-utmi-l1-suspend; 1254 snps,dis-u1-entry-quirk; 1255 snps,dis-u2-entry-quirk; 1256 snps,usb3_lpm_capable; 1257 snps,has-lpm-erratum; 1258 tx-fifo-resize; 1259 }; 1260 }; 1261 1262 adreno_smmu: iommu@5940000 { 1263 compatible = "qcom,sm6375-smmu-v2", "qcom,smmu-v2"; 1264 reg = <0 0x05940000 0 0x10000>; 1265 #iommu-cells = <1>; 1266 #global-interrupts = <2>; 1267 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1277 1278 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1279 clock-names = "bus"; 1280 1281 power-domains = <&gpucc GPU_CX_GDSC>; 1282 }; 1283 1284 gpucc: clock-controller@5990000 { 1285 compatible = "qcom,sm6375-gpucc"; 1286 reg = <0 0x05990000 0 0x9000>; 1287 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1288 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1289 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, 1290 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1291 power-domains = <&rpmpd SM6375_VDDGX>; 1292 required-opps = <&rpmpd_opp_low_svs>; 1293 #clock-cells = <1>; 1294 #reset-cells = <1>; 1295 #power-domain-cells = <1>; 1296 }; 1297 1298 remoteproc_mss: remoteproc@6000000 { 1299 compatible = "qcom,sm6375-mpss-pas"; 1300 reg = <0 0x06000000 0 0x4040>; 1301 1302 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1303 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1304 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1305 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1306 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1307 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1308 interrupt-names = "wdog", 1309 "fatal", 1310 "ready", 1311 "handover", 1312 "stop-ack", 1313 "shutdown-ack"; 1314 1315 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1316 clock-names = "xo"; 1317 1318 power-domains = <&rpmpd SM6375_VDDCX>; 1319 power-domain-names = "cx"; 1320 1321 memory-region = <&pil_mpss_wlan_mem>; 1322 1323 qcom,smem-states = <&smp2p_modem_out 0>; 1324 qcom,smem-state-names = "stop"; 1325 1326 status = "disabled"; 1327 1328 glink-edge { 1329 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1330 IPCC_MPROC_SIGNAL_GLINK_QMP 1331 IRQ_TYPE_EDGE_RISING>; 1332 mboxes = <&ipcc IPCC_CLIENT_MPSS 1333 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1334 label = "modem"; 1335 qcom,remote-pid = <1>; 1336 }; 1337 }; 1338 1339 remoteproc_adsp: remoteproc@a400000 { 1340 compatible = "qcom,sm6375-adsp-pas"; 1341 reg = <0 0x0a400000 0 0x100>; 1342 1343 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1344 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1345 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1346 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1347 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1348 interrupt-names = "wdog", "fatal", "ready", 1349 "handover", "stop-ack"; 1350 1351 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1352 clock-names = "xo"; 1353 1354 power-domains = <&rpmpd SM6375_VDD_LPI_CX>, 1355 <&rpmpd SM6375_VDD_LPI_MX>; 1356 power-domain-names = "lcx", "lmx"; 1357 1358 memory-region = <&pil_adsp_mem>; 1359 1360 qcom,smem-states = <&smp2p_adsp_out 0>; 1361 qcom,smem-state-names = "stop"; 1362 1363 status = "disabled"; 1364 1365 glink-edge { 1366 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1367 IPCC_MPROC_SIGNAL_GLINK_QMP 1368 IRQ_TYPE_EDGE_RISING>; 1369 mboxes = <&ipcc IPCC_CLIENT_LPASS 1370 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1371 1372 label = "lpass"; 1373 qcom,remote-pid = <2>; 1374 }; 1375 }; 1376 1377 remoteproc_cdsp: remoteproc@b000000 { 1378 compatible = "qcom,sm6375-cdsp-pas"; 1379 reg = <0x0 0x0b000000 0x0 0x100000>; 1380 1381 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 1382 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1383 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1384 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1385 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1386 interrupt-names = "wdog", "fatal", "ready", 1387 "handover", "stop-ack"; 1388 1389 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1390 clock-names = "xo"; 1391 1392 power-domains = <&rpmpd SM6375_VDDCX>; 1393 power-domain-names = "cx"; 1394 1395 memory-region = <&pil_cdsp_mem>; 1396 1397 qcom,smem-states = <&smp2p_cdsp_out 0>; 1398 qcom,smem-state-names = "stop"; 1399 1400 status = "disabled"; 1401 1402 glink-edge { 1403 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1404 IPCC_MPROC_SIGNAL_GLINK_QMP 1405 IRQ_TYPE_EDGE_RISING>; 1406 mboxes = <&ipcc IPCC_CLIENT_CDSP 1407 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1408 label = "cdsp"; 1409 qcom,remote-pid = <5>; 1410 }; 1411 }; 1412 1413 sram@c125000 { 1414 compatible = "qcom,sm6375-imem", "syscon", "simple-mfd"; 1415 reg = <0 0x0c125000 0 0x1000>; 1416 ranges = <0 0 0x0c125000 0x1000>; 1417 1418 #address-cells = <1>; 1419 #size-cells = <1>; 1420 1421 pil-reloc@94c { 1422 compatible = "qcom,pil-reloc-info"; 1423 reg = <0x94c 0xc8>; 1424 }; 1425 }; 1426 1427 apps_smmu: iommu@c600000 { 1428 compatible = "qcom,sm6375-smmu-500", "arm,mmu-500"; 1429 reg = <0 0x0c600000 0 0x100000>; 1430 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1495 1496 power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>, 1497 <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC>, 1498 <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 1499 #global-interrupts = <1>; 1500 #iommu-cells = <2>; 1501 }; 1502 1503 wifi: wifi@c800000 { 1504 compatible = "qcom,wcn3990-wifi"; 1505 reg = <0 0x0c800000 0 0x800000>; 1506 reg-names = "membase"; 1507 memory-region = <&pil_wlan_mem>; 1508 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1520 iommus = <&apps_smmu 0x80 0x1>; 1521 qcom,msa-fixed-perm; 1522 status = "disabled"; 1523 }; 1524 1525 intc: interrupt-controller@f200000 { 1526 compatible = "arm,gic-v3"; 1527 reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */ 1528 <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */ 1529 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1530 #redistributor-regions = <1>; 1531 #interrupt-cells = <3>; 1532 redistributor-stride = <0 0x20000>; 1533 interrupt-controller; 1534 }; 1535 1536 timer@f420000 { 1537 compatible = "arm,armv7-timer-mem"; 1538 reg = <0 0x0f420000 0 0x1000>; 1539 ranges = <0 0 0 0x20000000>; 1540 #address-cells = <1>; 1541 #size-cells = <1>; 1542 1543 frame@f421000 { 1544 reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>; 1545 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1547 frame-number = <0>; 1548 }; 1549 1550 frame@f423000 { 1551 reg = <0x0f243000 0x1000>; 1552 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1553 frame-number = <1>; 1554 status = "disabled"; 1555 }; 1556 1557 frame@f425000 { 1558 reg = <0x0f425000 0x1000>; 1559 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1560 frame-number = <2>; 1561 status = "disabled"; 1562 }; 1563 1564 frame@f427000 { 1565 reg = <0x0f427000 0x1000>; 1566 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1567 frame-number = <3>; 1568 status = "disabled"; 1569 }; 1570 1571 frame@f429000 { 1572 reg = <0x0f429000 0x1000>; 1573 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1574 frame-number = <4>; 1575 status = "disabled"; 1576 }; 1577 1578 frame@f42b000 { 1579 reg = <0x0f42b000 0x1000>; 1580 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1581 frame-number = <5>; 1582 status = "disabled"; 1583 }; 1584 1585 frame@f42d000 { 1586 reg = <0x0f42d000 0x1000>; 1587 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1588 frame-number = <6>; 1589 status = "disabled"; 1590 }; 1591 }; 1592 1593 cpucp_l3: interconnect@fd90000 { 1594 compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3"; 1595 reg = <0 0x0fd90000 0 0x1000>; 1596 1597 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1598 clock-names = "xo", "alternate"; 1599 #interconnect-cells = <1>; 1600 }; 1601 1602 cpufreq_hw: cpufreq@fd91000 { 1603 compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; 1604 reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; 1605 reg-names = "freq-domain0", "freq-domain1"; 1606 1607 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1608 clock-names = "xo", "alternate"; 1609 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1611 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 1612 #freq-domain-cells = <1>; 1613 #clock-cells = <1>; 1614 }; 1615 }; 1616 1617 thermal-zones { 1618 mapss0-thermal { 1619 polling-delay-passive = <0>; 1620 polling-delay = <0>; 1621 1622 thermal-sensors = <&tsens0 0>; 1623 1624 trips { 1625 mapss0_alert0: trip-point0 { 1626 temperature = <90000>; 1627 hysteresis = <2000>; 1628 type = "passive"; 1629 }; 1630 1631 mapss0_alert1: trip-point1 { 1632 temperature = <95000>; 1633 hysteresis = <2000>; 1634 type = "passive"; 1635 }; 1636 1637 mapss0_crit: mapss-crit { 1638 temperature = <110000>; 1639 hysteresis = <1000>; 1640 type = "critical"; 1641 }; 1642 }; 1643 }; 1644 1645 cpu0-thermal { 1646 polling-delay-passive = <0>; 1647 polling-delay = <0>; 1648 1649 thermal-sensors = <&tsens0 1>; 1650 1651 trips { 1652 cpu0_alert0: trip-point0 { 1653 temperature = <90000>; 1654 hysteresis = <2000>; 1655 type = "passive"; 1656 }; 1657 1658 cpu0_alert1: trip-point1 { 1659 temperature = <95000>; 1660 hysteresis = <2000>; 1661 type = "passive"; 1662 }; 1663 1664 cpu0_crit: cpu-crit { 1665 temperature = <110000>; 1666 hysteresis = <1000>; 1667 type = "critical"; 1668 }; 1669 }; 1670 }; 1671 1672 cpu1-thermal { 1673 polling-delay-passive = <0>; 1674 polling-delay = <0>; 1675 1676 thermal-sensors = <&tsens0 2>; 1677 1678 trips { 1679 cpu1_alert0: trip-point0 { 1680 temperature = <90000>; 1681 hysteresis = <2000>; 1682 type = "passive"; 1683 }; 1684 1685 cpu1_alert1: trip-point1 { 1686 temperature = <95000>; 1687 hysteresis = <2000>; 1688 type = "passive"; 1689 }; 1690 1691 cpu1_crit: cpu-crit { 1692 temperature = <110000>; 1693 hysteresis = <1000>; 1694 type = "critical"; 1695 }; 1696 }; 1697 }; 1698 1699 cpu2-thermal { 1700 polling-delay-passive = <0>; 1701 polling-delay = <0>; 1702 1703 thermal-sensors = <&tsens0 3>; 1704 1705 trips { 1706 cpu2_alert0: trip-point0 { 1707 temperature = <90000>; 1708 hysteresis = <2000>; 1709 type = "passive"; 1710 }; 1711 1712 cpu2_alert1: trip-point1 { 1713 temperature = <95000>; 1714 hysteresis = <2000>; 1715 type = "passive"; 1716 }; 1717 1718 cpu2_crit: cpu-crit { 1719 temperature = <110000>; 1720 hysteresis = <1000>; 1721 type = "critical"; 1722 }; 1723 }; 1724 }; 1725 1726 cpu3-thermal { 1727 polling-delay-passive = <0>; 1728 polling-delay = <0>; 1729 1730 thermal-sensors = <&tsens0 4>; 1731 1732 trips { 1733 cpu3_alert0: trip-point0 { 1734 temperature = <90000>; 1735 hysteresis = <2000>; 1736 type = "passive"; 1737 }; 1738 1739 cpu3_alert1: trip-point1 { 1740 temperature = <95000>; 1741 hysteresis = <2000>; 1742 type = "passive"; 1743 }; 1744 1745 cpu3_crit: cpu-crit { 1746 temperature = <110000>; 1747 hysteresis = <1000>; 1748 type = "critical"; 1749 }; 1750 }; 1751 }; 1752 1753 cpu4-thermal { 1754 polling-delay-passive = <0>; 1755 polling-delay = <0>; 1756 1757 thermal-sensors = <&tsens0 5>; 1758 1759 trips { 1760 cpu4_alert0: trip-point0 { 1761 temperature = <90000>; 1762 hysteresis = <2000>; 1763 type = "passive"; 1764 }; 1765 1766 cpu4_alert1: trip-point1 { 1767 temperature = <95000>; 1768 hysteresis = <2000>; 1769 type = "passive"; 1770 }; 1771 1772 cpu4_crit: cpu-crit { 1773 temperature = <110000>; 1774 hysteresis = <1000>; 1775 type = "critical"; 1776 }; 1777 }; 1778 }; 1779 1780 cpu5-thermal { 1781 polling-delay-passive = <0>; 1782 polling-delay = <0>; 1783 1784 thermal-sensors = <&tsens0 6>; 1785 1786 trips { 1787 cpu5_alert0: trip-point0 { 1788 temperature = <90000>; 1789 hysteresis = <2000>; 1790 type = "passive"; 1791 }; 1792 1793 cpu5_alert1: trip-point1 { 1794 temperature = <95000>; 1795 hysteresis = <2000>; 1796 type = "passive"; 1797 }; 1798 1799 cpu5_crit: cpu-crit { 1800 temperature = <110000>; 1801 hysteresis = <1000>; 1802 type = "critical"; 1803 }; 1804 }; 1805 }; 1806 1807 cluster0-thermal { 1808 polling-delay-passive = <0>; 1809 polling-delay = <0>; 1810 1811 thermal-sensors = <&tsens0 7>; 1812 1813 trips { 1814 cluster0_alert0: trip-point0 { 1815 temperature = <90000>; 1816 hysteresis = <2000>; 1817 type = "passive"; 1818 }; 1819 1820 cluster0_alert1: trip-point1 { 1821 temperature = <95000>; 1822 hysteresis = <2000>; 1823 type = "passive"; 1824 }; 1825 1826 cluster0_crit: cpu-crit { 1827 temperature = <110000>; 1828 hysteresis = <1000>; 1829 type = "critical"; 1830 }; 1831 }; 1832 }; 1833 1834 cluster1-thermal { 1835 polling-delay-passive = <0>; 1836 polling-delay = <0>; 1837 1838 thermal-sensors = <&tsens0 8>; 1839 1840 trips { 1841 cluster1_alert0: trip-point0 { 1842 temperature = <90000>; 1843 hysteresis = <2000>; 1844 type = "passive"; 1845 }; 1846 1847 cluster1_alert1: trip-point1 { 1848 temperature = <95000>; 1849 hysteresis = <2000>; 1850 type = "passive"; 1851 }; 1852 1853 cluster1_crit: cpu-crit { 1854 temperature = <110000>; 1855 hysteresis = <1000>; 1856 type = "critical"; 1857 }; 1858 }; 1859 }; 1860 1861 cpu6-thermal { 1862 polling-delay-passive = <0>; 1863 polling-delay = <0>; 1864 1865 thermal-sensors = <&tsens0 9>; 1866 1867 trips { 1868 cpu6_alert0: trip-point0 { 1869 temperature = <90000>; 1870 hysteresis = <2000>; 1871 type = "passive"; 1872 }; 1873 1874 cpu6_alert1: trip-point1 { 1875 temperature = <95000>; 1876 hysteresis = <2000>; 1877 type = "passive"; 1878 }; 1879 1880 cpu6_crit: cpu-crit { 1881 temperature = <110000>; 1882 hysteresis = <1000>; 1883 type = "critical"; 1884 }; 1885 }; 1886 }; 1887 1888 cpu7-thermal { 1889 polling-delay-passive = <0>; 1890 polling-delay = <0>; 1891 1892 thermal-sensors = <&tsens0 10>; 1893 1894 trips { 1895 cpu7_alert0: trip-point0 { 1896 temperature = <90000>; 1897 hysteresis = <2000>; 1898 type = "passive"; 1899 }; 1900 1901 cpu7_alert1: trip-point1 { 1902 temperature = <95000>; 1903 hysteresis = <2000>; 1904 type = "passive"; 1905 }; 1906 1907 cpu7_crit: cpu-crit { 1908 temperature = <110000>; 1909 hysteresis = <1000>; 1910 type = "critical"; 1911 }; 1912 }; 1913 }; 1914 1915 cpu-unk0-thermal { 1916 polling-delay-passive = <0>; 1917 polling-delay = <0>; 1918 1919 thermal-sensors = <&tsens0 11>; 1920 1921 trips { 1922 cpu_unk0_alert0: trip-point0 { 1923 temperature = <90000>; 1924 hysteresis = <2000>; 1925 type = "passive"; 1926 }; 1927 1928 cpu_unk0_alert1: trip-point1 { 1929 temperature = <95000>; 1930 hysteresis = <2000>; 1931 type = "passive"; 1932 }; 1933 1934 cpu_unk0_crit: cpu-crit { 1935 temperature = <110000>; 1936 hysteresis = <1000>; 1937 type = "critical"; 1938 }; 1939 }; 1940 }; 1941 1942 cpu-unk1-thermal { 1943 polling-delay-passive = <0>; 1944 polling-delay = <0>; 1945 1946 thermal-sensors = <&tsens0 12>; 1947 1948 trips { 1949 cpu_unk1_alert0: trip-point0 { 1950 temperature = <90000>; 1951 hysteresis = <2000>; 1952 type = "passive"; 1953 }; 1954 1955 cpu_unk1_alert1: trip-point1 { 1956 temperature = <95000>; 1957 hysteresis = <2000>; 1958 type = "passive"; 1959 }; 1960 1961 cpu_unk1_crit: cpu-crit { 1962 temperature = <110000>; 1963 hysteresis = <1000>; 1964 type = "critical"; 1965 }; 1966 }; 1967 }; 1968 1969 gpuss0-thermal { 1970 polling-delay-passive = <0>; 1971 polling-delay = <0>; 1972 1973 thermal-sensors = <&tsens0 13>; 1974 1975 trips { 1976 gpuss0_alert0: trip-point0 { 1977 temperature = <90000>; 1978 hysteresis = <2000>; 1979 type = "passive"; 1980 }; 1981 1982 gpuss0_alert1: trip-point1 { 1983 temperature = <95000>; 1984 hysteresis = <2000>; 1985 type = "passive"; 1986 }; 1987 1988 gpuss0_crit: gpu-crit { 1989 temperature = <110000>; 1990 hysteresis = <1000>; 1991 type = "critical"; 1992 }; 1993 }; 1994 }; 1995 1996 gpuss1-thermal { 1997 polling-delay-passive = <0>; 1998 polling-delay = <0>; 1999 2000 thermal-sensors = <&tsens0 14>; 2001 2002 trips { 2003 gpuss1_alert0: trip-point0 { 2004 temperature = <90000>; 2005 hysteresis = <2000>; 2006 type = "passive"; 2007 }; 2008 2009 gpuss1_alert1: trip-point1 { 2010 temperature = <95000>; 2011 hysteresis = <2000>; 2012 type = "passive"; 2013 }; 2014 2015 gpuss1_crit: gpu-crit { 2016 temperature = <110000>; 2017 hysteresis = <1000>; 2018 type = "critical"; 2019 }; 2020 }; 2021 }; 2022 2023 mapss1-thermal { 2024 polling-delay-passive = <0>; 2025 polling-delay = <0>; 2026 2027 thermal-sensors = <&tsens1 0>; 2028 2029 trips { 2030 mapss1_alert0: trip-point0 { 2031 temperature = <90000>; 2032 hysteresis = <2000>; 2033 type = "passive"; 2034 }; 2035 2036 mapss1_alert1: trip-point1 { 2037 temperature = <95000>; 2038 hysteresis = <2000>; 2039 type = "passive"; 2040 }; 2041 2042 mapss1_crit: mapss-crit { 2043 temperature = <110000>; 2044 hysteresis = <1000>; 2045 type = "critical"; 2046 }; 2047 }; 2048 }; 2049 2050 cwlan-thermal { 2051 polling-delay-passive = <0>; 2052 polling-delay = <0>; 2053 2054 thermal-sensors = <&tsens1 1>; 2055 2056 trips { 2057 cwlan_alert0: trip-point0 { 2058 temperature = <90000>; 2059 hysteresis = <2000>; 2060 type = "passive"; 2061 }; 2062 2063 cwlan_alert1: trip-point1 { 2064 temperature = <95000>; 2065 hysteresis = <2000>; 2066 type = "passive"; 2067 }; 2068 2069 cwlan_crit: cwlan-crit { 2070 temperature = <110000>; 2071 hysteresis = <1000>; 2072 type = "critical"; 2073 }; 2074 }; 2075 }; 2076 2077 audio-thermal { 2078 polling-delay-passive = <0>; 2079 polling-delay = <0>; 2080 2081 thermal-sensors = <&tsens1 2>; 2082 2083 trips { 2084 audio_alert0: trip-point0 { 2085 temperature = <90000>; 2086 hysteresis = <2000>; 2087 type = "passive"; 2088 }; 2089 2090 audio_alert1: trip-point1 { 2091 temperature = <95000>; 2092 hysteresis = <2000>; 2093 type = "passive"; 2094 }; 2095 2096 audio_crit: audio-crit { 2097 temperature = <110000>; 2098 hysteresis = <1000>; 2099 type = "critical"; 2100 }; 2101 }; 2102 }; 2103 2104 ddr-thermal { 2105 polling-delay-passive = <0>; 2106 polling-delay = <0>; 2107 2108 thermal-sensors = <&tsens1 3>; 2109 2110 trips { 2111 ddr_alert0: trip-point0 { 2112 temperature = <90000>; 2113 hysteresis = <2000>; 2114 type = "passive"; 2115 }; 2116 2117 ddr_alert1: trip-point1 { 2118 temperature = <95000>; 2119 hysteresis = <2000>; 2120 type = "passive"; 2121 }; 2122 2123 ddr_crit: ddr-crit { 2124 temperature = <110000>; 2125 hysteresis = <1000>; 2126 type = "critical"; 2127 }; 2128 }; 2129 }; 2130 2131 q6hvx-thermal { 2132 polling-delay-passive = <0>; 2133 polling-delay = <0>; 2134 2135 thermal-sensors = <&tsens1 4>; 2136 2137 trips { 2138 q6hvx_alert0: trip-point0 { 2139 temperature = <90000>; 2140 hysteresis = <2000>; 2141 type = "passive"; 2142 }; 2143 2144 q6hvx_alert1: trip-point1 { 2145 temperature = <95000>; 2146 hysteresis = <2000>; 2147 type = "passive"; 2148 }; 2149 2150 q6hvx_crit: q6hvx-crit { 2151 temperature = <110000>; 2152 hysteresis = <1000>; 2153 type = "critical"; 2154 }; 2155 }; 2156 }; 2157 2158 camera-thermal { 2159 polling-delay-passive = <0>; 2160 polling-delay = <0>; 2161 2162 thermal-sensors = <&tsens1 5>; 2163 2164 trips { 2165 camera_alert0: trip-point0 { 2166 temperature = <90000>; 2167 hysteresis = <2000>; 2168 type = "passive"; 2169 }; 2170 2171 camera_alert1: trip-point1 { 2172 temperature = <95000>; 2173 hysteresis = <2000>; 2174 type = "passive"; 2175 }; 2176 2177 camera_crit: camera-crit { 2178 temperature = <110000>; 2179 hysteresis = <1000>; 2180 type = "critical"; 2181 }; 2182 }; 2183 }; 2184 2185 mdm-core0-thermal { 2186 polling-delay-passive = <0>; 2187 polling-delay = <0>; 2188 2189 thermal-sensors = <&tsens1 6>; 2190 2191 trips { 2192 mdm_core0_alert0: trip-point0 { 2193 temperature = <90000>; 2194 hysteresis = <2000>; 2195 type = "passive"; 2196 }; 2197 2198 mdm_core0_alert1: trip-point1 { 2199 temperature = <95000>; 2200 hysteresis = <2000>; 2201 type = "passive"; 2202 }; 2203 2204 mdm_core0_crit: mdm-core0-crit { 2205 temperature = <110000>; 2206 hysteresis = <1000>; 2207 type = "critical"; 2208 }; 2209 }; 2210 }; 2211 2212 mdm-core1-thermal { 2213 polling-delay-passive = <0>; 2214 polling-delay = <0>; 2215 2216 thermal-sensors = <&tsens1 7>; 2217 2218 trips { 2219 mdm_core1_alert0: trip-point0 { 2220 temperature = <90000>; 2221 hysteresis = <2000>; 2222 type = "passive"; 2223 }; 2224 2225 mdm_core1_alert1: trip-point1 { 2226 temperature = <95000>; 2227 hysteresis = <2000>; 2228 type = "passive"; 2229 }; 2230 2231 mdm_core1_crit: mdm-core1-crit { 2232 temperature = <110000>; 2233 hysteresis = <1000>; 2234 type = "critical"; 2235 }; 2236 }; 2237 }; 2238 2239 mdm-vec-thermal { 2240 polling-delay-passive = <0>; 2241 polling-delay = <0>; 2242 2243 thermal-sensors = <&tsens1 8>; 2244 2245 trips { 2246 mdm_vec_alert0: trip-point0 { 2247 temperature = <90000>; 2248 hysteresis = <2000>; 2249 type = "passive"; 2250 }; 2251 2252 mdm_vec_alert1: trip-point1 { 2253 temperature = <95000>; 2254 hysteresis = <2000>; 2255 type = "passive"; 2256 }; 2257 2258 mdm_vec_crit: mdm-vec-crit { 2259 temperature = <110000>; 2260 hysteresis = <1000>; 2261 type = "critical"; 2262 }; 2263 }; 2264 }; 2265 2266 msm-scl-thermal { 2267 polling-delay-passive = <0>; 2268 polling-delay = <0>; 2269 2270 thermal-sensors = <&tsens1 9>; 2271 2272 trips { 2273 msm_scl_alert0: trip-point0 { 2274 temperature = <90000>; 2275 hysteresis = <2000>; 2276 type = "passive"; 2277 }; 2278 2279 msm_scl_alert1: trip-point1 { 2280 temperature = <95000>; 2281 hysteresis = <2000>; 2282 type = "passive"; 2283 }; 2284 2285 msm_scl_crit: msm-scl-crit { 2286 temperature = <110000>; 2287 hysteresis = <1000>; 2288 type = "critical"; 2289 }; 2290 }; 2291 }; 2292 2293 video-thermal { 2294 polling-delay-passive = <0>; 2295 polling-delay = <0>; 2296 2297 thermal-sensors = <&tsens1 10>; 2298 2299 trips { 2300 video_alert0: trip-point0 { 2301 temperature = <90000>; 2302 hysteresis = <2000>; 2303 type = "passive"; 2304 }; 2305 2306 video_alert1: trip-point1 { 2307 temperature = <95000>; 2308 hysteresis = <2000>; 2309 type = "passive"; 2310 }; 2311 2312 video_crit: video-crit { 2313 temperature = <110000>; 2314 hysteresis = <1000>; 2315 type = "critical"; 2316 }; 2317 }; 2318 }; 2319 }; 2320 2321 timer { 2322 compatible = "arm,armv8-timer"; 2323 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2324 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2325 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2326 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2327 }; 2328}; 2329