1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2017 NXP 4 * Copyright 2011,2016 Freescale Semiconductor, Inc. 5 * Copyright 2011 Linaro Ltd. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/hrtimer.h> 10 #include <linux/init.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/perf_event.h> 18 #include <linux/slab.h> 19 20 #include "common.h" 21 22 #define MMDC_MAPSR 0x404 23 #define BP_MMDC_MAPSR_PSD 0 24 #define BP_MMDC_MAPSR_PSS 4 25 26 #define MMDC_MDMISC 0x18 27 #define BM_MMDC_MDMISC_DDR_TYPE 0x18 28 #define BP_MMDC_MDMISC_DDR_TYPE 0x3 29 30 #define TOTAL_CYCLES 0x0 31 #define BUSY_CYCLES 0x1 32 #define READ_ACCESSES 0x2 33 #define WRITE_ACCESSES 0x3 34 #define READ_BYTES 0x4 35 #define WRITE_BYTES 0x5 36 37 /* Enables, resets, freezes, overflow profiling*/ 38 #define DBG_DIS 0x0 39 #define DBG_EN 0x1 40 #define DBG_RST 0x2 41 #define PRF_FRZ 0x4 42 #define CYC_OVF 0x8 43 #define PROFILE_SEL 0x10 44 45 #define MMDC_MADPCR0 0x410 46 #define MMDC_MADPCR1 0x414 47 #define MMDC_MADPSR0 0x418 48 #define MMDC_MADPSR1 0x41C 49 #define MMDC_MADPSR2 0x420 50 #define MMDC_MADPSR3 0x424 51 #define MMDC_MADPSR4 0x428 52 #define MMDC_MADPSR5 0x42C 53 54 #define MMDC_NUM_COUNTERS 6 55 56 #define MMDC_FLAG_PROFILE_SEL 0x1 57 #define MMDC_PRF_AXI_ID_CLEAR 0x0 58 59 #define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu) 60 61 static int ddr_type; 62 63 struct fsl_mmdc_devtype_data { 64 unsigned int flags; 65 }; 66 67 static const struct fsl_mmdc_devtype_data imx6q_data = { 68 }; 69 70 static const struct fsl_mmdc_devtype_data imx6qp_data = { 71 .flags = MMDC_FLAG_PROFILE_SEL, 72 }; 73 74 static const struct of_device_id imx_mmdc_dt_ids[] = { 75 { .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data}, 76 { .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data}, 77 { /* sentinel */ } 78 }; 79 80 #ifdef CONFIG_PERF_EVENTS 81 82 static enum cpuhp_state cpuhp_mmdc_state; 83 static DEFINE_IDA(mmdc_ida); 84 85 PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00") 86 PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01") 87 PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02") 88 PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "event=0x03") 89 PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04") 90 PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB"); 91 PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001"); 92 PMU_EVENT_ATTR_STRING(write-bytes, mmdc_pmu_write_bytes, "event=0x05") 93 PMU_EVENT_ATTR_STRING(write-bytes.unit, mmdc_pmu_write_bytes_unit, "MB"); 94 PMU_EVENT_ATTR_STRING(write-bytes.scale, mmdc_pmu_write_bytes_scale, "0.000001"); 95 96 struct mmdc_pmu { 97 struct pmu pmu; 98 void __iomem *mmdc_base; 99 cpumask_t cpu; 100 struct hrtimer hrtimer; 101 unsigned int active_events; 102 int id; 103 struct device *dev; 104 struct perf_event *mmdc_events[MMDC_NUM_COUNTERS]; 105 struct hlist_node node; 106 struct fsl_mmdc_devtype_data *devtype_data; 107 struct clk *mmdc_ipg_clk; 108 }; 109 110 /* 111 * Polling period is set to one second, overflow of total-cycles (the fastest 112 * increasing counter) takes ten seconds so one second is safe 113 */ 114 static unsigned int mmdc_pmu_poll_period_us = 1000000; 115 116 module_param_named(pmu_pmu_poll_period_us, mmdc_pmu_poll_period_us, uint, 117 S_IRUGO | S_IWUSR); 118 119 static ktime_t mmdc_pmu_timer_period(void) 120 { 121 return ns_to_ktime((u64)mmdc_pmu_poll_period_us * 1000); 122 } 123 124 static ssize_t mmdc_pmu_cpumask_show(struct device *dev, 125 struct device_attribute *attr, char *buf) 126 { 127 struct mmdc_pmu *pmu_mmdc = dev_get_drvdata(dev); 128 129 return cpumap_print_to_pagebuf(true, buf, &pmu_mmdc->cpu); 130 } 131 132 static struct device_attribute mmdc_pmu_cpumask_attr = 133 __ATTR(cpumask, S_IRUGO, mmdc_pmu_cpumask_show, NULL); 134 135 static struct attribute *mmdc_pmu_cpumask_attrs[] = { 136 &mmdc_pmu_cpumask_attr.attr, 137 NULL, 138 }; 139 140 static struct attribute_group mmdc_pmu_cpumask_attr_group = { 141 .attrs = mmdc_pmu_cpumask_attrs, 142 }; 143 144 static struct attribute *mmdc_pmu_events_attrs[] = { 145 &mmdc_pmu_total_cycles.attr.attr, 146 &mmdc_pmu_busy_cycles.attr.attr, 147 &mmdc_pmu_read_accesses.attr.attr, 148 &mmdc_pmu_write_accesses.attr.attr, 149 &mmdc_pmu_read_bytes.attr.attr, 150 &mmdc_pmu_read_bytes_unit.attr.attr, 151 &mmdc_pmu_read_bytes_scale.attr.attr, 152 &mmdc_pmu_write_bytes.attr.attr, 153 &mmdc_pmu_write_bytes_unit.attr.attr, 154 &mmdc_pmu_write_bytes_scale.attr.attr, 155 NULL, 156 }; 157 158 static struct attribute_group mmdc_pmu_events_attr_group = { 159 .name = "events", 160 .attrs = mmdc_pmu_events_attrs, 161 }; 162 163 PMU_FORMAT_ATTR(event, "config:0-63"); 164 PMU_FORMAT_ATTR(axi_id, "config1:0-63"); 165 166 static struct attribute *mmdc_pmu_format_attrs[] = { 167 &format_attr_event.attr, 168 &format_attr_axi_id.attr, 169 NULL, 170 }; 171 172 static struct attribute_group mmdc_pmu_format_attr_group = { 173 .name = "format", 174 .attrs = mmdc_pmu_format_attrs, 175 }; 176 177 static const struct attribute_group *attr_groups[] = { 178 &mmdc_pmu_events_attr_group, 179 &mmdc_pmu_format_attr_group, 180 &mmdc_pmu_cpumask_attr_group, 181 NULL, 182 }; 183 184 static u32 mmdc_pmu_read_counter(struct mmdc_pmu *pmu_mmdc, int cfg) 185 { 186 void __iomem *mmdc_base, *reg; 187 188 mmdc_base = pmu_mmdc->mmdc_base; 189 190 switch (cfg) { 191 case TOTAL_CYCLES: 192 reg = mmdc_base + MMDC_MADPSR0; 193 break; 194 case BUSY_CYCLES: 195 reg = mmdc_base + MMDC_MADPSR1; 196 break; 197 case READ_ACCESSES: 198 reg = mmdc_base + MMDC_MADPSR2; 199 break; 200 case WRITE_ACCESSES: 201 reg = mmdc_base + MMDC_MADPSR3; 202 break; 203 case READ_BYTES: 204 reg = mmdc_base + MMDC_MADPSR4; 205 break; 206 case WRITE_BYTES: 207 reg = mmdc_base + MMDC_MADPSR5; 208 break; 209 default: 210 return WARN_ONCE(1, 211 "invalid configuration %d for mmdc counter", cfg); 212 } 213 return readl(reg); 214 } 215 216 static int mmdc_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) 217 { 218 struct mmdc_pmu *pmu_mmdc = hlist_entry_safe(node, struct mmdc_pmu, node); 219 int target; 220 221 if (!cpumask_test_and_clear_cpu(cpu, &pmu_mmdc->cpu)) 222 return 0; 223 224 target = cpumask_any_but(cpu_online_mask, cpu); 225 if (target >= nr_cpu_ids) 226 return 0; 227 228 perf_pmu_migrate_context(&pmu_mmdc->pmu, cpu, target); 229 cpumask_set_cpu(target, &pmu_mmdc->cpu); 230 231 return 0; 232 } 233 234 static bool mmdc_pmu_group_event_is_valid(struct perf_event *event, 235 struct pmu *pmu, 236 unsigned long *used_counters) 237 { 238 int cfg = event->attr.config; 239 240 if (is_software_event(event)) 241 return true; 242 243 if (event->pmu != pmu) 244 return false; 245 246 return !test_and_set_bit(cfg, used_counters); 247 } 248 249 /* 250 * Each event has a single fixed-purpose counter, so we can only have a 251 * single active event for each at any point in time. Here we just check 252 * for duplicates, and rely on mmdc_pmu_event_init to verify that the HW 253 * event numbers are valid. 254 */ 255 static bool mmdc_pmu_group_is_valid(struct perf_event *event) 256 { 257 struct pmu *pmu = event->pmu; 258 struct perf_event *leader = event->group_leader; 259 struct perf_event *sibling; 260 unsigned long counter_mask = 0; 261 262 set_bit(leader->attr.config, &counter_mask); 263 264 if (event != leader) { 265 if (!mmdc_pmu_group_event_is_valid(event, pmu, &counter_mask)) 266 return false; 267 } 268 269 for_each_sibling_event(sibling, leader) { 270 if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask)) 271 return false; 272 } 273 274 return true; 275 } 276 277 static int mmdc_pmu_event_init(struct perf_event *event) 278 { 279 struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); 280 int cfg = event->attr.config; 281 282 if (event->attr.type != event->pmu->type) 283 return -ENOENT; 284 285 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) 286 return -EOPNOTSUPP; 287 288 if (event->cpu < 0) { 289 dev_warn(pmu_mmdc->dev, "Can't provide per-task data!\n"); 290 return -EOPNOTSUPP; 291 } 292 293 if (event->attr.sample_period) 294 return -EINVAL; 295 296 if (cfg < 0 || cfg >= MMDC_NUM_COUNTERS) 297 return -EINVAL; 298 299 if (!mmdc_pmu_group_is_valid(event)) 300 return -EINVAL; 301 302 event->cpu = cpumask_first(&pmu_mmdc->cpu); 303 return 0; 304 } 305 306 static void mmdc_pmu_event_update(struct perf_event *event) 307 { 308 struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); 309 struct hw_perf_event *hwc = &event->hw; 310 u64 delta, prev_raw_count, new_raw_count; 311 312 do { 313 prev_raw_count = local64_read(&hwc->prev_count); 314 new_raw_count = mmdc_pmu_read_counter(pmu_mmdc, 315 event->attr.config); 316 } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, 317 new_raw_count) != prev_raw_count); 318 319 delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF; 320 321 local64_add(delta, &event->count); 322 } 323 324 static void mmdc_pmu_event_start(struct perf_event *event, int flags) 325 { 326 struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); 327 struct hw_perf_event *hwc = &event->hw; 328 void __iomem *mmdc_base, *reg; 329 u32 val; 330 331 mmdc_base = pmu_mmdc->mmdc_base; 332 reg = mmdc_base + MMDC_MADPCR0; 333 334 /* 335 * hrtimer is required because mmdc does not provide an interrupt so 336 * polling is necessary 337 */ 338 hrtimer_start(&pmu_mmdc->hrtimer, mmdc_pmu_timer_period(), 339 HRTIMER_MODE_REL_PINNED); 340 341 local64_set(&hwc->prev_count, 0); 342 343 writel(DBG_RST, reg); 344 345 /* 346 * Write the AXI id parameter to MADPCR1. 347 */ 348 val = event->attr.config1; 349 reg = mmdc_base + MMDC_MADPCR1; 350 writel(val, reg); 351 352 reg = mmdc_base + MMDC_MADPCR0; 353 val = DBG_EN; 354 if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL) 355 val |= PROFILE_SEL; 356 357 writel(val, reg); 358 } 359 360 static int mmdc_pmu_event_add(struct perf_event *event, int flags) 361 { 362 struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); 363 struct hw_perf_event *hwc = &event->hw; 364 365 int cfg = event->attr.config; 366 367 if (flags & PERF_EF_START) 368 mmdc_pmu_event_start(event, flags); 369 370 if (pmu_mmdc->mmdc_events[cfg] != NULL) 371 return -EAGAIN; 372 373 pmu_mmdc->mmdc_events[cfg] = event; 374 pmu_mmdc->active_events++; 375 376 local64_set(&hwc->prev_count, mmdc_pmu_read_counter(pmu_mmdc, cfg)); 377 378 return 0; 379 } 380 381 static void mmdc_pmu_event_stop(struct perf_event *event, int flags) 382 { 383 struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); 384 void __iomem *mmdc_base, *reg; 385 386 mmdc_base = pmu_mmdc->mmdc_base; 387 reg = mmdc_base + MMDC_MADPCR0; 388 389 writel(PRF_FRZ, reg); 390 391 reg = mmdc_base + MMDC_MADPCR1; 392 writel(MMDC_PRF_AXI_ID_CLEAR, reg); 393 394 mmdc_pmu_event_update(event); 395 } 396 397 static void mmdc_pmu_event_del(struct perf_event *event, int flags) 398 { 399 struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); 400 int cfg = event->attr.config; 401 402 pmu_mmdc->mmdc_events[cfg] = NULL; 403 pmu_mmdc->active_events--; 404 405 if (pmu_mmdc->active_events == 0) 406 hrtimer_cancel(&pmu_mmdc->hrtimer); 407 408 mmdc_pmu_event_stop(event, PERF_EF_UPDATE); 409 } 410 411 static void mmdc_pmu_overflow_handler(struct mmdc_pmu *pmu_mmdc) 412 { 413 int i; 414 415 for (i = 0; i < MMDC_NUM_COUNTERS; i++) { 416 struct perf_event *event = pmu_mmdc->mmdc_events[i]; 417 418 if (event) 419 mmdc_pmu_event_update(event); 420 } 421 } 422 423 static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer) 424 { 425 struct mmdc_pmu *pmu_mmdc = container_of(hrtimer, struct mmdc_pmu, 426 hrtimer); 427 428 mmdc_pmu_overflow_handler(pmu_mmdc); 429 hrtimer_forward_now(hrtimer, mmdc_pmu_timer_period()); 430 431 return HRTIMER_RESTART; 432 } 433 434 static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc, 435 void __iomem *mmdc_base, struct device *dev) 436 { 437 *pmu_mmdc = (struct mmdc_pmu) { 438 .pmu = (struct pmu) { 439 .task_ctx_nr = perf_invalid_context, 440 .attr_groups = attr_groups, 441 .event_init = mmdc_pmu_event_init, 442 .add = mmdc_pmu_event_add, 443 .del = mmdc_pmu_event_del, 444 .start = mmdc_pmu_event_start, 445 .stop = mmdc_pmu_event_stop, 446 .read = mmdc_pmu_event_update, 447 .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 448 }, 449 .mmdc_base = mmdc_base, 450 .dev = dev, 451 .active_events = 0, 452 }; 453 454 pmu_mmdc->id = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL); 455 456 return pmu_mmdc->id; 457 } 458 459 static void imx_mmdc_remove(struct platform_device *pdev) 460 { 461 struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev); 462 463 ida_simple_remove(&mmdc_ida, pmu_mmdc->id); 464 cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); 465 perf_pmu_unregister(&pmu_mmdc->pmu); 466 iounmap(pmu_mmdc->mmdc_base); 467 clk_disable_unprepare(pmu_mmdc->mmdc_ipg_clk); 468 kfree(pmu_mmdc); 469 } 470 471 static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_base, 472 struct clk *mmdc_ipg_clk) 473 { 474 struct mmdc_pmu *pmu_mmdc; 475 char *name; 476 int ret; 477 const struct of_device_id *of_id = 478 of_match_device(imx_mmdc_dt_ids, &pdev->dev); 479 480 pmu_mmdc = kzalloc(sizeof(*pmu_mmdc), GFP_KERNEL); 481 if (!pmu_mmdc) { 482 pr_err("failed to allocate PMU device!\n"); 483 return -ENOMEM; 484 } 485 486 /* The first instance registers the hotplug state */ 487 if (!cpuhp_mmdc_state) { 488 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, 489 "perf/arm/mmdc:online", NULL, 490 mmdc_pmu_offline_cpu); 491 if (ret < 0) { 492 pr_err("cpuhp_setup_state_multi failed\n"); 493 goto pmu_free; 494 } 495 cpuhp_mmdc_state = ret; 496 } 497 498 ret = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev); 499 if (ret < 0) 500 goto pmu_free; 501 502 name = devm_kasprintf(&pdev->dev, 503 GFP_KERNEL, "mmdc%d", ret); 504 505 pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk; 506 pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data; 507 508 hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC, 509 HRTIMER_MODE_REL); 510 pmu_mmdc->hrtimer.function = mmdc_pmu_timer_handler; 511 512 cpumask_set_cpu(raw_smp_processor_id(), &pmu_mmdc->cpu); 513 514 /* Register the pmu instance for cpu hotplug */ 515 cpuhp_state_add_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); 516 517 ret = perf_pmu_register(&(pmu_mmdc->pmu), name, -1); 518 if (ret) 519 goto pmu_register_err; 520 521 platform_set_drvdata(pdev, pmu_mmdc); 522 return 0; 523 524 pmu_register_err: 525 pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret); 526 ida_simple_remove(&mmdc_ida, pmu_mmdc->id); 527 cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); 528 hrtimer_cancel(&pmu_mmdc->hrtimer); 529 pmu_free: 530 kfree(pmu_mmdc); 531 return ret; 532 } 533 534 #else 535 #define imx_mmdc_remove NULL 536 #define imx_mmdc_perf_init(pdev, mmdc_base, mmdc_ipg_clk) 0 537 #endif 538 539 static int imx_mmdc_probe(struct platform_device *pdev) 540 { 541 struct device_node *np = pdev->dev.of_node; 542 void __iomem *mmdc_base, *reg; 543 struct clk *mmdc_ipg_clk; 544 u32 val; 545 int err; 546 547 /* the ipg clock is optional */ 548 mmdc_ipg_clk = devm_clk_get(&pdev->dev, NULL); 549 if (IS_ERR(mmdc_ipg_clk)) 550 mmdc_ipg_clk = NULL; 551 552 err = clk_prepare_enable(mmdc_ipg_clk); 553 if (err) { 554 dev_err(&pdev->dev, "Unable to enable mmdc ipg clock.\n"); 555 return err; 556 } 557 558 mmdc_base = of_iomap(np, 0); 559 WARN_ON(!mmdc_base); 560 561 reg = mmdc_base + MMDC_MDMISC; 562 /* Get ddr type */ 563 val = readl_relaxed(reg); 564 ddr_type = (val & BM_MMDC_MDMISC_DDR_TYPE) >> 565 BP_MMDC_MDMISC_DDR_TYPE; 566 567 reg = mmdc_base + MMDC_MAPSR; 568 569 /* Enable automatic power saving */ 570 val = readl_relaxed(reg); 571 val &= ~(1 << BP_MMDC_MAPSR_PSD); 572 writel_relaxed(val, reg); 573 574 err = imx_mmdc_perf_init(pdev, mmdc_base, mmdc_ipg_clk); 575 if (err) { 576 iounmap(mmdc_base); 577 clk_disable_unprepare(mmdc_ipg_clk); 578 } 579 580 return err; 581 } 582 583 int imx_mmdc_get_ddr_type(void) 584 { 585 return ddr_type; 586 } 587 588 static struct platform_driver imx_mmdc_driver = { 589 .driver = { 590 .name = "imx-mmdc", 591 .of_match_table = imx_mmdc_dt_ids, 592 }, 593 .probe = imx_mmdc_probe, 594 .remove_new = imx_mmdc_remove, 595 }; 596 597 static int __init imx_mmdc_init(void) 598 { 599 return platform_driver_register(&imx_mmdc_driver); 600 } 601 postcore_initcall(imx_mmdc_init); 602