1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - apple,icestorm
89      - apple,firestorm
90      - arm,arm710t
91      - arm,arm720t
92      - arm,arm740t
93      - arm,arm7ej-s
94      - arm,arm7tdmi
95      - arm,arm7tdmi-s
96      - arm,arm9es
97      - arm,arm9ej-s
98      - arm,arm920t
99      - arm,arm922t
100      - arm,arm925
101      - arm,arm926e-s
102      - arm,arm926ej-s
103      - arm,arm940t
104      - arm,arm946e-s
105      - arm,arm966e-s
106      - arm,arm968e-s
107      - arm,arm9tdmi
108      - arm,arm1020e
109      - arm,arm1020t
110      - arm,arm1022e
111      - arm,arm1026ej-s
112      - arm,arm1136j-s
113      - arm,arm1136jf-s
114      - arm,arm1156t2-s
115      - arm,arm1156t2f-s
116      - arm,arm1176jzf
117      - arm,arm1176jz-s
118      - arm,arm1176jzf-s
119      - arm,arm11mpcore
120      - arm,armv8 # Only for s/w models
121      - arm,cortex-a5
122      - arm,cortex-a7
123      - arm,cortex-a8
124      - arm,cortex-a9
125      - arm,cortex-a12
126      - arm,cortex-a15
127      - arm,cortex-a17
128      - arm,cortex-a32
129      - arm,cortex-a34
130      - arm,cortex-a35
131      - arm,cortex-a53
132      - arm,cortex-a55
133      - arm,cortex-a57
134      - arm,cortex-a65
135      - arm,cortex-a72
136      - arm,cortex-a73
137      - arm,cortex-a75
138      - arm,cortex-a76
139      - arm,cortex-a77
140      - arm,cortex-m0
141      - arm,cortex-m0+
142      - arm,cortex-m1
143      - arm,cortex-m3
144      - arm,cortex-m4
145      - arm,cortex-r4
146      - arm,cortex-r5
147      - arm,cortex-r7
148      - arm,neoverse-e1
149      - arm,neoverse-n1
150      - brcm,brahma-b15
151      - brcm,brahma-b53
152      - brcm,vulcan
153      - cavium,thunder
154      - cavium,thunder2
155      - faraday,fa526
156      - intel,sa110
157      - intel,sa1100
158      - marvell,feroceon
159      - marvell,mohawk
160      - marvell,pj4a
161      - marvell,pj4b
162      - marvell,sheeva-v5
163      - marvell,sheeva-v7
164      - nvidia,tegra132-denver
165      - nvidia,tegra186-denver
166      - nvidia,tegra194-carmel
167      - qcom,krait
168      - qcom,kryo
169      - qcom,kryo260
170      - qcom,kryo280
171      - qcom,kryo385
172      - qcom,kryo468
173      - qcom,kryo485
174      - qcom,kryo560
175      - qcom,kryo685
176      - qcom,scorpion
177
178  enable-method:
179    $ref: '/schemas/types.yaml#/definitions/string'
180    oneOf:
181      # On ARM v8 64-bit this property is required
182      - enum:
183          - psci
184          - spin-table
185      # On ARM 32-bit systems this property is optional
186      - enum:
187          - actions,s500-smp
188          - allwinner,sun6i-a31
189          - allwinner,sun8i-a23
190          - allwinner,sun9i-a80-smp
191          - allwinner,sun8i-a83t-smp
192          - amlogic,meson8-smp
193          - amlogic,meson8b-smp
194          - arm,realview-smp
195          - aspeed,ast2600-smp
196          - brcm,bcm11351-cpu-method
197          - brcm,bcm23550
198          - brcm,bcm2836-smp
199          - brcm,bcm63138
200          - brcm,bcm-nsp-smp
201          - brcm,brahma-b15
202          - marvell,armada-375-smp
203          - marvell,armada-380-smp
204          - marvell,armada-390-smp
205          - marvell,armada-xp-smp
206          - marvell,98dx3236-smp
207          - marvell,mmp3-smp
208          - mediatek,mt6589-smp
209          - mediatek,mt81xx-tz-smp
210          - qcom,gcc-msm8660
211          - qcom,kpss-acc-v1
212          - qcom,kpss-acc-v2
213          - renesas,apmu
214          - renesas,r9a06g032-smp
215          - rockchip,rk3036-smp
216          - rockchip,rk3066-smp
217          - socionext,milbeaut-m10v-smp
218          - ste,dbx500-smp
219          - ti,am3352
220          - ti,am4372
221
222  cpu-release-addr:
223    $ref: '/schemas/types.yaml#/definitions/uint64'
224
225    description:
226      Required for systems that have an "enable-method"
227        property value of "spin-table".
228      On ARM v8 64-bit systems must be a two cell
229        property identifying a 64-bit zero-initialised
230        memory location.
231
232  cpu-idle-states:
233    $ref: '/schemas/types.yaml#/definitions/phandle-array'
234    description: |
235      List of phandles to idle state nodes supported
236      by this cpu (see ./idle-states.yaml).
237
238  capacity-dmips-mhz:
239    description:
240      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
241      DMIPS/MHz, relative to highest capacity-dmips-mhz
242      in the system.
243
244  dynamic-power-coefficient:
245    $ref: '/schemas/types.yaml#/definitions/uint32'
246    description:
247      A u32 value that represents the running time dynamic
248      power coefficient in units of uW/MHz/V^2. The
249      coefficient can either be calculated from power
250      measurements or derived by analysis.
251
252      The dynamic power consumption of the CPU  is
253      proportional to the square of the Voltage (V) and
254      the clock frequency (f). The coefficient is used to
255      calculate the dynamic power as below -
256
257      Pdyn = dynamic-power-coefficient * V^2 * f
258
259      where voltage is in V, frequency is in MHz.
260
261  performance-domains:
262    maxItems: 1
263    description:
264      List of phandles and performance domain specifiers, as defined by
265      bindings of the performance domain provider. See also
266      dvfs/performance-domain.yaml.
267
268  power-domains:
269    description:
270      List of phandles and PM domain specifiers, as defined by bindings of the
271      PM domain provider (see also ../power_domain.txt).
272
273  power-domain-names:
274    description:
275      A list of power domain name strings sorted in the same order as the
276      power-domains property.
277
278      For PSCI based platforms, the name corresponding to the index of the PSCI
279      PM domain provider, must be "psci".
280
281  qcom,saw:
282    $ref: '/schemas/types.yaml#/definitions/phandle'
283    description: |
284      Specifies the SAW* node associated with this CPU.
285
286      Required for systems that have an "enable-method" property
287      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
288
289      * arm/msm/qcom,saw2.txt
290
291  qcom,acc:
292    $ref: '/schemas/types.yaml#/definitions/phandle'
293    description: |
294      Specifies the ACC* node associated with this CPU.
295
296      Required for systems that have an "enable-method" property
297      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
298
299      * arm/msm/qcom,kpss-acc.txt
300
301  rockchip,pmu:
302    $ref: '/schemas/types.yaml#/definitions/phandle'
303    description: |
304      Specifies the syscon node controlling the cpu core power domains.
305
306      Optional for systems that have an "enable-method"
307      property value of "rockchip,rk3066-smp"
308      While optional, it is the preferred way to get access to
309      the cpu-core power-domains.
310
311  secondary-boot-reg:
312    $ref: '/schemas/types.yaml#/definitions/uint32'
313    description: |
314      Required for systems that have an "enable-method" property value of
315      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
316
317      This includes the following SoCs: |
318      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
319      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
320
321      The secondary-boot-reg property is a u32 value that specifies the
322      physical address of the register used to request the ROM holding pen
323      code release a secondary CPU. The value written to the register is
324      formed by encoding the target CPU id into the low bits of the
325      physical start address it should jump to.
326
327if:
328  # If the enable-method property contains one of those values
329  properties:
330    enable-method:
331      contains:
332        enum:
333          - brcm,bcm11351-cpu-method
334          - brcm,bcm23550
335          - brcm,bcm-nsp-smp
336  # and if enable-method is present
337  required:
338    - enable-method
339
340then:
341  required:
342    - secondary-boot-reg
343
344required:
345  - device_type
346  - reg
347  - compatible
348
349dependencies:
350  rockchip,pmu: [enable-method]
351
352additionalProperties: true
353
354examples:
355  - |
356    cpus {
357      #size-cells = <0>;
358      #address-cells = <1>;
359
360      cpu@0 {
361        device_type = "cpu";
362        compatible = "arm,cortex-a15";
363        reg = <0x0>;
364      };
365
366      cpu@1 {
367        device_type = "cpu";
368        compatible = "arm,cortex-a15";
369        reg = <0x1>;
370      };
371
372      cpu@100 {
373        device_type = "cpu";
374        compatible = "arm,cortex-a7";
375        reg = <0x100>;
376      };
377
378      cpu@101 {
379        device_type = "cpu";
380        compatible = "arm,cortex-a7";
381        reg = <0x101>;
382      };
383    };
384
385  - |
386    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
387    cpus {
388      #size-cells = <0>;
389      #address-cells = <1>;
390
391      cpu@0 {
392        device_type = "cpu";
393        compatible = "arm,cortex-a8";
394        reg = <0x0>;
395      };
396    };
397
398  - |
399    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
400    cpus {
401      #size-cells = <0>;
402      #address-cells = <1>;
403
404      cpu@0 {
405        device_type = "cpu";
406        compatible = "arm,arm926ej-s";
407        reg = <0x0>;
408      };
409    };
410
411  - |
412    //  Example 4 (ARM Cortex-A57 64-bit system):
413    cpus {
414      #size-cells = <0>;
415      #address-cells = <2>;
416
417      cpu@0 {
418        device_type = "cpu";
419        compatible = "arm,cortex-a57";
420        reg = <0x0 0x0>;
421        enable-method = "spin-table";
422        cpu-release-addr = <0 0x20000000>;
423      };
424
425      cpu@1 {
426        device_type = "cpu";
427        compatible = "arm,cortex-a57";
428        reg = <0x0 0x1>;
429        enable-method = "spin-table";
430        cpu-release-addr = <0 0x20000000>;
431      };
432
433      cpu@100 {
434        device_type = "cpu";
435        compatible = "arm,cortex-a57";
436        reg = <0x0 0x100>;
437        enable-method = "spin-table";
438        cpu-release-addr = <0 0x20000000>;
439      };
440
441      cpu@101 {
442        device_type = "cpu";
443        compatible = "arm,cortex-a57";
444        reg = <0x0 0x101>;
445        enable-method = "spin-table";
446        cpu-release-addr = <0 0x20000000>;
447      };
448
449      cpu@10000 {
450        device_type = "cpu";
451        compatible = "arm,cortex-a57";
452        reg = <0x0 0x10000>;
453        enable-method = "spin-table";
454        cpu-release-addr = <0 0x20000000>;
455      };
456
457      cpu@10001 {
458        device_type = "cpu";
459        compatible = "arm,cortex-a57";
460        reg = <0x0 0x10001>;
461        enable-method = "spin-table";
462        cpu-release-addr = <0 0x20000000>;
463      };
464
465      cpu@10100 {
466        device_type = "cpu";
467        compatible = "arm,cortex-a57";
468        reg = <0x0 0x10100>;
469        enable-method = "spin-table";
470        cpu-release-addr = <0 0x20000000>;
471      };
472
473      cpu@10101 {
474        device_type = "cpu";
475        compatible = "arm,cortex-a57";
476        reg = <0x0 0x10101>;
477        enable-method = "spin-table";
478        cpu-release-addr = <0 0x20000000>;
479      };
480
481      cpu@100000000 {
482        device_type = "cpu";
483        compatible = "arm,cortex-a57";
484        reg = <0x1 0x0>;
485        enable-method = "spin-table";
486        cpu-release-addr = <0 0x20000000>;
487      };
488
489      cpu@100000001 {
490        device_type = "cpu";
491        compatible = "arm,cortex-a57";
492        reg = <0x1 0x1>;
493        enable-method = "spin-table";
494        cpu-release-addr = <0 0x20000000>;
495      };
496
497      cpu@100000100 {
498        device_type = "cpu";
499        compatible = "arm,cortex-a57";
500        reg = <0x1 0x100>;
501        enable-method = "spin-table";
502        cpu-release-addr = <0 0x20000000>;
503      };
504
505      cpu@100000101 {
506        device_type = "cpu";
507        compatible = "arm,cortex-a57";
508        reg = <0x1 0x101>;
509        enable-method = "spin-table";
510        cpu-release-addr = <0 0x20000000>;
511      };
512
513      cpu@100010000 {
514        device_type = "cpu";
515        compatible = "arm,cortex-a57";
516        reg = <0x1 0x10000>;
517        enable-method = "spin-table";
518        cpu-release-addr = <0 0x20000000>;
519      };
520
521      cpu@100010001 {
522        device_type = "cpu";
523        compatible = "arm,cortex-a57";
524        reg = <0x1 0x10001>;
525        enable-method = "spin-table";
526        cpu-release-addr = <0 0x20000000>;
527      };
528
529      cpu@100010100 {
530        device_type = "cpu";
531        compatible = "arm,cortex-a57";
532        reg = <0x1 0x10100>;
533        enable-method = "spin-table";
534        cpu-release-addr = <0 0x20000000>;
535      };
536
537      cpu@100010101 {
538        device_type = "cpu";
539        compatible = "arm,cortex-a57";
540        reg = <0x1 0x10101>;
541        enable-method = "spin-table";
542        cpu-release-addr = <0 0x20000000>;
543      };
544    };
545...
546