1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality 4 * 5 * Copyright (C) 2014-2015 Intel Corp 6 * Author: Jeeja KP <jeeja.kp@intel.com> 7 * 8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 9 * 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 */ 12 13 #include <linux/pci.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/delay.h> 16 #include <sound/pcm_params.h> 17 #include <sound/soc.h> 18 #include "skl.h" 19 #include "skl-topology.h" 20 #include "skl-sst-dsp.h" 21 #include "skl-sst-ipc.h" 22 23 #define HDA_MONO 1 24 #define HDA_STEREO 2 25 #define HDA_QUAD 4 26 #define HDA_MAX 8 27 28 static const struct snd_pcm_hardware azx_pcm_hw = { 29 .info = (SNDRV_PCM_INFO_MMAP | 30 SNDRV_PCM_INFO_INTERLEAVED | 31 SNDRV_PCM_INFO_BLOCK_TRANSFER | 32 SNDRV_PCM_INFO_MMAP_VALID | 33 SNDRV_PCM_INFO_PAUSE | 34 SNDRV_PCM_INFO_RESUME | 35 SNDRV_PCM_INFO_SYNC_START | 36 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */ 37 SNDRV_PCM_INFO_HAS_LINK_ATIME | 38 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 39 .formats = SNDRV_PCM_FMTBIT_S16_LE | 40 SNDRV_PCM_FMTBIT_S32_LE | 41 SNDRV_PCM_FMTBIT_S24_LE, 42 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | 43 SNDRV_PCM_RATE_8000, 44 .rate_min = 8000, 45 .rate_max = 48000, 46 .channels_min = 1, 47 .channels_max = 8, 48 .buffer_bytes_max = AZX_MAX_BUF_SIZE, 49 .period_bytes_min = 128, 50 .period_bytes_max = AZX_MAX_BUF_SIZE / 2, 51 .periods_min = 2, 52 .periods_max = AZX_MAX_FRAG, 53 .fifo_size = 0, 54 }; 55 56 static inline 57 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream) 58 { 59 return substream->runtime->private_data; 60 } 61 62 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream) 63 { 64 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 65 struct hdac_stream *hstream = hdac_stream(stream); 66 struct hdac_bus *bus = hstream->bus; 67 return bus; 68 } 69 70 static int skl_substream_alloc_pages(struct hdac_bus *bus, 71 struct snd_pcm_substream *substream, 72 size_t size) 73 { 74 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 75 76 hdac_stream(stream)->bufsize = 0; 77 hdac_stream(stream)->period_bytes = 0; 78 hdac_stream(stream)->format_val = 0; 79 80 return 0; 81 } 82 83 static void skl_set_pcm_constrains(struct hdac_bus *bus, 84 struct snd_pcm_runtime *runtime) 85 { 86 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 87 88 /* avoid wrap-around with wall-clock */ 89 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, 90 20, 178000000); 91 } 92 93 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus) 94 { 95 if (bus->ppcap) 96 return HDAC_EXT_STREAM_TYPE_HOST; 97 else 98 return HDAC_EXT_STREAM_TYPE_COUPLED; 99 } 100 101 /* 102 * check if the stream opened is marked as ignore_suspend by machine, if so 103 * then enable suspend_active refcount 104 * 105 * The count supend_active does not need lock as it is used in open/close 106 * and suspend context 107 */ 108 static void skl_set_suspend_active(struct snd_pcm_substream *substream, 109 struct snd_soc_dai *dai, bool enable) 110 { 111 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 112 struct snd_soc_dapm_widget *w; 113 struct skl_dev *skl = bus_to_skl(bus); 114 115 w = snd_soc_dai_get_widget(dai, substream->stream); 116 117 if (w->ignore_suspend && enable) 118 skl->supend_active++; 119 else if (w->ignore_suspend && !enable) 120 skl->supend_active--; 121 } 122 123 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params) 124 { 125 struct hdac_bus *bus = dev_get_drvdata(dev); 126 struct skl_dev *skl = bus_to_skl(bus); 127 unsigned int format_val; 128 struct hdac_stream *hstream; 129 struct hdac_ext_stream *stream; 130 int err; 131 132 hstream = snd_hdac_get_stream(bus, params->stream, 133 params->host_dma_id + 1); 134 if (!hstream) 135 return -EINVAL; 136 137 stream = stream_to_hdac_ext_stream(hstream); 138 snd_hdac_ext_stream_decouple(bus, stream, true); 139 140 format_val = snd_hdac_calc_stream_format(params->s_freq, 141 params->ch, params->format, params->host_bps, 0); 142 143 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n", 144 format_val, params->s_freq, params->ch, params->format); 145 146 snd_hdac_stream_reset(hdac_stream(stream)); 147 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val); 148 if (err < 0) 149 return err; 150 151 /* 152 * The recommended SDxFMT programming sequence for BXT 153 * platforms is to couple the stream before writing the format 154 */ 155 if (IS_BXT(skl->pci)) { 156 snd_hdac_ext_stream_decouple(bus, stream, false); 157 err = snd_hdac_stream_setup(hdac_stream(stream)); 158 snd_hdac_ext_stream_decouple(bus, stream, true); 159 } else { 160 err = snd_hdac_stream_setup(hdac_stream(stream)); 161 } 162 163 if (err < 0) 164 return err; 165 166 hdac_stream(stream)->prepared = 1; 167 168 return 0; 169 } 170 171 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params) 172 { 173 struct hdac_bus *bus = dev_get_drvdata(dev); 174 unsigned int format_val; 175 struct hdac_stream *hstream; 176 struct hdac_ext_stream *stream; 177 struct hdac_ext_link *link; 178 unsigned char stream_tag; 179 180 hstream = snd_hdac_get_stream(bus, params->stream, 181 params->link_dma_id + 1); 182 if (!hstream) 183 return -EINVAL; 184 185 stream = stream_to_hdac_ext_stream(hstream); 186 snd_hdac_ext_stream_decouple(bus, stream, true); 187 format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch, 188 params->format, params->link_bps, 0); 189 190 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n", 191 format_val, params->s_freq, params->ch, params->format); 192 193 snd_hdac_ext_link_stream_reset(stream); 194 195 snd_hdac_ext_link_stream_setup(stream, format_val); 196 197 stream_tag = hstream->stream_tag; 198 if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) { 199 list_for_each_entry(link, &bus->hlink_list, list) { 200 if (link->index == params->link_index) 201 snd_hdac_ext_link_set_stream_id(link, 202 stream_tag); 203 } 204 } 205 206 stream->link_prepared = 1; 207 208 return 0; 209 } 210 211 static int skl_pcm_open(struct snd_pcm_substream *substream, 212 struct snd_soc_dai *dai) 213 { 214 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 215 struct hdac_ext_stream *stream; 216 struct snd_pcm_runtime *runtime = substream->runtime; 217 struct skl_dma_params *dma_params; 218 struct skl_dev *skl = get_skl_ctx(dai->dev); 219 struct skl_module_cfg *mconfig; 220 221 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 222 223 stream = snd_hdac_ext_stream_assign(bus, substream, 224 skl_get_host_stream_type(bus)); 225 if (stream == NULL) 226 return -EBUSY; 227 228 skl_set_pcm_constrains(bus, runtime); 229 230 /* 231 * disable WALLCLOCK timestamps for capture streams 232 * until we figure out how to handle digital inputs 233 */ 234 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 235 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */ 236 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME; 237 } 238 239 runtime->private_data = stream; 240 241 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL); 242 if (!dma_params) 243 return -ENOMEM; 244 245 dma_params->stream_tag = hdac_stream(stream)->stream_tag; 246 snd_soc_dai_set_dma_data(dai, substream, dma_params); 247 248 dev_dbg(dai->dev, "stream tag set in dma params=%d\n", 249 dma_params->stream_tag); 250 skl_set_suspend_active(substream, dai, true); 251 snd_pcm_set_sync(substream); 252 253 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 254 if (!mconfig) 255 return -EINVAL; 256 257 skl_tplg_d0i3_get(skl, mconfig->d0i3_caps); 258 259 return 0; 260 } 261 262 static int skl_pcm_prepare(struct snd_pcm_substream *substream, 263 struct snd_soc_dai *dai) 264 { 265 struct skl_dev *skl = get_skl_ctx(dai->dev); 266 struct skl_module_cfg *mconfig; 267 int ret; 268 269 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 270 271 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 272 273 /* 274 * In case of XRUN recovery or in the case when the application 275 * calls prepare another time, reset the FW pipe to clean state 276 */ 277 if (mconfig && 278 (substream->runtime->state == SNDRV_PCM_STATE_XRUN || 279 mconfig->pipe->state == SKL_PIPE_CREATED || 280 mconfig->pipe->state == SKL_PIPE_PAUSED)) { 281 282 ret = skl_reset_pipe(skl, mconfig->pipe); 283 284 if (ret < 0) 285 return ret; 286 287 ret = skl_pcm_host_dma_prepare(dai->dev, 288 mconfig->pipe->p_params); 289 if (ret < 0) 290 return ret; 291 } 292 293 return 0; 294 } 295 296 static int skl_pcm_hw_params(struct snd_pcm_substream *substream, 297 struct snd_pcm_hw_params *params, 298 struct snd_soc_dai *dai) 299 { 300 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 301 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 302 struct snd_pcm_runtime *runtime = substream->runtime; 303 struct skl_pipe_params p_params = {0}; 304 struct skl_module_cfg *m_cfg; 305 int ret, dma_id; 306 307 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 308 ret = skl_substream_alloc_pages(bus, substream, 309 params_buffer_bytes(params)); 310 if (ret < 0) 311 return ret; 312 313 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n", 314 runtime->rate, runtime->channels, runtime->format); 315 316 dma_id = hdac_stream(stream)->stream_tag - 1; 317 dev_dbg(dai->dev, "dma_id=%d\n", dma_id); 318 319 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 320 p_params.s_cont = snd_pcm_format_physical_width(params_format(params)); 321 p_params.ch = params_channels(params); 322 p_params.s_freq = params_rate(params); 323 p_params.host_dma_id = dma_id; 324 p_params.stream = substream->stream; 325 p_params.format = params_format(params); 326 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 327 p_params.host_bps = dai->driver->playback.sig_bits; 328 else 329 p_params.host_bps = dai->driver->capture.sig_bits; 330 331 332 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream); 333 if (m_cfg) 334 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params); 335 336 return 0; 337 } 338 339 static void skl_pcm_close(struct snd_pcm_substream *substream, 340 struct snd_soc_dai *dai) 341 { 342 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 343 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 344 struct skl_dma_params *dma_params = NULL; 345 struct skl_dev *skl = bus_to_skl(bus); 346 struct skl_module_cfg *mconfig; 347 348 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 349 350 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus)); 351 352 dma_params = snd_soc_dai_get_dma_data(dai, substream); 353 /* 354 * now we should set this to NULL as we are freeing by the 355 * dma_params 356 */ 357 snd_soc_dai_set_dma_data(dai, substream, NULL); 358 skl_set_suspend_active(substream, dai, false); 359 360 /* 361 * check if close is for "Reference Pin" and set back the 362 * CGCTL.MISCBDCGE if disabled by driver 363 */ 364 if (!strncmp(dai->name, "Reference Pin", 13) && 365 skl->miscbdcg_disabled) { 366 skl->enable_miscbdcge(dai->dev, true); 367 skl->miscbdcg_disabled = false; 368 } 369 370 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 371 if (mconfig) 372 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps); 373 374 kfree(dma_params); 375 } 376 377 static int skl_pcm_hw_free(struct snd_pcm_substream *substream, 378 struct snd_soc_dai *dai) 379 { 380 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 381 struct skl_dev *skl = get_skl_ctx(dai->dev); 382 struct skl_module_cfg *mconfig; 383 int ret; 384 385 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 386 387 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 388 389 if (mconfig) { 390 ret = skl_reset_pipe(skl, mconfig->pipe); 391 if (ret < 0) 392 dev_err(dai->dev, "%s:Reset failed ret =%d", 393 __func__, ret); 394 } 395 396 snd_hdac_stream_cleanup(hdac_stream(stream)); 397 hdac_stream(stream)->prepared = 0; 398 399 return 0; 400 } 401 402 static int skl_be_hw_params(struct snd_pcm_substream *substream, 403 struct snd_pcm_hw_params *params, 404 struct snd_soc_dai *dai) 405 { 406 struct skl_pipe_params p_params = {0}; 407 408 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 409 p_params.s_cont = snd_pcm_format_physical_width(params_format(params)); 410 p_params.ch = params_channels(params); 411 p_params.s_freq = params_rate(params); 412 p_params.stream = substream->stream; 413 414 return skl_tplg_be_update_params(dai, &p_params); 415 } 416 417 static int skl_decoupled_trigger(struct snd_pcm_substream *substream, 418 int cmd) 419 { 420 struct hdac_bus *bus = get_bus_ctx(substream); 421 struct hdac_ext_stream *stream; 422 int start; 423 unsigned long cookie; 424 struct hdac_stream *hstr; 425 426 stream = get_hdac_ext_stream(substream); 427 hstr = hdac_stream(stream); 428 429 if (!hstr->prepared) 430 return -EPIPE; 431 432 switch (cmd) { 433 case SNDRV_PCM_TRIGGER_START: 434 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 435 case SNDRV_PCM_TRIGGER_RESUME: 436 start = 1; 437 break; 438 439 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 440 case SNDRV_PCM_TRIGGER_SUSPEND: 441 case SNDRV_PCM_TRIGGER_STOP: 442 start = 0; 443 break; 444 445 default: 446 return -EINVAL; 447 } 448 449 spin_lock_irqsave(&bus->reg_lock, cookie); 450 451 if (start) { 452 snd_hdac_stream_start(hdac_stream(stream), true); 453 snd_hdac_stream_timecounter_init(hstr, 0); 454 } else { 455 snd_hdac_stream_stop(hdac_stream(stream)); 456 } 457 458 spin_unlock_irqrestore(&bus->reg_lock, cookie); 459 460 return 0; 461 } 462 463 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd, 464 struct snd_soc_dai *dai) 465 { 466 struct skl_dev *skl = get_skl_ctx(dai->dev); 467 struct skl_module_cfg *mconfig; 468 struct hdac_bus *bus = get_bus_ctx(substream); 469 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 470 struct snd_soc_dapm_widget *w; 471 int ret; 472 473 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 474 if (!mconfig) 475 return -EIO; 476 477 w = snd_soc_dai_get_widget(dai, substream->stream); 478 479 switch (cmd) { 480 case SNDRV_PCM_TRIGGER_RESUME: 481 if (!w->ignore_suspend) { 482 /* 483 * enable DMA Resume enable bit for the stream, set the 484 * dpib & lpib position to resume before starting the 485 * DMA 486 */ 487 snd_hdac_ext_stream_drsm_enable(bus, true, 488 hdac_stream(stream)->index); 489 snd_hdac_ext_stream_set_dpibr(bus, stream, 490 stream->lpib); 491 snd_hdac_ext_stream_set_lpib(stream, stream->lpib); 492 } 493 fallthrough; 494 495 case SNDRV_PCM_TRIGGER_START: 496 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 497 /* 498 * Start HOST DMA and Start FE Pipe.This is to make sure that 499 * there are no underrun/overrun in the case when the FE 500 * pipeline is started but there is a delay in starting the 501 * DMA channel on the host. 502 */ 503 ret = skl_decoupled_trigger(substream, cmd); 504 if (ret < 0) 505 return ret; 506 return skl_run_pipe(skl, mconfig->pipe); 507 508 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 509 case SNDRV_PCM_TRIGGER_SUSPEND: 510 case SNDRV_PCM_TRIGGER_STOP: 511 /* 512 * Stop FE Pipe first and stop DMA. This is to make sure that 513 * there are no underrun/overrun in the case if there is a delay 514 * between the two operations. 515 */ 516 ret = skl_stop_pipe(skl, mconfig->pipe); 517 if (ret < 0) 518 return ret; 519 520 ret = skl_decoupled_trigger(substream, cmd); 521 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) { 522 /* save the dpib and lpib positions */ 523 stream->dpib = readl(bus->remap_addr + 524 AZX_REG_VS_SDXDPIB_XBASE + 525 (AZX_REG_VS_SDXDPIB_XINTERVAL * 526 hdac_stream(stream)->index)); 527 528 stream->lpib = snd_hdac_stream_get_pos_lpib( 529 hdac_stream(stream)); 530 snd_hdac_ext_stream_decouple(bus, stream, false); 531 } 532 break; 533 534 default: 535 return -EINVAL; 536 } 537 538 return 0; 539 } 540 541 542 static int skl_link_hw_params(struct snd_pcm_substream *substream, 543 struct snd_pcm_hw_params *params, 544 struct snd_soc_dai *dai) 545 { 546 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 547 struct hdac_ext_stream *link_dev; 548 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 549 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0); 550 struct skl_pipe_params p_params = {0}; 551 struct hdac_ext_link *link; 552 int stream_tag; 553 554 link_dev = snd_hdac_ext_stream_assign(bus, substream, 555 HDAC_EXT_STREAM_TYPE_LINK); 556 if (!link_dev) 557 return -EBUSY; 558 559 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev); 560 561 link = snd_hdac_ext_bus_get_link(bus, codec_dai->component->name); 562 if (!link) 563 return -EINVAL; 564 565 stream_tag = hdac_stream(link_dev)->stream_tag; 566 567 /* set the hdac_stream in the codec dai */ 568 snd_soc_dai_set_stream(codec_dai, hdac_stream(link_dev), substream->stream); 569 570 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 571 p_params.s_cont = snd_pcm_format_physical_width(params_format(params)); 572 p_params.ch = params_channels(params); 573 p_params.s_freq = params_rate(params); 574 p_params.stream = substream->stream; 575 p_params.link_dma_id = stream_tag - 1; 576 p_params.link_index = link->index; 577 p_params.format = params_format(params); 578 579 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 580 p_params.link_bps = codec_dai->driver->playback.sig_bits; 581 else 582 p_params.link_bps = codec_dai->driver->capture.sig_bits; 583 584 return skl_tplg_be_update_params(dai, &p_params); 585 } 586 587 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream, 588 struct snd_soc_dai *dai) 589 { 590 struct skl_dev *skl = get_skl_ctx(dai->dev); 591 struct skl_module_cfg *mconfig = NULL; 592 593 /* In case of XRUN recovery, reset the FW pipe to clean state */ 594 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream); 595 if (mconfig && !mconfig->pipe->passthru && 596 (substream->runtime->state == SNDRV_PCM_STATE_XRUN)) 597 skl_reset_pipe(skl, mconfig->pipe); 598 599 return 0; 600 } 601 602 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream, 603 int cmd, struct snd_soc_dai *dai) 604 { 605 struct hdac_ext_stream *link_dev = 606 snd_soc_dai_get_dma_data(dai, substream); 607 struct hdac_bus *bus = get_bus_ctx(substream); 608 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 609 610 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd); 611 switch (cmd) { 612 case SNDRV_PCM_TRIGGER_RESUME: 613 case SNDRV_PCM_TRIGGER_START: 614 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 615 snd_hdac_ext_link_stream_start(link_dev); 616 break; 617 618 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 619 case SNDRV_PCM_TRIGGER_SUSPEND: 620 case SNDRV_PCM_TRIGGER_STOP: 621 snd_hdac_ext_link_stream_clear(link_dev); 622 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND) 623 snd_hdac_ext_stream_decouple(bus, stream, false); 624 break; 625 626 default: 627 return -EINVAL; 628 } 629 return 0; 630 } 631 632 static int skl_link_hw_free(struct snd_pcm_substream *substream, 633 struct snd_soc_dai *dai) 634 { 635 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 636 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 637 struct hdac_ext_stream *link_dev = 638 snd_soc_dai_get_dma_data(dai, substream); 639 struct hdac_ext_link *link; 640 unsigned char stream_tag; 641 642 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 643 644 link_dev->link_prepared = 0; 645 646 link = snd_hdac_ext_bus_get_link(bus, asoc_rtd_to_codec(rtd, 0)->component->name); 647 if (!link) 648 return -EINVAL; 649 650 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 651 stream_tag = hdac_stream(link_dev)->stream_tag; 652 snd_hdac_ext_link_clear_stream_id(link, stream_tag); 653 } 654 655 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK); 656 return 0; 657 } 658 659 static const struct snd_soc_dai_ops skl_pcm_dai_ops = { 660 .startup = skl_pcm_open, 661 .shutdown = skl_pcm_close, 662 .prepare = skl_pcm_prepare, 663 .hw_params = skl_pcm_hw_params, 664 .hw_free = skl_pcm_hw_free, 665 .trigger = skl_pcm_trigger, 666 }; 667 668 static const struct snd_soc_dai_ops skl_dmic_dai_ops = { 669 .hw_params = skl_be_hw_params, 670 }; 671 672 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = { 673 .hw_params = skl_be_hw_params, 674 }; 675 676 static const struct snd_soc_dai_ops skl_link_dai_ops = { 677 .prepare = skl_link_pcm_prepare, 678 .hw_params = skl_link_hw_params, 679 .hw_free = skl_link_hw_free, 680 .trigger = skl_link_pcm_trigger, 681 }; 682 683 static struct snd_soc_dai_driver skl_fe_dai[] = { 684 { 685 .name = "System Pin", 686 .ops = &skl_pcm_dai_ops, 687 .playback = { 688 .stream_name = "System Playback", 689 .channels_min = HDA_MONO, 690 .channels_max = HDA_STEREO, 691 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000, 692 .formats = SNDRV_PCM_FMTBIT_S16_LE | 693 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 694 .sig_bits = 32, 695 }, 696 .capture = { 697 .stream_name = "System Capture", 698 .channels_min = HDA_MONO, 699 .channels_max = HDA_STEREO, 700 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 701 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 702 .sig_bits = 32, 703 }, 704 }, 705 { 706 .name = "System Pin2", 707 .ops = &skl_pcm_dai_ops, 708 .playback = { 709 .stream_name = "Headset Playback", 710 .channels_min = HDA_MONO, 711 .channels_max = HDA_STEREO, 712 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | 713 SNDRV_PCM_RATE_8000, 714 .formats = SNDRV_PCM_FMTBIT_S16_LE | 715 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 716 }, 717 }, 718 { 719 .name = "Echoref Pin", 720 .ops = &skl_pcm_dai_ops, 721 .capture = { 722 .stream_name = "Echoreference Capture", 723 .channels_min = HDA_STEREO, 724 .channels_max = HDA_STEREO, 725 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | 726 SNDRV_PCM_RATE_8000, 727 .formats = SNDRV_PCM_FMTBIT_S16_LE | 728 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 729 }, 730 }, 731 { 732 .name = "Reference Pin", 733 .ops = &skl_pcm_dai_ops, 734 .capture = { 735 .stream_name = "Reference Capture", 736 .channels_min = HDA_MONO, 737 .channels_max = HDA_QUAD, 738 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 739 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 740 .sig_bits = 32, 741 }, 742 }, 743 { 744 .name = "Deepbuffer Pin", 745 .ops = &skl_pcm_dai_ops, 746 .playback = { 747 .stream_name = "Deepbuffer Playback", 748 .channels_min = HDA_STEREO, 749 .channels_max = HDA_STEREO, 750 .rates = SNDRV_PCM_RATE_48000, 751 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 752 .sig_bits = 32, 753 }, 754 }, 755 { 756 .name = "LowLatency Pin", 757 .ops = &skl_pcm_dai_ops, 758 .playback = { 759 .stream_name = "Low Latency Playback", 760 .channels_min = HDA_STEREO, 761 .channels_max = HDA_STEREO, 762 .rates = SNDRV_PCM_RATE_48000, 763 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 764 .sig_bits = 32, 765 }, 766 }, 767 { 768 .name = "DMIC Pin", 769 .ops = &skl_pcm_dai_ops, 770 .capture = { 771 .stream_name = "DMIC Capture", 772 .channels_min = HDA_MONO, 773 .channels_max = HDA_QUAD, 774 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 775 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 776 .sig_bits = 32, 777 }, 778 }, 779 { 780 .name = "HDMI1 Pin", 781 .ops = &skl_pcm_dai_ops, 782 .playback = { 783 .stream_name = "HDMI1 Playback", 784 .channels_min = HDA_STEREO, 785 .channels_max = 8, 786 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 787 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 788 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 789 SNDRV_PCM_RATE_192000, 790 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 791 SNDRV_PCM_FMTBIT_S32_LE, 792 .sig_bits = 32, 793 }, 794 }, 795 { 796 .name = "HDMI2 Pin", 797 .ops = &skl_pcm_dai_ops, 798 .playback = { 799 .stream_name = "HDMI2 Playback", 800 .channels_min = HDA_STEREO, 801 .channels_max = 8, 802 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 803 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 804 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 805 SNDRV_PCM_RATE_192000, 806 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 807 SNDRV_PCM_FMTBIT_S32_LE, 808 .sig_bits = 32, 809 }, 810 }, 811 { 812 .name = "HDMI3 Pin", 813 .ops = &skl_pcm_dai_ops, 814 .playback = { 815 .stream_name = "HDMI3 Playback", 816 .channels_min = HDA_STEREO, 817 .channels_max = 8, 818 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 819 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 820 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 821 SNDRV_PCM_RATE_192000, 822 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 823 SNDRV_PCM_FMTBIT_S32_LE, 824 .sig_bits = 32, 825 }, 826 }, 827 }; 828 829 /* BE CPU Dais */ 830 static struct snd_soc_dai_driver skl_platform_dai[] = { 831 { 832 .name = "SSP0 Pin", 833 .ops = &skl_be_ssp_dai_ops, 834 .playback = { 835 .stream_name = "ssp0 Tx", 836 .channels_min = HDA_STEREO, 837 .channels_max = HDA_STEREO, 838 .rates = SNDRV_PCM_RATE_48000, 839 .formats = SNDRV_PCM_FMTBIT_S16_LE, 840 }, 841 .capture = { 842 .stream_name = "ssp0 Rx", 843 .channels_min = HDA_STEREO, 844 .channels_max = HDA_STEREO, 845 .rates = SNDRV_PCM_RATE_48000, 846 .formats = SNDRV_PCM_FMTBIT_S16_LE, 847 }, 848 }, 849 { 850 .name = "SSP1 Pin", 851 .ops = &skl_be_ssp_dai_ops, 852 .playback = { 853 .stream_name = "ssp1 Tx", 854 .channels_min = HDA_STEREO, 855 .channels_max = HDA_STEREO, 856 .rates = SNDRV_PCM_RATE_48000, 857 .formats = SNDRV_PCM_FMTBIT_S16_LE, 858 }, 859 .capture = { 860 .stream_name = "ssp1 Rx", 861 .channels_min = HDA_STEREO, 862 .channels_max = HDA_STEREO, 863 .rates = SNDRV_PCM_RATE_48000, 864 .formats = SNDRV_PCM_FMTBIT_S16_LE, 865 }, 866 }, 867 { 868 .name = "SSP2 Pin", 869 .ops = &skl_be_ssp_dai_ops, 870 .playback = { 871 .stream_name = "ssp2 Tx", 872 .channels_min = HDA_STEREO, 873 .channels_max = HDA_STEREO, 874 .rates = SNDRV_PCM_RATE_48000, 875 .formats = SNDRV_PCM_FMTBIT_S16_LE, 876 }, 877 .capture = { 878 .stream_name = "ssp2 Rx", 879 .channels_min = HDA_STEREO, 880 .channels_max = HDA_STEREO, 881 .rates = SNDRV_PCM_RATE_48000, 882 .formats = SNDRV_PCM_FMTBIT_S16_LE, 883 }, 884 }, 885 { 886 .name = "SSP3 Pin", 887 .ops = &skl_be_ssp_dai_ops, 888 .playback = { 889 .stream_name = "ssp3 Tx", 890 .channels_min = HDA_STEREO, 891 .channels_max = HDA_STEREO, 892 .rates = SNDRV_PCM_RATE_48000, 893 .formats = SNDRV_PCM_FMTBIT_S16_LE, 894 }, 895 .capture = { 896 .stream_name = "ssp3 Rx", 897 .channels_min = HDA_STEREO, 898 .channels_max = HDA_STEREO, 899 .rates = SNDRV_PCM_RATE_48000, 900 .formats = SNDRV_PCM_FMTBIT_S16_LE, 901 }, 902 }, 903 { 904 .name = "SSP4 Pin", 905 .ops = &skl_be_ssp_dai_ops, 906 .playback = { 907 .stream_name = "ssp4 Tx", 908 .channels_min = HDA_STEREO, 909 .channels_max = HDA_STEREO, 910 .rates = SNDRV_PCM_RATE_48000, 911 .formats = SNDRV_PCM_FMTBIT_S16_LE, 912 }, 913 .capture = { 914 .stream_name = "ssp4 Rx", 915 .channels_min = HDA_STEREO, 916 .channels_max = HDA_STEREO, 917 .rates = SNDRV_PCM_RATE_48000, 918 .formats = SNDRV_PCM_FMTBIT_S16_LE, 919 }, 920 }, 921 { 922 .name = "SSP5 Pin", 923 .ops = &skl_be_ssp_dai_ops, 924 .playback = { 925 .stream_name = "ssp5 Tx", 926 .channels_min = HDA_STEREO, 927 .channels_max = HDA_STEREO, 928 .rates = SNDRV_PCM_RATE_48000, 929 .formats = SNDRV_PCM_FMTBIT_S16_LE, 930 }, 931 .capture = { 932 .stream_name = "ssp5 Rx", 933 .channels_min = HDA_STEREO, 934 .channels_max = HDA_STEREO, 935 .rates = SNDRV_PCM_RATE_48000, 936 .formats = SNDRV_PCM_FMTBIT_S16_LE, 937 }, 938 }, 939 { 940 .name = "iDisp1 Pin", 941 .ops = &skl_link_dai_ops, 942 .playback = { 943 .stream_name = "iDisp1 Tx", 944 .channels_min = HDA_STEREO, 945 .channels_max = 8, 946 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000, 947 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 948 SNDRV_PCM_FMTBIT_S24_LE, 949 }, 950 }, 951 { 952 .name = "iDisp2 Pin", 953 .ops = &skl_link_dai_ops, 954 .playback = { 955 .stream_name = "iDisp2 Tx", 956 .channels_min = HDA_STEREO, 957 .channels_max = 8, 958 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000| 959 SNDRV_PCM_RATE_48000, 960 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 961 SNDRV_PCM_FMTBIT_S24_LE, 962 }, 963 }, 964 { 965 .name = "iDisp3 Pin", 966 .ops = &skl_link_dai_ops, 967 .playback = { 968 .stream_name = "iDisp3 Tx", 969 .channels_min = HDA_STEREO, 970 .channels_max = 8, 971 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000| 972 SNDRV_PCM_RATE_48000, 973 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 974 SNDRV_PCM_FMTBIT_S24_LE, 975 }, 976 }, 977 { 978 .name = "DMIC01 Pin", 979 .ops = &skl_dmic_dai_ops, 980 .capture = { 981 .stream_name = "DMIC01 Rx", 982 .channels_min = HDA_MONO, 983 .channels_max = HDA_QUAD, 984 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 985 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 986 }, 987 }, 988 { 989 .name = "DMIC16k Pin", 990 .ops = &skl_dmic_dai_ops, 991 .capture = { 992 .stream_name = "DMIC16k Rx", 993 .channels_min = HDA_MONO, 994 .channels_max = HDA_QUAD, 995 .rates = SNDRV_PCM_RATE_16000, 996 .formats = SNDRV_PCM_FMTBIT_S16_LE, 997 }, 998 }, 999 { 1000 .name = "Analog CPU DAI", 1001 .ops = &skl_link_dai_ops, 1002 .playback = { 1003 .stream_name = "Analog CPU Playback", 1004 .channels_min = HDA_MONO, 1005 .channels_max = HDA_MAX, 1006 .rates = SNDRV_PCM_RATE_8000_192000, 1007 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1008 SNDRV_PCM_FMTBIT_S32_LE, 1009 }, 1010 .capture = { 1011 .stream_name = "Analog CPU Capture", 1012 .channels_min = HDA_MONO, 1013 .channels_max = HDA_MAX, 1014 .rates = SNDRV_PCM_RATE_8000_192000, 1015 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1016 SNDRV_PCM_FMTBIT_S32_LE, 1017 }, 1018 }, 1019 { 1020 .name = "Alt Analog CPU DAI", 1021 .ops = &skl_link_dai_ops, 1022 .playback = { 1023 .stream_name = "Alt Analog CPU Playback", 1024 .channels_min = HDA_MONO, 1025 .channels_max = HDA_MAX, 1026 .rates = SNDRV_PCM_RATE_8000_192000, 1027 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1028 SNDRV_PCM_FMTBIT_S32_LE, 1029 }, 1030 .capture = { 1031 .stream_name = "Alt Analog CPU Capture", 1032 .channels_min = HDA_MONO, 1033 .channels_max = HDA_MAX, 1034 .rates = SNDRV_PCM_RATE_8000_192000, 1035 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1036 SNDRV_PCM_FMTBIT_S32_LE, 1037 }, 1038 }, 1039 { 1040 .name = "Digital CPU DAI", 1041 .ops = &skl_link_dai_ops, 1042 .playback = { 1043 .stream_name = "Digital CPU Playback", 1044 .channels_min = HDA_MONO, 1045 .channels_max = HDA_MAX, 1046 .rates = SNDRV_PCM_RATE_8000_192000, 1047 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1048 SNDRV_PCM_FMTBIT_S32_LE, 1049 }, 1050 .capture = { 1051 .stream_name = "Digital CPU Capture", 1052 .channels_min = HDA_MONO, 1053 .channels_max = HDA_MAX, 1054 .rates = SNDRV_PCM_RATE_8000_192000, 1055 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1056 SNDRV_PCM_FMTBIT_S32_LE, 1057 }, 1058 }, 1059 }; 1060 1061 int skl_dai_load(struct snd_soc_component *cmp, int index, 1062 struct snd_soc_dai_driver *dai_drv, 1063 struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai) 1064 { 1065 dai_drv->ops = &skl_pcm_dai_ops; 1066 1067 return 0; 1068 } 1069 1070 static int skl_platform_soc_open(struct snd_soc_component *component, 1071 struct snd_pcm_substream *substream) 1072 { 1073 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 1074 struct snd_soc_dai_link *dai_link = rtd->dai_link; 1075 1076 dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "In %s:%s\n", __func__, 1077 dai_link->cpus->dai_name); 1078 1079 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw); 1080 1081 return 0; 1082 } 1083 1084 static int skl_coupled_trigger(struct snd_pcm_substream *substream, 1085 int cmd) 1086 { 1087 struct hdac_bus *bus = get_bus_ctx(substream); 1088 struct hdac_ext_stream *stream; 1089 struct snd_pcm_substream *s; 1090 bool start; 1091 int sbits = 0; 1092 unsigned long cookie; 1093 struct hdac_stream *hstr; 1094 1095 stream = get_hdac_ext_stream(substream); 1096 hstr = hdac_stream(stream); 1097 1098 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd); 1099 1100 if (!hstr->prepared) 1101 return -EPIPE; 1102 1103 switch (cmd) { 1104 case SNDRV_PCM_TRIGGER_START: 1105 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1106 case SNDRV_PCM_TRIGGER_RESUME: 1107 start = true; 1108 break; 1109 1110 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1111 case SNDRV_PCM_TRIGGER_SUSPEND: 1112 case SNDRV_PCM_TRIGGER_STOP: 1113 start = false; 1114 break; 1115 1116 default: 1117 return -EINVAL; 1118 } 1119 1120 snd_pcm_group_for_each_entry(s, substream) { 1121 if (s->pcm->card != substream->pcm->card) 1122 continue; 1123 stream = get_hdac_ext_stream(s); 1124 sbits |= 1 << hdac_stream(stream)->index; 1125 snd_pcm_trigger_done(s, substream); 1126 } 1127 1128 spin_lock_irqsave(&bus->reg_lock, cookie); 1129 1130 /* first, set SYNC bits of corresponding streams */ 1131 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC); 1132 1133 snd_pcm_group_for_each_entry(s, substream) { 1134 if (s->pcm->card != substream->pcm->card) 1135 continue; 1136 stream = get_hdac_ext_stream(s); 1137 if (start) 1138 snd_hdac_stream_start(hdac_stream(stream), true); 1139 else 1140 snd_hdac_stream_stop(hdac_stream(stream)); 1141 } 1142 spin_unlock_irqrestore(&bus->reg_lock, cookie); 1143 1144 snd_hdac_stream_sync(hstr, start, sbits); 1145 1146 spin_lock_irqsave(&bus->reg_lock, cookie); 1147 1148 /* reset SYNC bits */ 1149 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC); 1150 if (start) 1151 snd_hdac_stream_timecounter_init(hstr, sbits); 1152 spin_unlock_irqrestore(&bus->reg_lock, cookie); 1153 1154 return 0; 1155 } 1156 1157 static int skl_platform_soc_trigger(struct snd_soc_component *component, 1158 struct snd_pcm_substream *substream, 1159 int cmd) 1160 { 1161 struct hdac_bus *bus = get_bus_ctx(substream); 1162 1163 if (!bus->ppcap) 1164 return skl_coupled_trigger(substream, cmd); 1165 1166 return 0; 1167 } 1168 1169 static snd_pcm_uframes_t skl_platform_soc_pointer( 1170 struct snd_soc_component *component, 1171 struct snd_pcm_substream *substream) 1172 { 1173 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream); 1174 struct hdac_bus *bus = get_bus_ctx(substream); 1175 unsigned int pos; 1176 1177 /* 1178 * Use DPIB for Playback stream as the periodic DMA Position-in- 1179 * Buffer Writes may be scheduled at the same time or later than 1180 * the MSI and does not guarantee to reflect the Position of the 1181 * last buffer that was transferred. Whereas DPIB register in 1182 * HAD space reflects the actual data that is transferred. 1183 * Use the position buffer for capture, as DPIB write gets 1184 * completed earlier than the actual data written to the DDR. 1185 * 1186 * For capture stream following workaround is required to fix the 1187 * incorrect position reporting. 1188 * 1189 * 1. Wait for 20us before reading the DMA position in buffer once 1190 * the interrupt is generated for stream completion as update happens 1191 * on the HDA frame boundary i.e. 20.833uSec. 1192 * 2. Read DPIB register to flush the DMA position value. This dummy 1193 * read is required to flush DMA position value. 1194 * 3. Read the DMA Position-in-Buffer. This value now will be equal to 1195 * or greater than period boundary. 1196 */ 1197 1198 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1199 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE + 1200 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1201 hdac_stream(hstream)->index)); 1202 } else { 1203 udelay(20); 1204 readl(bus->remap_addr + 1205 AZX_REG_VS_SDXDPIB_XBASE + 1206 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1207 hdac_stream(hstream)->index)); 1208 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream)); 1209 } 1210 1211 if (pos >= hdac_stream(hstream)->bufsize) 1212 pos = 0; 1213 1214 return bytes_to_frames(substream->runtime, pos); 1215 } 1216 1217 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream, 1218 u64 nsec) 1219 { 1220 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 1221 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0); 1222 u64 codec_frames, codec_nsecs; 1223 1224 if (!codec_dai->driver->ops->delay) 1225 return nsec; 1226 1227 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai); 1228 codec_nsecs = div_u64(codec_frames * 1000000000LL, 1229 substream->runtime->rate); 1230 1231 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 1232 return nsec + codec_nsecs; 1233 1234 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; 1235 } 1236 1237 static int skl_platform_soc_get_time_info( 1238 struct snd_soc_component *component, 1239 struct snd_pcm_substream *substream, 1240 struct timespec64 *system_ts, struct timespec64 *audio_ts, 1241 struct snd_pcm_audio_tstamp_config *audio_tstamp_config, 1242 struct snd_pcm_audio_tstamp_report *audio_tstamp_report) 1243 { 1244 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream); 1245 struct hdac_stream *hstr = hdac_stream(sstream); 1246 u64 nsec; 1247 1248 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) && 1249 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) { 1250 1251 snd_pcm_gettime(substream->runtime, system_ts); 1252 1253 nsec = timecounter_read(&hstr->tc); 1254 if (audio_tstamp_config->report_delay) 1255 nsec = skl_adjust_codec_delay(substream, nsec); 1256 1257 *audio_ts = ns_to_timespec64(nsec); 1258 1259 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK; 1260 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */ 1261 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */ 1262 1263 } else { 1264 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT; 1265 } 1266 1267 return 0; 1268 } 1269 1270 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) 1271 1272 static int skl_platform_soc_new(struct snd_soc_component *component, 1273 struct snd_soc_pcm_runtime *rtd) 1274 { 1275 struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0); 1276 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 1277 struct snd_pcm *pcm = rtd->pcm; 1278 unsigned int size; 1279 struct skl_dev *skl = bus_to_skl(bus); 1280 1281 if (dai->driver->playback.channels_min || 1282 dai->driver->capture.channels_min) { 1283 /* buffer pre-allocation */ 1284 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; 1285 if (size > MAX_PREALLOC_SIZE) 1286 size = MAX_PREALLOC_SIZE; 1287 snd_pcm_set_managed_buffer_all(pcm, 1288 SNDRV_DMA_TYPE_DEV_SG, 1289 &skl->pci->dev, 1290 size, MAX_PREALLOC_SIZE); 1291 } 1292 1293 return 0; 1294 } 1295 1296 static int skl_get_module_info(struct skl_dev *skl, 1297 struct skl_module_cfg *mconfig) 1298 { 1299 struct skl_module_inst_id *pin_id; 1300 guid_t *uuid_mod, *uuid_tplg; 1301 struct skl_module *skl_module; 1302 struct uuid_module *module; 1303 int i, ret = -EIO; 1304 1305 uuid_mod = (guid_t *)mconfig->guid; 1306 1307 if (list_empty(&skl->uuid_list)) { 1308 dev_err(skl->dev, "Module list is empty\n"); 1309 return -EIO; 1310 } 1311 1312 for (i = 0; i < skl->nr_modules; i++) { 1313 skl_module = skl->modules[i]; 1314 uuid_tplg = &skl_module->uuid; 1315 if (guid_equal(uuid_mod, uuid_tplg)) { 1316 mconfig->module = skl_module; 1317 ret = 0; 1318 break; 1319 } 1320 } 1321 1322 if (skl->nr_modules && ret) 1323 return ret; 1324 1325 ret = -EIO; 1326 list_for_each_entry(module, &skl->uuid_list, list) { 1327 if (guid_equal(uuid_mod, &module->uuid)) { 1328 mconfig->id.module_id = module->id; 1329 mconfig->module->loadable = module->is_loadable; 1330 ret = 0; 1331 } 1332 1333 for (i = 0; i < MAX_IN_QUEUE; i++) { 1334 pin_id = &mconfig->m_in_pin[i].id; 1335 if (guid_equal(&pin_id->mod_uuid, &module->uuid)) 1336 pin_id->module_id = module->id; 1337 } 1338 1339 for (i = 0; i < MAX_OUT_QUEUE; i++) { 1340 pin_id = &mconfig->m_out_pin[i].id; 1341 if (guid_equal(&pin_id->mod_uuid, &module->uuid)) 1342 pin_id->module_id = module->id; 1343 } 1344 } 1345 1346 return ret; 1347 } 1348 1349 static int skl_populate_modules(struct skl_dev *skl) 1350 { 1351 struct skl_pipeline *p; 1352 struct skl_pipe_module *m; 1353 struct snd_soc_dapm_widget *w; 1354 struct skl_module_cfg *mconfig; 1355 int ret = 0; 1356 1357 list_for_each_entry(p, &skl->ppl_list, node) { 1358 list_for_each_entry(m, &p->pipe->w_list, node) { 1359 w = m->w; 1360 mconfig = w->priv; 1361 1362 ret = skl_get_module_info(skl, mconfig); 1363 if (ret < 0) { 1364 dev_err(skl->dev, 1365 "query module info failed\n"); 1366 return ret; 1367 } 1368 1369 skl_tplg_add_moduleid_in_bind_params(skl, w); 1370 } 1371 } 1372 1373 return ret; 1374 } 1375 1376 static int skl_platform_soc_probe(struct snd_soc_component *component) 1377 { 1378 struct hdac_bus *bus = dev_get_drvdata(component->dev); 1379 struct skl_dev *skl = bus_to_skl(bus); 1380 const struct skl_dsp_ops *ops; 1381 int ret; 1382 1383 ret = pm_runtime_resume_and_get(component->dev); 1384 if (ret < 0 && ret != -EACCES) 1385 return ret; 1386 1387 if (bus->ppcap) { 1388 skl->component = component; 1389 1390 /* init debugfs */ 1391 skl->debugfs = skl_debugfs_init(skl); 1392 1393 ret = skl_tplg_init(component, bus); 1394 if (ret < 0) { 1395 dev_err(component->dev, "Failed to init topology!\n"); 1396 return ret; 1397 } 1398 1399 /* load the firmwares, since all is set */ 1400 ops = skl_get_dsp_ops(skl->pci->device); 1401 if (!ops) 1402 return -EIO; 1403 1404 /* 1405 * Disable dynamic clock and power gating during firmware 1406 * and library download 1407 */ 1408 skl->enable_miscbdcge(component->dev, false); 1409 skl->clock_power_gating(component->dev, false); 1410 1411 ret = ops->init_fw(component->dev, skl); 1412 skl->enable_miscbdcge(component->dev, true); 1413 skl->clock_power_gating(component->dev, true); 1414 if (ret < 0) { 1415 dev_err(component->dev, "Failed to boot first fw: %d\n", ret); 1416 return ret; 1417 } 1418 skl_populate_modules(skl); 1419 skl->update_d0i3c = skl_update_d0i3c; 1420 1421 if (skl->cfg.astate_cfg != NULL) { 1422 skl_dsp_set_astate_cfg(skl, 1423 skl->cfg.astate_cfg->count, 1424 skl->cfg.astate_cfg); 1425 } 1426 } 1427 pm_runtime_mark_last_busy(component->dev); 1428 pm_runtime_put_autosuspend(component->dev); 1429 1430 return 0; 1431 } 1432 1433 static void skl_platform_soc_remove(struct snd_soc_component *component) 1434 { 1435 struct hdac_bus *bus = dev_get_drvdata(component->dev); 1436 struct skl_dev *skl = bus_to_skl(bus); 1437 1438 skl_tplg_exit(component, bus); 1439 1440 skl_debugfs_exit(skl); 1441 } 1442 1443 static const struct snd_soc_component_driver skl_component = { 1444 .name = "pcm", 1445 .probe = skl_platform_soc_probe, 1446 .remove = skl_platform_soc_remove, 1447 .open = skl_platform_soc_open, 1448 .trigger = skl_platform_soc_trigger, 1449 .pointer = skl_platform_soc_pointer, 1450 .get_time_info = skl_platform_soc_get_time_info, 1451 .pcm_construct = skl_platform_soc_new, 1452 .module_get_upon_open = 1, /* increment refcount when a pcm is opened */ 1453 }; 1454 1455 int skl_platform_register(struct device *dev) 1456 { 1457 int ret; 1458 struct snd_soc_dai_driver *dais; 1459 int num_dais = ARRAY_SIZE(skl_platform_dai); 1460 struct hdac_bus *bus = dev_get_drvdata(dev); 1461 struct skl_dev *skl = bus_to_skl(bus); 1462 1463 skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai), 1464 GFP_KERNEL); 1465 if (!skl->dais) { 1466 ret = -ENOMEM; 1467 goto err; 1468 } 1469 1470 if (!skl->use_tplg_pcm) { 1471 dais = krealloc(skl->dais, sizeof(skl_fe_dai) + 1472 sizeof(skl_platform_dai), GFP_KERNEL); 1473 if (!dais) { 1474 ret = -ENOMEM; 1475 goto err; 1476 } 1477 1478 skl->dais = dais; 1479 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai, 1480 sizeof(skl_fe_dai)); 1481 num_dais += ARRAY_SIZE(skl_fe_dai); 1482 } 1483 1484 ret = devm_snd_soc_register_component(dev, &skl_component, 1485 skl->dais, num_dais); 1486 if (ret) 1487 dev_err(dev, "soc component registration failed %d\n", ret); 1488 err: 1489 return ret; 1490 } 1491 1492 int skl_platform_unregister(struct device *dev) 1493 { 1494 struct hdac_bus *bus = dev_get_drvdata(dev); 1495 struct skl_dev *skl = bus_to_skl(bus); 1496 struct skl_module_deferred_bind *modules, *tmp; 1497 1498 list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) { 1499 list_del(&modules->node); 1500 kfree(modules); 1501 } 1502 1503 kfree(skl->dais); 1504 1505 return 0; 1506 } 1507