1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_context.h" 8 #include "intel_engine_pm.h" 9 #include "intel_gpu_commands.h" 10 #include "intel_gt.h" 11 #include "intel_ring.h" 12 #include "intel_workarounds.h" 13 14 /** 15 * DOC: Hardware workarounds 16 * 17 * This file is intended as a central place to implement most [1]_ of the 18 * required workarounds for hardware to work as originally intended. They fall 19 * in five basic categories depending on how/when they are applied: 20 * 21 * - Workarounds that touch registers that are saved/restored to/from the HW 22 * context image. The list is emitted (via Load Register Immediate commands) 23 * everytime a new context is created. 24 * - GT workarounds. The list of these WAs is applied whenever these registers 25 * revert to default values (on GPU reset, suspend/resume [2]_, etc..). 26 * - Display workarounds. The list is applied during display clock-gating 27 * initialization. 28 * - Workarounds that whitelist a privileged register, so that UMDs can manage 29 * them directly. This is just a special case of a MMMIO workaround (as we 30 * write the list of these to/be-whitelisted registers to some special HW 31 * registers). 32 * - Workaround batchbuffers, that get executed automatically by the hardware 33 * on every HW context restore. 34 * 35 * .. [1] Please notice that there are other WAs that, due to their nature, 36 * cannot be applied from a central place. Those are peppered around the rest 37 * of the code, as needed. 38 * 39 * .. [2] Technically, some registers are powercontext saved & restored, so they 40 * survive a suspend/resume. In practice, writing them again is not too 41 * costly and simplifies things. We can revisit this in the future. 42 * 43 * Layout 44 * ~~~~~~ 45 * 46 * Keep things in this file ordered by WA type, as per the above (context, GT, 47 * display, register whitelist, batchbuffer). Then, inside each type, keep the 48 * following order: 49 * 50 * - Infrastructure functions and macros 51 * - WAs per platform in standard gen/chrono order 52 * - Public functions to init or apply the given workaround type. 53 */ 54 55 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) 56 { 57 wal->name = name; 58 wal->engine_name = engine_name; 59 } 60 61 #define WA_LIST_CHUNK (1 << 4) 62 63 static void wa_init_finish(struct i915_wa_list *wal) 64 { 65 /* Trim unused entries. */ 66 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 67 struct i915_wa *list = kmemdup(wal->list, 68 wal->count * sizeof(*list), 69 GFP_KERNEL); 70 71 if (list) { 72 kfree(wal->list); 73 wal->list = list; 74 } 75 } 76 77 if (!wal->count) 78 return; 79 80 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n", 81 wal->wa_count, wal->name, wal->engine_name); 82 } 83 84 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 85 { 86 unsigned int addr = i915_mmio_reg_offset(wa->reg); 87 unsigned int start = 0, end = wal->count; 88 const unsigned int grow = WA_LIST_CHUNK; 89 struct i915_wa *wa_; 90 91 GEM_BUG_ON(!is_power_of_2(grow)); 92 93 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 94 struct i915_wa *list; 95 96 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 97 GFP_KERNEL); 98 if (!list) { 99 DRM_ERROR("No space for workaround init!\n"); 100 return; 101 } 102 103 if (wal->list) { 104 memcpy(list, wal->list, sizeof(*wa) * wal->count); 105 kfree(wal->list); 106 } 107 108 wal->list = list; 109 } 110 111 while (start < end) { 112 unsigned int mid = start + (end - start) / 2; 113 114 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 115 start = mid + 1; 116 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 117 end = mid; 118 } else { 119 wa_ = &wal->list[mid]; 120 121 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 122 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 123 i915_mmio_reg_offset(wa_->reg), 124 wa_->clr, wa_->set); 125 126 wa_->set &= ~wa->clr; 127 } 128 129 wal->wa_count++; 130 wa_->set |= wa->set; 131 wa_->clr |= wa->clr; 132 wa_->read |= wa->read; 133 return; 134 } 135 } 136 137 wal->wa_count++; 138 wa_ = &wal->list[wal->count++]; 139 *wa_ = *wa; 140 141 while (wa_-- > wal->list) { 142 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 143 i915_mmio_reg_offset(wa_[1].reg)); 144 if (i915_mmio_reg_offset(wa_[1].reg) > 145 i915_mmio_reg_offset(wa_[0].reg)) 146 break; 147 148 swap(wa_[1], wa_[0]); 149 } 150 } 151 152 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 153 u32 clear, u32 set, u32 read_mask, bool masked_reg) 154 { 155 struct i915_wa wa = { 156 .reg = reg, 157 .clr = clear, 158 .set = set, 159 .read = read_mask, 160 .masked_reg = masked_reg, 161 }; 162 163 _wa_add(wal, &wa); 164 } 165 166 static void 167 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 168 { 169 wa_add(wal, reg, clear, set, clear, false); 170 } 171 172 static void 173 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 174 { 175 wa_write_clr_set(wal, reg, ~0, set); 176 } 177 178 static void 179 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 180 { 181 wa_write_clr_set(wal, reg, set, set); 182 } 183 184 static void 185 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 186 { 187 wa_write_clr_set(wal, reg, clr, 0); 188 } 189 190 /* 191 * WA operations on "masked register". A masked register has the upper 16 bits 192 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 193 * portion of the register without a rmw: you simply write in the upper 16 bits 194 * the mask of bits you are going to modify. 195 * 196 * The wa_masked_* family of functions already does the necessary operations to 197 * calculate the mask based on the parameters passed, so user only has to 198 * provide the lower 16 bits of that register. 199 */ 200 201 static void 202 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 203 { 204 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 205 } 206 207 static void 208 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 209 { 210 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 211 } 212 213 static void 214 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 215 u32 mask, u32 val) 216 { 217 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 218 } 219 220 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 221 struct i915_wa_list *wal) 222 { 223 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 224 } 225 226 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 227 struct i915_wa_list *wal) 228 { 229 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 230 } 231 232 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 233 struct i915_wa_list *wal) 234 { 235 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 236 237 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 238 wa_masked_en(wal, MI_MODE, ASYNC_FLIP_PERF_DISABLE); 239 240 /* WaDisablePartialInstShootdown:bdw,chv */ 241 wa_masked_en(wal, GEN8_ROW_CHICKEN, 242 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 243 244 /* Use Force Non-Coherent whenever executing a 3D context. This is a 245 * workaround for a possible hang in the unlikely event a TLB 246 * invalidation occurs during a PSD flush. 247 */ 248 /* WaForceEnableNonCoherent:bdw,chv */ 249 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 250 wa_masked_en(wal, HDC_CHICKEN0, 251 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 252 HDC_FORCE_NON_COHERENT); 253 254 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 255 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 256 * polygons in the same 8x4 pixel/sample area to be processed without 257 * stalling waiting for the earlier ones to write to Hierarchical Z 258 * buffer." 259 * 260 * This optimization is off by default for BDW and CHV; turn it on. 261 */ 262 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 263 264 /* Wa4x4STCOptimizationDisable:bdw,chv */ 265 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 266 267 /* 268 * BSpec recommends 8x4 when MSAA is used, 269 * however in practice 16x4 seems fastest. 270 * 271 * Note that PS/WM thread counts depend on the WIZ hashing 272 * disable bit, which we don't touch here, but it's good 273 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 274 */ 275 wa_masked_field_set(wal, GEN7_GT_MODE, 276 GEN6_WIZ_HASHING_MASK, 277 GEN6_WIZ_HASHING_16x4); 278 } 279 280 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 281 struct i915_wa_list *wal) 282 { 283 struct drm_i915_private *i915 = engine->i915; 284 285 gen8_ctx_workarounds_init(engine, wal); 286 287 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 288 wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 289 290 /* WaDisableDopClockGating:bdw 291 * 292 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 293 * to disable EUTC clock gating. 294 */ 295 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 296 DOP_CLOCK_GATING_DISABLE); 297 298 wa_masked_en(wal, HALF_SLICE_CHICKEN3, 299 GEN8_SAMPLER_POWER_BYPASS_DIS); 300 301 wa_masked_en(wal, HDC_CHICKEN0, 302 /* WaForceContextSaveRestoreNonCoherent:bdw */ 303 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 304 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 305 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 306 } 307 308 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 309 struct i915_wa_list *wal) 310 { 311 gen8_ctx_workarounds_init(engine, wal); 312 313 /* WaDisableThreadStallDopClockGating:chv */ 314 wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 315 316 /* Improve HiZ throughput on CHV. */ 317 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 318 } 319 320 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 321 struct i915_wa_list *wal) 322 { 323 struct drm_i915_private *i915 = engine->i915; 324 325 if (HAS_LLC(i915)) { 326 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 327 * 328 * Must match Display Engine. See 329 * WaCompressedResourceDisplayNewHashMode. 330 */ 331 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 332 GEN9_PBE_COMPRESSED_HASH_SELECTION); 333 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 334 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 335 } 336 337 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 338 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 339 wa_masked_en(wal, GEN8_ROW_CHICKEN, 340 FLOW_CONTROL_ENABLE | 341 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 342 343 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 344 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 345 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 346 GEN9_ENABLE_YV12_BUGFIX | 347 GEN9_ENABLE_GPGPU_PREEMPTION); 348 349 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 350 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 351 wa_masked_en(wal, CACHE_MODE_1, 352 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 353 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 354 355 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 356 wa_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 357 GEN9_CCS_TLB_PREFETCH_ENABLE); 358 359 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 360 wa_masked_en(wal, HDC_CHICKEN0, 361 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 362 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 363 364 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 365 * both tied to WaForceContextSaveRestoreNonCoherent 366 * in some hsds for skl. We keep the tie for all gen9. The 367 * documentation is a bit hazy and so we want to get common behaviour, 368 * even though there is no clear evidence we would need both on kbl/bxt. 369 * This area has been source of system hangs so we play it safe 370 * and mimic the skl regardless of what bspec says. 371 * 372 * Use Force Non-Coherent whenever executing a 3D context. This 373 * is a workaround for a possible hang in the unlikely event 374 * a TLB invalidation occurs during a PSD flush. 375 */ 376 377 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 378 wa_masked_en(wal, HDC_CHICKEN0, 379 HDC_FORCE_NON_COHERENT); 380 381 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 382 if (IS_SKYLAKE(i915) || 383 IS_KABYLAKE(i915) || 384 IS_COFFEELAKE(i915) || 385 IS_COMETLAKE(i915)) 386 wa_masked_en(wal, HALF_SLICE_CHICKEN3, 387 GEN8_SAMPLER_POWER_BYPASS_DIS); 388 389 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 390 wa_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 391 392 /* 393 * Supporting preemption with fine-granularity requires changes in the 394 * batch buffer programming. Since we can't break old userspace, we 395 * need to set our default preemption level to safe value. Userspace is 396 * still able to use more fine-grained preemption levels, since in 397 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 398 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 399 * not real HW workarounds, but merely a way to start using preemption 400 * while maintaining old contract with userspace. 401 */ 402 403 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 404 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 405 406 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 407 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 408 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 409 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 410 411 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 412 if (IS_GEN9_LP(i915)) 413 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 414 } 415 416 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 417 struct i915_wa_list *wal) 418 { 419 struct intel_gt *gt = engine->gt; 420 u8 vals[3] = { 0, 0, 0 }; 421 unsigned int i; 422 423 for (i = 0; i < 3; i++) { 424 u8 ss; 425 426 /* 427 * Only consider slices where one, and only one, subslice has 7 428 * EUs 429 */ 430 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 431 continue; 432 433 /* 434 * subslice_7eu[i] != 0 (because of the check above) and 435 * ss_max == 4 (maximum number of subslices possible per slice) 436 * 437 * -> 0 <= ss <= 3; 438 */ 439 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 440 vals[i] = 3 - ss; 441 } 442 443 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 444 return; 445 446 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 447 wa_masked_field_set(wal, GEN7_GT_MODE, 448 GEN9_IZ_HASHING_MASK(2) | 449 GEN9_IZ_HASHING_MASK(1) | 450 GEN9_IZ_HASHING_MASK(0), 451 GEN9_IZ_HASHING(2, vals[2]) | 452 GEN9_IZ_HASHING(1, vals[1]) | 453 GEN9_IZ_HASHING(0, vals[0])); 454 } 455 456 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 457 struct i915_wa_list *wal) 458 { 459 gen9_ctx_workarounds_init(engine, wal); 460 skl_tune_iz_hashing(engine, wal); 461 } 462 463 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 464 struct i915_wa_list *wal) 465 { 466 gen9_ctx_workarounds_init(engine, wal); 467 468 /* WaDisableThreadStallDopClockGating:bxt */ 469 wa_masked_en(wal, GEN8_ROW_CHICKEN, 470 STALL_DOP_GATING_DISABLE); 471 472 /* WaToEnableHwFixForPushConstHWBug:bxt */ 473 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 474 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 475 } 476 477 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 478 struct i915_wa_list *wal) 479 { 480 struct drm_i915_private *i915 = engine->i915; 481 482 gen9_ctx_workarounds_init(engine, wal); 483 484 /* WaToEnableHwFixForPushConstHWBug:kbl */ 485 if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) 486 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 487 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 488 489 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 490 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 491 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 492 } 493 494 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 495 struct i915_wa_list *wal) 496 { 497 gen9_ctx_workarounds_init(engine, wal); 498 499 /* WaToEnableHwFixForPushConstHWBug:glk */ 500 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 501 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 502 } 503 504 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 505 struct i915_wa_list *wal) 506 { 507 gen9_ctx_workarounds_init(engine, wal); 508 509 /* WaToEnableHwFixForPushConstHWBug:cfl */ 510 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 511 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 512 513 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 514 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 515 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 516 } 517 518 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 519 struct i915_wa_list *wal) 520 { 521 /* Wa_1406697149 (WaDisableBankHangMode:icl) */ 522 wa_write(wal, 523 GEN8_L3CNTLREG, 524 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 525 GEN8_ERRDETBCTRL); 526 527 /* WaForceEnableNonCoherent:icl 528 * This is not the same workaround as in early Gen9 platforms, where 529 * lacking this could cause system hangs, but coherency performance 530 * overhead is high and only a few compute workloads really need it 531 * (the register is whitelisted in hardware now, so UMDs can opt in 532 * for coherency if they have a good reason). 533 */ 534 wa_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 535 536 /* WaEnableFloatBlendOptimization:icl */ 537 wa_add(wal, GEN10_CACHE_MODE_SS, 0, 538 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 539 0 /* write-only, so skip validation */, 540 true); 541 542 /* WaDisableGPGPUMidThreadPreemption:icl */ 543 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 544 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 545 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 546 547 /* allow headerless messages for preemptible GPGPU context */ 548 wa_masked_en(wal, GEN10_SAMPLER_MODE, 549 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 550 551 /* Wa_1604278689:icl,ehl */ 552 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 553 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 554 0, /* write-only register; skip validation */ 555 0xFFFFFFFF); 556 557 /* Wa_1406306137:icl,ehl */ 558 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 559 } 560 561 /* 562 * These settings aren't actually workarounds, but general tuning settings that 563 * need to be programmed on dg2 platform. 564 */ 565 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, 566 struct i915_wa_list *wal) 567 { 568 wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 569 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); 570 wa_add(wal, 571 FF_MODE2, 572 FF_MODE2_TDS_TIMER_MASK, 573 FF_MODE2_TDS_TIMER_128, 574 0, false); 575 } 576 577 /* 578 * These settings aren't actually workarounds, but general tuning settings that 579 * need to be programmed on several platforms. 580 */ 581 static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, 582 struct i915_wa_list *wal) 583 { 584 /* 585 * Although some platforms refer to it as Wa_1604555607, we need to 586 * program it even on those that don't explicitly list that 587 * workaround. 588 * 589 * Note that the programming of this register is further modified 590 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 591 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong 592 * value when read. The default value for this register is zero for all 593 * fields and there are no bit masks. So instead of doing a RMW we 594 * should just write TDS timer value. For the same reason read 595 * verification is ignored. 596 */ 597 wa_add(wal, 598 FF_MODE2, 599 FF_MODE2_TDS_TIMER_MASK, 600 FF_MODE2_TDS_TIMER_128, 601 0, false); 602 } 603 604 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 605 struct i915_wa_list *wal) 606 { 607 gen12_ctx_gt_tuning_init(engine, wal); 608 609 /* 610 * Wa_1409142259:tgl,dg1,adl-p 611 * Wa_1409347922:tgl,dg1,adl-p 612 * Wa_1409252684:tgl,dg1,adl-p 613 * Wa_1409217633:tgl,dg1,adl-p 614 * Wa_1409207793:tgl,dg1,adl-p 615 * Wa_1409178076:tgl,dg1,adl-p 616 * Wa_1408979724:tgl,dg1,adl-p 617 * Wa_14010443199:tgl,rkl,dg1,adl-p 618 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p 619 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p 620 */ 621 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 622 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 623 624 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 625 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 626 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 627 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 628 629 /* 630 * Wa_16011163337 631 * 632 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due 633 * to Wa_1608008084. 634 */ 635 wa_add(wal, 636 FF_MODE2, 637 FF_MODE2_GS_TIMER_MASK, 638 FF_MODE2_GS_TIMER_224, 639 0, false); 640 } 641 642 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 643 struct i915_wa_list *wal) 644 { 645 gen12_ctx_workarounds_init(engine, wal); 646 647 /* Wa_1409044764 */ 648 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 649 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 650 651 /* Wa_22010493298 */ 652 wa_masked_en(wal, HIZ_CHICKEN, 653 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 654 } 655 656 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 657 struct i915_wa_list *wal) 658 { 659 dg2_ctx_gt_tuning_init(engine, wal); 660 661 /* Wa_16011186671:dg2_g11 */ 662 if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 663 wa_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH); 664 wa_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE); 665 } 666 667 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 668 /* Wa_14010469329:dg2_g10 */ 669 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 670 XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE); 671 672 /* 673 * Wa_22010465075:dg2_g10 674 * Wa_22010613112:dg2_g10 675 * Wa_14010698770:dg2_g10 676 */ 677 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 678 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 679 } 680 681 /* Wa_16013271637:dg2 */ 682 wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1, 683 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 684 685 /* Wa_22012532006:dg2 */ 686 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) || 687 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) 688 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 689 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA); 690 } 691 692 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, 693 struct i915_wa_list *wal) 694 { 695 /* 696 * This is a "fake" workaround defined by software to ensure we 697 * maintain reliable, backward-compatible behavior for userspace with 698 * regards to how nested MI_BATCH_BUFFER_START commands are handled. 699 * 700 * The per-context setting of MI_MODE[12] determines whether the bits 701 * of a nested MI_BATCH_BUFFER_START instruction should be interpreted 702 * in the traditional manner or whether they should instead use a new 703 * tgl+ meaning that breaks backward compatibility, but allows nesting 704 * into 3rd-level batchbuffers. When this new capability was first 705 * added in TGL, it remained off by default unless a context 706 * intentionally opted in to the new behavior. However Xe_HPG now 707 * flips this on by default and requires that we explicitly opt out if 708 * we don't want the new behavior. 709 * 710 * From a SW perspective, we want to maintain the backward-compatible 711 * behavior for userspace, so we'll apply a fake workaround to set it 712 * back to the legacy behavior on platforms where the hardware default 713 * is to break compatibility. At the moment there is no Linux 714 * userspace that utilizes third-level batchbuffers, so this will avoid 715 * userspace from needing to make any changes. using the legacy 716 * meaning is the correct thing to do. If/when we have userspace 717 * consumers that want to utilize third-level batch nesting, we can 718 * provide a context parameter to allow them to opt-in. 719 */ 720 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); 721 } 722 723 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine, 724 struct i915_wa_list *wal) 725 { 726 u8 mocs; 727 728 /* 729 * Some blitter commands do not have a field for MOCS, those 730 * commands will use MOCS index pointed by BLIT_CCTL. 731 * BLIT_CCTL registers are needed to be programmed to un-cached. 732 */ 733 if (engine->class == COPY_ENGINE_CLASS) { 734 mocs = engine->gt->mocs.uc_index; 735 wa_write_clr_set(wal, 736 BLIT_CCTL(engine->mmio_base), 737 BLIT_CCTL_MASK, 738 BLIT_CCTL_MOCS(mocs, mocs)); 739 } 740 } 741 742 /* 743 * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround 744 * defined by the hardware team, but it programming general context registers. 745 * Adding those context register programming in context workaround 746 * allow us to use the wa framework for proper application and validation. 747 */ 748 static void 749 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine, 750 struct i915_wa_list *wal) 751 { 752 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) 753 fakewa_disable_nestedbb_mode(engine, wal); 754 755 gen12_ctx_gt_mocs_init(engine, wal); 756 } 757 758 static void 759 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 760 struct i915_wa_list *wal, 761 const char *name) 762 { 763 struct drm_i915_private *i915 = engine->i915; 764 765 wa_init_start(wal, name, engine->name); 766 767 /* Applies to all engines */ 768 /* 769 * Fake workarounds are not the actual workaround but 770 * programming of context registers using workaround framework. 771 */ 772 if (GRAPHICS_VER(i915) >= 12) 773 gen12_ctx_gt_fake_wa_init(engine, wal); 774 775 if (engine->class != RENDER_CLASS) 776 goto done; 777 778 if (IS_DG2(i915)) 779 dg2_ctx_workarounds_init(engine, wal); 780 else if (IS_XEHPSDV(i915)) 781 ; /* noop; none at this time */ 782 else if (IS_DG1(i915)) 783 dg1_ctx_workarounds_init(engine, wal); 784 else if (GRAPHICS_VER(i915) == 12) 785 gen12_ctx_workarounds_init(engine, wal); 786 else if (GRAPHICS_VER(i915) == 11) 787 icl_ctx_workarounds_init(engine, wal); 788 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 789 cfl_ctx_workarounds_init(engine, wal); 790 else if (IS_GEMINILAKE(i915)) 791 glk_ctx_workarounds_init(engine, wal); 792 else if (IS_KABYLAKE(i915)) 793 kbl_ctx_workarounds_init(engine, wal); 794 else if (IS_BROXTON(i915)) 795 bxt_ctx_workarounds_init(engine, wal); 796 else if (IS_SKYLAKE(i915)) 797 skl_ctx_workarounds_init(engine, wal); 798 else if (IS_CHERRYVIEW(i915)) 799 chv_ctx_workarounds_init(engine, wal); 800 else if (IS_BROADWELL(i915)) 801 bdw_ctx_workarounds_init(engine, wal); 802 else if (GRAPHICS_VER(i915) == 7) 803 gen7_ctx_workarounds_init(engine, wal); 804 else if (GRAPHICS_VER(i915) == 6) 805 gen6_ctx_workarounds_init(engine, wal); 806 else if (GRAPHICS_VER(i915) < 8) 807 ; 808 else 809 MISSING_CASE(GRAPHICS_VER(i915)); 810 811 done: 812 wa_init_finish(wal); 813 } 814 815 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 816 { 817 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 818 } 819 820 int intel_engine_emit_ctx_wa(struct i915_request *rq) 821 { 822 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 823 struct i915_wa *wa; 824 unsigned int i; 825 u32 *cs; 826 int ret; 827 828 if (wal->count == 0) 829 return 0; 830 831 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 832 if (ret) 833 return ret; 834 835 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 836 if (IS_ERR(cs)) 837 return PTR_ERR(cs); 838 839 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 840 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 841 *cs++ = i915_mmio_reg_offset(wa->reg); 842 *cs++ = wa->set; 843 } 844 *cs++ = MI_NOOP; 845 846 intel_ring_advance(rq, cs); 847 848 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 849 if (ret) 850 return ret; 851 852 return 0; 853 } 854 855 static void 856 gen4_gt_workarounds_init(struct intel_gt *gt, 857 struct i915_wa_list *wal) 858 { 859 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 860 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 861 } 862 863 static void 864 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 865 { 866 gen4_gt_workarounds_init(gt, wal); 867 868 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 869 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 870 } 871 872 static void 873 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 874 { 875 g4x_gt_workarounds_init(gt, wal); 876 877 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 878 } 879 880 static void 881 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 882 { 883 } 884 885 static void 886 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 887 { 888 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 889 wa_masked_dis(wal, 890 GEN7_COMMON_SLICE_CHICKEN1, 891 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 892 893 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 894 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 895 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 896 897 /* WaForceL3Serialization:ivb */ 898 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 899 } 900 901 static void 902 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 903 { 904 /* WaForceL3Serialization:vlv */ 905 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 906 907 /* 908 * WaIncreaseL3CreditsForVLVB0:vlv 909 * This is the hardware default actually. 910 */ 911 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 912 } 913 914 static void 915 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 916 { 917 /* L3 caching of data atomics doesn't work -- disable it. */ 918 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 919 920 wa_add(wal, 921 HSW_ROW_CHICKEN3, 0, 922 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 923 0 /* XXX does this reg exist? */, true); 924 925 /* WaVSRefCountFullforceMissDisable:hsw */ 926 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 927 } 928 929 static void 930 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 931 { 932 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; 933 unsigned int slice, subslice; 934 u32 mcr, mcr_mask; 935 936 GEM_BUG_ON(GRAPHICS_VER(i915) != 9); 937 938 /* 939 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml 940 * Before any MMIO read into slice/subslice specific registers, MCR 941 * packet control register needs to be programmed to point to any 942 * enabled s/ss pair. Otherwise, incorrect values will be returned. 943 * This means each subsequent MMIO read will be forwarded to an 944 * specific s/ss combination, but this is OK since these registers 945 * are consistent across s/ss in almost all cases. In the rare 946 * occasions, such as INSTDONE, where this value is dependent 947 * on s/ss combo, the read should be done with read_subslice_reg. 948 */ 949 slice = ffs(sseu->slice_mask) - 1; 950 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask)); 951 subslice = ffs(intel_sseu_get_subslices(sseu, slice)); 952 GEM_BUG_ON(!subslice); 953 subslice--; 954 955 /* 956 * We use GEN8_MCR..() macros to calculate the |mcr| value for 957 * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads 958 */ 959 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 960 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 961 962 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); 963 964 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 965 } 966 967 static void 968 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 969 { 970 struct drm_i915_private *i915 = gt->i915; 971 972 /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ 973 gen9_wa_init_mcr(i915, wal); 974 975 /* WaDisableKillLogic:bxt,skl,kbl */ 976 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 977 wa_write_or(wal, 978 GAM_ECOCHK, 979 ECOCHK_DIS_TLB); 980 981 if (HAS_LLC(i915)) { 982 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 983 * 984 * Must match Display Engine. See 985 * WaCompressedResourceDisplayNewHashMode. 986 */ 987 wa_write_or(wal, 988 MMCD_MISC_CTRL, 989 MMCD_PCLA | MMCD_HOTSPOT_EN); 990 } 991 992 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 993 wa_write_or(wal, 994 GAM_ECOCHK, 995 BDW_DISABLE_HDC_INVALIDATION); 996 } 997 998 static void 999 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1000 { 1001 gen9_gt_workarounds_init(gt, wal); 1002 1003 /* WaDisableGafsUnitClkGating:skl */ 1004 wa_write_or(wal, 1005 GEN7_UCGCTL4, 1006 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1007 1008 /* WaInPlaceDecompressionHang:skl */ 1009 if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) 1010 wa_write_or(wal, 1011 GEN9_GAMT_ECO_REG_RW_IA, 1012 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1013 } 1014 1015 static void 1016 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1017 { 1018 gen9_gt_workarounds_init(gt, wal); 1019 1020 /* WaDisableDynamicCreditSharing:kbl */ 1021 if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) 1022 wa_write_or(wal, 1023 GAMT_CHKN_BIT_REG, 1024 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1025 1026 /* WaDisableGafsUnitClkGating:kbl */ 1027 wa_write_or(wal, 1028 GEN7_UCGCTL4, 1029 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1030 1031 /* WaInPlaceDecompressionHang:kbl */ 1032 wa_write_or(wal, 1033 GEN9_GAMT_ECO_REG_RW_IA, 1034 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1035 } 1036 1037 static void 1038 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1039 { 1040 gen9_gt_workarounds_init(gt, wal); 1041 } 1042 1043 static void 1044 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1045 { 1046 gen9_gt_workarounds_init(gt, wal); 1047 1048 /* WaDisableGafsUnitClkGating:cfl */ 1049 wa_write_or(wal, 1050 GEN7_UCGCTL4, 1051 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1052 1053 /* WaInPlaceDecompressionHang:cfl */ 1054 wa_write_or(wal, 1055 GEN9_GAMT_ECO_REG_RW_IA, 1056 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1057 } 1058 1059 static void __set_mcr_steering(struct i915_wa_list *wal, 1060 i915_reg_t steering_reg, 1061 unsigned int slice, unsigned int subslice) 1062 { 1063 u32 mcr, mcr_mask; 1064 1065 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1066 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1067 1068 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); 1069 } 1070 1071 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, 1072 unsigned int slice, unsigned int subslice) 1073 { 1074 drm_dbg(>->i915->drm, "MCR slice=0x%x, subslice=0x%x\n", slice, subslice); 1075 1076 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); 1077 } 1078 1079 static void 1080 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1081 { 1082 const struct sseu_dev_info *sseu = >->info.sseu; 1083 unsigned int slice, subslice; 1084 1085 GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); 1086 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 1087 slice = 0; 1088 1089 /* 1090 * Although a platform may have subslices, we need to always steer 1091 * reads to the lowest instance that isn't fused off. When Render 1092 * Power Gating is enabled, grabbing forcewake will only power up a 1093 * single subslice (the "minconfig") if there isn't a real workload 1094 * that needs to be run; this means that if we steer register reads to 1095 * one of the higher subslices, we run the risk of reading back 0's or 1096 * random garbage. 1097 */ 1098 subslice = __ffs(intel_sseu_get_subslices(sseu, slice)); 1099 1100 /* 1101 * If the subslice we picked above also steers us to a valid L3 bank, 1102 * then we can just rely on the default steering and won't need to 1103 * worry about explicitly re-steering L3BANK reads later. 1104 */ 1105 if (gt->info.l3bank_mask & BIT(subslice)) 1106 gt->steering_table[L3BANK] = NULL; 1107 1108 __add_mcr_wa(gt, wal, slice, subslice); 1109 } 1110 1111 static void 1112 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1113 { 1114 const struct sseu_dev_info *sseu = >->info.sseu; 1115 unsigned long slice, subslice = 0, slice_mask = 0; 1116 u64 dss_mask = 0; 1117 u32 lncf_mask = 0; 1118 int i; 1119 1120 /* 1121 * On Xe_HP the steering increases in complexity. There are now several 1122 * more units that require steering and we're not guaranteed to be able 1123 * to find a common setting for all of them. These are: 1124 * - GSLICE (fusable) 1125 * - DSS (sub-unit within gslice; fusable) 1126 * - L3 Bank (fusable) 1127 * - MSLICE (fusable) 1128 * - LNCF (sub-unit within mslice; always present if mslice is present) 1129 * 1130 * We'll do our default/implicit steering based on GSLICE (in the 1131 * sliceid field) and DSS (in the subsliceid field). If we can 1132 * find overlap between the valid MSLICE and/or LNCF values with 1133 * a suitable GSLICE, then we can just re-use the default value and 1134 * skip and explicit steering at runtime. 1135 * 1136 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find 1137 * a valid sliceid value. DSS steering is the only type of steering 1138 * that utilizes the 'subsliceid' bits. 1139 * 1140 * Also note that, even though the steering domain is called "GSlice" 1141 * and it is encoded in the register using the gslice format, the spec 1142 * says that the combined (geometry | compute) fuse should be used to 1143 * select the steering. 1144 */ 1145 1146 /* Find the potential gslice candidates */ 1147 dss_mask = intel_sseu_get_subslices(sseu, 0); 1148 slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE); 1149 1150 /* 1151 * Find the potential LNCF candidates. Either LNCF within a valid 1152 * mslice is fine. 1153 */ 1154 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) 1155 lncf_mask |= (0x3 << (i * 2)); 1156 1157 /* 1158 * Are there any sliceid values that work for both GSLICE and LNCF 1159 * steering? 1160 */ 1161 if (slice_mask & lncf_mask) { 1162 slice_mask &= lncf_mask; 1163 gt->steering_table[LNCF] = NULL; 1164 } 1165 1166 /* How about sliceid values that also work for MSLICE steering? */ 1167 if (slice_mask & gt->info.mslice_mask) { 1168 slice_mask &= gt->info.mslice_mask; 1169 gt->steering_table[MSLICE] = NULL; 1170 } 1171 1172 slice = __ffs(slice_mask); 1173 subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE)); 1174 WARN_ON(subslice > GEN_DSS_PER_GSLICE); 1175 WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0); 1176 1177 __add_mcr_wa(gt, wal, slice, subslice); 1178 1179 /* 1180 * SQIDI ranges are special because they use different steering 1181 * registers than everything else we work with. On XeHP SDV and 1182 * DG2-G10, any value in the steering registers will work fine since 1183 * all instances are present, but DG2-G11 only has SQIDI instances at 1184 * ID's 2 and 3, so we need to steer to one of those. For simplicity 1185 * we'll just steer to a hardcoded "2" since that value will work 1186 * everywhere. 1187 */ 1188 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); 1189 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); 1190 } 1191 1192 static void 1193 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1194 { 1195 struct drm_i915_private *i915 = gt->i915; 1196 1197 icl_wa_init_mcr(gt, wal); 1198 1199 /* WaModifyGamTlbPartitioning:icl */ 1200 wa_write_clr_set(wal, 1201 GEN11_GACB_PERF_CTRL, 1202 GEN11_HASH_CTRL_MASK, 1203 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1204 1205 /* Wa_1405766107:icl 1206 * Formerly known as WaCL2SFHalfMaxAlloc 1207 */ 1208 wa_write_or(wal, 1209 GEN11_LSN_UNSLCVC, 1210 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1211 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1212 1213 /* Wa_220166154:icl 1214 * Formerly known as WaDisCtxReload 1215 */ 1216 wa_write_or(wal, 1217 GEN8_GAMW_ECO_DEV_RW_IA, 1218 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1219 1220 /* Wa_1406463099:icl 1221 * Formerly known as WaGamTlbPendError 1222 */ 1223 wa_write_or(wal, 1224 GAMT_CHKN_BIT_REG, 1225 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1226 1227 /* Wa_1407352427:icl,ehl */ 1228 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1229 PSDUNIT_CLKGATE_DIS); 1230 1231 /* Wa_1406680159:icl,ehl */ 1232 wa_write_or(wal, 1233 SUBSLICE_UNIT_LEVEL_CLKGATE, 1234 GWUNIT_CLKGATE_DIS); 1235 1236 /* Wa_1607087056:icl,ehl,jsl */ 1237 if (IS_ICELAKE(i915) || 1238 IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1239 wa_write_or(wal, 1240 SLICE_UNIT_LEVEL_CLKGATE, 1241 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1242 1243 /* 1244 * This is not a documented workaround, but rather an optimization 1245 * to reduce sampler power. 1246 */ 1247 wa_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1248 } 1249 1250 /* 1251 * Though there are per-engine instances of these registers, 1252 * they retain their value through engine resets and should 1253 * only be provided on the GT workaround list rather than 1254 * the engine-specific workaround list. 1255 */ 1256 static void 1257 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) 1258 { 1259 struct intel_engine_cs *engine; 1260 int id; 1261 1262 for_each_engine(engine, gt, id) { 1263 if (engine->class != VIDEO_DECODE_CLASS || 1264 (engine->instance % 2)) 1265 continue; 1266 1267 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), 1268 IECPUNIT_CLKGATE_DIS); 1269 } 1270 } 1271 1272 static void 1273 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1274 { 1275 icl_wa_init_mcr(gt, wal); 1276 1277 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ 1278 wa_14011060649(gt, wal); 1279 1280 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ 1281 wa_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1282 } 1283 1284 static void 1285 tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1286 { 1287 struct drm_i915_private *i915 = gt->i915; 1288 1289 gen12_gt_workarounds_init(gt, wal); 1290 1291 /* Wa_1409420604:tgl */ 1292 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1293 wa_write_or(wal, 1294 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1295 CPSSUNIT_CLKGATE_DIS); 1296 1297 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1298 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1299 wa_write_or(wal, 1300 SLICE_UNIT_LEVEL_CLKGATE, 1301 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1302 1303 /* Wa_1408615072:tgl[a0] */ 1304 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1305 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1306 VSUNIT_CLKGATE_DIS_TGL); 1307 } 1308 1309 static void 1310 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1311 { 1312 struct drm_i915_private *i915 = gt->i915; 1313 1314 gen12_gt_workarounds_init(gt, wal); 1315 1316 /* Wa_1607087056:dg1 */ 1317 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1318 wa_write_or(wal, 1319 SLICE_UNIT_LEVEL_CLKGATE, 1320 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1321 1322 /* Wa_1409420604:dg1 */ 1323 if (IS_DG1(i915)) 1324 wa_write_or(wal, 1325 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1326 CPSSUNIT_CLKGATE_DIS); 1327 1328 /* Wa_1408615072:dg1 */ 1329 /* Empirical testing shows this register is unaffected by engine reset. */ 1330 if (IS_DG1(i915)) 1331 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1332 VSUNIT_CLKGATE_DIS_TGL); 1333 } 1334 1335 static void 1336 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1337 { 1338 struct drm_i915_private *i915 = gt->i915; 1339 1340 xehp_init_mcr(gt, wal); 1341 1342 /* Wa_1409757795:xehpsdv */ 1343 wa_write_or(wal, SCCGCTL94DC, CG3DDISURB); 1344 1345 /* Wa_18011725039:xehpsdv */ 1346 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { 1347 wa_masked_dis(wal, MLTICTXCTL, TDONRENDER); 1348 wa_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); 1349 } 1350 1351 /* Wa_16011155590:xehpsdv */ 1352 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1353 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1354 TSGUNIT_CLKGATE_DIS); 1355 1356 /* Wa_14011780169:xehpsdv */ 1357 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) { 1358 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1359 GAMTLBVDBOX7_CLKGATE_DIS | 1360 GAMTLBVDBOX6_CLKGATE_DIS | 1361 GAMTLBVDBOX5_CLKGATE_DIS | 1362 GAMTLBVDBOX4_CLKGATE_DIS | 1363 GAMTLBVDBOX3_CLKGATE_DIS | 1364 GAMTLBVDBOX2_CLKGATE_DIS | 1365 GAMTLBVDBOX1_CLKGATE_DIS | 1366 GAMTLBVDBOX0_CLKGATE_DIS | 1367 GAMTLBKCR_CLKGATE_DIS | 1368 GAMTLBGUC_CLKGATE_DIS | 1369 GAMTLBBLT_CLKGATE_DIS); 1370 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1371 GAMTLBGFXA1_CLKGATE_DIS | 1372 GAMTLBCOMPA0_CLKGATE_DIS | 1373 GAMTLBCOMPA1_CLKGATE_DIS | 1374 GAMTLBCOMPB0_CLKGATE_DIS | 1375 GAMTLBCOMPB1_CLKGATE_DIS | 1376 GAMTLBCOMPC0_CLKGATE_DIS | 1377 GAMTLBCOMPC1_CLKGATE_DIS | 1378 GAMTLBCOMPD0_CLKGATE_DIS | 1379 GAMTLBCOMPD1_CLKGATE_DIS | 1380 GAMTLBMERT_CLKGATE_DIS | 1381 GAMTLBVEBOX3_CLKGATE_DIS | 1382 GAMTLBVEBOX2_CLKGATE_DIS | 1383 GAMTLBVEBOX1_CLKGATE_DIS | 1384 GAMTLBVEBOX0_CLKGATE_DIS); 1385 } 1386 1387 /* Wa_14012362059:xehpsdv */ 1388 wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB); 1389 1390 /* Wa_16012725990:xehpsdv */ 1391 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER)) 1392 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS); 1393 1394 /* Wa_14011060649:xehpsdv */ 1395 wa_14011060649(gt, wal); 1396 1397 /* Wa_14014368820:xehpsdv */ 1398 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 1399 GLOBAL_INVALIDATION_MODE); 1400 } 1401 1402 static void 1403 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1404 { 1405 struct intel_engine_cs *engine; 1406 int id; 1407 1408 xehp_init_mcr(gt, wal); 1409 1410 /* Wa_14011060649:dg2 */ 1411 wa_14011060649(gt, wal); 1412 1413 /* 1414 * Although there are per-engine instances of these registers, 1415 * they technically exist outside the engine itself and are not 1416 * impacted by engine resets. Furthermore, they're part of the 1417 * GuC blacklist so trying to treat them as engine workarounds 1418 * will result in GuC initialization failure and a wedged GPU. 1419 */ 1420 for_each_engine(engine, gt, id) { 1421 if (engine->class != VIDEO_DECODE_CLASS) 1422 continue; 1423 1424 /* Wa_16010515920:dg2_g10 */ 1425 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) 1426 wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base), 1427 ALNUNIT_CLKGATE_DIS); 1428 } 1429 1430 if (IS_DG2_G10(gt->i915)) { 1431 /* Wa_22010523718:dg2 */ 1432 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1433 CG3DDISCFEG_CLKGATE_DIS); 1434 1435 /* Wa_14011006942:dg2 */ 1436 wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE, 1437 DSS_ROUTER_CLKGATE_DIS); 1438 } 1439 1440 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) { 1441 /* Wa_14010680813:dg2_g10 */ 1442 wa_write_or(wal, GEN12_GAMSTLB_CTRL, CONTROL_BLOCK_CLKGATE_DIS | 1443 EGRESS_BLOCK_CLKGATE_DIS | TAG_BLOCK_CLKGATE_DIS); 1444 1445 /* Wa_14010948348:dg2_g10 */ 1446 wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS); 1447 1448 /* Wa_14011037102:dg2_g10 */ 1449 wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS); 1450 1451 /* Wa_14011371254:dg2_g10 */ 1452 wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS); 1453 1454 /* Wa_14011431319:dg2_g10 */ 1455 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1456 GAMTLBVDBOX7_CLKGATE_DIS | 1457 GAMTLBVDBOX6_CLKGATE_DIS | 1458 GAMTLBVDBOX5_CLKGATE_DIS | 1459 GAMTLBVDBOX4_CLKGATE_DIS | 1460 GAMTLBVDBOX3_CLKGATE_DIS | 1461 GAMTLBVDBOX2_CLKGATE_DIS | 1462 GAMTLBVDBOX1_CLKGATE_DIS | 1463 GAMTLBVDBOX0_CLKGATE_DIS | 1464 GAMTLBKCR_CLKGATE_DIS | 1465 GAMTLBGUC_CLKGATE_DIS | 1466 GAMTLBBLT_CLKGATE_DIS); 1467 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1468 GAMTLBGFXA1_CLKGATE_DIS | 1469 GAMTLBCOMPA0_CLKGATE_DIS | 1470 GAMTLBCOMPA1_CLKGATE_DIS | 1471 GAMTLBCOMPB0_CLKGATE_DIS | 1472 GAMTLBCOMPB1_CLKGATE_DIS | 1473 GAMTLBCOMPC0_CLKGATE_DIS | 1474 GAMTLBCOMPC1_CLKGATE_DIS | 1475 GAMTLBCOMPD0_CLKGATE_DIS | 1476 GAMTLBCOMPD1_CLKGATE_DIS | 1477 GAMTLBMERT_CLKGATE_DIS | 1478 GAMTLBVEBOX3_CLKGATE_DIS | 1479 GAMTLBVEBOX2_CLKGATE_DIS | 1480 GAMTLBVEBOX1_CLKGATE_DIS | 1481 GAMTLBVEBOX0_CLKGATE_DIS); 1482 1483 /* Wa_14010569222:dg2_g10 */ 1484 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1485 GAMEDIA_CLKGATE_DIS); 1486 1487 /* Wa_14011028019:dg2_g10 */ 1488 wa_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS); 1489 } 1490 1491 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0) || 1492 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) { 1493 /* Wa_14012362059:dg2 */ 1494 wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB); 1495 } 1496 1497 /* Wa_1509235366:dg2 */ 1498 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 1499 GLOBAL_INVALIDATION_MODE); 1500 1501 /* Wa_14014830051:dg2 */ 1502 wa_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1503 1504 /* 1505 * The following are not actually "workarounds" but rather 1506 * recommended tuning settings documented in the bspec's 1507 * performance guide section. 1508 */ 1509 wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 1510 wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS); 1511 } 1512 1513 static void 1514 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 1515 { 1516 struct drm_i915_private *i915 = gt->i915; 1517 1518 if (IS_DG2(i915)) 1519 dg2_gt_workarounds_init(gt, wal); 1520 else if (IS_XEHPSDV(i915)) 1521 xehpsdv_gt_workarounds_init(gt, wal); 1522 else if (IS_DG1(i915)) 1523 dg1_gt_workarounds_init(gt, wal); 1524 else if (IS_TIGERLAKE(i915)) 1525 tgl_gt_workarounds_init(gt, wal); 1526 else if (GRAPHICS_VER(i915) == 12) 1527 gen12_gt_workarounds_init(gt, wal); 1528 else if (GRAPHICS_VER(i915) == 11) 1529 icl_gt_workarounds_init(gt, wal); 1530 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1531 cfl_gt_workarounds_init(gt, wal); 1532 else if (IS_GEMINILAKE(i915)) 1533 glk_gt_workarounds_init(gt, wal); 1534 else if (IS_KABYLAKE(i915)) 1535 kbl_gt_workarounds_init(gt, wal); 1536 else if (IS_BROXTON(i915)) 1537 gen9_gt_workarounds_init(gt, wal); 1538 else if (IS_SKYLAKE(i915)) 1539 skl_gt_workarounds_init(gt, wal); 1540 else if (IS_HASWELL(i915)) 1541 hsw_gt_workarounds_init(gt, wal); 1542 else if (IS_VALLEYVIEW(i915)) 1543 vlv_gt_workarounds_init(gt, wal); 1544 else if (IS_IVYBRIDGE(i915)) 1545 ivb_gt_workarounds_init(gt, wal); 1546 else if (GRAPHICS_VER(i915) == 6) 1547 snb_gt_workarounds_init(gt, wal); 1548 else if (GRAPHICS_VER(i915) == 5) 1549 ilk_gt_workarounds_init(gt, wal); 1550 else if (IS_G4X(i915)) 1551 g4x_gt_workarounds_init(gt, wal); 1552 else if (GRAPHICS_VER(i915) == 4) 1553 gen4_gt_workarounds_init(gt, wal); 1554 else if (GRAPHICS_VER(i915) <= 8) 1555 ; 1556 else 1557 MISSING_CASE(GRAPHICS_VER(i915)); 1558 } 1559 1560 void intel_gt_init_workarounds(struct intel_gt *gt) 1561 { 1562 struct i915_wa_list *wal = >->wa_list; 1563 1564 wa_init_start(wal, "GT", "global"); 1565 gt_init_workarounds(gt, wal); 1566 wa_init_finish(wal); 1567 } 1568 1569 static enum forcewake_domains 1570 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1571 { 1572 enum forcewake_domains fw = 0; 1573 struct i915_wa *wa; 1574 unsigned int i; 1575 1576 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1577 fw |= intel_uncore_forcewake_for_reg(uncore, 1578 wa->reg, 1579 FW_REG_READ | 1580 FW_REG_WRITE); 1581 1582 return fw; 1583 } 1584 1585 static bool 1586 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from) 1587 { 1588 if ((cur ^ wa->set) & wa->read) { 1589 DRM_ERROR("%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1590 name, from, i915_mmio_reg_offset(wa->reg), 1591 cur, cur & wa->read, wa->set & wa->read); 1592 1593 return false; 1594 } 1595 1596 return true; 1597 } 1598 1599 static void 1600 wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal) 1601 { 1602 struct intel_uncore *uncore = gt->uncore; 1603 enum forcewake_domains fw; 1604 unsigned long flags; 1605 struct i915_wa *wa; 1606 unsigned int i; 1607 1608 if (!wal->count) 1609 return; 1610 1611 fw = wal_get_fw_for_rmw(uncore, wal); 1612 1613 spin_lock_irqsave(&uncore->lock, flags); 1614 intel_uncore_forcewake_get__locked(uncore, fw); 1615 1616 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1617 u32 val, old = 0; 1618 1619 /* open-coded rmw due to steering */ 1620 old = wa->clr ? intel_gt_read_register_fw(gt, wa->reg) : 0; 1621 val = (old & ~wa->clr) | wa->set; 1622 if (val != old || !wa->clr) 1623 intel_uncore_write_fw(uncore, wa->reg, val); 1624 1625 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 1626 wa_verify(wa, intel_gt_read_register_fw(gt, wa->reg), 1627 wal->name, "application"); 1628 } 1629 1630 intel_uncore_forcewake_put__locked(uncore, fw); 1631 spin_unlock_irqrestore(&uncore->lock, flags); 1632 } 1633 1634 void intel_gt_apply_workarounds(struct intel_gt *gt) 1635 { 1636 wa_list_apply(gt, >->wa_list); 1637 } 1638 1639 static bool wa_list_verify(struct intel_gt *gt, 1640 const struct i915_wa_list *wal, 1641 const char *from) 1642 { 1643 struct intel_uncore *uncore = gt->uncore; 1644 struct i915_wa *wa; 1645 enum forcewake_domains fw; 1646 unsigned long flags; 1647 unsigned int i; 1648 bool ok = true; 1649 1650 fw = wal_get_fw_for_rmw(uncore, wal); 1651 1652 spin_lock_irqsave(&uncore->lock, flags); 1653 intel_uncore_forcewake_get__locked(uncore, fw); 1654 1655 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1656 ok &= wa_verify(wa, 1657 intel_gt_read_register_fw(gt, wa->reg), 1658 wal->name, from); 1659 1660 intel_uncore_forcewake_put__locked(uncore, fw); 1661 spin_unlock_irqrestore(&uncore->lock, flags); 1662 1663 return ok; 1664 } 1665 1666 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1667 { 1668 return wa_list_verify(gt, >->wa_list, from); 1669 } 1670 1671 __maybe_unused 1672 static bool is_nonpriv_flags_valid(u32 flags) 1673 { 1674 /* Check only valid flag bits are set */ 1675 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1676 return false; 1677 1678 /* NB: Only 3 out of 4 enum values are valid for access field */ 1679 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1680 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1681 return false; 1682 1683 return true; 1684 } 1685 1686 static void 1687 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1688 { 1689 struct i915_wa wa = { 1690 .reg = reg 1691 }; 1692 1693 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1694 return; 1695 1696 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1697 return; 1698 1699 wa.reg.reg |= flags; 1700 _wa_add(wal, &wa); 1701 } 1702 1703 static void 1704 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1705 { 1706 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1707 } 1708 1709 static void gen9_whitelist_build(struct i915_wa_list *w) 1710 { 1711 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1712 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1713 1714 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1715 whitelist_reg(w, GEN8_CS_CHICKEN1); 1716 1717 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1718 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1719 1720 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1721 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1722 } 1723 1724 static void skl_whitelist_build(struct intel_engine_cs *engine) 1725 { 1726 struct i915_wa_list *w = &engine->whitelist; 1727 1728 if (engine->class != RENDER_CLASS) 1729 return; 1730 1731 gen9_whitelist_build(w); 1732 1733 /* WaDisableLSQCROPERFforOCL:skl */ 1734 whitelist_reg(w, GEN8_L3SQCREG4); 1735 } 1736 1737 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1738 { 1739 if (engine->class != RENDER_CLASS) 1740 return; 1741 1742 gen9_whitelist_build(&engine->whitelist); 1743 } 1744 1745 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1746 { 1747 struct i915_wa_list *w = &engine->whitelist; 1748 1749 if (engine->class != RENDER_CLASS) 1750 return; 1751 1752 gen9_whitelist_build(w); 1753 1754 /* WaDisableLSQCROPERFforOCL:kbl */ 1755 whitelist_reg(w, GEN8_L3SQCREG4); 1756 } 1757 1758 static void glk_whitelist_build(struct intel_engine_cs *engine) 1759 { 1760 struct i915_wa_list *w = &engine->whitelist; 1761 1762 if (engine->class != RENDER_CLASS) 1763 return; 1764 1765 gen9_whitelist_build(w); 1766 1767 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1768 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1769 } 1770 1771 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1772 { 1773 struct i915_wa_list *w = &engine->whitelist; 1774 1775 if (engine->class != RENDER_CLASS) 1776 return; 1777 1778 gen9_whitelist_build(w); 1779 1780 /* 1781 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1782 * 1783 * This covers 4 register which are next to one another : 1784 * - PS_INVOCATION_COUNT 1785 * - PS_INVOCATION_COUNT_UDW 1786 * - PS_DEPTH_COUNT 1787 * - PS_DEPTH_COUNT_UDW 1788 */ 1789 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1790 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1791 RING_FORCE_TO_NONPRIV_RANGE_4); 1792 } 1793 1794 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine) 1795 { 1796 struct i915_wa_list *w = &engine->whitelist; 1797 1798 if (engine->class != RENDER_CLASS) 1799 whitelist_reg_ext(w, 1800 RING_CTX_TIMESTAMP(engine->mmio_base), 1801 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1802 } 1803 1804 static void cml_whitelist_build(struct intel_engine_cs *engine) 1805 { 1806 allow_read_ctx_timestamp(engine); 1807 1808 cfl_whitelist_build(engine); 1809 } 1810 1811 static void icl_whitelist_build(struct intel_engine_cs *engine) 1812 { 1813 struct i915_wa_list *w = &engine->whitelist; 1814 1815 allow_read_ctx_timestamp(engine); 1816 1817 switch (engine->class) { 1818 case RENDER_CLASS: 1819 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1820 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1821 1822 /* WaAllowUMDToModifySamplerMode:icl */ 1823 whitelist_reg(w, GEN10_SAMPLER_MODE); 1824 1825 /* WaEnableStateCacheRedirectToCS:icl */ 1826 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1827 1828 /* 1829 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1830 * 1831 * This covers 4 register which are next to one another : 1832 * - PS_INVOCATION_COUNT 1833 * - PS_INVOCATION_COUNT_UDW 1834 * - PS_DEPTH_COUNT 1835 * - PS_DEPTH_COUNT_UDW 1836 */ 1837 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1838 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1839 RING_FORCE_TO_NONPRIV_RANGE_4); 1840 break; 1841 1842 case VIDEO_DECODE_CLASS: 1843 /* hucStatusRegOffset */ 1844 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1845 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1846 /* hucUKernelHdrInfoRegOffset */ 1847 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1848 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1849 /* hucStatus2RegOffset */ 1850 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1851 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1852 break; 1853 1854 default: 1855 break; 1856 } 1857 } 1858 1859 static void tgl_whitelist_build(struct intel_engine_cs *engine) 1860 { 1861 struct i915_wa_list *w = &engine->whitelist; 1862 1863 allow_read_ctx_timestamp(engine); 1864 1865 switch (engine->class) { 1866 case RENDER_CLASS: 1867 /* 1868 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 1869 * Wa_1408556865:tgl 1870 * 1871 * This covers 4 registers which are next to one another : 1872 * - PS_INVOCATION_COUNT 1873 * - PS_INVOCATION_COUNT_UDW 1874 * - PS_DEPTH_COUNT 1875 * - PS_DEPTH_COUNT_UDW 1876 */ 1877 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1878 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1879 RING_FORCE_TO_NONPRIV_RANGE_4); 1880 1881 /* 1882 * Wa_1808121037:tgl 1883 * Wa_14012131227:dg1 1884 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p 1885 */ 1886 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 1887 1888 /* Wa_1806527549:tgl */ 1889 whitelist_reg(w, HIZ_CHICKEN); 1890 break; 1891 default: 1892 break; 1893 } 1894 } 1895 1896 static void dg1_whitelist_build(struct intel_engine_cs *engine) 1897 { 1898 struct i915_wa_list *w = &engine->whitelist; 1899 1900 tgl_whitelist_build(engine); 1901 1902 /* GEN:BUG:1409280441:dg1 */ 1903 if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) && 1904 (engine->class == RENDER_CLASS || 1905 engine->class == COPY_ENGINE_CLASS)) 1906 whitelist_reg_ext(w, RING_ID(engine->mmio_base), 1907 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1908 } 1909 1910 static void xehpsdv_whitelist_build(struct intel_engine_cs *engine) 1911 { 1912 allow_read_ctx_timestamp(engine); 1913 } 1914 1915 static void dg2_whitelist_build(struct intel_engine_cs *engine) 1916 { 1917 struct i915_wa_list *w = &engine->whitelist; 1918 1919 allow_read_ctx_timestamp(engine); 1920 1921 switch (engine->class) { 1922 case RENDER_CLASS: 1923 /* 1924 * Wa_1507100340:dg2_g10 1925 * 1926 * This covers 4 registers which are next to one another : 1927 * - PS_INVOCATION_COUNT 1928 * - PS_INVOCATION_COUNT_UDW 1929 * - PS_DEPTH_COUNT 1930 * - PS_DEPTH_COUNT_UDW 1931 */ 1932 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 1933 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1934 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1935 RING_FORCE_TO_NONPRIV_RANGE_4); 1936 1937 break; 1938 default: 1939 break; 1940 } 1941 } 1942 1943 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 1944 { 1945 struct drm_i915_private *i915 = engine->i915; 1946 struct i915_wa_list *w = &engine->whitelist; 1947 1948 wa_init_start(w, "whitelist", engine->name); 1949 1950 if (IS_DG2(i915)) 1951 dg2_whitelist_build(engine); 1952 else if (IS_XEHPSDV(i915)) 1953 xehpsdv_whitelist_build(engine); 1954 else if (IS_DG1(i915)) 1955 dg1_whitelist_build(engine); 1956 else if (GRAPHICS_VER(i915) == 12) 1957 tgl_whitelist_build(engine); 1958 else if (GRAPHICS_VER(i915) == 11) 1959 icl_whitelist_build(engine); 1960 else if (IS_COMETLAKE(i915)) 1961 cml_whitelist_build(engine); 1962 else if (IS_COFFEELAKE(i915)) 1963 cfl_whitelist_build(engine); 1964 else if (IS_GEMINILAKE(i915)) 1965 glk_whitelist_build(engine); 1966 else if (IS_KABYLAKE(i915)) 1967 kbl_whitelist_build(engine); 1968 else if (IS_BROXTON(i915)) 1969 bxt_whitelist_build(engine); 1970 else if (IS_SKYLAKE(i915)) 1971 skl_whitelist_build(engine); 1972 else if (GRAPHICS_VER(i915) <= 8) 1973 ; 1974 else 1975 MISSING_CASE(GRAPHICS_VER(i915)); 1976 1977 wa_init_finish(w); 1978 } 1979 1980 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 1981 { 1982 const struct i915_wa_list *wal = &engine->whitelist; 1983 struct intel_uncore *uncore = engine->uncore; 1984 const u32 base = engine->mmio_base; 1985 struct i915_wa *wa; 1986 unsigned int i; 1987 1988 if (!wal->count) 1989 return; 1990 1991 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1992 intel_uncore_write(uncore, 1993 RING_FORCE_TO_NONPRIV(base, i), 1994 i915_mmio_reg_offset(wa->reg)); 1995 1996 /* And clear the rest just in case of garbage */ 1997 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 1998 intel_uncore_write(uncore, 1999 RING_FORCE_TO_NONPRIV(base, i), 2000 i915_mmio_reg_offset(RING_NOPID(base))); 2001 } 2002 2003 /* 2004 * engine_fake_wa_init(), a place holder to program the registers 2005 * which are not part of an official workaround defined by the 2006 * hardware team. 2007 * Adding programming of those register inside workaround will 2008 * allow utilizing wa framework to proper application and verification. 2009 */ 2010 static void 2011 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2012 { 2013 u8 mocs; 2014 2015 /* 2016 * RING_CMD_CCTL are need to be programed to un-cached 2017 * for memory writes and reads outputted by Command 2018 * Streamers on Gen12 onward platforms. 2019 */ 2020 if (GRAPHICS_VER(engine->i915) >= 12) { 2021 mocs = engine->gt->mocs.uc_index; 2022 wa_masked_field_set(wal, 2023 RING_CMD_CCTL(engine->mmio_base), 2024 CMD_CCTL_MOCS_MASK, 2025 CMD_CCTL_MOCS_OVERRIDE(mocs, mocs)); 2026 } 2027 } 2028 2029 static bool needs_wa_1308578152(struct intel_engine_cs *engine) 2030 { 2031 u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0); 2032 2033 return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0; 2034 } 2035 2036 static void 2037 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2038 { 2039 struct drm_i915_private *i915 = engine->i915; 2040 2041 if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 2042 /* Wa_14013392000:dg2_g11 */ 2043 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); 2044 2045 /* Wa_16011620976:dg2_g11 */ 2046 wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); 2047 } 2048 2049 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) || 2050 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 2051 /* Wa_14012419201:dg2 */ 2052 wa_masked_en(wal, GEN9_ROW_CHICKEN4, 2053 GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); 2054 } 2055 2056 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_C0) || 2057 IS_DG2_G11(engine->i915)) { 2058 /* 2059 * Wa_22012826095:dg2 2060 * Wa_22013059131:dg2 2061 */ 2062 wa_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, 2063 MAXREQS_PER_BANK, 2064 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); 2065 2066 /* Wa_22013059131:dg2 */ 2067 wa_write_or(wal, LSC_CHICKEN_BIT_0, 2068 FORCE_1_SUB_MESSAGE_PER_FRAGMENT); 2069 } 2070 2071 /* Wa_1308578152:dg2_g10 when first gslice is fused off */ 2072 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_C0) && 2073 needs_wa_1308578152(engine)) { 2074 wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON, 2075 GEN12_REPLAY_MODE_GRANULARITY); 2076 } 2077 2078 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || 2079 IS_DG2_G11(engine->i915)) { 2080 /* Wa_22013037850:dg2 */ 2081 wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, 2082 DISABLE_128B_EVICTION_COMMAND_UDW); 2083 2084 /* Wa_22012856258:dg2 */ 2085 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 2086 GEN12_DISABLE_READ_SUPPRESSION); 2087 2088 /* 2089 * Wa_22010960976:dg2 2090 * Wa_14013347512:dg2 2091 */ 2092 wa_masked_dis(wal, GEN12_HDC_CHICKEN0, 2093 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK); 2094 } 2095 2096 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 2097 /* 2098 * Wa_1608949956:dg2_g10 2099 * Wa_14010198302:dg2_g10 2100 */ 2101 wa_masked_en(wal, GEN8_ROW_CHICKEN, 2102 MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); 2103 2104 /* 2105 * Wa_14010918519:dg2_g10 2106 * 2107 * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, 2108 * so ignoring verification. 2109 */ 2110 wa_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, 2111 FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, 2112 0, false); 2113 } 2114 2115 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 2116 /* Wa_22010430635:dg2 */ 2117 wa_masked_en(wal, 2118 GEN9_ROW_CHICKEN4, 2119 GEN12_DISABLE_GRF_CLEAR); 2120 2121 /* Wa_14010648519:dg2 */ 2122 wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 2123 } 2124 2125 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) || 2126 IS_DG2_G11(engine->i915)) { 2127 /* Wa_22012654132:dg2 */ 2128 wa_add(wal, GEN10_CACHE_MODE_SS, 0, 2129 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), 2130 0 /* write-only, so skip validation */, 2131 true); 2132 } 2133 2134 /* Wa_14013202645:dg2 */ 2135 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_C0) || 2136 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) 2137 wa_write_or(wal, RT_CTRL, DIS_NULL_QUERY); 2138 2139 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2140 IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2141 /* 2142 * Wa_1607138336:tgl[a0],dg1[a0] 2143 * Wa_1607063988:tgl[a0],dg1[a0] 2144 */ 2145 wa_write_or(wal, 2146 GEN9_CTX_PREEMPT_REG, 2147 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 2148 } 2149 2150 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2151 /* 2152 * Wa_1606679103:tgl 2153 * (see also Wa_1606682166:icl) 2154 */ 2155 wa_write_or(wal, 2156 GEN7_SARCHKMD, 2157 GEN7_DISABLE_SAMPLER_PREFETCH); 2158 } 2159 2160 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || 2161 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2162 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ 2163 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 2164 2165 /* 2166 * Wa_1407928979:tgl A* 2167 * Wa_18011464164:tgl[B0+],dg1[B0+] 2168 * Wa_22010931296:tgl[B0+],dg1[B0+] 2169 * Wa_14010919138:rkl,dg1,adl-s,adl-p 2170 */ 2171 wa_write_or(wal, GEN7_FF_THREAD_MODE, 2172 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2173 2174 /* 2175 * Wa_1606700617:tgl,dg1,adl-p 2176 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p 2177 * Wa_14010826681:tgl,dg1,rkl,adl-p 2178 */ 2179 wa_masked_en(wal, 2180 GEN9_CS_DEBUG_MODE1, 2181 FF_DOP_CLOCK_GATE_DISABLE); 2182 } 2183 2184 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 2185 IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2186 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2187 /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */ 2188 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 2189 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 2190 2191 /* 2192 * Wa_1409085225:tgl 2193 * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p 2194 */ 2195 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 2196 } 2197 2198 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2199 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2200 /* 2201 * Wa_1607030317:tgl 2202 * Wa_1607186500:tgl 2203 * Wa_1607297627:tgl,rkl,dg1[a0] 2204 * 2205 * On TGL and RKL there are multiple entries for this WA in the 2206 * BSpec; some indicate this is an A0-only WA, others indicate 2207 * it applies to all steppings so we trust the "all steppings." 2208 * For DG1 this only applies to A0. 2209 */ 2210 wa_masked_en(wal, 2211 GEN6_RC_SLEEP_PSMI_CONTROL, 2212 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 2213 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 2214 } 2215 2216 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || 2217 IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { 2218 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ 2219 wa_masked_en(wal, 2220 GEN10_SAMPLER_MODE, 2221 ENABLE_SMALLPL); 2222 } 2223 2224 if (GRAPHICS_VER(i915) == 11) { 2225 /* This is not an Wa. Enable for better image quality */ 2226 wa_masked_en(wal, 2227 _3D_CHICKEN3, 2228 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 2229 2230 /* 2231 * Wa_1405543622:icl 2232 * Formerly known as WaGAPZPriorityScheme 2233 */ 2234 wa_write_or(wal, 2235 GEN8_GARBCNTL, 2236 GEN11_ARBITRATION_PRIO_ORDER_MASK); 2237 2238 /* 2239 * Wa_1604223664:icl 2240 * Formerly known as WaL3BankAddressHashing 2241 */ 2242 wa_write_clr_set(wal, 2243 GEN8_GARBCNTL, 2244 GEN11_HASH_CTRL_EXCL_MASK, 2245 GEN11_HASH_CTRL_EXCL_BIT0); 2246 wa_write_clr_set(wal, 2247 GEN11_GLBLINVL, 2248 GEN11_BANK_HASH_ADDR_EXCL_MASK, 2249 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 2250 2251 /* 2252 * Wa_1405733216:icl 2253 * Formerly known as WaDisableCleanEvicts 2254 */ 2255 wa_write_or(wal, 2256 GEN8_L3SQCREG4, 2257 GEN11_LQSC_CLEAN_EVICT_DISABLE); 2258 2259 /* Wa_1606682166:icl */ 2260 wa_write_or(wal, 2261 GEN7_SARCHKMD, 2262 GEN7_DISABLE_SAMPLER_PREFETCH); 2263 2264 /* Wa_1409178092:icl */ 2265 wa_write_clr_set(wal, 2266 GEN11_SCRATCH2, 2267 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 2268 0); 2269 2270 /* WaEnable32PlaneMode:icl */ 2271 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 2272 GEN11_ENABLE_32_PLANE_MODE); 2273 2274 /* 2275 * Wa_1408615072:icl,ehl (vsunit) 2276 * Wa_1407596294:icl,ehl (hsunit) 2277 */ 2278 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 2279 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 2280 2281 /* 2282 * Wa_1408767742:icl[a2..forever],ehl[all] 2283 * Wa_1605460711:icl[a0..c0] 2284 */ 2285 wa_write_or(wal, 2286 GEN7_FF_THREAD_MODE, 2287 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2288 2289 /* Wa_22010271021 */ 2290 wa_masked_en(wal, 2291 GEN9_CS_DEBUG_MODE1, 2292 FF_DOP_CLOCK_GATE_DISABLE); 2293 } 2294 2295 if (IS_GRAPHICS_VER(i915, 9, 12)) { 2296 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ 2297 wa_masked_en(wal, 2298 GEN7_FF_SLICE_CS_CHICKEN1, 2299 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 2300 } 2301 2302 if (IS_SKYLAKE(i915) || 2303 IS_KABYLAKE(i915) || 2304 IS_COFFEELAKE(i915) || 2305 IS_COMETLAKE(i915)) { 2306 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 2307 wa_write_or(wal, 2308 GEN8_GARBCNTL, 2309 GEN9_GAPS_TSV_CREDIT_DISABLE); 2310 } 2311 2312 if (IS_BROXTON(i915)) { 2313 /* WaDisablePooledEuLoadBalancingFix:bxt */ 2314 wa_masked_en(wal, 2315 FF_SLICE_CS_CHICKEN2, 2316 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 2317 } 2318 2319 if (GRAPHICS_VER(i915) == 9) { 2320 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 2321 wa_masked_en(wal, 2322 GEN9_CSFE_CHICKEN1_RCS, 2323 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 2324 2325 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 2326 wa_write_or(wal, 2327 BDW_SCRATCH1, 2328 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 2329 2330 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 2331 if (IS_GEN9_LP(i915)) 2332 wa_write_clr_set(wal, 2333 GEN8_L3SQCREG1, 2334 L3_PRIO_CREDITS_MASK, 2335 L3_GENERAL_PRIO_CREDITS(62) | 2336 L3_HIGH_PRIO_CREDITS(2)); 2337 2338 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 2339 wa_write_or(wal, 2340 GEN8_L3SQCREG4, 2341 GEN8_LQSC_FLUSH_COHERENT_LINES); 2342 2343 /* Disable atomics in L3 to prevent unrecoverable hangs */ 2344 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, 2345 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2346 wa_write_clr_set(wal, GEN8_L3SQCREG4, 2347 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2348 wa_write_clr_set(wal, GEN9_SCRATCH1, 2349 EVICTION_PERF_FIX_ENABLE, 0); 2350 } 2351 2352 if (IS_HASWELL(i915)) { 2353 /* WaSampleCChickenBitEnable:hsw */ 2354 wa_masked_en(wal, 2355 HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 2356 2357 wa_masked_dis(wal, 2358 CACHE_MODE_0_GEN7, 2359 /* enable HiZ Raw Stall Optimization */ 2360 HIZ_RAW_STALL_OPT_DISABLE); 2361 } 2362 2363 if (IS_VALLEYVIEW(i915)) { 2364 /* WaDisableEarlyCull:vlv */ 2365 wa_masked_en(wal, 2366 _3D_CHICKEN3, 2367 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2368 2369 /* 2370 * WaVSThreadDispatchOverride:ivb,vlv 2371 * 2372 * This actually overrides the dispatch 2373 * mode for all thread types. 2374 */ 2375 wa_write_clr_set(wal, 2376 GEN7_FF_THREAD_MODE, 2377 GEN7_FF_SCHED_MASK, 2378 GEN7_FF_TS_SCHED_HW | 2379 GEN7_FF_VS_SCHED_HW | 2380 GEN7_FF_DS_SCHED_HW); 2381 2382 /* WaPsdDispatchEnable:vlv */ 2383 /* WaDisablePSDDualDispatchEnable:vlv */ 2384 wa_masked_en(wal, 2385 GEN7_HALF_SLICE_CHICKEN1, 2386 GEN7_MAX_PS_THREAD_DEP | 2387 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2388 } 2389 2390 if (IS_IVYBRIDGE(i915)) { 2391 /* WaDisableEarlyCull:ivb */ 2392 wa_masked_en(wal, 2393 _3D_CHICKEN3, 2394 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2395 2396 if (0) { /* causes HiZ corruption on ivb:gt1 */ 2397 /* enable HiZ Raw Stall Optimization */ 2398 wa_masked_dis(wal, 2399 CACHE_MODE_0_GEN7, 2400 HIZ_RAW_STALL_OPT_DISABLE); 2401 } 2402 2403 /* 2404 * WaVSThreadDispatchOverride:ivb,vlv 2405 * 2406 * This actually overrides the dispatch 2407 * mode for all thread types. 2408 */ 2409 wa_write_clr_set(wal, 2410 GEN7_FF_THREAD_MODE, 2411 GEN7_FF_SCHED_MASK, 2412 GEN7_FF_TS_SCHED_HW | 2413 GEN7_FF_VS_SCHED_HW | 2414 GEN7_FF_DS_SCHED_HW); 2415 2416 /* WaDisablePSDDualDispatchEnable:ivb */ 2417 if (IS_IVB_GT1(i915)) 2418 wa_masked_en(wal, 2419 GEN7_HALF_SLICE_CHICKEN1, 2420 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2421 } 2422 2423 if (GRAPHICS_VER(i915) == 7) { 2424 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 2425 wa_masked_en(wal, 2426 GFX_MODE_GEN7, 2427 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 2428 2429 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 2430 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 2431 2432 /* 2433 * BSpec says this must be set, even though 2434 * WaDisable4x2SubspanOptimization:ivb,hsw 2435 * WaDisable4x2SubspanOptimization isn't listed for VLV. 2436 */ 2437 wa_masked_en(wal, 2438 CACHE_MODE_1, 2439 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 2440 2441 /* 2442 * BSpec recommends 8x4 when MSAA is used, 2443 * however in practice 16x4 seems fastest. 2444 * 2445 * Note that PS/WM thread counts depend on the WIZ hashing 2446 * disable bit, which we don't touch here, but it's good 2447 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2448 */ 2449 wa_masked_field_set(wal, 2450 GEN7_GT_MODE, 2451 GEN6_WIZ_HASHING_MASK, 2452 GEN6_WIZ_HASHING_16x4); 2453 } 2454 2455 if (IS_GRAPHICS_VER(i915, 6, 7)) 2456 /* 2457 * We need to disable the AsyncFlip performance optimisations in 2458 * order to use MI_WAIT_FOR_EVENT within the CS. It should 2459 * already be programmed to '1' on all products. 2460 * 2461 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 2462 */ 2463 wa_masked_en(wal, 2464 MI_MODE, 2465 ASYNC_FLIP_PERF_DISABLE); 2466 2467 if (GRAPHICS_VER(i915) == 6) { 2468 /* 2469 * Required for the hardware to program scanline values for 2470 * waiting 2471 * WaEnableFlushTlbInvalidationMode:snb 2472 */ 2473 wa_masked_en(wal, 2474 GFX_MODE, 2475 GFX_TLB_INVALIDATE_EXPLICIT); 2476 2477 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 2478 wa_masked_en(wal, 2479 _3D_CHICKEN, 2480 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 2481 2482 wa_masked_en(wal, 2483 _3D_CHICKEN3, 2484 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 2485 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 2486 /* 2487 * Bspec says: 2488 * "This bit must be set if 3DSTATE_CLIP clip mode is set 2489 * to normal and 3DSTATE_SF number of SF output attributes 2490 * is more than 16." 2491 */ 2492 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 2493 2494 /* 2495 * BSpec recommends 8x4 when MSAA is used, 2496 * however in practice 16x4 seems fastest. 2497 * 2498 * Note that PS/WM thread counts depend on the WIZ hashing 2499 * disable bit, which we don't touch here, but it's good 2500 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2501 */ 2502 wa_masked_field_set(wal, 2503 GEN6_GT_MODE, 2504 GEN6_WIZ_HASHING_MASK, 2505 GEN6_WIZ_HASHING_16x4); 2506 2507 /* WaDisable_RenderCache_OperationalFlush:snb */ 2508 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 2509 2510 /* 2511 * From the Sandybridge PRM, volume 1 part 3, page 24: 2512 * "If this bit is set, STCunit will have LRA as replacement 2513 * policy. [...] This bit must be reset. LRA replacement 2514 * policy is not supported." 2515 */ 2516 wa_masked_dis(wal, 2517 CACHE_MODE_0, 2518 CM0_STC_EVICT_DISABLE_LRA_SNB); 2519 } 2520 2521 if (IS_GRAPHICS_VER(i915, 4, 6)) 2522 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2523 wa_add(wal, MI_MODE, 2524 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2525 /* XXX bit doesn't stick on Broadwater */ 2526 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); 2527 2528 if (GRAPHICS_VER(i915) == 4) 2529 /* 2530 * Disable CONSTANT_BUFFER before it is loaded from the context 2531 * image. For as it is loaded, it is executed and the stored 2532 * address may no longer be valid, leading to a GPU hang. 2533 * 2534 * This imposes the requirement that userspace reload their 2535 * CONSTANT_BUFFER on every batch, fortunately a requirement 2536 * they are already accustomed to from before contexts were 2537 * enabled. 2538 */ 2539 wa_add(wal, ECOSKPD, 2540 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2541 0 /* XXX bit doesn't stick on Broadwater */, 2542 true); 2543 } 2544 2545 static void 2546 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2547 { 2548 struct drm_i915_private *i915 = engine->i915; 2549 2550 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2551 if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { 2552 wa_write(wal, 2553 RING_SEMA_WAIT_POLL(engine->mmio_base), 2554 1); 2555 } 2556 } 2557 2558 static void 2559 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2560 { 2561 if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4)) 2562 return; 2563 2564 engine_fake_wa_init(engine, wal); 2565 2566 if (engine->class == RENDER_CLASS) 2567 rcs_engine_wa_init(engine, wal); 2568 else 2569 xcs_engine_wa_init(engine, wal); 2570 } 2571 2572 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 2573 { 2574 struct i915_wa_list *wal = &engine->wa_list; 2575 2576 if (GRAPHICS_VER(engine->i915) < 4) 2577 return; 2578 2579 wa_init_start(wal, "engine", engine->name); 2580 engine_init_workarounds(engine, wal); 2581 wa_init_finish(wal); 2582 } 2583 2584 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 2585 { 2586 wa_list_apply(engine->gt, &engine->wa_list); 2587 } 2588 2589 static const struct i915_range mcr_ranges_gen8[] = { 2590 { .start = 0x5500, .end = 0x55ff }, 2591 { .start = 0x7000, .end = 0x7fff }, 2592 { .start = 0x9400, .end = 0x97ff }, 2593 { .start = 0xb000, .end = 0xb3ff }, 2594 { .start = 0xe000, .end = 0xe7ff }, 2595 {}, 2596 }; 2597 2598 static const struct i915_range mcr_ranges_gen12[] = { 2599 { .start = 0x8150, .end = 0x815f }, 2600 { .start = 0x9520, .end = 0x955f }, 2601 { .start = 0xb100, .end = 0xb3ff }, 2602 { .start = 0xde80, .end = 0xe8ff }, 2603 { .start = 0x24a00, .end = 0x24a7f }, 2604 {}, 2605 }; 2606 2607 static const struct i915_range mcr_ranges_xehp[] = { 2608 { .start = 0x4000, .end = 0x4aff }, 2609 { .start = 0x5200, .end = 0x52ff }, 2610 { .start = 0x5400, .end = 0x7fff }, 2611 { .start = 0x8140, .end = 0x815f }, 2612 { .start = 0x8c80, .end = 0x8dff }, 2613 { .start = 0x94d0, .end = 0x955f }, 2614 { .start = 0x9680, .end = 0x96ff }, 2615 { .start = 0xb000, .end = 0xb3ff }, 2616 { .start = 0xc800, .end = 0xcfff }, 2617 { .start = 0xd800, .end = 0xd8ff }, 2618 { .start = 0xdc00, .end = 0xffff }, 2619 { .start = 0x17000, .end = 0x17fff }, 2620 { .start = 0x24a00, .end = 0x24a7f }, 2621 {}, 2622 }; 2623 2624 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 2625 { 2626 const struct i915_range *mcr_ranges; 2627 int i; 2628 2629 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 2630 mcr_ranges = mcr_ranges_xehp; 2631 else if (GRAPHICS_VER(i915) >= 12) 2632 mcr_ranges = mcr_ranges_gen12; 2633 else if (GRAPHICS_VER(i915) >= 8) 2634 mcr_ranges = mcr_ranges_gen8; 2635 else 2636 return false; 2637 2638 /* 2639 * Registers in these ranges are affected by the MCR selector 2640 * which only controls CPU initiated MMIO. Routing does not 2641 * work for CS access so we cannot verify them on this path. 2642 */ 2643 for (i = 0; mcr_ranges[i].start; i++) 2644 if (offset >= mcr_ranges[i].start && 2645 offset <= mcr_ranges[i].end) 2646 return true; 2647 2648 return false; 2649 } 2650 2651 static int 2652 wa_list_srm(struct i915_request *rq, 2653 const struct i915_wa_list *wal, 2654 struct i915_vma *vma) 2655 { 2656 struct drm_i915_private *i915 = rq->engine->i915; 2657 unsigned int i, count = 0; 2658 const struct i915_wa *wa; 2659 u32 srm, *cs; 2660 2661 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 2662 if (GRAPHICS_VER(i915) >= 8) 2663 srm++; 2664 2665 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2666 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 2667 count++; 2668 } 2669 2670 cs = intel_ring_begin(rq, 4 * count); 2671 if (IS_ERR(cs)) 2672 return PTR_ERR(cs); 2673 2674 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2675 u32 offset = i915_mmio_reg_offset(wa->reg); 2676 2677 if (mcr_range(i915, offset)) 2678 continue; 2679 2680 *cs++ = srm; 2681 *cs++ = offset; 2682 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 2683 *cs++ = 0; 2684 } 2685 intel_ring_advance(rq, cs); 2686 2687 return 0; 2688 } 2689 2690 static int engine_wa_list_verify(struct intel_context *ce, 2691 const struct i915_wa_list * const wal, 2692 const char *from) 2693 { 2694 const struct i915_wa *wa; 2695 struct i915_request *rq; 2696 struct i915_vma *vma; 2697 struct i915_gem_ww_ctx ww; 2698 unsigned int i; 2699 u32 *results; 2700 int err; 2701 2702 if (!wal->count) 2703 return 0; 2704 2705 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 2706 wal->count * sizeof(u32)); 2707 if (IS_ERR(vma)) 2708 return PTR_ERR(vma); 2709 2710 intel_engine_pm_get(ce->engine); 2711 i915_gem_ww_ctx_init(&ww, false); 2712 retry: 2713 err = i915_gem_object_lock(vma->obj, &ww); 2714 if (err == 0) 2715 err = intel_context_pin_ww(ce, &ww); 2716 if (err) 2717 goto err_pm; 2718 2719 err = i915_vma_pin_ww(vma, &ww, 0, 0, 2720 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 2721 if (err) 2722 goto err_unpin; 2723 2724 rq = i915_request_create(ce); 2725 if (IS_ERR(rq)) { 2726 err = PTR_ERR(rq); 2727 goto err_vma; 2728 } 2729 2730 err = i915_request_await_object(rq, vma->obj, true); 2731 if (err == 0) 2732 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 2733 if (err == 0) 2734 err = wa_list_srm(rq, wal, vma); 2735 2736 i915_request_get(rq); 2737 if (err) 2738 i915_request_set_error_once(rq, err); 2739 i915_request_add(rq); 2740 2741 if (err) 2742 goto err_rq; 2743 2744 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 2745 err = -ETIME; 2746 goto err_rq; 2747 } 2748 2749 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 2750 if (IS_ERR(results)) { 2751 err = PTR_ERR(results); 2752 goto err_rq; 2753 } 2754 2755 err = 0; 2756 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2757 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 2758 continue; 2759 2760 if (!wa_verify(wa, results[i], wal->name, from)) 2761 err = -ENXIO; 2762 } 2763 2764 i915_gem_object_unpin_map(vma->obj); 2765 2766 err_rq: 2767 i915_request_put(rq); 2768 err_vma: 2769 i915_vma_unpin(vma); 2770 err_unpin: 2771 intel_context_unpin(ce); 2772 err_pm: 2773 if (err == -EDEADLK) { 2774 err = i915_gem_ww_ctx_backoff(&ww); 2775 if (!err) 2776 goto retry; 2777 } 2778 i915_gem_ww_ctx_fini(&ww); 2779 intel_engine_pm_put(ce->engine); 2780 i915_vma_put(vma); 2781 return err; 2782 } 2783 2784 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 2785 const char *from) 2786 { 2787 return engine_wa_list_verify(engine->kernel_context, 2788 &engine->wa_list, 2789 from); 2790 } 2791 2792 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2793 #include "selftest_workarounds.c" 2794 #endif 2795