xref: /openbmc/linux/drivers/clk/at91/dt-compat.c (revision c4a7b9b5)
1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/clk/at91_pmc.h>
4 #include <linux/of.h>
5 #include <linux/mfd/syscon.h>
6 #include <linux/regmap.h>
7 #include <linux/slab.h>
8 
9 #include "pmc.h"
10 
11 #define MASTER_SOURCE_MAX	4
12 
13 #define PERIPHERAL_AT91RM9200	0
14 #define PERIPHERAL_AT91SAM9X5	1
15 
16 #define PERIPHERAL_MAX		64
17 
18 #define PERIPHERAL_ID_MIN	2
19 
20 #define PROG_SOURCE_MAX		5
21 #define PROG_ID_MAX		7
22 
23 #define SYSTEM_MAX_ID		31
24 
25 #define GCK_INDEX_DT_AUDIO_PLL	5
26 
27 static DEFINE_SPINLOCK(mck_lock);
28 
29 #ifdef CONFIG_HAVE_AT91_AUDIO_PLL
30 static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)
31 {
32 	struct clk_hw *hw;
33 	const char *name = np->name;
34 	const char *parent_name;
35 	struct regmap *regmap;
36 	struct device_node *parent_np;
37 
38 	parent_np = of_get_parent(np);
39 	regmap = syscon_node_to_regmap(parent_np);
40 	of_node_put(parent_np);
41 	if (IS_ERR(regmap))
42 		return;
43 
44 	parent_name = of_clk_get_parent_name(np, 0);
45 
46 	hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name);
47 	if (IS_ERR(hw))
48 		return;
49 
50 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
51 }
52 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup,
53 	       "atmel,sama5d2-clk-audio-pll-frac",
54 	       of_sama5d2_clk_audio_pll_frac_setup);
55 
56 static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
57 {
58 	struct clk_hw *hw;
59 	const char *name = np->name;
60 	const char *parent_name;
61 	struct regmap *regmap;
62 	struct device_node *parent_np;
63 
64 	parent_np = of_get_parent(np);
65 	regmap = syscon_node_to_regmap(parent_np);
66 	of_node_put(parent_np);
67 	if (IS_ERR(regmap))
68 		return;
69 
70 	parent_name = of_clk_get_parent_name(np, 0);
71 
72 	hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name);
73 	if (IS_ERR(hw))
74 		return;
75 
76 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
77 }
78 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup,
79 	       "atmel,sama5d2-clk-audio-pll-pad",
80 	       of_sama5d2_clk_audio_pll_pad_setup);
81 
82 static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
83 {
84 	struct clk_hw *hw;
85 	const char *name = np->name;
86 	const char *parent_name;
87 	struct regmap *regmap;
88 	struct device_node *parent_np;
89 
90 	parent_np = of_get_parent(np);
91 	regmap = syscon_node_to_regmap(parent_np);
92 	of_node_put(parent_np);
93 	if (IS_ERR(regmap))
94 		return;
95 
96 	parent_name = of_clk_get_parent_name(np, 0);
97 
98 	hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name);
99 	if (IS_ERR(hw))
100 		return;
101 
102 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
103 }
104 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup,
105 	       "atmel,sama5d2-clk-audio-pll-pmc",
106 	       of_sama5d2_clk_audio_pll_pmc_setup);
107 #endif /* CONFIG_HAVE_AT91_AUDIO_PLL */
108 
109 static const struct clk_pcr_layout dt_pcr_layout = {
110 	.offset = 0x10c,
111 	.cmd = BIT(12),
112 	.pid_mask = GENMASK(5, 0),
113 	.div_mask = GENMASK(17, 16),
114 	.gckcss_mask = GENMASK(10, 8),
115 };
116 
117 #ifdef CONFIG_HAVE_AT91_GENERATED_CLK
118 #define GENERATED_SOURCE_MAX	6
119 
120 #define GCK_ID_I2S0		54
121 #define GCK_ID_I2S1		55
122 #define GCK_ID_CLASSD		59
123 
124 static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
125 {
126 	int num;
127 	u32 id;
128 	const char *name;
129 	struct clk_hw *hw;
130 	unsigned int num_parents;
131 	const char *parent_names[GENERATED_SOURCE_MAX];
132 	struct device_node *gcknp, *parent_np;
133 	struct clk_range range = CLK_RANGE(0, 0);
134 	struct regmap *regmap;
135 
136 	num_parents = of_clk_get_parent_count(np);
137 	if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
138 		return;
139 
140 	of_clk_parent_fill(np, parent_names, num_parents);
141 
142 	num = of_get_child_count(np);
143 	if (!num || num > PERIPHERAL_MAX)
144 		return;
145 
146 	parent_np = of_get_parent(np);
147 	regmap = syscon_node_to_regmap(parent_np);
148 	of_node_put(parent_np);
149 	if (IS_ERR(regmap))
150 		return;
151 
152 	for_each_child_of_node(np, gcknp) {
153 		int chg_pid = INT_MIN;
154 
155 		if (of_property_read_u32(gcknp, "reg", &id))
156 			continue;
157 
158 		if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
159 			continue;
160 
161 		if (of_property_read_string(np, "clock-output-names", &name))
162 			name = gcknp->name;
163 
164 		of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
165 				      &range);
166 
167 		if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&
168 		    (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||
169 		     id == GCK_ID_CLASSD))
170 			chg_pid = GCK_INDEX_DT_AUDIO_PLL;
171 
172 		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
173 						 &dt_pcr_layout, name,
174 						 parent_names, NULL,
175 						 num_parents, id, &range,
176 						 chg_pid);
177 		if (IS_ERR(hw))
178 			continue;
179 
180 		of_clk_add_hw_provider(gcknp, of_clk_hw_simple_get, hw);
181 	}
182 }
183 CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated",
184 	       of_sama5d2_clk_generated_setup);
185 #endif /* CONFIG_HAVE_AT91_GENERATED_CLK */
186 
187 #ifdef CONFIG_HAVE_AT91_H32MX
188 static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
189 {
190 	struct clk_hw *hw;
191 	const char *name = np->name;
192 	const char *parent_name;
193 	struct regmap *regmap;
194 	struct device_node *parent_np;
195 
196 	parent_np = of_get_parent(np);
197 	regmap = syscon_node_to_regmap(parent_np);
198 	of_node_put(parent_np);
199 	if (IS_ERR(regmap))
200 		return;
201 
202 	parent_name = of_clk_get_parent_name(np, 0);
203 
204 	hw = at91_clk_register_h32mx(regmap, name, parent_name);
205 	if (IS_ERR(hw))
206 		return;
207 
208 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
209 }
210 CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx",
211 	       of_sama5d4_clk_h32mx_setup);
212 #endif /* CONFIG_HAVE_AT91_H32MX */
213 
214 #ifdef CONFIG_HAVE_AT91_I2S_MUX_CLK
215 #define	I2S_BUS_NR	2
216 
217 static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np)
218 {
219 	struct regmap *regmap_sfr;
220 	u8 bus_id;
221 	const char *parent_names[2];
222 	struct device_node *i2s_mux_np;
223 	struct clk_hw *hw;
224 	int ret;
225 
226 	regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
227 	if (IS_ERR(regmap_sfr))
228 		return;
229 
230 	for_each_child_of_node(np, i2s_mux_np) {
231 		if (of_property_read_u8(i2s_mux_np, "reg", &bus_id))
232 			continue;
233 
234 		if (bus_id > I2S_BUS_NR)
235 			continue;
236 
237 		ret = of_clk_parent_fill(i2s_mux_np, parent_names, 2);
238 		if (ret != 2)
239 			continue;
240 
241 		hw = at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name,
242 					       parent_names, 2, bus_id);
243 		if (IS_ERR(hw))
244 			continue;
245 
246 		of_clk_add_hw_provider(i2s_mux_np, of_clk_hw_simple_get, hw);
247 	}
248 }
249 CLK_OF_DECLARE(sama5d2_clk_i2s_mux, "atmel,sama5d2-clk-i2s-mux",
250 	       of_sama5d2_clk_i2s_mux_setup);
251 #endif /* CONFIG_HAVE_AT91_I2S_MUX_CLK */
252 
253 static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
254 {
255 	struct clk_hw *hw;
256 	const char *name = np->name;
257 	const char *parent_name;
258 	struct regmap *regmap;
259 	bool bypass;
260 	struct device_node *parent_np;
261 
262 	of_property_read_string(np, "clock-output-names", &name);
263 	bypass = of_property_read_bool(np, "atmel,osc-bypass");
264 	parent_name = of_clk_get_parent_name(np, 0);
265 
266 	parent_np = of_get_parent(np);
267 	regmap = syscon_node_to_regmap(parent_np);
268 	of_node_put(parent_np);
269 	if (IS_ERR(regmap))
270 		return;
271 
272 	hw = at91_clk_register_main_osc(regmap, name, parent_name, bypass);
273 	if (IS_ERR(hw))
274 		return;
275 
276 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
277 }
278 CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc",
279 	       of_at91rm9200_clk_main_osc_setup);
280 
281 static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np)
282 {
283 	struct clk_hw *hw;
284 	u32 frequency = 0;
285 	u32 accuracy = 0;
286 	const char *name = np->name;
287 	struct regmap *regmap;
288 	struct device_node *parent_np;
289 
290 	of_property_read_string(np, "clock-output-names", &name);
291 	of_property_read_u32(np, "clock-frequency", &frequency);
292 	of_property_read_u32(np, "clock-accuracy", &accuracy);
293 
294 	parent_np = of_get_parent(np);
295 	regmap = syscon_node_to_regmap(parent_np);
296 	of_node_put(parent_np);
297 	if (IS_ERR(regmap))
298 		return;
299 
300 	hw = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy);
301 	if (IS_ERR(hw))
302 		return;
303 
304 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
305 }
306 CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc",
307 	       of_at91sam9x5_clk_main_rc_osc_setup);
308 
309 static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
310 {
311 	struct clk_hw *hw;
312 	const char *parent_name;
313 	const char *name = np->name;
314 	struct regmap *regmap;
315 	struct device_node *parent_np;
316 
317 	parent_name = of_clk_get_parent_name(np, 0);
318 	of_property_read_string(np, "clock-output-names", &name);
319 
320 	parent_np = of_get_parent(np);
321 	regmap = syscon_node_to_regmap(parent_np);
322 	of_node_put(parent_np);
323 	if (IS_ERR(regmap))
324 		return;
325 
326 	hw = at91_clk_register_rm9200_main(regmap, name, parent_name);
327 	if (IS_ERR(hw))
328 		return;
329 
330 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
331 }
332 CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
333 	       of_at91rm9200_clk_main_setup);
334 
335 static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
336 {
337 	struct clk_hw *hw;
338 	const char *parent_names[2];
339 	unsigned int num_parents;
340 	const char *name = np->name;
341 	struct regmap *regmap;
342 	struct device_node *parent_np;
343 
344 	num_parents = of_clk_get_parent_count(np);
345 	if (num_parents == 0 || num_parents > 2)
346 		return;
347 
348 	of_clk_parent_fill(np, parent_names, num_parents);
349 	parent_np = of_get_parent(np);
350 	regmap = syscon_node_to_regmap(parent_np);
351 	of_node_put(parent_np);
352 	if (IS_ERR(regmap))
353 		return;
354 
355 	of_property_read_string(np, "clock-output-names", &name);
356 
357 	hw = at91_clk_register_sam9x5_main(regmap, name, parent_names,
358 					   num_parents);
359 	if (IS_ERR(hw))
360 		return;
361 
362 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
363 }
364 CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main",
365 	       of_at91sam9x5_clk_main_setup);
366 
367 static struct clk_master_characteristics * __init
368 of_at91_clk_master_get_characteristics(struct device_node *np)
369 {
370 	struct clk_master_characteristics *characteristics;
371 
372 	characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
373 	if (!characteristics)
374 		return NULL;
375 
376 	if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output))
377 		goto out_free_characteristics;
378 
379 	of_property_read_u32_array(np, "atmel,clk-divisors",
380 				   characteristics->divisors, 4);
381 
382 	characteristics->have_div3_pres =
383 		of_property_read_bool(np, "atmel,master-clk-have-div3-pres");
384 
385 	return characteristics;
386 
387 out_free_characteristics:
388 	kfree(characteristics);
389 	return NULL;
390 }
391 
392 static void __init
393 of_at91_clk_master_setup(struct device_node *np,
394 			 const struct clk_master_layout *layout)
395 {
396 	struct clk_hw *hw;
397 	unsigned int num_parents;
398 	const char *parent_names[MASTER_SOURCE_MAX];
399 	const char *name = np->name;
400 	struct clk_master_characteristics *characteristics;
401 	struct regmap *regmap;
402 	struct device_node *parent_np;
403 
404 	num_parents = of_clk_get_parent_count(np);
405 	if (num_parents == 0 || num_parents > MASTER_SOURCE_MAX)
406 		return;
407 
408 	of_clk_parent_fill(np, parent_names, num_parents);
409 
410 	of_property_read_string(np, "clock-output-names", &name);
411 
412 	characteristics = of_at91_clk_master_get_characteristics(np);
413 	if (!characteristics)
414 		return;
415 
416 	parent_np = of_get_parent(np);
417 	regmap = syscon_node_to_regmap(parent_np);
418 	of_node_put(parent_np);
419 	if (IS_ERR(regmap))
420 		return;
421 
422 	hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents,
423 					   parent_names, layout,
424 					   characteristics, &mck_lock);
425 	if (IS_ERR(hw))
426 		goto out_free_characteristics;
427 
428 	hw = at91_clk_register_master_div(regmap, name, "masterck_pres",
429 					  layout, characteristics,
430 					  &mck_lock, CLK_SET_RATE_GATE, 0);
431 	if (IS_ERR(hw))
432 		goto out_free_characteristics;
433 
434 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
435 	return;
436 
437 out_free_characteristics:
438 	kfree(characteristics);
439 }
440 
441 static void __init of_at91rm9200_clk_master_setup(struct device_node *np)
442 {
443 	of_at91_clk_master_setup(np, &at91rm9200_master_layout);
444 }
445 CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master",
446 	       of_at91rm9200_clk_master_setup);
447 
448 static void __init of_at91sam9x5_clk_master_setup(struct device_node *np)
449 {
450 	of_at91_clk_master_setup(np, &at91sam9x5_master_layout);
451 }
452 CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master",
453 	       of_at91sam9x5_clk_master_setup);
454 
455 static void __init
456 of_at91_clk_periph_setup(struct device_node *np, u8 type)
457 {
458 	int num;
459 	u32 id;
460 	struct clk_hw *hw;
461 	const char *parent_name;
462 	const char *name;
463 	struct device_node *periphclknp;
464 	struct regmap *regmap;
465 	struct device_node *parent_np;
466 
467 	parent_name = of_clk_get_parent_name(np, 0);
468 	if (!parent_name)
469 		return;
470 
471 	num = of_get_child_count(np);
472 	if (!num || num > PERIPHERAL_MAX)
473 		return;
474 
475 	parent_np = of_get_parent(np);
476 	regmap = syscon_node_to_regmap(parent_np);
477 	of_node_put(parent_np);
478 	if (IS_ERR(regmap))
479 		return;
480 
481 	for_each_child_of_node(np, periphclknp) {
482 		if (of_property_read_u32(periphclknp, "reg", &id))
483 			continue;
484 
485 		if (id >= PERIPHERAL_MAX)
486 			continue;
487 
488 		if (of_property_read_string(np, "clock-output-names", &name))
489 			name = periphclknp->name;
490 
491 		if (type == PERIPHERAL_AT91RM9200) {
492 			hw = at91_clk_register_peripheral(regmap, name,
493 							  parent_name, id);
494 		} else {
495 			struct clk_range range = CLK_RANGE(0, 0);
496 
497 			of_at91_get_clk_range(periphclknp,
498 					      "atmel,clk-output-range",
499 					      &range);
500 
501 			hw = at91_clk_register_sam9x5_peripheral(regmap,
502 								 &pmc_pcr_lock,
503 								 &dt_pcr_layout,
504 								 name,
505 								 parent_name,
506 								 id, &range,
507 								 INT_MIN);
508 		}
509 
510 		if (IS_ERR(hw))
511 			continue;
512 
513 		of_clk_add_hw_provider(periphclknp, of_clk_hw_simple_get, hw);
514 	}
515 }
516 
517 static void __init of_at91rm9200_clk_periph_setup(struct device_node *np)
518 {
519 	of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200);
520 }
521 CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral",
522 	       of_at91rm9200_clk_periph_setup);
523 
524 static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np)
525 {
526 	of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5);
527 }
528 CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral",
529 	       of_at91sam9x5_clk_periph_setup);
530 
531 static struct clk_pll_characteristics * __init
532 of_at91_clk_pll_get_characteristics(struct device_node *np)
533 {
534 	int i;
535 	int offset;
536 	u32 tmp;
537 	int num_output;
538 	u32 num_cells;
539 	struct clk_range input;
540 	struct clk_range *output;
541 	u8 *out = NULL;
542 	u16 *icpll = NULL;
543 	struct clk_pll_characteristics *characteristics;
544 
545 	if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
546 		return NULL;
547 
548 	if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
549 				 &num_cells))
550 		return NULL;
551 
552 	if (num_cells < 2 || num_cells > 4)
553 		return NULL;
554 
555 	if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
556 		return NULL;
557 	num_output = tmp / (sizeof(u32) * num_cells);
558 
559 	characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
560 	if (!characteristics)
561 		return NULL;
562 
563 	output = kcalloc(num_output, sizeof(*output), GFP_KERNEL);
564 	if (!output)
565 		goto out_free_characteristics;
566 
567 	if (num_cells > 2) {
568 		out = kcalloc(num_output, sizeof(*out), GFP_KERNEL);
569 		if (!out)
570 			goto out_free_output;
571 	}
572 
573 	if (num_cells > 3) {
574 		icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL);
575 		if (!icpll)
576 			goto out_free_output;
577 	}
578 
579 	for (i = 0; i < num_output; i++) {
580 		offset = i * num_cells;
581 		if (of_property_read_u32_index(np,
582 					       "atmel,pll-clk-output-ranges",
583 					       offset, &tmp))
584 			goto out_free_output;
585 		output[i].min = tmp;
586 		if (of_property_read_u32_index(np,
587 					       "atmel,pll-clk-output-ranges",
588 					       offset + 1, &tmp))
589 			goto out_free_output;
590 		output[i].max = tmp;
591 
592 		if (num_cells == 2)
593 			continue;
594 
595 		if (of_property_read_u32_index(np,
596 					       "atmel,pll-clk-output-ranges",
597 					       offset + 2, &tmp))
598 			goto out_free_output;
599 		out[i] = tmp;
600 
601 		if (num_cells == 3)
602 			continue;
603 
604 		if (of_property_read_u32_index(np,
605 					       "atmel,pll-clk-output-ranges",
606 					       offset + 3, &tmp))
607 			goto out_free_output;
608 		icpll[i] = tmp;
609 	}
610 
611 	characteristics->input = input;
612 	characteristics->num_output = num_output;
613 	characteristics->output = output;
614 	characteristics->out = out;
615 	characteristics->icpll = icpll;
616 	return characteristics;
617 
618 out_free_output:
619 	kfree(icpll);
620 	kfree(out);
621 	kfree(output);
622 out_free_characteristics:
623 	kfree(characteristics);
624 	return NULL;
625 }
626 
627 static void __init
628 of_at91_clk_pll_setup(struct device_node *np,
629 		      const struct clk_pll_layout *layout)
630 {
631 	u32 id;
632 	struct clk_hw *hw;
633 	struct regmap *regmap;
634 	const char *parent_name;
635 	const char *name = np->name;
636 	struct device_node *parent_np;
637 	struct clk_pll_characteristics *characteristics;
638 
639 	if (of_property_read_u32(np, "reg", &id))
640 		return;
641 
642 	parent_name = of_clk_get_parent_name(np, 0);
643 
644 	of_property_read_string(np, "clock-output-names", &name);
645 
646 	parent_np = of_get_parent(np);
647 	regmap = syscon_node_to_regmap(parent_np);
648 	of_node_put(parent_np);
649 	if (IS_ERR(regmap))
650 		return;
651 
652 	characteristics = of_at91_clk_pll_get_characteristics(np);
653 	if (!characteristics)
654 		return;
655 
656 	hw = at91_clk_register_pll(regmap, name, parent_name, id, layout,
657 				   characteristics);
658 	if (IS_ERR(hw))
659 		goto out_free_characteristics;
660 
661 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
662 	return;
663 
664 out_free_characteristics:
665 	kfree(characteristics);
666 }
667 
668 static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
669 {
670 	of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
671 }
672 CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
673 	       of_at91rm9200_clk_pll_setup);
674 
675 static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
676 {
677 	of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
678 }
679 CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
680 	       of_at91sam9g45_clk_pll_setup);
681 
682 static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
683 {
684 	of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
685 }
686 CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
687 	       of_at91sam9g20_clk_pllb_setup);
688 
689 static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
690 {
691 	of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
692 }
693 CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
694 	       of_sama5d3_clk_pll_setup);
695 
696 static void __init
697 of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
698 {
699 	struct clk_hw *hw;
700 	const char *parent_name;
701 	const char *name = np->name;
702 	struct regmap *regmap;
703 	struct device_node *parent_np;
704 
705 	parent_name = of_clk_get_parent_name(np, 0);
706 
707 	of_property_read_string(np, "clock-output-names", &name);
708 
709 	parent_np = of_get_parent(np);
710 	regmap = syscon_node_to_regmap(parent_np);
711 	of_node_put(parent_np);
712 	if (IS_ERR(regmap))
713 		return;
714 
715 	hw = at91_clk_register_plldiv(regmap, name, parent_name);
716 	if (IS_ERR(hw))
717 		return;
718 
719 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
720 }
721 CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
722 	       of_at91sam9x5_clk_plldiv_setup);
723 
724 static void __init
725 of_at91_clk_prog_setup(struct device_node *np,
726 		       const struct clk_programmable_layout *layout,
727 		       u32 *mux_table)
728 {
729 	int num;
730 	u32 id;
731 	struct clk_hw *hw;
732 	unsigned int num_parents;
733 	const char *parent_names[PROG_SOURCE_MAX];
734 	const char *name;
735 	struct device_node *progclknp, *parent_np;
736 	struct regmap *regmap;
737 
738 	num_parents = of_clk_get_parent_count(np);
739 	if (num_parents == 0 || num_parents > PROG_SOURCE_MAX)
740 		return;
741 
742 	of_clk_parent_fill(np, parent_names, num_parents);
743 
744 	num = of_get_child_count(np);
745 	if (!num || num > (PROG_ID_MAX + 1))
746 		return;
747 
748 	parent_np = of_get_parent(np);
749 	regmap = syscon_node_to_regmap(parent_np);
750 	of_node_put(parent_np);
751 	if (IS_ERR(regmap))
752 		return;
753 
754 	for_each_child_of_node(np, progclknp) {
755 		if (of_property_read_u32(progclknp, "reg", &id))
756 			continue;
757 
758 		if (of_property_read_string(np, "clock-output-names", &name))
759 			name = progclknp->name;
760 
761 		hw = at91_clk_register_programmable(regmap, name,
762 						    parent_names, num_parents,
763 						    id, layout, mux_table);
764 		if (IS_ERR(hw))
765 			continue;
766 
767 		of_clk_add_hw_provider(progclknp, of_clk_hw_simple_get, hw);
768 	}
769 }
770 
771 static void __init of_at91rm9200_clk_prog_setup(struct device_node *np)
772 {
773 	of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout, NULL);
774 }
775 CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable",
776 	       of_at91rm9200_clk_prog_setup);
777 
778 static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np)
779 {
780 	of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout, NULL);
781 }
782 CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable",
783 	       of_at91sam9g45_clk_prog_setup);
784 
785 static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np)
786 {
787 	of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout, NULL);
788 }
789 CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable",
790 	       of_at91sam9x5_clk_prog_setup);
791 
792 static void __init of_at91sam9260_clk_slow_setup(struct device_node *np)
793 {
794 	struct clk_hw *hw;
795 	const char *parent_names[2];
796 	unsigned int num_parents;
797 	const char *name = np->name;
798 	struct regmap *regmap;
799 	struct device_node *parent_np;
800 
801 	num_parents = of_clk_get_parent_count(np);
802 	if (num_parents != 2)
803 		return;
804 
805 	of_clk_parent_fill(np, parent_names, num_parents);
806 	parent_np = of_get_parent(np);
807 	regmap = syscon_node_to_regmap(parent_np);
808 	of_node_put(parent_np);
809 	if (IS_ERR(regmap))
810 		return;
811 
812 	of_property_read_string(np, "clock-output-names", &name);
813 
814 	hw = at91_clk_register_sam9260_slow(regmap, name, parent_names,
815 					    num_parents);
816 	if (IS_ERR(hw))
817 		return;
818 
819 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
820 }
821 CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow",
822 	       of_at91sam9260_clk_slow_setup);
823 
824 #ifdef CONFIG_HAVE_AT91_SMD
825 #define SMD_SOURCE_MAX		2
826 
827 static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
828 {
829 	struct clk_hw *hw;
830 	unsigned int num_parents;
831 	const char *parent_names[SMD_SOURCE_MAX];
832 	const char *name = np->name;
833 	struct regmap *regmap;
834 	struct device_node *parent_np;
835 
836 	num_parents = of_clk_get_parent_count(np);
837 	if (num_parents == 0 || num_parents > SMD_SOURCE_MAX)
838 		return;
839 
840 	of_clk_parent_fill(np, parent_names, num_parents);
841 
842 	of_property_read_string(np, "clock-output-names", &name);
843 
844 	parent_np = of_get_parent(np);
845 	regmap = syscon_node_to_regmap(parent_np);
846 	of_node_put(parent_np);
847 	if (IS_ERR(regmap))
848 		return;
849 
850 	hw = at91sam9x5_clk_register_smd(regmap, name, parent_names,
851 					 num_parents);
852 	if (IS_ERR(hw))
853 		return;
854 
855 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
856 }
857 CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd",
858 	       of_at91sam9x5_clk_smd_setup);
859 #endif /* CONFIG_HAVE_AT91_SMD */
860 
861 static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
862 {
863 	int num;
864 	u32 id;
865 	struct clk_hw *hw;
866 	const char *name;
867 	struct device_node *sysclknp, *parent_np;
868 	const char *parent_name;
869 	struct regmap *regmap;
870 
871 	num = of_get_child_count(np);
872 	if (num > (SYSTEM_MAX_ID + 1))
873 		return;
874 
875 	parent_np = of_get_parent(np);
876 	regmap = syscon_node_to_regmap(parent_np);
877 	of_node_put(parent_np);
878 	if (IS_ERR(regmap))
879 		return;
880 
881 	for_each_child_of_node(np, sysclknp) {
882 		if (of_property_read_u32(sysclknp, "reg", &id))
883 			continue;
884 
885 		if (of_property_read_string(np, "clock-output-names", &name))
886 			name = sysclknp->name;
887 
888 		parent_name = of_clk_get_parent_name(sysclknp, 0);
889 
890 		hw = at91_clk_register_system(regmap, name, parent_name, id);
891 		if (IS_ERR(hw))
892 			continue;
893 
894 		of_clk_add_hw_provider(sysclknp, of_clk_hw_simple_get, hw);
895 	}
896 }
897 CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system",
898 	       of_at91rm9200_clk_sys_setup);
899 
900 #ifdef CONFIG_HAVE_AT91_USB_CLK
901 #define USB_SOURCE_MAX		2
902 
903 static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
904 {
905 	struct clk_hw *hw;
906 	unsigned int num_parents;
907 	const char *parent_names[USB_SOURCE_MAX];
908 	const char *name = np->name;
909 	struct regmap *regmap;
910 	struct device_node *parent_np;
911 
912 	num_parents = of_clk_get_parent_count(np);
913 	if (num_parents == 0 || num_parents > USB_SOURCE_MAX)
914 		return;
915 
916 	of_clk_parent_fill(np, parent_names, num_parents);
917 
918 	of_property_read_string(np, "clock-output-names", &name);
919 
920 	parent_np = of_get_parent(np);
921 	regmap = syscon_node_to_regmap(parent_np);
922 	of_node_put(parent_np);
923 	if (IS_ERR(regmap))
924 		return;
925 
926 	hw = at91sam9x5_clk_register_usb(regmap, name, parent_names,
927 					 num_parents);
928 	if (IS_ERR(hw))
929 		return;
930 
931 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
932 }
933 CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb",
934 	       of_at91sam9x5_clk_usb_setup);
935 
936 static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)
937 {
938 	struct clk_hw *hw;
939 	const char *parent_name;
940 	const char *name = np->name;
941 	struct regmap *regmap;
942 	struct device_node *parent_np;
943 
944 	parent_name = of_clk_get_parent_name(np, 0);
945 	if (!parent_name)
946 		return;
947 
948 	of_property_read_string(np, "clock-output-names", &name);
949 
950 	parent_np = of_get_parent(np);
951 	regmap = syscon_node_to_regmap(parent_np);
952 	of_node_put(parent_np);
953 	if (IS_ERR(regmap))
954 		return;
955 
956 	hw = at91sam9n12_clk_register_usb(regmap, name, parent_name);
957 	if (IS_ERR(hw))
958 		return;
959 
960 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
961 }
962 CLK_OF_DECLARE(at91sam9n12_clk_usb, "atmel,at91sam9n12-clk-usb",
963 	       of_at91sam9n12_clk_usb_setup);
964 
965 static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
966 {
967 	struct clk_hw *hw;
968 	const char *parent_name;
969 	const char *name = np->name;
970 	u32 divisors[4] = {0, 0, 0, 0};
971 	struct regmap *regmap;
972 	struct device_node *parent_np;
973 
974 	parent_name = of_clk_get_parent_name(np, 0);
975 	if (!parent_name)
976 		return;
977 
978 	of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4);
979 	if (!divisors[0])
980 		return;
981 
982 	of_property_read_string(np, "clock-output-names", &name);
983 
984 	parent_np = of_get_parent(np);
985 	regmap = syscon_node_to_regmap(parent_np);
986 	of_node_put(parent_np);
987 	if (IS_ERR(regmap))
988 		return;
989 	hw = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors);
990 	if (IS_ERR(hw))
991 		return;
992 
993 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
994 }
995 CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb",
996 	       of_at91rm9200_clk_usb_setup);
997 #endif /* CONFIG_HAVE_AT91_USB_CLK */
998 
999 #ifdef CONFIG_HAVE_AT91_UTMI
1000 static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
1001 {
1002 	struct clk_hw *hw;
1003 	const char *parent_name;
1004 	const char *name = np->name;
1005 	struct regmap *regmap_pmc, *regmap_sfr;
1006 	struct device_node *parent_np;
1007 
1008 	parent_name = of_clk_get_parent_name(np, 0);
1009 
1010 	of_property_read_string(np, "clock-output-names", &name);
1011 
1012 	parent_np = of_get_parent(np);
1013 	regmap_pmc = syscon_node_to_regmap(parent_np);
1014 	of_node_put(parent_np);
1015 	if (IS_ERR(regmap_pmc))
1016 		return;
1017 
1018 	/*
1019 	 * If the device supports different mainck rates, this value has to be
1020 	 * set in the UTMI Clock Trimming register.
1021 	 * - 9x5: mainck supports several rates but it is indicated that a
1022 	 *   12 MHz is needed in case of USB.
1023 	 * - sama5d3 and sama5d2: mainck supports several rates. Configuring
1024 	 *   the FREQ field of the UTMI Clock Trimming register is mandatory.
1025 	 * - sama5d4: mainck is at 12 MHz.
1026 	 *
1027 	 * We only need to retrieve sama5d3 or sama5d2 sfr regmap.
1028 	 */
1029 	regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr");
1030 	if (IS_ERR(regmap_sfr)) {
1031 		regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
1032 		if (IS_ERR(regmap_sfr))
1033 			regmap_sfr = NULL;
1034 	}
1035 
1036 	hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name);
1037 	if (IS_ERR(hw))
1038 		return;
1039 
1040 	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
1041 }
1042 CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi",
1043 	       of_at91sam9x5_clk_utmi_setup);
1044 #endif /* CONFIG_HAVE_AT91_UTMI */
1045