xref: /openbmc/linux/drivers/net/phy/mscc/mscc_main.c (revision 724ba675)
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3  * Driver for Microsemi VSC85xx PHYs
4  *
5  * Author: Nagaraju Lakkaraju
6  * License: Dual MIT/GPL
7  * Copyright (c) 2016 Microsemi Corporation
8  */
9 
10 #include <linux/firmware.h>
11 #include <linux/jiffies.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/mdio.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
17 #include <linux/of.h>
18 #include <linux/netdevice.h>
19 #include <dt-bindings/net/mscc-phy-vsc8531.h>
20 #include "mscc_serdes.h"
21 #include "mscc.h"
22 
23 static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = {
24 	{
25 		.string	= "phy_receive_errors",
26 		.reg	= MSCC_PHY_ERR_RX_CNT,
27 		.page	= MSCC_PHY_PAGE_STANDARD,
28 		.mask	= ERR_CNT_MASK,
29 	}, {
30 		.string	= "phy_false_carrier",
31 		.reg	= MSCC_PHY_ERR_FALSE_CARRIER_CNT,
32 		.page	= MSCC_PHY_PAGE_STANDARD,
33 		.mask	= ERR_CNT_MASK,
34 	}, {
35 		.string	= "phy_cu_media_link_disconnect",
36 		.reg	= MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
37 		.page	= MSCC_PHY_PAGE_STANDARD,
38 		.mask	= ERR_CNT_MASK,
39 	}, {
40 		.string	= "phy_cu_media_crc_good_count",
41 		.reg	= MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
42 		.page	= MSCC_PHY_PAGE_EXTENDED,
43 		.mask	= VALID_CRC_CNT_CRC_MASK,
44 	}, {
45 		.string	= "phy_cu_media_crc_error_count",
46 		.reg	= MSCC_PHY_EXT_PHY_CNTL_4,
47 		.page	= MSCC_PHY_PAGE_EXTENDED,
48 		.mask	= ERR_CNT_MASK,
49 	},
50 };
51 
52 static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = {
53 	{
54 		.string	= "phy_receive_errors",
55 		.reg	= MSCC_PHY_ERR_RX_CNT,
56 		.page	= MSCC_PHY_PAGE_STANDARD,
57 		.mask	= ERR_CNT_MASK,
58 	}, {
59 		.string	= "phy_false_carrier",
60 		.reg	= MSCC_PHY_ERR_FALSE_CARRIER_CNT,
61 		.page	= MSCC_PHY_PAGE_STANDARD,
62 		.mask	= ERR_CNT_MASK,
63 	}, {
64 		.string	= "phy_cu_media_link_disconnect",
65 		.reg	= MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
66 		.page	= MSCC_PHY_PAGE_STANDARD,
67 		.mask	= ERR_CNT_MASK,
68 	}, {
69 		.string	= "phy_cu_media_crc_good_count",
70 		.reg	= MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
71 		.page	= MSCC_PHY_PAGE_EXTENDED,
72 		.mask	= VALID_CRC_CNT_CRC_MASK,
73 	}, {
74 		.string	= "phy_cu_media_crc_error_count",
75 		.reg	= MSCC_PHY_EXT_PHY_CNTL_4,
76 		.page	= MSCC_PHY_PAGE_EXTENDED,
77 		.mask	= ERR_CNT_MASK,
78 	}, {
79 		.string	= "phy_serdes_tx_good_pkt_count",
80 		.reg	= MSCC_PHY_SERDES_TX_VALID_CNT,
81 		.page	= MSCC_PHY_PAGE_EXTENDED_3,
82 		.mask	= VALID_CRC_CNT_CRC_MASK,
83 	}, {
84 		.string	= "phy_serdes_tx_bad_crc_count",
85 		.reg	= MSCC_PHY_SERDES_TX_CRC_ERR_CNT,
86 		.page	= MSCC_PHY_PAGE_EXTENDED_3,
87 		.mask	= ERR_CNT_MASK,
88 	}, {
89 		.string	= "phy_serdes_rx_good_pkt_count",
90 		.reg	= MSCC_PHY_SERDES_RX_VALID_CNT,
91 		.page	= MSCC_PHY_PAGE_EXTENDED_3,
92 		.mask	= VALID_CRC_CNT_CRC_MASK,
93 	}, {
94 		.string	= "phy_serdes_rx_bad_crc_count",
95 		.reg	= MSCC_PHY_SERDES_RX_CRC_ERR_CNT,
96 		.page	= MSCC_PHY_PAGE_EXTENDED_3,
97 		.mask	= ERR_CNT_MASK,
98 	},
99 };
100 
101 #if IS_ENABLED(CONFIG_OF_MDIO)
102 static const struct vsc8531_edge_rate_table edge_table[] = {
103 	{MSCC_VDDMAC_3300, { 0, 2,  4,  7, 10, 17, 29, 53} },
104 	{MSCC_VDDMAC_2500, { 0, 3,  6, 10, 14, 23, 37, 63} },
105 	{MSCC_VDDMAC_1800, { 0, 5,  9, 16, 23, 35, 52, 76} },
106 	{MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
107 };
108 #endif
109 
110 static int vsc85xx_phy_read_page(struct phy_device *phydev)
111 {
112 	return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS);
113 }
114 
115 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page)
116 {
117 	return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
118 }
119 
120 static int vsc85xx_get_sset_count(struct phy_device *phydev)
121 {
122 	struct vsc8531_private *priv = phydev->priv;
123 
124 	if (!priv)
125 		return 0;
126 
127 	return priv->nstats;
128 }
129 
130 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data)
131 {
132 	struct vsc8531_private *priv = phydev->priv;
133 	int i;
134 
135 	if (!priv)
136 		return;
137 
138 	for (i = 0; i < priv->nstats; i++)
139 		strscpy(data + i * ETH_GSTRING_LEN, priv->hw_stats[i].string,
140 			ETH_GSTRING_LEN);
141 }
142 
143 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i)
144 {
145 	struct vsc8531_private *priv = phydev->priv;
146 	int val;
147 
148 	val = phy_read_paged(phydev, priv->hw_stats[i].page,
149 			     priv->hw_stats[i].reg);
150 	if (val < 0)
151 		return U64_MAX;
152 
153 	val = val & priv->hw_stats[i].mask;
154 	priv->stats[i] += val;
155 
156 	return priv->stats[i];
157 }
158 
159 static void vsc85xx_get_stats(struct phy_device *phydev,
160 			      struct ethtool_stats *stats, u64 *data)
161 {
162 	struct vsc8531_private *priv = phydev->priv;
163 	int i;
164 
165 	if (!priv)
166 		return;
167 
168 	for (i = 0; i < priv->nstats; i++)
169 		data[i] = vsc85xx_get_stat(phydev, i);
170 }
171 
172 static int vsc85xx_led_cntl_set(struct phy_device *phydev,
173 				u8 led_num,
174 				u8 mode)
175 {
176 	int rc;
177 	u16 reg_val;
178 
179 	mutex_lock(&phydev->lock);
180 	reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
181 	reg_val &= ~LED_MODE_SEL_MASK(led_num);
182 	reg_val |= LED_MODE_SEL(led_num, (u16)mode);
183 	rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
184 	mutex_unlock(&phydev->lock);
185 
186 	return rc;
187 }
188 
189 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
190 {
191 	u16 reg_val;
192 
193 	reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
194 	if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
195 		*mdix = ETH_TP_MDI_X;
196 	else
197 		*mdix = ETH_TP_MDI;
198 
199 	return 0;
200 }
201 
202 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
203 {
204 	int rc;
205 	u16 reg_val;
206 
207 	reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
208 	if (mdix == ETH_TP_MDI || mdix == ETH_TP_MDI_X) {
209 		reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
210 			    DISABLE_POLARITY_CORR_MASK  |
211 			    DISABLE_HP_AUTO_MDIX_MASK);
212 	} else {
213 		reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
214 			     DISABLE_POLARITY_CORR_MASK  |
215 			     DISABLE_HP_AUTO_MDIX_MASK);
216 	}
217 	rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
218 	if (rc)
219 		return rc;
220 
221 	reg_val = 0;
222 
223 	if (mdix == ETH_TP_MDI)
224 		reg_val = FORCE_MDI_CROSSOVER_MDI;
225 	else if (mdix == ETH_TP_MDI_X)
226 		reg_val = FORCE_MDI_CROSSOVER_MDIX;
227 
228 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
229 			      MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK,
230 			      reg_val);
231 	if (rc < 0)
232 		return rc;
233 
234 	return genphy_restart_aneg(phydev);
235 }
236 
237 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
238 {
239 	int reg_val;
240 
241 	reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
242 				 MSCC_PHY_ACTIPHY_CNTL);
243 	if (reg_val < 0)
244 		return reg_val;
245 
246 	reg_val &= DOWNSHIFT_CNTL_MASK;
247 	if (!(reg_val & DOWNSHIFT_EN))
248 		*count = DOWNSHIFT_DEV_DISABLE;
249 	else
250 		*count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2;
251 
252 	return 0;
253 }
254 
255 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count)
256 {
257 	if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) {
258 		/* Default downshift count 3 (i.e. Bit3:2 = 0b01) */
259 		count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
260 	} else if (count > DOWNSHIFT_COUNT_MAX || count == 1) {
261 		phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");
262 		return -ERANGE;
263 	} else if (count) {
264 		/* Downshift count is either 2,3,4 or 5 */
265 		count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
266 	}
267 
268 	return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
269 				MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK,
270 				count);
271 }
272 
273 static int vsc85xx_wol_set(struct phy_device *phydev,
274 			   struct ethtool_wolinfo *wol)
275 {
276 	const u8 *mac_addr = phydev->attached_dev->dev_addr;
277 	int rc;
278 	u16 reg_val;
279 	u8  i;
280 	u16 pwd[3] = {0, 0, 0};
281 	struct ethtool_wolinfo *wol_conf = wol;
282 
283 	rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
284 	if (rc < 0)
285 		return phy_restore_page(phydev, rc, rc);
286 
287 	if (wol->wolopts & WAKE_MAGIC) {
288 		/* Store the device address for the magic packet */
289 		for (i = 0; i < ARRAY_SIZE(pwd); i++)
290 			pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
291 				 mac_addr[5 - i * 2];
292 		__phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
293 		__phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
294 		__phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
295 	} else {
296 		__phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
297 		__phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
298 		__phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
299 	}
300 
301 	if (wol_conf->wolopts & WAKE_MAGICSECURE) {
302 		for (i = 0; i < ARRAY_SIZE(pwd); i++)
303 			pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
304 				 wol_conf->sopass[5 - i * 2];
305 		__phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
306 		__phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
307 		__phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
308 	} else {
309 		__phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
310 		__phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
311 		__phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
312 	}
313 
314 	reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
315 	if (wol_conf->wolopts & WAKE_MAGICSECURE)
316 		reg_val |= SECURE_ON_ENABLE;
317 	else
318 		reg_val &= ~SECURE_ON_ENABLE;
319 	__phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
320 
321 	rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
322 	if (rc < 0)
323 		return rc;
324 
325 	if (wol->wolopts & WAKE_MAGIC) {
326 		/* Enable the WOL interrupt */
327 		reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
328 		reg_val |= MII_VSC85XX_INT_MASK_WOL;
329 		rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
330 		if (rc)
331 			return rc;
332 	} else {
333 		/* Disable the WOL interrupt */
334 		reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
335 		reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
336 		rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
337 		if (rc)
338 			return rc;
339 	}
340 	/* Clear WOL iterrupt status */
341 	reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
342 
343 	return 0;
344 }
345 
346 static void vsc85xx_wol_get(struct phy_device *phydev,
347 			    struct ethtool_wolinfo *wol)
348 {
349 	int rc;
350 	u16 reg_val;
351 	u8  i;
352 	u16 pwd[3] = {0, 0, 0};
353 	struct ethtool_wolinfo *wol_conf = wol;
354 
355 	rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
356 	if (rc < 0)
357 		goto out_restore_page;
358 
359 	reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
360 	if (reg_val & SECURE_ON_ENABLE)
361 		wol_conf->wolopts |= WAKE_MAGICSECURE;
362 	if (wol_conf->wolopts & WAKE_MAGICSECURE) {
363 		pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
364 		pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
365 		pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
366 		for (i = 0; i < ARRAY_SIZE(pwd); i++) {
367 			wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff;
368 			wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00)
369 							    >> 8;
370 		}
371 	}
372 
373 out_restore_page:
374 	phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
375 }
376 
377 #if IS_ENABLED(CONFIG_OF_MDIO)
378 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
379 {
380 	u32 vdd, sd;
381 	int i, j;
382 	struct device *dev = &phydev->mdio.dev;
383 	struct device_node *of_node = dev->of_node;
384 	u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown);
385 
386 	if (!of_node)
387 		return -ENODEV;
388 
389 	if (of_property_read_u32(of_node, "vsc8531,vddmac", &vdd))
390 		vdd = MSCC_VDDMAC_3300;
391 
392 	if (of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd))
393 		sd = 0;
394 
395 	for (i = 0; i < ARRAY_SIZE(edge_table); i++)
396 		if (edge_table[i].vddmac == vdd)
397 			for (j = 0; j < sd_array_size; j++)
398 				if (edge_table[i].slowdown[j] == sd)
399 					return (sd_array_size - j - 1);
400 
401 	return -EINVAL;
402 }
403 
404 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
405 				   char *led,
406 				   u32 default_mode)
407 {
408 	struct vsc8531_private *priv = phydev->priv;
409 	struct device *dev = &phydev->mdio.dev;
410 	struct device_node *of_node = dev->of_node;
411 	u32 led_mode;
412 	int err;
413 
414 	if (!of_node)
415 		return -ENODEV;
416 
417 	led_mode = default_mode;
418 	err = of_property_read_u32(of_node, led, &led_mode);
419 	if (!err && !(BIT(led_mode) & priv->supp_led_modes)) {
420 		phydev_err(phydev, "DT %s invalid\n", led);
421 		return -EINVAL;
422 	}
423 
424 	return led_mode;
425 }
426 
427 #else
428 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
429 {
430 	return 0;
431 }
432 
433 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
434 				   char *led,
435 				   u8 default_mode)
436 {
437 	return default_mode;
438 }
439 #endif /* CONFIG_OF_MDIO */
440 
441 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev,
442 				    u32 *default_mode)
443 {
444 	struct vsc8531_private *priv = phydev->priv;
445 	char led_dt_prop[28];
446 	int i, ret;
447 
448 	for (i = 0; i < priv->nleds; i++) {
449 		ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i);
450 		if (ret < 0)
451 			return ret;
452 
453 		ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop,
454 					      default_mode[i]);
455 		if (ret < 0)
456 			return ret;
457 		priv->leds_mode[i] = ret;
458 	}
459 
460 	return 0;
461 }
462 
463 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
464 {
465 	int rc;
466 
467 	mutex_lock(&phydev->lock);
468 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
469 			      MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK,
470 			      edge_rate << EDGE_RATE_CNTL_POS);
471 	mutex_unlock(&phydev->lock);
472 
473 	return rc;
474 }
475 
476 static int vsc85xx_mac_if_set(struct phy_device *phydev,
477 			      phy_interface_t interface)
478 {
479 	int rc;
480 	u16 reg_val;
481 
482 	mutex_lock(&phydev->lock);
483 	reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
484 	reg_val &= ~(MAC_IF_SELECTION_MASK);
485 	switch (interface) {
486 	case PHY_INTERFACE_MODE_RGMII_TXID:
487 	case PHY_INTERFACE_MODE_RGMII_RXID:
488 	case PHY_INTERFACE_MODE_RGMII_ID:
489 	case PHY_INTERFACE_MODE_RGMII:
490 		reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
491 		break;
492 	case PHY_INTERFACE_MODE_RMII:
493 		reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
494 		break;
495 	case PHY_INTERFACE_MODE_MII:
496 	case PHY_INTERFACE_MODE_GMII:
497 		reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
498 		break;
499 	default:
500 		rc = -EINVAL;
501 		goto out_unlock;
502 	}
503 	rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
504 	if (rc)
505 		goto out_unlock;
506 
507 	rc = genphy_soft_reset(phydev);
508 
509 out_unlock:
510 	mutex_unlock(&phydev->lock);
511 
512 	return rc;
513 }
514 
515 /* Set the RGMII RX and TX clock skews individually, according to the PHY
516  * interface type, to:
517  *  * 0.2 ns (their default, and lowest, hardware value) if delays should
518  *    not be enabled
519  *  * 2.0 ns (which causes the data to be sampled at exactly half way between
520  *    clock transitions at 1000 Mbps) if delays should be enabled
521  */
522 static int vsc85xx_rgmii_set_skews(struct phy_device *phydev, u32 rgmii_cntl,
523 				   u16 rgmii_rx_delay_mask,
524 				   u16 rgmii_tx_delay_mask)
525 {
526 	u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1;
527 	u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1;
528 	u16 reg_val = 0;
529 	int rc;
530 
531 	mutex_lock(&phydev->lock);
532 
533 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
534 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
535 		reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_rx_delay_pos;
536 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
537 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
538 		reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_tx_delay_pos;
539 
540 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
541 			      rgmii_cntl,
542 			      rgmii_rx_delay_mask | rgmii_tx_delay_mask,
543 			      reg_val);
544 
545 	mutex_unlock(&phydev->lock);
546 
547 	return rc;
548 }
549 
550 static int vsc85xx_default_config(struct phy_device *phydev)
551 {
552 	int rc;
553 
554 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
555 
556 	if (phy_interface_mode_is_rgmii(phydev->interface)) {
557 		rc = vsc85xx_rgmii_set_skews(phydev, VSC8502_RGMII_CNTL,
558 					     VSC8502_RGMII_RX_DELAY_MASK,
559 					     VSC8502_RGMII_TX_DELAY_MASK);
560 		if (rc)
561 			return rc;
562 	}
563 
564 	return 0;
565 }
566 
567 static int vsc85xx_get_tunable(struct phy_device *phydev,
568 			       struct ethtool_tunable *tuna, void *data)
569 {
570 	switch (tuna->id) {
571 	case ETHTOOL_PHY_DOWNSHIFT:
572 		return vsc85xx_downshift_get(phydev, (u8 *)data);
573 	default:
574 		return -EINVAL;
575 	}
576 }
577 
578 static int vsc85xx_set_tunable(struct phy_device *phydev,
579 			       struct ethtool_tunable *tuna,
580 			       const void *data)
581 {
582 	switch (tuna->id) {
583 	case ETHTOOL_PHY_DOWNSHIFT:
584 		return vsc85xx_downshift_set(phydev, *(u8 *)data);
585 	default:
586 		return -EINVAL;
587 	}
588 }
589 
590 /* mdiobus lock should be locked when using this function */
591 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val)
592 {
593 	__phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
594 	__phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
595 	__phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
596 }
597 
598 static int vsc8531_pre_init_seq_set(struct phy_device *phydev)
599 {
600 	int rc;
601 	static const struct reg_val init_seq[] = {
602 		{0x0f90, 0x00688980},
603 		{0x0696, 0x00000003},
604 		{0x07fa, 0x0050100f},
605 		{0x1686, 0x00000004},
606 	};
607 	unsigned int i;
608 	int oldpage;
609 
610 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD,
611 			      MSCC_PHY_EXT_CNTL_STATUS, SMI_BROADCAST_WR_EN,
612 			      SMI_BROADCAST_WR_EN);
613 	if (rc < 0)
614 		return rc;
615 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
616 			      MSCC_PHY_TEST_PAGE_24, 0, 0x0400);
617 	if (rc < 0)
618 		return rc;
619 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
620 			      MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00);
621 	if (rc < 0)
622 		return rc;
623 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
624 			      MSCC_PHY_TEST_PAGE_8, TR_CLK_DISABLE, TR_CLK_DISABLE);
625 	if (rc < 0)
626 		return rc;
627 
628 	mutex_lock(&phydev->lock);
629 	oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
630 	if (oldpage < 0)
631 		goto out_unlock;
632 
633 	for (i = 0; i < ARRAY_SIZE(init_seq); i++)
634 		vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val);
635 
636 out_unlock:
637 	oldpage = phy_restore_page(phydev, oldpage, oldpage);
638 	mutex_unlock(&phydev->lock);
639 
640 	return oldpage;
641 }
642 
643 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev)
644 {
645 	static const struct reg_val init_eee[] = {
646 		{0x0f82, 0x0012b00a},
647 		{0x1686, 0x00000004},
648 		{0x168c, 0x00d2c46f},
649 		{0x17a2, 0x00000620},
650 		{0x16a0, 0x00eeffdd},
651 		{0x16a6, 0x00071448},
652 		{0x16a4, 0x0013132f},
653 		{0x16a8, 0x00000000},
654 		{0x0ffc, 0x00c0a028},
655 		{0x0fe8, 0x0091b06c},
656 		{0x0fea, 0x00041600},
657 		{0x0f80, 0x00000af4},
658 		{0x0fec, 0x00901809},
659 		{0x0fee, 0x0000a6a1},
660 		{0x0ffe, 0x00b01007},
661 		{0x16b0, 0x00eeff00},
662 		{0x16b2, 0x00007000},
663 		{0x16b4, 0x00000814},
664 	};
665 	unsigned int i;
666 	int oldpage;
667 
668 	mutex_lock(&phydev->lock);
669 	oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
670 	if (oldpage < 0)
671 		goto out_unlock;
672 
673 	for (i = 0; i < ARRAY_SIZE(init_eee); i++)
674 		vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val);
675 
676 out_unlock:
677 	oldpage = phy_restore_page(phydev, oldpage, oldpage);
678 	mutex_unlock(&phydev->lock);
679 
680 	return oldpage;
681 }
682 
683 /* phydev->bus->mdio_lock should be locked when using this function */
684 int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)
685 {
686 	if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
687 		dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
688 		dump_stack();
689 	}
690 
691 	return __phy_package_write(phydev, regnum, val);
692 }
693 
694 /* phydev->bus->mdio_lock should be locked when using this function */
695 int phy_base_read(struct phy_device *phydev, u32 regnum)
696 {
697 	if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
698 		dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
699 		dump_stack();
700 	}
701 
702 	return __phy_package_read(phydev, regnum);
703 }
704 
705 u32 vsc85xx_csr_read(struct phy_device *phydev,
706 		     enum csr_target target, u32 reg)
707 {
708 	unsigned long deadline;
709 	u32 val, val_l, val_h;
710 
711 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
712 
713 	/* CSR registers are grouped under different Target IDs.
714 	 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
715 	 * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
716 	 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
717 	 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
718 	 */
719 
720 	/* Setup the Target ID */
721 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
722 		       MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
723 
724 	if ((target >> 2 == 0x1) || (target >> 2 == 0x3))
725 		/* non-MACsec access */
726 		target &= 0x3;
727 	else
728 		target = 0;
729 
730 	/* Trigger CSR Action - Read into the CSR's */
731 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
732 		       MSCC_PHY_CSR_CNTL_19_CMD | MSCC_PHY_CSR_CNTL_19_READ |
733 		       MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
734 		       MSCC_PHY_CSR_CNTL_19_TARGET(target));
735 
736 	/* Wait for register access*/
737 	deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
738 	do {
739 		usleep_range(500, 1000);
740 		val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
741 	} while (time_before(jiffies, deadline) &&
742 		!(val & MSCC_PHY_CSR_CNTL_19_CMD));
743 
744 	if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
745 		return 0xffffffff;
746 
747 	/* Read the Least Significant Word (LSW) (17) */
748 	val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17);
749 
750 	/* Read the Most Significant Word (MSW) (18) */
751 	val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18);
752 
753 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
754 		       MSCC_PHY_PAGE_STANDARD);
755 
756 	return (val_h << 16) | val_l;
757 }
758 
759 int vsc85xx_csr_write(struct phy_device *phydev,
760 		      enum csr_target target, u32 reg, u32 val)
761 {
762 	unsigned long deadline;
763 
764 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
765 
766 	/* CSR registers are grouped under different Target IDs.
767 	 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
768 	 * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
769 	 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
770 	 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
771 	 */
772 
773 	/* Setup the Target ID */
774 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
775 		       MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
776 
777 	/* Write the Least Significant Word (LSW) (17) */
778 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);
779 
780 	/* Write the Most Significant Word (MSW) (18) */
781 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));
782 
783 	if ((target >> 2 == 0x1) || (target >> 2 == 0x3))
784 		/* non-MACsec access */
785 		target &= 0x3;
786 	else
787 		target = 0;
788 
789 	/* Trigger CSR Action - Write into the CSR's */
790 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
791 		       MSCC_PHY_CSR_CNTL_19_CMD |
792 		       MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
793 		       MSCC_PHY_CSR_CNTL_19_TARGET(target));
794 
795 	/* Wait for register access */
796 	deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
797 	do {
798 		usleep_range(500, 1000);
799 		val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
800 	} while (time_before(jiffies, deadline) &&
801 		 !(val & MSCC_PHY_CSR_CNTL_19_CMD));
802 
803 	if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
804 		return -ETIMEDOUT;
805 
806 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
807 		       MSCC_PHY_PAGE_STANDARD);
808 
809 	return 0;
810 }
811 
812 /* bus->mdio_lock should be locked when using this function */
813 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val)
814 {
815 	phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
816 	phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
817 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
818 }
819 
820 /* bus->mdio_lock should be locked when using this function */
821 int vsc8584_cmd(struct phy_device *phydev, u16 val)
822 {
823 	unsigned long deadline;
824 	u16 reg_val;
825 
826 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
827 		       MSCC_PHY_PAGE_EXTENDED_GPIO);
828 
829 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);
830 
831 	deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
832 	do {
833 		reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);
834 	} while (time_before(jiffies, deadline) &&
835 		 (reg_val & PROC_CMD_NCOMPLETED) &&
836 		 !(reg_val & PROC_CMD_FAILED));
837 
838 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
839 
840 	if (reg_val & PROC_CMD_FAILED)
841 		return -EIO;
842 
843 	if (reg_val & PROC_CMD_NCOMPLETED)
844 		return -ETIMEDOUT;
845 
846 	return 0;
847 }
848 
849 /* bus->mdio_lock should be locked when using this function */
850 static int vsc8584_micro_deassert_reset(struct phy_device *phydev,
851 					bool patch_en)
852 {
853 	u32 enable, release;
854 
855 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
856 		       MSCC_PHY_PAGE_EXTENDED_GPIO);
857 
858 	enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN;
859 	release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
860 		MICRO_CLK_EN;
861 
862 	if (patch_en) {
863 		enable |= MICRO_PATCH_EN;
864 		release |= MICRO_PATCH_EN;
865 
866 		/* Clear all patches */
867 		phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
868 	}
869 
870 	/* Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock
871 	 * override and addr. auto-incr; operate at 125 MHz
872 	 */
873 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);
874 	/* Release 8051 Micro SW reset */
875 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);
876 
877 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
878 
879 	return 0;
880 }
881 
882 /* bus->mdio_lock should be locked when using this function */
883 static int vsc8584_micro_assert_reset(struct phy_device *phydev)
884 {
885 	int ret;
886 	u16 reg;
887 
888 	ret = vsc8584_cmd(phydev, PROC_CMD_NOP);
889 	if (ret)
890 		return ret;
891 
892 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
893 		       MSCC_PHY_PAGE_EXTENDED_GPIO);
894 
895 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
896 	reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
897 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
898 
899 	phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);
900 	phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);
901 
902 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
903 	reg |= EN_PATCH_RAM_TRAP_ADDR(4);
904 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
905 
906 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);
907 
908 	reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
909 	reg &= ~MICRO_NSOFT_RESET;
910 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);
911 
912 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |
913 		       PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF |
914 		       PROC_CMD_READ);
915 
916 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
917 	reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
918 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
919 
920 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
921 
922 	return 0;
923 }
924 
925 /* bus->mdio_lock should be locked when using this function */
926 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size,
927 			      u16 *crc)
928 {
929 	int ret;
930 
931 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
932 
933 	phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);
934 	phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);
935 
936 	/* Start Micro command */
937 	ret = vsc8584_cmd(phydev, PROC_CMD_CRC16);
938 	if (ret)
939 		goto out;
940 
941 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
942 
943 	*crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);
944 
945 out:
946 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
947 
948 	return ret;
949 }
950 
951 /* bus->mdio_lock should be locked when using this function */
952 static int vsc8584_patch_fw(struct phy_device *phydev,
953 			    const struct firmware *fw)
954 {
955 	int i, ret;
956 
957 	ret = vsc8584_micro_assert_reset(phydev);
958 	if (ret) {
959 		dev_err(&phydev->mdio.dev,
960 			"%s: failed to assert reset of micro\n", __func__);
961 		return ret;
962 	}
963 
964 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
965 		       MSCC_PHY_PAGE_EXTENDED_GPIO);
966 
967 	/* Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock
968 	 * Disable the 8051 Micro clock
969 	 */
970 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |
971 		       AUTOINC_ADDR | PATCH_RAM_CLK | MICRO_CLK_EN |
972 		       MICRO_CLK_DIVIDE(2));
973 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |
974 		       INT_MEM_DATA(2));
975 	phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);
976 
977 	for (i = 0; i < fw->size; i++)
978 		phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |
979 			       INT_MEM_WRITE_EN | fw->data[i]);
980 
981 	/* Clear internal memory access */
982 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
983 
984 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
985 
986 	return 0;
987 }
988 
989 /* bus->mdio_lock should be locked when using this function */
990 static bool vsc8574_is_serdes_init(struct phy_device *phydev)
991 {
992 	u16 reg;
993 	bool ret;
994 
995 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
996 		       MSCC_PHY_PAGE_EXTENDED_GPIO);
997 
998 	reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
999 	if (reg != 0x3eb7) {
1000 		ret = false;
1001 		goto out;
1002 	}
1003 
1004 	reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
1005 	if (reg != 0x4012) {
1006 		ret = false;
1007 		goto out;
1008 	}
1009 
1010 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1011 	if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) {
1012 		ret = false;
1013 		goto out;
1014 	}
1015 
1016 	reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
1017 	if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM |  DW8051_CLK_EN |
1018 	     MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) {
1019 		ret = false;
1020 		goto out;
1021 	}
1022 
1023 	ret = true;
1024 out:
1025 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1026 
1027 	return ret;
1028 }
1029 
1030 /* bus->mdio_lock should be locked when using this function */
1031 static int vsc8574_config_pre_init(struct phy_device *phydev)
1032 {
1033 	static const struct reg_val pre_init1[] = {
1034 		{0x0fae, 0x000401bd},
1035 		{0x0fac, 0x000f000f},
1036 		{0x17a0, 0x00a0f147},
1037 		{0x0fe4, 0x00052f54},
1038 		{0x1792, 0x0027303d},
1039 		{0x07fe, 0x00000704},
1040 		{0x0fe0, 0x00060150},
1041 		{0x0f82, 0x0012b00a},
1042 		{0x0f80, 0x00000d74},
1043 		{0x02e0, 0x00000012},
1044 		{0x03a2, 0x00050208},
1045 		{0x03b2, 0x00009186},
1046 		{0x0fb0, 0x000e3700},
1047 		{0x1688, 0x00049f81},
1048 		{0x0fd2, 0x0000ffff},
1049 		{0x168a, 0x00039fa2},
1050 		{0x1690, 0x0020640b},
1051 		{0x0258, 0x00002220},
1052 		{0x025a, 0x00002a20},
1053 		{0x025c, 0x00003060},
1054 		{0x025e, 0x00003fa0},
1055 		{0x03a6, 0x0000e0f0},
1056 		{0x0f92, 0x00001489},
1057 		{0x16a2, 0x00007000},
1058 		{0x16a6, 0x00071448},
1059 		{0x16a0, 0x00eeffdd},
1060 		{0x0fe8, 0x0091b06c},
1061 		{0x0fea, 0x00041600},
1062 		{0x16b0, 0x00eeff00},
1063 		{0x16b2, 0x00007000},
1064 		{0x16b4, 0x00000814},
1065 		{0x0f90, 0x00688980},
1066 		{0x03a4, 0x0000d8f0},
1067 		{0x0fc0, 0x00000400},
1068 		{0x07fa, 0x0050100f},
1069 		{0x0796, 0x00000003},
1070 		{0x07f8, 0x00c3ff98},
1071 		{0x0fa4, 0x0018292a},
1072 		{0x168c, 0x00d2c46f},
1073 		{0x17a2, 0x00000620},
1074 		{0x16a4, 0x0013132f},
1075 		{0x16a8, 0x00000000},
1076 		{0x0ffc, 0x00c0a028},
1077 		{0x0fec, 0x00901c09},
1078 		{0x0fee, 0x0004a6a1},
1079 		{0x0ffe, 0x00b01807},
1080 	};
1081 	static const struct reg_val pre_init2[] = {
1082 		{0x0486, 0x0008a518},
1083 		{0x0488, 0x006dc696},
1084 		{0x048a, 0x00000912},
1085 		{0x048e, 0x00000db6},
1086 		{0x049c, 0x00596596},
1087 		{0x049e, 0x00000514},
1088 		{0x04a2, 0x00410280},
1089 		{0x04a4, 0x00000000},
1090 		{0x04a6, 0x00000000},
1091 		{0x04a8, 0x00000000},
1092 		{0x04aa, 0x00000000},
1093 		{0x04ae, 0x007df7dd},
1094 		{0x04b0, 0x006d95d4},
1095 		{0x04b2, 0x00492410},
1096 	};
1097 	struct device *dev = &phydev->mdio.dev;
1098 	const struct firmware *fw;
1099 	unsigned int i;
1100 	u16 crc, reg;
1101 	bool serdes_init;
1102 	int ret;
1103 
1104 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1105 
1106 	/* all writes below are broadcasted to all PHYs in the same package */
1107 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1108 	reg |= SMI_BROADCAST_WR_EN;
1109 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1110 
1111 	phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1112 
1113 	/* The below register writes are tweaking analog and electrical
1114 	 * configuration that were determined through characterization by PHY
1115 	 * engineers. These don't mean anything more than "these are the best
1116 	 * values".
1117 	 */
1118 	phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);
1119 
1120 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1121 
1122 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);
1123 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);
1124 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);
1125 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);
1126 
1127 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1128 	reg |= TR_CLK_DISABLE;
1129 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1130 
1131 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1132 
1133 	for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1134 		vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1135 
1136 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1137 
1138 	phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1139 
1140 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1141 
1142 	for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1143 		vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1144 
1145 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1146 
1147 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1148 	reg &= ~TR_CLK_DISABLE;
1149 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1150 
1151 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1152 
1153 	/* end of write broadcasting */
1154 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1155 	reg &= ~SMI_BROADCAST_WR_EN;
1156 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1157 
1158 	ret = request_firmware(&fw, MSCC_VSC8574_REVB_INT8051_FW, dev);
1159 	if (ret) {
1160 		dev_err(dev, "failed to load firmware %s, ret: %d\n",
1161 			MSCC_VSC8574_REVB_INT8051_FW, ret);
1162 		return ret;
1163 	}
1164 
1165 	/* Add one byte to size for the one added by the patch_fw function */
1166 	ret = vsc8584_get_fw_crc(phydev,
1167 				 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1168 				 fw->size + 1, &crc);
1169 	if (ret)
1170 		goto out;
1171 
1172 	if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) {
1173 		serdes_init = vsc8574_is_serdes_init(phydev);
1174 
1175 		if (!serdes_init) {
1176 			ret = vsc8584_micro_assert_reset(phydev);
1177 			if (ret) {
1178 				dev_err(dev,
1179 					"%s: failed to assert reset of micro\n",
1180 					__func__);
1181 				goto out;
1182 			}
1183 		}
1184 	} else {
1185 		dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1186 
1187 		serdes_init = false;
1188 
1189 		if (vsc8584_patch_fw(phydev, fw))
1190 			dev_warn(dev,
1191 				 "failed to patch FW, expect non-optimal device\n");
1192 	}
1193 
1194 	if (!serdes_init) {
1195 		phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1196 			       MSCC_PHY_PAGE_EXTENDED_GPIO);
1197 
1198 		phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);
1199 		phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);
1200 		phy_base_write(phydev, MSCC_INT_MEM_CNTL,
1201 			       EN_PATCH_RAM_TRAP_ADDR(1));
1202 
1203 		vsc8584_micro_deassert_reset(phydev, false);
1204 
1205 		/* Add one byte to size for the one added by the patch_fw
1206 		 * function
1207 		 */
1208 		ret = vsc8584_get_fw_crc(phydev,
1209 					 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1210 					 fw->size + 1, &crc);
1211 		if (ret)
1212 			goto out;
1213 
1214 		if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC)
1215 			dev_warn(dev,
1216 				 "FW CRC after patching is not the expected one, expect non-optimal device\n");
1217 	}
1218 
1219 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1220 		       MSCC_PHY_PAGE_EXTENDED_GPIO);
1221 
1222 	ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT |
1223 			  PROC_CMD_PHY_INIT);
1224 
1225 out:
1226 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1227 
1228 	release_firmware(fw);
1229 
1230 	return ret;
1231 }
1232 
1233 /* Access LCPLL Cfg_2 */
1234 static void vsc8584_pll5g_cfg2_wr(struct phy_device *phydev,
1235 				  bool disable_fsm)
1236 {
1237 	u32 rd_dat;
1238 
1239 	rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2);
1240 	rd_dat &= ~BIT(PHY_S6G_CFG2_FSM_DIS);
1241 	rd_dat |= (disable_fsm << PHY_S6G_CFG2_FSM_DIS);
1242 	vsc85xx_csr_write(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2, rd_dat);
1243 }
1244 
1245 /* trigger a read to the spcified MCB */
1246 static int vsc8584_mcb_rd_trig(struct phy_device *phydev,
1247 			       u32 mcb_reg_addr, u8 mcb_slave_num)
1248 {
1249 	u32 rd_dat = 0;
1250 
1251 	/* read MCB */
1252 	vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr,
1253 			  (0x40000000 | (1L << mcb_slave_num)));
1254 
1255 	return read_poll_timeout(vsc85xx_csr_read, rd_dat,
1256 				 !(rd_dat & 0x40000000),
1257 				 4000, 200000, 0,
1258 				 phydev, MACRO_CTRL, mcb_reg_addr);
1259 }
1260 
1261 /* trigger a write to the spcified MCB */
1262 static int vsc8584_mcb_wr_trig(struct phy_device *phydev,
1263 			       u32 mcb_reg_addr,
1264 			       u8 mcb_slave_num)
1265 {
1266 	u32 rd_dat = 0;
1267 
1268 	/* write back MCB */
1269 	vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr,
1270 			  (0x80000000 | (1L << mcb_slave_num)));
1271 
1272 	return read_poll_timeout(vsc85xx_csr_read, rd_dat,
1273 				 !(rd_dat & 0x80000000),
1274 				 4000, 200000, 0,
1275 				 phydev, MACRO_CTRL, mcb_reg_addr);
1276 }
1277 
1278 /* Sequence to Reset LCPLL for the VIPER and ELISE PHY */
1279 static int vsc8584_pll5g_reset(struct phy_device *phydev)
1280 {
1281 	bool dis_fsm;
1282 	int ret = 0;
1283 
1284 	ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0);
1285 	if (ret < 0)
1286 		goto done;
1287 	dis_fsm = 1;
1288 
1289 	/* Reset LCPLL */
1290 	vsc8584_pll5g_cfg2_wr(phydev, dis_fsm);
1291 
1292 	/* write back LCPLL MCB */
1293 	ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0);
1294 	if (ret < 0)
1295 		goto done;
1296 
1297 	/* 10 mSec sleep while LCPLL is hold in reset */
1298 	usleep_range(10000, 20000);
1299 
1300 	/* read LCPLL MCB into CSRs */
1301 	ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0);
1302 	if (ret < 0)
1303 		goto done;
1304 	dis_fsm = 0;
1305 
1306 	/* Release the Reset of LCPLL */
1307 	vsc8584_pll5g_cfg2_wr(phydev, dis_fsm);
1308 
1309 	/* write back LCPLL MCB */
1310 	ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0);
1311 	if (ret < 0)
1312 		goto done;
1313 
1314 	usleep_range(110000, 200000);
1315 done:
1316 	return ret;
1317 }
1318 
1319 /* bus->mdio_lock should be locked when using this function */
1320 static int vsc8584_config_pre_init(struct phy_device *phydev)
1321 {
1322 	static const struct reg_val pre_init1[] = {
1323 		{0x07fa, 0x0050100f},
1324 		{0x1688, 0x00049f81},
1325 		{0x0f90, 0x00688980},
1326 		{0x03a4, 0x0000d8f0},
1327 		{0x0fc0, 0x00000400},
1328 		{0x0f82, 0x0012b002},
1329 		{0x1686, 0x00000004},
1330 		{0x168c, 0x00d2c46f},
1331 		{0x17a2, 0x00000620},
1332 		{0x16a0, 0x00eeffdd},
1333 		{0x16a6, 0x00071448},
1334 		{0x16a4, 0x0013132f},
1335 		{0x16a8, 0x00000000},
1336 		{0x0ffc, 0x00c0a028},
1337 		{0x0fe8, 0x0091b06c},
1338 		{0x0fea, 0x00041600},
1339 		{0x0f80, 0x00fffaff},
1340 		{0x0fec, 0x00901809},
1341 		{0x0ffe, 0x00b01007},
1342 		{0x16b0, 0x00eeff00},
1343 		{0x16b2, 0x00007000},
1344 		{0x16b4, 0x00000814},
1345 	};
1346 	static const struct reg_val pre_init2[] = {
1347 		{0x0486, 0x0008a518},
1348 		{0x0488, 0x006dc696},
1349 		{0x048a, 0x00000912},
1350 	};
1351 	const struct firmware *fw;
1352 	struct device *dev = &phydev->mdio.dev;
1353 	unsigned int i;
1354 	u16 crc, reg;
1355 	int ret;
1356 
1357 	ret = vsc8584_pll5g_reset(phydev);
1358 	if (ret < 0) {
1359 		dev_err(dev, "failed LCPLL reset, ret: %d\n", ret);
1360 		return ret;
1361 	}
1362 
1363 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1364 
1365 	/* all writes below are broadcasted to all PHYs in the same package */
1366 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1367 	reg |= SMI_BROADCAST_WR_EN;
1368 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1369 
1370 	phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1371 
1372 	reg = phy_base_read(phydev,  MSCC_PHY_BYPASS_CONTROL);
1373 	reg |= PARALLEL_DET_IGNORE_ADVERTISED;
1374 	phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);
1375 
1376 	/* The below register writes are tweaking analog and electrical
1377 	 * configuration that were determined through characterization by PHY
1378 	 * engineers. These don't mean anything more than "these are the best
1379 	 * values".
1380 	 */
1381 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);
1382 
1383 	phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);
1384 
1385 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1386 
1387 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);
1388 
1389 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1390 	reg |= TR_CLK_DISABLE;
1391 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1392 
1393 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1394 
1395 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));
1396 
1397 	reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
1398 	reg &= ~0x007f;
1399 	reg |= 0x0019;
1400 	phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);
1401 
1402 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));
1403 
1404 	for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1405 		vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1406 
1407 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1408 
1409 	phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1410 
1411 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1412 
1413 	for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1414 		vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1415 
1416 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1417 
1418 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1419 	reg &= ~TR_CLK_DISABLE;
1420 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1421 
1422 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1423 
1424 	/* end of write broadcasting */
1425 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1426 	reg &= ~SMI_BROADCAST_WR_EN;
1427 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1428 
1429 	ret = request_firmware(&fw, MSCC_VSC8584_REVB_INT8051_FW, dev);
1430 	if (ret) {
1431 		dev_err(dev, "failed to load firmware %s, ret: %d\n",
1432 			MSCC_VSC8584_REVB_INT8051_FW, ret);
1433 		return ret;
1434 	}
1435 
1436 	/* Add one byte to size for the one added by the patch_fw function */
1437 	ret = vsc8584_get_fw_crc(phydev,
1438 				 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1439 				 fw->size + 1, &crc);
1440 	if (ret)
1441 		goto out;
1442 
1443 	if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) {
1444 		dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1445 		if (vsc8584_patch_fw(phydev, fw))
1446 			dev_warn(dev,
1447 				 "failed to patch FW, expect non-optimal device\n");
1448 	}
1449 
1450 	vsc8584_micro_deassert_reset(phydev, false);
1451 
1452 	/* Add one byte to size for the one added by the patch_fw function */
1453 	ret = vsc8584_get_fw_crc(phydev,
1454 				 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1455 				 fw->size + 1, &crc);
1456 	if (ret)
1457 		goto out;
1458 
1459 	if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC)
1460 		dev_warn(dev,
1461 			 "FW CRC after patching is not the expected one, expect non-optimal device\n");
1462 
1463 	ret = vsc8584_micro_assert_reset(phydev);
1464 	if (ret)
1465 		goto out;
1466 
1467 	/* Write patch vector 0, to skip IB cal polling  */
1468 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_GPIO);
1469 	reg = MSCC_ROM_TRAP_SERDES_6G_CFG; /* ROM address to trap, for patch vector 0 */
1470 	ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg);
1471 	if (ret)
1472 		goto out;
1473 
1474 	reg = MSCC_RAM_TRAP_SERDES_6G_CFG; /* RAM address to jump to, when patch vector 0 enabled */
1475 	ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg);
1476 	if (ret)
1477 		goto out;
1478 
1479 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1480 	reg |= PATCH_VEC_ZERO_EN; /* bit 8, enable patch vector 0 */
1481 	ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
1482 	if (ret)
1483 		goto out;
1484 
1485 	vsc8584_micro_deassert_reset(phydev, true);
1486 
1487 out:
1488 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1489 
1490 	release_firmware(fw);
1491 
1492 	return ret;
1493 }
1494 
1495 static void vsc8584_get_base_addr(struct phy_device *phydev)
1496 {
1497 	struct vsc8531_private *vsc8531 = phydev->priv;
1498 	u16 val, addr;
1499 
1500 	phy_lock_mdio_bus(phydev);
1501 	__phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1502 
1503 	addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4);
1504 	addr >>= PHY_CNTL_4_ADDR_POS;
1505 
1506 	val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
1507 
1508 	__phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1509 	phy_unlock_mdio_bus(phydev);
1510 
1511 	/* In the package, there are two pairs of PHYs (PHY0 + PHY2 and
1512 	 * PHY1 + PHY3). The first PHY of each pair (PHY0 and PHY1) is
1513 	 * the base PHY for timestamping operations.
1514 	 */
1515 	vsc8531->ts_base_addr = phydev->mdio.addr;
1516 	vsc8531->ts_base_phy = addr;
1517 
1518 	if (val & PHY_ADDR_REVERSED) {
1519 		vsc8531->base_addr = phydev->mdio.addr + addr;
1520 		if (addr > 1) {
1521 			vsc8531->ts_base_addr += 2;
1522 			vsc8531->ts_base_phy += 2;
1523 		}
1524 	} else {
1525 		vsc8531->base_addr = phydev->mdio.addr - addr;
1526 		if (addr > 1) {
1527 			vsc8531->ts_base_addr -= 2;
1528 			vsc8531->ts_base_phy -= 2;
1529 		}
1530 	}
1531 
1532 	vsc8531->addr = addr;
1533 }
1534 
1535 static void vsc85xx_coma_mode_release(struct phy_device *phydev)
1536 {
1537 	/* The coma mode (pin or reg) provides an optional feature that
1538 	 * may be used to control when the PHYs become active.
1539 	 * Alternatively the COMA_MODE pin may be connected low
1540 	 * so that the PHYs are fully active once out of reset.
1541 	 */
1542 
1543 	/* Enable output (mode=0) and write zero to it */
1544 	vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_EXTENDED_GPIO);
1545 	__phy_modify(phydev, MSCC_PHY_GPIO_CONTROL_2,
1546 		     MSCC_PHY_COMA_MODE | MSCC_PHY_COMA_OUTPUT, 0);
1547 	vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_STANDARD);
1548 }
1549 
1550 static int vsc8584_config_host_serdes(struct phy_device *phydev)
1551 {
1552 	struct vsc8531_private *vsc8531 = phydev->priv;
1553 	int ret;
1554 	u16 val;
1555 
1556 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1557 			     MSCC_PHY_PAGE_EXTENDED_GPIO);
1558 	if (ret)
1559 		return ret;
1560 
1561 	val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1562 	val &= ~MAC_CFG_MASK;
1563 	if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
1564 		val |= MAC_CFG_QSGMII;
1565 	} else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1566 		val |= MAC_CFG_SGMII;
1567 	} else {
1568 		ret = -EINVAL;
1569 		return ret;
1570 	}
1571 
1572 	ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1573 	if (ret)
1574 		return ret;
1575 
1576 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1577 			     MSCC_PHY_PAGE_STANDARD);
1578 	if (ret)
1579 		return ret;
1580 
1581 	val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
1582 		PROC_CMD_READ_MOD_WRITE_PORT;
1583 	if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1584 		val |= PROC_CMD_QSGMII_MAC;
1585 	else
1586 		val |= PROC_CMD_SGMII_MAC;
1587 
1588 	ret = vsc8584_cmd(phydev, val);
1589 	if (ret)
1590 		return ret;
1591 
1592 	usleep_range(10000, 20000);
1593 
1594 	/* Disable SerDes for 100Base-FX */
1595 	ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1596 			  PROC_CMD_FIBER_PORT(vsc8531->addr) |
1597 			  PROC_CMD_FIBER_DISABLE |
1598 			  PROC_CMD_READ_MOD_WRITE_PORT |
1599 			  PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX);
1600 	if (ret)
1601 		return ret;
1602 
1603 	/* Disable SerDes for 1000Base-X */
1604 	ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1605 			  PROC_CMD_FIBER_PORT(vsc8531->addr) |
1606 			  PROC_CMD_FIBER_DISABLE |
1607 			  PROC_CMD_READ_MOD_WRITE_PORT |
1608 			  PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X);
1609 	if (ret)
1610 		return ret;
1611 
1612 	return vsc85xx_sd6g_config_v2(phydev);
1613 }
1614 
1615 static int vsc8574_config_host_serdes(struct phy_device *phydev)
1616 {
1617 	struct vsc8531_private *vsc8531 = phydev->priv;
1618 	int ret;
1619 	u16 val;
1620 
1621 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1622 			     MSCC_PHY_PAGE_EXTENDED_GPIO);
1623 	if (ret)
1624 		return ret;
1625 
1626 	val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1627 	val &= ~MAC_CFG_MASK;
1628 	if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
1629 		val |= MAC_CFG_QSGMII;
1630 	} else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1631 		val |= MAC_CFG_SGMII;
1632 	} else if (phy_interface_is_rgmii(phydev)) {
1633 		val |= MAC_CFG_RGMII;
1634 	} else {
1635 		ret = -EINVAL;
1636 		return ret;
1637 	}
1638 
1639 	ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1640 	if (ret)
1641 		return ret;
1642 
1643 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1644 			     MSCC_PHY_PAGE_STANDARD);
1645 	if (ret)
1646 		return ret;
1647 
1648 	if (!phy_interface_is_rgmii(phydev)) {
1649 		val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
1650 			PROC_CMD_READ_MOD_WRITE_PORT;
1651 		if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1652 			val |= PROC_CMD_QSGMII_MAC;
1653 		else
1654 			val |= PROC_CMD_SGMII_MAC;
1655 
1656 		ret = vsc8584_cmd(phydev, val);
1657 		if (ret)
1658 			return ret;
1659 
1660 		usleep_range(10000, 20000);
1661 	}
1662 
1663 	/* Disable SerDes for 100Base-FX */
1664 	ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1665 			  PROC_CMD_FIBER_PORT(vsc8531->addr) |
1666 			  PROC_CMD_FIBER_DISABLE |
1667 			  PROC_CMD_READ_MOD_WRITE_PORT |
1668 			  PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX);
1669 	if (ret)
1670 		return ret;
1671 
1672 	/* Disable SerDes for 1000Base-X */
1673 	return vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1674 			   PROC_CMD_FIBER_PORT(vsc8531->addr) |
1675 			   PROC_CMD_FIBER_DISABLE |
1676 			   PROC_CMD_READ_MOD_WRITE_PORT |
1677 			   PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X);
1678 }
1679 
1680 static int vsc8584_config_init(struct phy_device *phydev)
1681 {
1682 	struct vsc8531_private *vsc8531 = phydev->priv;
1683 	int ret, i;
1684 	u16 val;
1685 
1686 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1687 
1688 	phy_lock_mdio_bus(phydev);
1689 
1690 	/* Some parts of the init sequence are identical for every PHY in the
1691 	 * package. Some parts are modifying the GPIO register bank which is a
1692 	 * set of registers that are affecting all PHYs, a few resetting the
1693 	 * microprocessor common to all PHYs. The CRC check responsible of the
1694 	 * checking the firmware within the 8051 microprocessor can only be
1695 	 * accessed via the PHY whose internal address in the package is 0.
1696 	 * All PHYs' interrupts mask register has to be zeroed before enabling
1697 	 * any PHY's interrupt in this register.
1698 	 * For all these reasons, we need to do the init sequence once and only
1699 	 * once whatever is the first PHY in the package that is initialized and
1700 	 * do the correct init sequence for all PHYs that are package-critical
1701 	 * in this pre-init function.
1702 	 */
1703 	if (phy_package_init_once(phydev)) {
1704 		/* The following switch statement assumes that the lowest
1705 		 * nibble of the phy_id_mask is always 0. This works because
1706 		 * the lowest nibble of the PHY_ID's below are also 0.
1707 		 */
1708 		WARN_ON(phydev->drv->phy_id_mask & 0xf);
1709 
1710 		switch (phydev->phy_id & phydev->drv->phy_id_mask) {
1711 		case PHY_ID_VSC8504:
1712 		case PHY_ID_VSC8552:
1713 		case PHY_ID_VSC8572:
1714 		case PHY_ID_VSC8574:
1715 			ret = vsc8574_config_pre_init(phydev);
1716 			if (ret)
1717 				goto err;
1718 			ret = vsc8574_config_host_serdes(phydev);
1719 			if (ret)
1720 				goto err;
1721 			break;
1722 		case PHY_ID_VSC856X:
1723 		case PHY_ID_VSC8575:
1724 		case PHY_ID_VSC8582:
1725 		case PHY_ID_VSC8584:
1726 			ret = vsc8584_config_pre_init(phydev);
1727 			if (ret)
1728 				goto err;
1729 			ret = vsc8584_config_host_serdes(phydev);
1730 			if (ret)
1731 				goto err;
1732 			vsc85xx_coma_mode_release(phydev);
1733 			break;
1734 		default:
1735 			ret = -EINVAL;
1736 			break;
1737 		}
1738 
1739 		if (ret)
1740 			goto err;
1741 	}
1742 
1743 	phy_unlock_mdio_bus(phydev);
1744 
1745 	ret = vsc8584_macsec_init(phydev);
1746 	if (ret)
1747 		return ret;
1748 
1749 	ret = vsc8584_ptp_init(phydev);
1750 	if (ret)
1751 		return ret;
1752 
1753 	val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
1754 	val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK);
1755 	val |= (MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS) |
1756 	       (VSC8584_MAC_IF_SELECTION_SGMII << VSC8584_MAC_IF_SELECTION_POS);
1757 	ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val);
1758 	if (ret)
1759 		return ret;
1760 
1761 	if (phy_interface_is_rgmii(phydev)) {
1762 		ret = vsc85xx_rgmii_set_skews(phydev, VSC8572_RGMII_CNTL,
1763 					      VSC8572_RGMII_RX_DELAY_MASK,
1764 					      VSC8572_RGMII_TX_DELAY_MASK);
1765 		if (ret)
1766 			return ret;
1767 	}
1768 
1769 	ret = genphy_soft_reset(phydev);
1770 	if (ret)
1771 		return ret;
1772 
1773 	for (i = 0; i < vsc8531->nleds; i++) {
1774 		ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1775 		if (ret)
1776 			return ret;
1777 	}
1778 
1779 	return 0;
1780 
1781 err:
1782 	phy_unlock_mdio_bus(phydev);
1783 	return ret;
1784 }
1785 
1786 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev)
1787 {
1788 	irqreturn_t ret;
1789 	int irq_status;
1790 
1791 	irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1792 	if (irq_status < 0)
1793 		return IRQ_NONE;
1794 
1795 	/* Timestamping IRQ does not set a bit in the global INT_STATUS, so
1796 	 * irq_status would be 0.
1797 	 */
1798 	ret = vsc8584_handle_ts_interrupt(phydev);
1799 	if (!(irq_status & MII_VSC85XX_INT_MASK_MASK))
1800 		return ret;
1801 
1802 	if (irq_status & MII_VSC85XX_INT_MASK_EXT)
1803 		vsc8584_handle_macsec_interrupt(phydev);
1804 
1805 	if (irq_status & MII_VSC85XX_INT_MASK_LINK_CHG)
1806 		phy_trigger_machine(phydev);
1807 
1808 	return IRQ_HANDLED;
1809 }
1810 
1811 static int vsc85xx_config_init(struct phy_device *phydev)
1812 {
1813 	int rc, i, phy_id;
1814 	struct vsc8531_private *vsc8531 = phydev->priv;
1815 
1816 	rc = vsc85xx_default_config(phydev);
1817 	if (rc)
1818 		return rc;
1819 
1820 	rc = vsc85xx_mac_if_set(phydev, phydev->interface);
1821 	if (rc)
1822 		return rc;
1823 
1824 	rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
1825 	if (rc)
1826 		return rc;
1827 
1828 	phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask;
1829 	if (PHY_ID_VSC8531 == phy_id || PHY_ID_VSC8541 == phy_id ||
1830 	    PHY_ID_VSC8530 == phy_id || PHY_ID_VSC8540 == phy_id) {
1831 		rc = vsc8531_pre_init_seq_set(phydev);
1832 		if (rc)
1833 			return rc;
1834 	}
1835 
1836 	rc = vsc85xx_eee_init_seq_set(phydev);
1837 	if (rc)
1838 		return rc;
1839 
1840 	for (i = 0; i < vsc8531->nleds; i++) {
1841 		rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1842 		if (rc)
1843 			return rc;
1844 	}
1845 
1846 	return 0;
1847 }
1848 
1849 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb,
1850 			       u32 op)
1851 {
1852 	unsigned long deadline;
1853 	u32 val;
1854 	int ret;
1855 
1856 	ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg,
1857 				op | (1 << mcb));
1858 	if (ret)
1859 		return -EINVAL;
1860 
1861 	deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1862 	do {
1863 		usleep_range(500, 1000);
1864 		val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg);
1865 
1866 		if (val == 0xffffffff)
1867 			return -EIO;
1868 
1869 	} while (time_before(jiffies, deadline) && (val & op));
1870 
1871 	if (val & op)
1872 		return -ETIMEDOUT;
1873 
1874 	return 0;
1875 }
1876 
1877 /* Trigger a read to the specified MCB */
1878 int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1879 {
1880 	return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ);
1881 }
1882 
1883 /* Trigger a write to the specified MCB */
1884 int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1885 {
1886 	return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE);
1887 }
1888 
1889 static int vsc8514_config_host_serdes(struct phy_device *phydev)
1890 {
1891 	int ret;
1892 	u16 val;
1893 
1894 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1895 			     MSCC_PHY_PAGE_EXTENDED_GPIO);
1896 	if (ret)
1897 		return ret;
1898 
1899 	val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1900 	val &= ~MAC_CFG_MASK;
1901 	val |= MAC_CFG_QSGMII;
1902 	ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1903 	if (ret)
1904 		return ret;
1905 
1906 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1907 			     MSCC_PHY_PAGE_STANDARD);
1908 	if (ret)
1909 		return ret;
1910 
1911 	ret = vsc8584_cmd(phydev, PROC_CMD_NOP);
1912 	if (ret)
1913 		return ret;
1914 
1915 	ret = vsc8584_cmd(phydev,
1916 			  PROC_CMD_MCB_ACCESS_MAC_CONF |
1917 			  PROC_CMD_RST_CONF_PORT |
1918 			  PROC_CMD_READ_MOD_WRITE_PORT | PROC_CMD_QSGMII_MAC);
1919 	if (ret) {
1920 		dev_err(&phydev->mdio.dev, "%s: QSGMII error: %d\n",
1921 			__func__, ret);
1922 		return ret;
1923 	}
1924 
1925 	/* Apply 6G SerDes FOJI Algorithm
1926 	 *  Initial condition requirement:
1927 	 *  1. hold 8051 in reset
1928 	 *  2. disable patch vector 0, in order to allow IB cal poll during FoJi
1929 	 *  3. deassert 8051 reset after change patch vector status
1930 	 *  4. proceed with FoJi (vsc85xx_sd6g_config_v2)
1931 	 */
1932 	vsc8584_micro_assert_reset(phydev);
1933 	val = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1934 	/* clear bit 8, to disable patch vector 0 */
1935 	val &= ~PATCH_VEC_ZERO_EN;
1936 	ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, val);
1937 	/* Enable 8051 clock, don't set patch present, disable PRAM clock override */
1938 	vsc8584_micro_deassert_reset(phydev, false);
1939 
1940 	return vsc85xx_sd6g_config_v2(phydev);
1941 }
1942 
1943 static int vsc8514_config_pre_init(struct phy_device *phydev)
1944 {
1945 	/* These are the settings to override the silicon default
1946 	 * values to handle hardware performance of PHY. They
1947 	 * are set at Power-On state and remain until PHY Reset.
1948 	 */
1949 	static const struct reg_val pre_init1[] = {
1950 		{0x0f90, 0x00688980},
1951 		{0x0786, 0x00000003},
1952 		{0x07fa, 0x0050100f},
1953 		{0x0f82, 0x0012b002},
1954 		{0x1686, 0x00000004},
1955 		{0x168c, 0x00d2c46f},
1956 		{0x17a2, 0x00000620},
1957 		{0x16a0, 0x00eeffdd},
1958 		{0x16a6, 0x00071448},
1959 		{0x16a4, 0x0013132f},
1960 		{0x16a8, 0x00000000},
1961 		{0x0ffc, 0x00c0a028},
1962 		{0x0fe8, 0x0091b06c},
1963 		{0x0fea, 0x00041600},
1964 		{0x0f80, 0x00fffaff},
1965 		{0x0fec, 0x00901809},
1966 		{0x0ffe, 0x00b01007},
1967 		{0x16b0, 0x00eeff00},
1968 		{0x16b2, 0x00007000},
1969 		{0x16b4, 0x00000814},
1970 	};
1971 	struct device *dev = &phydev->mdio.dev;
1972 	unsigned int i;
1973 	u16 reg;
1974 	int ret;
1975 
1976 	ret = vsc8584_pll5g_reset(phydev);
1977 	if (ret < 0) {
1978 		dev_err(dev, "failed LCPLL reset, ret: %d\n", ret);
1979 		return ret;
1980 	}
1981 
1982 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1983 
1984 	/* all writes below are broadcasted to all PHYs in the same package */
1985 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1986 	reg |= SMI_BROADCAST_WR_EN;
1987 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1988 
1989 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1990 
1991 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1992 	reg |= BIT(15);
1993 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1994 
1995 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1996 
1997 	for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1998 		vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1999 
2000 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
2001 
2002 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
2003 	reg &= ~BIT(15);
2004 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
2005 
2006 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
2007 
2008 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
2009 	reg &= ~SMI_BROADCAST_WR_EN;
2010 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
2011 
2012 	/* Add pre-patching commands to:
2013 	 * 1. enable 8051 clock, operate 8051 clock at 125 MHz
2014 	 * instead of HW default 62.5MHz
2015 	 * 2. write patch vector 0, to skip IB cal polling executed
2016 	 * as part of the 0x80E0 ROM command
2017 	 */
2018 	vsc8584_micro_deassert_reset(phydev, false);
2019 
2020 	vsc8584_micro_assert_reset(phydev);
2021 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
2022 		       MSCC_PHY_PAGE_EXTENDED_GPIO);
2023 	/* ROM address to trap, for patch vector 0 */
2024 	reg = MSCC_ROM_TRAP_SERDES_6G_CFG;
2025 	ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg);
2026 	if (ret)
2027 		goto err;
2028 	/* RAM address to jump to, when patch vector 0 enabled */
2029 	reg = MSCC_RAM_TRAP_SERDES_6G_CFG;
2030 	ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg);
2031 	if (ret)
2032 		goto err;
2033 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
2034 	reg |= PATCH_VEC_ZERO_EN; /* bit 8, enable patch vector 0 */
2035 	ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
2036 	if (ret)
2037 		goto err;
2038 
2039 	/* Enable 8051 clock, don't set patch present
2040 	 * yet, disable PRAM clock override
2041 	 */
2042 	vsc8584_micro_deassert_reset(phydev, false);
2043 	return ret;
2044  err:
2045 	/* restore 8051 and bail w error */
2046 	vsc8584_micro_deassert_reset(phydev, false);
2047 	return ret;
2048 }
2049 
2050 static int vsc8514_config_init(struct phy_device *phydev)
2051 {
2052 	struct vsc8531_private *vsc8531 = phydev->priv;
2053 	int ret, i;
2054 
2055 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
2056 
2057 	phy_lock_mdio_bus(phydev);
2058 
2059 	/* Some parts of the init sequence are identical for every PHY in the
2060 	 * package. Some parts are modifying the GPIO register bank which is a
2061 	 * set of registers that are affecting all PHYs, a few resetting the
2062 	 * microprocessor common to all PHYs.
2063 	 * All PHYs' interrupts mask register has to be zeroed before enabling
2064 	 * any PHY's interrupt in this register.
2065 	 * For all these reasons, we need to do the init sequence once and only
2066 	 * once whatever is the first PHY in the package that is initialized and
2067 	 * do the correct init sequence for all PHYs that are package-critical
2068 	 * in this pre-init function.
2069 	 */
2070 	if (phy_package_init_once(phydev)) {
2071 		ret = vsc8514_config_pre_init(phydev);
2072 		if (ret)
2073 			goto err;
2074 		ret = vsc8514_config_host_serdes(phydev);
2075 		if (ret)
2076 			goto err;
2077 		vsc85xx_coma_mode_release(phydev);
2078 	}
2079 
2080 	phy_unlock_mdio_bus(phydev);
2081 
2082 	ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK,
2083 			 MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS);
2084 
2085 	if (ret)
2086 		return ret;
2087 
2088 	ret = genphy_soft_reset(phydev);
2089 
2090 	if (ret)
2091 		return ret;
2092 
2093 	for (i = 0; i < vsc8531->nleds; i++) {
2094 		ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
2095 		if (ret)
2096 			return ret;
2097 	}
2098 
2099 	return ret;
2100 
2101 err:
2102 	phy_unlock_mdio_bus(phydev);
2103 	return ret;
2104 }
2105 
2106 static int vsc85xx_ack_interrupt(struct phy_device *phydev)
2107 {
2108 	int rc = 0;
2109 
2110 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
2111 		rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2112 
2113 	return (rc < 0) ? rc : 0;
2114 }
2115 
2116 static int vsc85xx_config_intr(struct phy_device *phydev)
2117 {
2118 	int rc;
2119 
2120 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2121 		rc = vsc85xx_ack_interrupt(phydev);
2122 		if (rc)
2123 			return rc;
2124 
2125 		vsc8584_config_macsec_intr(phydev);
2126 		vsc8584_config_ts_intr(phydev);
2127 
2128 		rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
2129 			       MII_VSC85XX_INT_MASK_MASK);
2130 	} else {
2131 		rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
2132 		if (rc < 0)
2133 			return rc;
2134 		rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2135 		if (rc < 0)
2136 			return rc;
2137 
2138 		rc = vsc85xx_ack_interrupt(phydev);
2139 	}
2140 
2141 	return rc;
2142 }
2143 
2144 static irqreturn_t vsc85xx_handle_interrupt(struct phy_device *phydev)
2145 {
2146 	int irq_status;
2147 
2148 	irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2149 	if (irq_status < 0) {
2150 		phy_error(phydev);
2151 		return IRQ_NONE;
2152 	}
2153 
2154 	if (!(irq_status & MII_VSC85XX_INT_MASK_MASK))
2155 		return IRQ_NONE;
2156 
2157 	phy_trigger_machine(phydev);
2158 
2159 	return IRQ_HANDLED;
2160 }
2161 
2162 static int vsc85xx_config_aneg(struct phy_device *phydev)
2163 {
2164 	int rc;
2165 
2166 	rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
2167 	if (rc < 0)
2168 		return rc;
2169 
2170 	return genphy_config_aneg(phydev);
2171 }
2172 
2173 static int vsc85xx_read_status(struct phy_device *phydev)
2174 {
2175 	int rc;
2176 
2177 	rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
2178 	if (rc < 0)
2179 		return rc;
2180 
2181 	return genphy_read_status(phydev);
2182 }
2183 
2184 static int vsc8514_probe(struct phy_device *phydev)
2185 {
2186 	struct vsc8531_private *vsc8531;
2187 	u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2188 	   VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2189 	   VSC8531_DUPLEX_COLLISION};
2190 
2191 	vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2192 	if (!vsc8531)
2193 		return -ENOMEM;
2194 
2195 	phydev->priv = vsc8531;
2196 
2197 	vsc8584_get_base_addr(phydev);
2198 	devm_phy_package_join(&phydev->mdio.dev, phydev,
2199 			      vsc8531->base_addr, 0);
2200 
2201 	vsc8531->nleds = 4;
2202 	vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
2203 	vsc8531->hw_stats = vsc85xx_hw_stats;
2204 	vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
2205 	vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2206 				      sizeof(u64), GFP_KERNEL);
2207 	if (!vsc8531->stats)
2208 		return -ENOMEM;
2209 
2210 	return vsc85xx_dt_led_modes_get(phydev, default_mode);
2211 }
2212 
2213 static int vsc8574_probe(struct phy_device *phydev)
2214 {
2215 	struct vsc8531_private *vsc8531;
2216 	u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2217 	   VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2218 	   VSC8531_DUPLEX_COLLISION};
2219 
2220 	vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2221 	if (!vsc8531)
2222 		return -ENOMEM;
2223 
2224 	phydev->priv = vsc8531;
2225 
2226 	vsc8584_get_base_addr(phydev);
2227 	devm_phy_package_join(&phydev->mdio.dev, phydev,
2228 			      vsc8531->base_addr, 0);
2229 
2230 	vsc8531->nleds = 4;
2231 	vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2232 	vsc8531->hw_stats = vsc8584_hw_stats;
2233 	vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2234 	vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2235 				      sizeof(u64), GFP_KERNEL);
2236 	if (!vsc8531->stats)
2237 		return -ENOMEM;
2238 
2239 	return vsc85xx_dt_led_modes_get(phydev, default_mode);
2240 }
2241 
2242 static int vsc8584_probe(struct phy_device *phydev)
2243 {
2244 	struct vsc8531_private *vsc8531;
2245 	u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2246 	   VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2247 	   VSC8531_DUPLEX_COLLISION};
2248 	int ret;
2249 
2250 	if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) {
2251 		dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n");
2252 		return -ENOTSUPP;
2253 	}
2254 
2255 	vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2256 	if (!vsc8531)
2257 		return -ENOMEM;
2258 
2259 	phydev->priv = vsc8531;
2260 
2261 	vsc8584_get_base_addr(phydev);
2262 	devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr,
2263 			      sizeof(struct vsc85xx_shared_private));
2264 
2265 	vsc8531->nleds = 4;
2266 	vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2267 	vsc8531->hw_stats = vsc8584_hw_stats;
2268 	vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2269 	vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2270 				      sizeof(u64), GFP_KERNEL);
2271 	if (!vsc8531->stats)
2272 		return -ENOMEM;
2273 
2274 	if (phy_package_probe_once(phydev)) {
2275 		ret = vsc8584_ptp_probe_once(phydev);
2276 		if (ret)
2277 			return ret;
2278 	}
2279 
2280 	ret = vsc8584_ptp_probe(phydev);
2281 	if (ret)
2282 		return ret;
2283 
2284 	return vsc85xx_dt_led_modes_get(phydev, default_mode);
2285 }
2286 
2287 static int vsc85xx_probe(struct phy_device *phydev)
2288 {
2289 	struct vsc8531_private *vsc8531;
2290 	int rate_magic;
2291 	u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY,
2292 	   VSC8531_LINK_100_ACTIVITY};
2293 
2294 	rate_magic = vsc85xx_edge_rate_magic_get(phydev);
2295 	if (rate_magic < 0)
2296 		return rate_magic;
2297 
2298 	vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2299 	if (!vsc8531)
2300 		return -ENOMEM;
2301 
2302 	phydev->priv = vsc8531;
2303 
2304 	vsc8531->rate_magic = rate_magic;
2305 	vsc8531->nleds = 2;
2306 	vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
2307 	vsc8531->hw_stats = vsc85xx_hw_stats;
2308 	vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
2309 	vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2310 				      sizeof(u64), GFP_KERNEL);
2311 	if (!vsc8531->stats)
2312 		return -ENOMEM;
2313 
2314 	return vsc85xx_dt_led_modes_get(phydev, default_mode);
2315 }
2316 
2317 /* Microsemi VSC85xx PHYs */
2318 static struct phy_driver vsc85xx_driver[] = {
2319 {
2320 	.phy_id		= PHY_ID_VSC8502,
2321 	.name		= "Microsemi GE VSC8502 SyncE",
2322 	.phy_id_mask	= 0xfffffff0,
2323 	/* PHY_BASIC_FEATURES */
2324 	.soft_reset	= &genphy_soft_reset,
2325 	.config_init	= &vsc85xx_config_init,
2326 	.config_aneg    = &vsc85xx_config_aneg,
2327 	.read_status	= &vsc85xx_read_status,
2328 	.handle_interrupt = vsc85xx_handle_interrupt,
2329 	.config_intr	= &vsc85xx_config_intr,
2330 	.suspend	= &genphy_suspend,
2331 	.resume		= &genphy_resume,
2332 	.probe		= &vsc85xx_probe,
2333 	.set_wol	= &vsc85xx_wol_set,
2334 	.get_wol	= &vsc85xx_wol_get,
2335 	.get_tunable	= &vsc85xx_get_tunable,
2336 	.set_tunable	= &vsc85xx_set_tunable,
2337 	.read_page	= &vsc85xx_phy_read_page,
2338 	.write_page	= &vsc85xx_phy_write_page,
2339 	.get_sset_count = &vsc85xx_get_sset_count,
2340 	.get_strings    = &vsc85xx_get_strings,
2341 	.get_stats      = &vsc85xx_get_stats,
2342 },
2343 {
2344 	.phy_id		= PHY_ID_VSC8504,
2345 	.name		= "Microsemi GE VSC8504 SyncE",
2346 	.phy_id_mask	= 0xfffffff0,
2347 	/* PHY_GBIT_FEATURES */
2348 	.soft_reset	= &genphy_soft_reset,
2349 	.config_init    = &vsc8584_config_init,
2350 	.config_aneg    = &vsc85xx_config_aneg,
2351 	.aneg_done	= &genphy_aneg_done,
2352 	.read_status	= &vsc85xx_read_status,
2353 	.handle_interrupt = vsc85xx_handle_interrupt,
2354 	.config_intr    = &vsc85xx_config_intr,
2355 	.suspend	= &genphy_suspend,
2356 	.resume		= &genphy_resume,
2357 	.probe		= &vsc8574_probe,
2358 	.set_wol	= &vsc85xx_wol_set,
2359 	.get_wol	= &vsc85xx_wol_get,
2360 	.get_tunable	= &vsc85xx_get_tunable,
2361 	.set_tunable	= &vsc85xx_set_tunable,
2362 	.read_page	= &vsc85xx_phy_read_page,
2363 	.write_page	= &vsc85xx_phy_write_page,
2364 	.get_sset_count = &vsc85xx_get_sset_count,
2365 	.get_strings    = &vsc85xx_get_strings,
2366 	.get_stats      = &vsc85xx_get_stats,
2367 },
2368 {
2369 	.phy_id		= PHY_ID_VSC8514,
2370 	.name		= "Microsemi GE VSC8514 SyncE",
2371 	.phy_id_mask	= 0xfffffff0,
2372 	.soft_reset	= &genphy_soft_reset,
2373 	.config_init    = &vsc8514_config_init,
2374 	.config_aneg    = &vsc85xx_config_aneg,
2375 	.read_status	= &vsc85xx_read_status,
2376 	.handle_interrupt = vsc85xx_handle_interrupt,
2377 	.config_intr    = &vsc85xx_config_intr,
2378 	.suspend	= &genphy_suspend,
2379 	.resume		= &genphy_resume,
2380 	.probe		= &vsc8514_probe,
2381 	.set_wol	= &vsc85xx_wol_set,
2382 	.get_wol	= &vsc85xx_wol_get,
2383 	.get_tunable	= &vsc85xx_get_tunable,
2384 	.set_tunable	= &vsc85xx_set_tunable,
2385 	.read_page      = &vsc85xx_phy_read_page,
2386 	.write_page     = &vsc85xx_phy_write_page,
2387 	.get_sset_count = &vsc85xx_get_sset_count,
2388 	.get_strings    = &vsc85xx_get_strings,
2389 	.get_stats      = &vsc85xx_get_stats,
2390 },
2391 {
2392 	.phy_id		= PHY_ID_VSC8530,
2393 	.name		= "Microsemi FE VSC8530",
2394 	.phy_id_mask	= 0xfffffff0,
2395 	/* PHY_BASIC_FEATURES */
2396 	.soft_reset	= &genphy_soft_reset,
2397 	.config_init	= &vsc85xx_config_init,
2398 	.config_aneg    = &vsc85xx_config_aneg,
2399 	.read_status	= &vsc85xx_read_status,
2400 	.handle_interrupt = vsc85xx_handle_interrupt,
2401 	.config_intr	= &vsc85xx_config_intr,
2402 	.suspend	= &genphy_suspend,
2403 	.resume		= &genphy_resume,
2404 	.probe		= &vsc85xx_probe,
2405 	.set_wol	= &vsc85xx_wol_set,
2406 	.get_wol	= &vsc85xx_wol_get,
2407 	.get_tunable	= &vsc85xx_get_tunable,
2408 	.set_tunable	= &vsc85xx_set_tunable,
2409 	.read_page	= &vsc85xx_phy_read_page,
2410 	.write_page	= &vsc85xx_phy_write_page,
2411 	.get_sset_count = &vsc85xx_get_sset_count,
2412 	.get_strings    = &vsc85xx_get_strings,
2413 	.get_stats      = &vsc85xx_get_stats,
2414 },
2415 {
2416 	.phy_id		= PHY_ID_VSC8531,
2417 	.name		= "Microsemi VSC8531",
2418 	.phy_id_mask    = 0xfffffff0,
2419 	/* PHY_GBIT_FEATURES */
2420 	.soft_reset	= &genphy_soft_reset,
2421 	.config_init    = &vsc85xx_config_init,
2422 	.config_aneg    = &vsc85xx_config_aneg,
2423 	.read_status	= &vsc85xx_read_status,
2424 	.handle_interrupt = vsc85xx_handle_interrupt,
2425 	.config_intr    = &vsc85xx_config_intr,
2426 	.suspend	= &genphy_suspend,
2427 	.resume		= &genphy_resume,
2428 	.probe		= &vsc85xx_probe,
2429 	.set_wol	= &vsc85xx_wol_set,
2430 	.get_wol	= &vsc85xx_wol_get,
2431 	.get_tunable	= &vsc85xx_get_tunable,
2432 	.set_tunable	= &vsc85xx_set_tunable,
2433 	.read_page	= &vsc85xx_phy_read_page,
2434 	.write_page	= &vsc85xx_phy_write_page,
2435 	.get_sset_count = &vsc85xx_get_sset_count,
2436 	.get_strings    = &vsc85xx_get_strings,
2437 	.get_stats      = &vsc85xx_get_stats,
2438 },
2439 {
2440 	.phy_id		= PHY_ID_VSC8540,
2441 	.name		= "Microsemi FE VSC8540 SyncE",
2442 	.phy_id_mask	= 0xfffffff0,
2443 	/* PHY_BASIC_FEATURES */
2444 	.soft_reset	= &genphy_soft_reset,
2445 	.config_init	= &vsc85xx_config_init,
2446 	.config_aneg	= &vsc85xx_config_aneg,
2447 	.read_status	= &vsc85xx_read_status,
2448 	.handle_interrupt = vsc85xx_handle_interrupt,
2449 	.config_intr	= &vsc85xx_config_intr,
2450 	.suspend	= &genphy_suspend,
2451 	.resume		= &genphy_resume,
2452 	.probe		= &vsc85xx_probe,
2453 	.set_wol	= &vsc85xx_wol_set,
2454 	.get_wol	= &vsc85xx_wol_get,
2455 	.get_tunable	= &vsc85xx_get_tunable,
2456 	.set_tunable	= &vsc85xx_set_tunable,
2457 	.read_page	= &vsc85xx_phy_read_page,
2458 	.write_page	= &vsc85xx_phy_write_page,
2459 	.get_sset_count = &vsc85xx_get_sset_count,
2460 	.get_strings    = &vsc85xx_get_strings,
2461 	.get_stats      = &vsc85xx_get_stats,
2462 },
2463 {
2464 	.phy_id		= PHY_ID_VSC8541,
2465 	.name		= "Microsemi VSC8541 SyncE",
2466 	.phy_id_mask    = 0xfffffff0,
2467 	/* PHY_GBIT_FEATURES */
2468 	.soft_reset	= &genphy_soft_reset,
2469 	.config_init    = &vsc85xx_config_init,
2470 	.config_aneg    = &vsc85xx_config_aneg,
2471 	.read_status	= &vsc85xx_read_status,
2472 	.handle_interrupt = vsc85xx_handle_interrupt,
2473 	.config_intr    = &vsc85xx_config_intr,
2474 	.suspend	= &genphy_suspend,
2475 	.resume		= &genphy_resume,
2476 	.probe		= &vsc85xx_probe,
2477 	.set_wol	= &vsc85xx_wol_set,
2478 	.get_wol	= &vsc85xx_wol_get,
2479 	.get_tunable	= &vsc85xx_get_tunable,
2480 	.set_tunable	= &vsc85xx_set_tunable,
2481 	.read_page	= &vsc85xx_phy_read_page,
2482 	.write_page	= &vsc85xx_phy_write_page,
2483 	.get_sset_count = &vsc85xx_get_sset_count,
2484 	.get_strings    = &vsc85xx_get_strings,
2485 	.get_stats      = &vsc85xx_get_stats,
2486 },
2487 {
2488 	.phy_id		= PHY_ID_VSC8552,
2489 	.name		= "Microsemi GE VSC8552 SyncE",
2490 	.phy_id_mask	= 0xfffffff0,
2491 	/* PHY_GBIT_FEATURES */
2492 	.soft_reset	= &genphy_soft_reset,
2493 	.config_init    = &vsc8584_config_init,
2494 	.config_aneg    = &vsc85xx_config_aneg,
2495 	.read_status	= &vsc85xx_read_status,
2496 	.handle_interrupt = vsc85xx_handle_interrupt,
2497 	.config_intr    = &vsc85xx_config_intr,
2498 	.suspend	= &genphy_suspend,
2499 	.resume		= &genphy_resume,
2500 	.probe		= &vsc8574_probe,
2501 	.set_wol	= &vsc85xx_wol_set,
2502 	.get_wol	= &vsc85xx_wol_get,
2503 	.get_tunable	= &vsc85xx_get_tunable,
2504 	.set_tunable	= &vsc85xx_set_tunable,
2505 	.read_page	= &vsc85xx_phy_read_page,
2506 	.write_page	= &vsc85xx_phy_write_page,
2507 	.get_sset_count = &vsc85xx_get_sset_count,
2508 	.get_strings    = &vsc85xx_get_strings,
2509 	.get_stats      = &vsc85xx_get_stats,
2510 },
2511 {
2512 	.phy_id		= PHY_ID_VSC856X,
2513 	.name		= "Microsemi GE VSC856X SyncE",
2514 	.phy_id_mask	= 0xfffffff0,
2515 	/* PHY_GBIT_FEATURES */
2516 	.soft_reset	= &genphy_soft_reset,
2517 	.config_init    = &vsc8584_config_init,
2518 	.config_aneg    = &vsc85xx_config_aneg,
2519 	.read_status	= &vsc85xx_read_status,
2520 	.handle_interrupt = vsc85xx_handle_interrupt,
2521 	.config_intr    = &vsc85xx_config_intr,
2522 	.suspend	= &genphy_suspend,
2523 	.resume		= &genphy_resume,
2524 	.probe		= &vsc8584_probe,
2525 	.get_tunable	= &vsc85xx_get_tunable,
2526 	.set_tunable	= &vsc85xx_set_tunable,
2527 	.read_page	= &vsc85xx_phy_read_page,
2528 	.write_page	= &vsc85xx_phy_write_page,
2529 	.get_sset_count = &vsc85xx_get_sset_count,
2530 	.get_strings    = &vsc85xx_get_strings,
2531 	.get_stats      = &vsc85xx_get_stats,
2532 },
2533 {
2534 	.phy_id		= PHY_ID_VSC8572,
2535 	.name		= "Microsemi GE VSC8572 SyncE",
2536 	.phy_id_mask	= 0xfffffff0,
2537 	/* PHY_GBIT_FEATURES */
2538 	.soft_reset	= &genphy_soft_reset,
2539 	.config_init    = &vsc8584_config_init,
2540 	.config_aneg    = &vsc85xx_config_aneg,
2541 	.aneg_done	= &genphy_aneg_done,
2542 	.read_status	= &vsc85xx_read_status,
2543 	.handle_interrupt = &vsc8584_handle_interrupt,
2544 	.config_intr    = &vsc85xx_config_intr,
2545 	.suspend	= &genphy_suspend,
2546 	.resume		= &genphy_resume,
2547 	.probe		= &vsc8574_probe,
2548 	.set_wol	= &vsc85xx_wol_set,
2549 	.get_wol	= &vsc85xx_wol_get,
2550 	.get_tunable	= &vsc85xx_get_tunable,
2551 	.set_tunable	= &vsc85xx_set_tunable,
2552 	.read_page	= &vsc85xx_phy_read_page,
2553 	.write_page	= &vsc85xx_phy_write_page,
2554 	.get_sset_count = &vsc85xx_get_sset_count,
2555 	.get_strings    = &vsc85xx_get_strings,
2556 	.get_stats      = &vsc85xx_get_stats,
2557 },
2558 {
2559 	.phy_id		= PHY_ID_VSC8574,
2560 	.name		= "Microsemi GE VSC8574 SyncE",
2561 	.phy_id_mask	= 0xfffffff0,
2562 	/* PHY_GBIT_FEATURES */
2563 	.soft_reset	= &genphy_soft_reset,
2564 	.config_init    = &vsc8584_config_init,
2565 	.config_aneg    = &vsc85xx_config_aneg,
2566 	.aneg_done	= &genphy_aneg_done,
2567 	.read_status	= &vsc85xx_read_status,
2568 	.handle_interrupt = vsc85xx_handle_interrupt,
2569 	.config_intr    = &vsc85xx_config_intr,
2570 	.suspend	= &genphy_suspend,
2571 	.resume		= &genphy_resume,
2572 	.probe		= &vsc8574_probe,
2573 	.set_wol	= &vsc85xx_wol_set,
2574 	.get_wol	= &vsc85xx_wol_get,
2575 	.get_tunable	= &vsc85xx_get_tunable,
2576 	.set_tunable	= &vsc85xx_set_tunable,
2577 	.read_page	= &vsc85xx_phy_read_page,
2578 	.write_page	= &vsc85xx_phy_write_page,
2579 	.get_sset_count = &vsc85xx_get_sset_count,
2580 	.get_strings    = &vsc85xx_get_strings,
2581 	.get_stats      = &vsc85xx_get_stats,
2582 },
2583 {
2584 	.phy_id		= PHY_ID_VSC8575,
2585 	.name		= "Microsemi GE VSC8575 SyncE",
2586 	.phy_id_mask	= 0xfffffff0,
2587 	/* PHY_GBIT_FEATURES */
2588 	.soft_reset	= &genphy_soft_reset,
2589 	.config_init    = &vsc8584_config_init,
2590 	.config_aneg    = &vsc85xx_config_aneg,
2591 	.aneg_done	= &genphy_aneg_done,
2592 	.read_status	= &vsc85xx_read_status,
2593 	.handle_interrupt = &vsc8584_handle_interrupt,
2594 	.config_intr    = &vsc85xx_config_intr,
2595 	.suspend	= &genphy_suspend,
2596 	.resume		= &genphy_resume,
2597 	.probe		= &vsc8584_probe,
2598 	.get_tunable	= &vsc85xx_get_tunable,
2599 	.set_tunable	= &vsc85xx_set_tunable,
2600 	.read_page	= &vsc85xx_phy_read_page,
2601 	.write_page	= &vsc85xx_phy_write_page,
2602 	.get_sset_count = &vsc85xx_get_sset_count,
2603 	.get_strings    = &vsc85xx_get_strings,
2604 	.get_stats      = &vsc85xx_get_stats,
2605 },
2606 {
2607 	.phy_id		= PHY_ID_VSC8582,
2608 	.name		= "Microsemi GE VSC8582 SyncE",
2609 	.phy_id_mask	= 0xfffffff0,
2610 	/* PHY_GBIT_FEATURES */
2611 	.soft_reset	= &genphy_soft_reset,
2612 	.config_init    = &vsc8584_config_init,
2613 	.config_aneg    = &vsc85xx_config_aneg,
2614 	.aneg_done	= &genphy_aneg_done,
2615 	.read_status	= &vsc85xx_read_status,
2616 	.handle_interrupt = &vsc8584_handle_interrupt,
2617 	.config_intr    = &vsc85xx_config_intr,
2618 	.suspend	= &genphy_suspend,
2619 	.resume		= &genphy_resume,
2620 	.probe		= &vsc8584_probe,
2621 	.get_tunable	= &vsc85xx_get_tunable,
2622 	.set_tunable	= &vsc85xx_set_tunable,
2623 	.read_page	= &vsc85xx_phy_read_page,
2624 	.write_page	= &vsc85xx_phy_write_page,
2625 	.get_sset_count = &vsc85xx_get_sset_count,
2626 	.get_strings    = &vsc85xx_get_strings,
2627 	.get_stats      = &vsc85xx_get_stats,
2628 },
2629 {
2630 	.phy_id		= PHY_ID_VSC8584,
2631 	.name		= "Microsemi GE VSC8584 SyncE",
2632 	.phy_id_mask	= 0xfffffff0,
2633 	/* PHY_GBIT_FEATURES */
2634 	.soft_reset	= &genphy_soft_reset,
2635 	.config_init    = &vsc8584_config_init,
2636 	.config_aneg    = &vsc85xx_config_aneg,
2637 	.aneg_done	= &genphy_aneg_done,
2638 	.read_status	= &vsc85xx_read_status,
2639 	.handle_interrupt = &vsc8584_handle_interrupt,
2640 	.config_intr    = &vsc85xx_config_intr,
2641 	.suspend	= &genphy_suspend,
2642 	.resume		= &genphy_resume,
2643 	.probe		= &vsc8584_probe,
2644 	.get_tunable	= &vsc85xx_get_tunable,
2645 	.set_tunable	= &vsc85xx_set_tunable,
2646 	.read_page	= &vsc85xx_phy_read_page,
2647 	.write_page	= &vsc85xx_phy_write_page,
2648 	.get_sset_count = &vsc85xx_get_sset_count,
2649 	.get_strings    = &vsc85xx_get_strings,
2650 	.get_stats      = &vsc85xx_get_stats,
2651 	.link_change_notify = &vsc85xx_link_change_notify,
2652 }
2653 
2654 };
2655 
2656 module_phy_driver(vsc85xx_driver);
2657 
2658 static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
2659 	{ PHY_ID_VSC8504, 0xfffffff0, },
2660 	{ PHY_ID_VSC8514, 0xfffffff0, },
2661 	{ PHY_ID_VSC8530, 0xfffffff0, },
2662 	{ PHY_ID_VSC8531, 0xfffffff0, },
2663 	{ PHY_ID_VSC8540, 0xfffffff0, },
2664 	{ PHY_ID_VSC8541, 0xfffffff0, },
2665 	{ PHY_ID_VSC8552, 0xfffffff0, },
2666 	{ PHY_ID_VSC856X, 0xfffffff0, },
2667 	{ PHY_ID_VSC8572, 0xfffffff0, },
2668 	{ PHY_ID_VSC8574, 0xfffffff0, },
2669 	{ PHY_ID_VSC8575, 0xfffffff0, },
2670 	{ PHY_ID_VSC8582, 0xfffffff0, },
2671 	{ PHY_ID_VSC8584, 0xfffffff0, },
2672 	{ }
2673 };
2674 
2675 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
2676 
2677 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver");
2678 MODULE_AUTHOR("Nagaraju Lakkaraju");
2679 MODULE_LICENSE("Dual MIT/GPL");
2680 
2681 MODULE_FIRMWARE(MSCC_VSC8584_REVB_INT8051_FW);
2682 MODULE_FIRMWARE(MSCC_VSC8574_REVB_INT8051_FW);
2683