xref: /openbmc/linux/drivers/clk/qcom/clk-alpha-pll.h (revision d088d6b6)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 
8 #ifndef __QCOM_CLK_ALPHA_PLL_H__
9 #define __QCOM_CLK_ALPHA_PLL_H__
10 
11 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
13 
14 /* Alpha PLL types */
15 enum {
16 	CLK_ALPHA_PLL_TYPE_DEFAULT,
17 	CLK_ALPHA_PLL_TYPE_HUAYRA,
18 	CLK_ALPHA_PLL_TYPE_BRAMMO,
19 	CLK_ALPHA_PLL_TYPE_FABIA,
20 	CLK_ALPHA_PLL_TYPE_TRION,
21 	CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
22 	CLK_ALPHA_PLL_TYPE_AGERA,
23 	CLK_ALPHA_PLL_TYPE_ZONDA,
24 	CLK_ALPHA_PLL_TYPE_LUCID_EVO,
25 	CLK_ALPHA_PLL_TYPE_LUCID_OLE,
26 	CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
27 	CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
28 	CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
29 	CLK_ALPHA_PLL_TYPE_STROMER,
30 	CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
31 	CLK_ALPHA_PLL_TYPE_MAX,
32 };
33 
34 enum {
35 	PLL_OFF_L_VAL,
36 	PLL_OFF_CAL_L_VAL,
37 	PLL_OFF_ALPHA_VAL,
38 	PLL_OFF_ALPHA_VAL_U,
39 	PLL_OFF_USER_CTL,
40 	PLL_OFF_USER_CTL_U,
41 	PLL_OFF_USER_CTL_U1,
42 	PLL_OFF_CONFIG_CTL,
43 	PLL_OFF_CONFIG_CTL_U,
44 	PLL_OFF_CONFIG_CTL_U1,
45 	PLL_OFF_TEST_CTL,
46 	PLL_OFF_TEST_CTL_U,
47 	PLL_OFF_TEST_CTL_U1,
48 	PLL_OFF_TEST_CTL_U2,
49 	PLL_OFF_STATE,
50 	PLL_OFF_STATUS,
51 	PLL_OFF_OPMODE,
52 	PLL_OFF_FRAC,
53 	PLL_OFF_CAL_VAL,
54 	PLL_OFF_MAX_REGS
55 };
56 
57 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
58 
59 struct pll_vco {
60 	unsigned long min_freq;
61 	unsigned long max_freq;
62 	u32 val;
63 };
64 
65 #define VCO(a, b, c) { \
66 	.val = a,\
67 	.min_freq = b,\
68 	.max_freq = c,\
69 }
70 
71 /**
72  * struct clk_alpha_pll - phase locked loop (PLL)
73  * @offset: base address of registers
74  * @vco_table: array of VCO settings
75  * @regs: alpha pll register map (see @clk_alpha_pll_regs)
76  * @clkr: regmap clock handle
77  */
78 struct clk_alpha_pll {
79 	u32 offset;
80 	const u8 *regs;
81 
82 	const struct pll_vco *vco_table;
83 	size_t num_vco;
84 #define SUPPORTS_OFFLINE_REQ		BIT(0)
85 #define SUPPORTS_FSM_MODE		BIT(2)
86 #define SUPPORTS_DYNAMIC_UPDATE	BIT(3)
87 #define SUPPORTS_FSM_LEGACY_MODE	BIT(4)
88 	u8 flags;
89 
90 	struct clk_regmap clkr;
91 };
92 
93 /**
94  * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
95  * @offset: base address of registers
96  * @regs: alpha pll register map (see @clk_alpha_pll_regs)
97  * @width: width of post-divider
98  * @post_div_shift: shift to differentiate between odd & even post-divider
99  * @post_div_table: table with PLL odd and even post-divider settings
100  * @num_post_div: Number of PLL post-divider settings
101  *
102  * @clkr: regmap clock handle
103  */
104 struct clk_alpha_pll_postdiv {
105 	u32 offset;
106 	u8 width;
107 	const u8 *regs;
108 
109 	struct clk_regmap clkr;
110 	int post_div_shift;
111 	const struct clk_div_table *post_div_table;
112 	size_t num_post_div;
113 };
114 
115 struct alpha_pll_config {
116 	u32 l;
117 	u32 alpha;
118 	u32 alpha_hi;
119 	u32 config_ctl_val;
120 	u32 config_ctl_hi_val;
121 	u32 config_ctl_hi1_val;
122 	u32 user_ctl_val;
123 	u32 user_ctl_hi_val;
124 	u32 user_ctl_hi1_val;
125 	u32 test_ctl_val;
126 	u32 test_ctl_mask;
127 	u32 test_ctl_hi_val;
128 	u32 test_ctl_hi_mask;
129 	u32 test_ctl_hi1_val;
130 	u32 test_ctl_hi2_val;
131 	u32 main_output_mask;
132 	u32 aux_output_mask;
133 	u32 aux2_output_mask;
134 	u32 early_output_mask;
135 	u32 alpha_en_mask;
136 	u32 alpha_mode_mask;
137 	u32 pre_div_val;
138 	u32 pre_div_mask;
139 	u32 post_div_val;
140 	u32 post_div_mask;
141 	u32 vco_val;
142 	u32 vco_mask;
143 	u32 status_val;
144 	u32 status_mask;
145 	u32 lock_det;
146 };
147 
148 extern const struct clk_ops clk_alpha_pll_ops;
149 extern const struct clk_ops clk_alpha_pll_fixed_ops;
150 extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
151 extern const struct clk_ops clk_alpha_pll_postdiv_ops;
152 extern const struct clk_ops clk_alpha_pll_huayra_ops;
153 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
154 extern const struct clk_ops clk_alpha_pll_stromer_ops;
155 
156 extern const struct clk_ops clk_alpha_pll_fabia_ops;
157 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
158 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
159 
160 extern const struct clk_ops clk_alpha_pll_trion_ops;
161 extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
162 extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
163 
164 extern const struct clk_ops clk_alpha_pll_lucid_ops;
165 #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
166 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
167 extern const struct clk_ops clk_alpha_pll_agera_ops;
168 
169 extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
170 extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
171 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
172 
173 extern const struct clk_ops clk_alpha_pll_zonda_ops;
174 #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
175 
176 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
177 extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
178 #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops
179 extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
180 #define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops
181 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
182 #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops
183 
184 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
185 #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
186 
187 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
188 			     const struct alpha_pll_config *config);
189 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
190 				const struct alpha_pll_config *config);
191 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
192 			     const struct alpha_pll_config *config);
193 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
194 				const struct alpha_pll_config *config);
195 #define clk_lucid_pll_configure(pll, regmap, config) \
196 	clk_trion_pll_configure(pll, regmap, config)
197 
198 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
199 			     const struct alpha_pll_config *config);
200 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
201 				 const struct alpha_pll_config *config);
202 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
203 				  const struct alpha_pll_config *config);
204 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
205 			       const struct alpha_pll_config *config);
206 
207 #endif
208