1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/math.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/tty.h> 18 #include <linux/serial_reg.h> 19 #include <linux/serial_core.h> 20 #include <linux/8250_pci.h> 21 #include <linux/bitops.h> 22 23 #include <asm/byteorder.h> 24 #include <asm/io.h> 25 26 #include "8250.h" 27 28 /* 29 * init function returns: 30 * > 0 - number of ports 31 * = 0 - use board->num_ports 32 * < 0 - error 33 */ 34 struct pci_serial_quirk { 35 u32 vendor; 36 u32 device; 37 u32 subvendor; 38 u32 subdevice; 39 int (*probe)(struct pci_dev *dev); 40 int (*init)(struct pci_dev *dev); 41 int (*setup)(struct serial_private *, 42 const struct pciserial_board *, 43 struct uart_8250_port *, int); 44 void (*exit)(struct pci_dev *dev); 45 }; 46 47 struct f815xxa_data { 48 spinlock_t lock; 49 int idx; 50 }; 51 52 struct serial_private { 53 struct pci_dev *dev; 54 unsigned int nr; 55 struct pci_serial_quirk *quirk; 56 const struct pciserial_board *board; 57 int line[]; 58 }; 59 60 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 61 62 static const struct pci_device_id pci_use_msi[] = { 63 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 64 0xA000, 0x1000) }, 65 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 66 0xA000, 0x1000) }, 67 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 68 0xA000, 0x1000) }, 69 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 70 PCI_ANY_ID, PCI_ANY_ID) }, 71 { } 72 }; 73 74 static int pci_default_setup(struct serial_private*, 75 const struct pciserial_board*, struct uart_8250_port *, int); 76 77 static void moan_device(const char *str, struct pci_dev *dev) 78 { 79 pci_err(dev, "%s\n" 80 "Please send the output of lspci -vv, this\n" 81 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 82 "manufacturer and name of serial board or\n" 83 "modem board to <linux-serial@vger.kernel.org>.\n", 84 str, dev->vendor, dev->device, 85 dev->subsystem_vendor, dev->subsystem_device); 86 } 87 88 static int 89 setup_port(struct serial_private *priv, struct uart_8250_port *port, 90 u8 bar, unsigned int offset, int regshift) 91 { 92 struct pci_dev *dev = priv->dev; 93 94 if (bar >= PCI_STD_NUM_BARS) 95 return -EINVAL; 96 97 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 98 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) 99 return -ENOMEM; 100 101 port->port.iotype = UPIO_MEM; 102 port->port.iobase = 0; 103 port->port.mapbase = pci_resource_start(dev, bar) + offset; 104 port->port.membase = pcim_iomap_table(dev)[bar] + offset; 105 port->port.regshift = regshift; 106 } else { 107 port->port.iotype = UPIO_PORT; 108 port->port.iobase = pci_resource_start(dev, bar) + offset; 109 port->port.mapbase = 0; 110 port->port.membase = NULL; 111 port->port.regshift = 0; 112 } 113 return 0; 114 } 115 116 /* 117 * ADDI-DATA GmbH communication cards <info@addi-data.com> 118 */ 119 static int addidata_apci7800_setup(struct serial_private *priv, 120 const struct pciserial_board *board, 121 struct uart_8250_port *port, int idx) 122 { 123 unsigned int bar = 0, offset = board->first_offset; 124 bar = FL_GET_BASE(board->flags); 125 126 if (idx < 2) { 127 offset += idx * board->uart_offset; 128 } else if ((idx >= 2) && (idx < 4)) { 129 bar += 1; 130 offset += ((idx - 2) * board->uart_offset); 131 } else if ((idx >= 4) && (idx < 6)) { 132 bar += 2; 133 offset += ((idx - 4) * board->uart_offset); 134 } else if (idx >= 6) { 135 bar += 3; 136 offset += ((idx - 6) * board->uart_offset); 137 } 138 139 return setup_port(priv, port, bar, offset, board->reg_shift); 140 } 141 142 /* 143 * AFAVLAB uses a different mixture of BARs and offsets 144 * Not that ugly ;) -- HW 145 */ 146 static int 147 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 148 struct uart_8250_port *port, int idx) 149 { 150 unsigned int bar, offset = board->first_offset; 151 152 bar = FL_GET_BASE(board->flags); 153 if (idx < 4) 154 bar += idx; 155 else { 156 bar = 4; 157 offset += (idx - 4) * board->uart_offset; 158 } 159 160 return setup_port(priv, port, bar, offset, board->reg_shift); 161 } 162 163 /* 164 * HP's Remote Management Console. The Diva chip came in several 165 * different versions. N-class, L2000 and A500 have two Diva chips, each 166 * with 3 UARTs (the third UART on the second chip is unused). Superdome 167 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 168 * one Diva chip, but it has been expanded to 5 UARTs. 169 */ 170 static int pci_hp_diva_init(struct pci_dev *dev) 171 { 172 int rc = 0; 173 174 switch (dev->subsystem_device) { 175 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 176 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 177 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 178 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 179 rc = 3; 180 break; 181 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 182 rc = 2; 183 break; 184 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 185 rc = 4; 186 break; 187 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 188 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 189 rc = 1; 190 break; 191 } 192 193 return rc; 194 } 195 196 /* 197 * HP's Diva chip puts the 4th/5th serial port further out, and 198 * some serial ports are supposed to be hidden on certain models. 199 */ 200 static int 201 pci_hp_diva_setup(struct serial_private *priv, 202 const struct pciserial_board *board, 203 struct uart_8250_port *port, int idx) 204 { 205 unsigned int offset = board->first_offset; 206 unsigned int bar = FL_GET_BASE(board->flags); 207 208 switch (priv->dev->subsystem_device) { 209 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 210 if (idx == 3) 211 idx++; 212 break; 213 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 214 if (idx > 0) 215 idx++; 216 if (idx > 2) 217 idx++; 218 break; 219 } 220 if (idx > 2) 221 offset = 0x18; 222 223 offset += idx * board->uart_offset; 224 225 return setup_port(priv, port, bar, offset, board->reg_shift); 226 } 227 228 /* 229 * Added for EKF Intel i960 serial boards 230 */ 231 static int pci_inteli960ni_init(struct pci_dev *dev) 232 { 233 u32 oldval; 234 235 if (!(dev->subsystem_device & 0x1000)) 236 return -ENODEV; 237 238 /* is firmware started? */ 239 pci_read_config_dword(dev, 0x44, &oldval); 240 if (oldval == 0x00001000L) { /* RESET value */ 241 pci_dbg(dev, "Local i960 firmware missing\n"); 242 return -ENODEV; 243 } 244 return 0; 245 } 246 247 /* 248 * Some PCI serial cards using the PLX 9050 PCI interface chip require 249 * that the card interrupt be explicitly enabled or disabled. This 250 * seems to be mainly needed on card using the PLX which also use I/O 251 * mapped memory. 252 */ 253 static int pci_plx9050_init(struct pci_dev *dev) 254 { 255 u8 irq_config; 256 void __iomem *p; 257 258 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 259 moan_device("no memory in bar 0", dev); 260 return 0; 261 } 262 263 irq_config = 0x41; 264 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 265 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 266 irq_config = 0x43; 267 268 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 269 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 270 /* 271 * As the megawolf cards have the int pins active 272 * high, and have 2 UART chips, both ints must be 273 * enabled on the 9050. Also, the UARTS are set in 274 * 16450 mode by default, so we have to enable the 275 * 16C950 'enhanced' mode so that we can use the 276 * deep FIFOs 277 */ 278 irq_config = 0x5b; 279 /* 280 * enable/disable interrupts 281 */ 282 p = ioremap(pci_resource_start(dev, 0), 0x80); 283 if (p == NULL) 284 return -ENOMEM; 285 writel(irq_config, p + 0x4c); 286 287 /* 288 * Read the register back to ensure that it took effect. 289 */ 290 readl(p + 0x4c); 291 iounmap(p); 292 293 return 0; 294 } 295 296 static void pci_plx9050_exit(struct pci_dev *dev) 297 { 298 u8 __iomem *p; 299 300 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 301 return; 302 303 /* 304 * disable interrupts 305 */ 306 p = ioremap(pci_resource_start(dev, 0), 0x80); 307 if (p != NULL) { 308 writel(0, p + 0x4c); 309 310 /* 311 * Read the register back to ensure that it took effect. 312 */ 313 readl(p + 0x4c); 314 iounmap(p); 315 } 316 } 317 318 #define NI8420_INT_ENABLE_REG 0x38 319 #define NI8420_INT_ENABLE_BIT 0x2000 320 321 static void pci_ni8420_exit(struct pci_dev *dev) 322 { 323 void __iomem *p; 324 unsigned int bar = 0; 325 326 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 327 moan_device("no memory in bar", dev); 328 return; 329 } 330 331 p = pci_ioremap_bar(dev, bar); 332 if (p == NULL) 333 return; 334 335 /* Disable the CPU Interrupt */ 336 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 337 p + NI8420_INT_ENABLE_REG); 338 iounmap(p); 339 } 340 341 342 /* MITE registers */ 343 #define MITE_IOWBSR1 0xc4 344 #define MITE_IOWCR1 0xf4 345 #define MITE_LCIMR1 0x08 346 #define MITE_LCIMR2 0x10 347 348 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 349 350 static void pci_ni8430_exit(struct pci_dev *dev) 351 { 352 void __iomem *p; 353 unsigned int bar = 0; 354 355 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 356 moan_device("no memory in bar", dev); 357 return; 358 } 359 360 p = pci_ioremap_bar(dev, bar); 361 if (p == NULL) 362 return; 363 364 /* Disable the CPU Interrupt */ 365 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 366 iounmap(p); 367 } 368 369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 370 static int 371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 372 struct uart_8250_port *port, int idx) 373 { 374 unsigned int bar, offset = board->first_offset; 375 376 bar = 0; 377 378 if (idx < 4) { 379 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 380 offset += idx * board->uart_offset; 381 } else if (idx < 8) { 382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 383 offset += idx * board->uart_offset + 0xC00; 384 } else /* we have only 8 ports on PMC-OCTALPRO */ 385 return 1; 386 387 return setup_port(priv, port, bar, offset, board->reg_shift); 388 } 389 390 /* 391 * This does initialization for PMC OCTALPRO cards: 392 * maps the device memory, resets the UARTs (needed, bc 393 * if the module is removed and inserted again, the card 394 * is in the sleep mode) and enables global interrupt. 395 */ 396 397 /* global control register offset for SBS PMC-OctalPro */ 398 #define OCT_REG_CR_OFF 0x500 399 400 static int sbs_init(struct pci_dev *dev) 401 { 402 u8 __iomem *p; 403 404 p = pci_ioremap_bar(dev, 0); 405 406 if (p == NULL) 407 return -ENOMEM; 408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 409 writeb(0x10, p + OCT_REG_CR_OFF); 410 udelay(50); 411 writeb(0x0, p + OCT_REG_CR_OFF); 412 413 /* Set bit-2 (INTENABLE) of Control Register */ 414 writeb(0x4, p + OCT_REG_CR_OFF); 415 iounmap(p); 416 417 return 0; 418 } 419 420 /* 421 * Disables the global interrupt of PMC-OctalPro 422 */ 423 424 static void sbs_exit(struct pci_dev *dev) 425 { 426 u8 __iomem *p; 427 428 p = pci_ioremap_bar(dev, 0); 429 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 430 if (p != NULL) 431 writeb(0, p + OCT_REG_CR_OFF); 432 iounmap(p); 433 } 434 435 /* 436 * SIIG serial cards have an PCI interface chip which also controls 437 * the UART clocking frequency. Each UART can be clocked independently 438 * (except cards equipped with 4 UARTs) and initial clocking settings 439 * are stored in the EEPROM chip. It can cause problems because this 440 * version of serial driver doesn't support differently clocked UART's 441 * on single PCI card. To prevent this, initialization functions set 442 * high frequency clocking for all UART's on given card. It is safe (I 443 * hope) because it doesn't touch EEPROM settings to prevent conflicts 444 * with other OSes (like M$ DOS). 445 * 446 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 447 * 448 * There is two family of SIIG serial cards with different PCI 449 * interface chip and different configuration methods: 450 * - 10x cards have control registers in IO and/or memory space; 451 * - 20x cards have control registers in standard PCI configuration space. 452 * 453 * Note: all 10x cards have PCI device ids 0x10.. 454 * all 20x cards have PCI device ids 0x20.. 455 * 456 * There are also Quartet Serial cards which use Oxford Semiconductor 457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 458 * 459 * Note: some SIIG cards are probed by the parport_serial object. 460 */ 461 462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 464 465 static int pci_siig10x_init(struct pci_dev *dev) 466 { 467 u16 data; 468 void __iomem *p; 469 470 switch (dev->device & 0xfff8) { 471 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 472 data = 0xffdf; 473 break; 474 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 475 data = 0xf7ff; 476 break; 477 default: /* 1S1P, 4S */ 478 data = 0xfffb; 479 break; 480 } 481 482 p = ioremap(pci_resource_start(dev, 0), 0x80); 483 if (p == NULL) 484 return -ENOMEM; 485 486 writew(readw(p + 0x28) & data, p + 0x28); 487 readw(p + 0x28); 488 iounmap(p); 489 return 0; 490 } 491 492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 494 495 static int pci_siig20x_init(struct pci_dev *dev) 496 { 497 u8 data; 498 499 /* Change clock frequency for the first UART. */ 500 pci_read_config_byte(dev, 0x6f, &data); 501 pci_write_config_byte(dev, 0x6f, data & 0xef); 502 503 /* If this card has 2 UART, we have to do the same with second UART. */ 504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 506 pci_read_config_byte(dev, 0x73, &data); 507 pci_write_config_byte(dev, 0x73, data & 0xef); 508 } 509 return 0; 510 } 511 512 static int pci_siig_init(struct pci_dev *dev) 513 { 514 unsigned int type = dev->device & 0xff00; 515 516 if (type == 0x1000) 517 return pci_siig10x_init(dev); 518 if (type == 0x2000) 519 return pci_siig20x_init(dev); 520 521 moan_device("Unknown SIIG card", dev); 522 return -ENODEV; 523 } 524 525 static int pci_siig_setup(struct serial_private *priv, 526 const struct pciserial_board *board, 527 struct uart_8250_port *port, int idx) 528 { 529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 530 531 if (idx > 3) { 532 bar = 4; 533 offset = (idx - 4) * 8; 534 } 535 536 return setup_port(priv, port, bar, offset, 0); 537 } 538 539 /* 540 * Timedia has an explosion of boards, and to avoid the PCI table from 541 * growing *huge*, we use this function to collapse some 70 entries 542 * in the PCI table into one, for sanity's and compactness's sake. 543 */ 544 static const unsigned short timedia_single_port[] = { 545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 546 }; 547 548 static const unsigned short timedia_dual_port[] = { 549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 553 0xD079, 0 554 }; 555 556 static const unsigned short timedia_quad_port[] = { 557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 560 0xB157, 0 561 }; 562 563 static const unsigned short timedia_eight_port[] = { 564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 566 }; 567 568 static const struct timedia_struct { 569 int num; 570 const unsigned short *ids; 571 } timedia_data[] = { 572 { 1, timedia_single_port }, 573 { 2, timedia_dual_port }, 574 { 4, timedia_quad_port }, 575 { 8, timedia_eight_port } 576 }; 577 578 /* 579 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 580 * listing them individually, this driver merely grabs them all with 581 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 582 * and should be left free to be claimed by parport_serial instead. 583 */ 584 static int pci_timedia_probe(struct pci_dev *dev) 585 { 586 /* 587 * Check the third digit of the subdevice ID 588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 589 */ 590 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 591 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n", 592 dev->subsystem_device); 593 return -ENODEV; 594 } 595 596 return 0; 597 } 598 599 static int pci_timedia_init(struct pci_dev *dev) 600 { 601 const unsigned short *ids; 602 int i, j; 603 604 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 605 ids = timedia_data[i].ids; 606 for (j = 0; ids[j]; j++) 607 if (dev->subsystem_device == ids[j]) 608 return timedia_data[i].num; 609 } 610 return 0; 611 } 612 613 /* 614 * Timedia/SUNIX uses a mixture of BARs and offsets 615 * Ugh, this is ugly as all hell --- TYT 616 */ 617 static int 618 pci_timedia_setup(struct serial_private *priv, 619 const struct pciserial_board *board, 620 struct uart_8250_port *port, int idx) 621 { 622 unsigned int bar = 0, offset = board->first_offset; 623 624 switch (idx) { 625 case 0: 626 bar = 0; 627 break; 628 case 1: 629 offset = board->uart_offset; 630 bar = 0; 631 break; 632 case 2: 633 bar = 1; 634 break; 635 case 3: 636 offset = board->uart_offset; 637 fallthrough; 638 case 4: /* BAR 2 */ 639 case 5: /* BAR 3 */ 640 case 6: /* BAR 4 */ 641 case 7: /* BAR 5 */ 642 bar = idx - 2; 643 } 644 645 return setup_port(priv, port, bar, offset, board->reg_shift); 646 } 647 648 /* 649 * Some Titan cards are also a little weird 650 */ 651 static int 652 titan_400l_800l_setup(struct serial_private *priv, 653 const struct pciserial_board *board, 654 struct uart_8250_port *port, int idx) 655 { 656 unsigned int bar, offset = board->first_offset; 657 658 switch (idx) { 659 case 0: 660 bar = 1; 661 break; 662 case 1: 663 bar = 2; 664 break; 665 default: 666 bar = 4; 667 offset = (idx - 2) * board->uart_offset; 668 } 669 670 return setup_port(priv, port, bar, offset, board->reg_shift); 671 } 672 673 static int pci_xircom_init(struct pci_dev *dev) 674 { 675 msleep(100); 676 return 0; 677 } 678 679 static int pci_ni8420_init(struct pci_dev *dev) 680 { 681 void __iomem *p; 682 unsigned int bar = 0; 683 684 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 685 moan_device("no memory in bar", dev); 686 return 0; 687 } 688 689 p = pci_ioremap_bar(dev, bar); 690 if (p == NULL) 691 return -ENOMEM; 692 693 /* Enable CPU Interrupt */ 694 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 695 p + NI8420_INT_ENABLE_REG); 696 697 iounmap(p); 698 return 0; 699 } 700 701 #define MITE_IOWBSR1_WSIZE 0xa 702 #define MITE_IOWBSR1_WIN_OFFSET 0x800 703 #define MITE_IOWBSR1_WENAB (1 << 7) 704 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 705 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 706 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 707 708 static int pci_ni8430_init(struct pci_dev *dev) 709 { 710 void __iomem *p; 711 struct pci_bus_region region; 712 u32 device_window; 713 unsigned int bar = 0; 714 715 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 716 moan_device("no memory in bar", dev); 717 return 0; 718 } 719 720 p = pci_ioremap_bar(dev, bar); 721 if (p == NULL) 722 return -ENOMEM; 723 724 /* 725 * Set device window address and size in BAR0, while acknowledging that 726 * the resource structure may contain a translated address that differs 727 * from the address the device responds to. 728 */ 729 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 730 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 731 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 732 writel(device_window, p + MITE_IOWBSR1); 733 734 /* Set window access to go to RAMSEL IO address space */ 735 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 736 p + MITE_IOWCR1); 737 738 /* Enable IO Bus Interrupt 0 */ 739 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 740 741 /* Enable CPU Interrupt */ 742 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 743 744 iounmap(p); 745 return 0; 746 } 747 748 /* UART Port Control Register */ 749 #define NI8430_PORTCON 0x0f 750 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 751 752 static int 753 pci_ni8430_setup(struct serial_private *priv, 754 const struct pciserial_board *board, 755 struct uart_8250_port *port, int idx) 756 { 757 struct pci_dev *dev = priv->dev; 758 void __iomem *p; 759 unsigned int bar, offset = board->first_offset; 760 761 if (idx >= board->num_ports) 762 return 1; 763 764 bar = FL_GET_BASE(board->flags); 765 offset += idx * board->uart_offset; 766 767 p = pci_ioremap_bar(dev, bar); 768 if (!p) 769 return -ENOMEM; 770 771 /* enable the transceiver */ 772 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 773 p + offset + NI8430_PORTCON); 774 775 iounmap(p); 776 777 return setup_port(priv, port, bar, offset, board->reg_shift); 778 } 779 780 static int pci_netmos_9900_setup(struct serial_private *priv, 781 const struct pciserial_board *board, 782 struct uart_8250_port *port, int idx) 783 { 784 unsigned int bar; 785 786 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 787 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 788 /* netmos apparently orders BARs by datasheet layout, so serial 789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 790 */ 791 bar = 3 * idx; 792 793 return setup_port(priv, port, bar, 0, board->reg_shift); 794 } 795 796 return pci_default_setup(priv, board, port, idx); 797 } 798 799 /* the 99xx series comes with a range of device IDs and a variety 800 * of capabilities: 801 * 802 * 9900 has varying capabilities and can cascade to sub-controllers 803 * (cascading should be purely internal) 804 * 9904 is hardwired with 4 serial ports 805 * 9912 and 9922 are hardwired with 2 serial ports 806 */ 807 static int pci_netmos_9900_numports(struct pci_dev *dev) 808 { 809 unsigned int c = dev->class; 810 unsigned int pi; 811 unsigned short sub_serports; 812 813 pi = c & 0xff; 814 815 if (pi == 2) 816 return 1; 817 818 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 819 /* two possibilities: 0x30ps encodes number of parallel and 820 * serial ports, or 0x1000 indicates *something*. This is not 821 * immediately obvious, since the 2s1p+4s configuration seems 822 * to offer all functionality on functions 0..2, while still 823 * advertising the same function 3 as the 4s+2s1p config. 824 */ 825 sub_serports = dev->subsystem_device & 0xf; 826 if (sub_serports > 0) 827 return sub_serports; 828 829 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 830 return 0; 831 } 832 833 moan_device("unknown NetMos/Mostech program interface", dev); 834 return 0; 835 } 836 837 static int pci_netmos_init(struct pci_dev *dev) 838 { 839 /* subdevice 0x00PS means <P> parallel, <S> serial */ 840 unsigned int num_serial = dev->subsystem_device & 0xf; 841 842 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 843 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 844 return 0; 845 846 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 847 dev->subsystem_device == 0x0299) 848 return 0; 849 850 switch (dev->device) { /* FALLTHROUGH on all */ 851 case PCI_DEVICE_ID_NETMOS_9904: 852 case PCI_DEVICE_ID_NETMOS_9912: 853 case PCI_DEVICE_ID_NETMOS_9922: 854 case PCI_DEVICE_ID_NETMOS_9900: 855 num_serial = pci_netmos_9900_numports(dev); 856 break; 857 858 default: 859 break; 860 } 861 862 if (num_serial == 0) { 863 moan_device("unknown NetMos/Mostech device", dev); 864 return -ENODEV; 865 } 866 867 return num_serial; 868 } 869 870 /* 871 * These chips are available with optionally one parallel port and up to 872 * two serial ports. Unfortunately they all have the same product id. 873 * 874 * Basic configuration is done over a region of 32 I/O ports. The base 875 * ioport is called INTA or INTC, depending on docs/other drivers. 876 * 877 * The region of the 32 I/O ports is configured in POSIO0R... 878 */ 879 880 /* registers */ 881 #define ITE_887x_MISCR 0x9c 882 #define ITE_887x_INTCBAR 0x78 883 #define ITE_887x_UARTBAR 0x7c 884 #define ITE_887x_PS0BAR 0x10 885 #define ITE_887x_POSIO0 0x60 886 887 /* I/O space size */ 888 #define ITE_887x_IOSIZE 32 889 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 890 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 891 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 892 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 893 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 894 #define ITE_887x_POSIO_SPEED (3 << 29) 895 /* enable IO_Space bit */ 896 #define ITE_887x_POSIO_ENABLE (1 << 31) 897 898 /* inta_addr are the configuration addresses of the ITE */ 899 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 }; 900 static int pci_ite887x_init(struct pci_dev *dev) 901 { 902 int ret, i, type; 903 struct resource *iobase = NULL; 904 u32 miscr, uartbar, ioport; 905 906 /* search for the base-ioport */ 907 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { 908 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 909 "ite887x"); 910 if (iobase != NULL) { 911 /* write POSIO0R - speed | size | ioport */ 912 pci_write_config_dword(dev, ITE_887x_POSIO0, 913 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 914 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 915 /* write INTCBAR - ioport */ 916 pci_write_config_dword(dev, ITE_887x_INTCBAR, 917 inta_addr[i]); 918 ret = inb(inta_addr[i]); 919 if (ret != 0xff) { 920 /* ioport connected */ 921 break; 922 } 923 release_region(iobase->start, ITE_887x_IOSIZE); 924 } 925 } 926 927 if (i == ARRAY_SIZE(inta_addr)) { 928 pci_err(dev, "could not find iobase\n"); 929 return -ENODEV; 930 } 931 932 /* start of undocumented type checking (see parport_pc.c) */ 933 type = inb(iobase->start + 0x18) & 0x0f; 934 935 switch (type) { 936 case 0x2: /* ITE8871 (1P) */ 937 case 0xa: /* ITE8875 (1P) */ 938 ret = 0; 939 break; 940 case 0xe: /* ITE8872 (2S1P) */ 941 ret = 2; 942 break; 943 case 0x6: /* ITE8873 (1S) */ 944 ret = 1; 945 break; 946 case 0x8: /* ITE8874 (2S) */ 947 ret = 2; 948 break; 949 default: 950 moan_device("Unknown ITE887x", dev); 951 ret = -ENODEV; 952 } 953 954 /* configure all serial ports */ 955 for (i = 0; i < ret; i++) { 956 /* read the I/O port from the device */ 957 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 958 &ioport); 959 ioport &= 0x0000FF00; /* the actual base address */ 960 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 961 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 962 ITE_887x_POSIO_IOSIZE_8 | ioport); 963 964 /* write the ioport to the UARTBAR */ 965 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 966 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 967 uartbar |= (ioport << (16 * i)); /* set the ioport */ 968 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 969 970 /* get current config */ 971 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 972 /* disable interrupts (UARTx_Routing[3:0]) */ 973 miscr &= ~(0xf << (12 - 4 * i)); 974 /* activate the UART (UARTx_En) */ 975 miscr |= 1 << (23 - i); 976 /* write new config with activated UART */ 977 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 978 } 979 980 if (ret <= 0) { 981 /* the device has no UARTs if we get here */ 982 release_region(iobase->start, ITE_887x_IOSIZE); 983 } 984 985 return ret; 986 } 987 988 static void pci_ite887x_exit(struct pci_dev *dev) 989 { 990 u32 ioport; 991 /* the ioport is bit 0-15 in POSIO0R */ 992 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 993 ioport &= 0xffff; 994 release_region(ioport, ITE_887x_IOSIZE); 995 } 996 997 /* 998 * Oxford Semiconductor Inc. 999 * Check if an OxSemi device is part of the Tornado range of devices. 1000 */ 1001 #define PCI_VENDOR_ID_ENDRUN 0x7401 1002 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1003 1004 static bool pci_oxsemi_tornado_p(struct pci_dev *dev) 1005 { 1006 /* OxSemi Tornado devices are all 0xCxxx */ 1007 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1008 (dev->device & 0xf000) != 0xc000) 1009 return false; 1010 1011 /* EndRun devices are all 0xExxx */ 1012 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1013 (dev->device & 0xf000) != 0xe000) 1014 return false; 1015 1016 return true; 1017 } 1018 1019 /* 1020 * Determine the number of ports available on a Tornado device. 1021 */ 1022 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1023 { 1024 u8 __iomem *p; 1025 unsigned long deviceID; 1026 unsigned int number_uarts = 0; 1027 1028 if (!pci_oxsemi_tornado_p(dev)) 1029 return 0; 1030 1031 p = pci_iomap(dev, 0, 5); 1032 if (p == NULL) 1033 return -ENOMEM; 1034 1035 deviceID = ioread32(p); 1036 /* Tornado device */ 1037 if (deviceID == 0x07000200) { 1038 number_uarts = ioread8(p + 4); 1039 pci_dbg(dev, "%d ports detected on %s PCI Express device\n", 1040 number_uarts, 1041 dev->vendor == PCI_VENDOR_ID_ENDRUN ? 1042 "EndRun" : "Oxford"); 1043 } 1044 pci_iounmap(dev, p); 1045 return number_uarts; 1046 } 1047 1048 /* Tornado-specific constants for the TCR and CPR registers; see below. */ 1049 #define OXSEMI_TORNADO_TCR_MASK 0xf 1050 #define OXSEMI_TORNADO_CPR_MASK 0x1ff 1051 #define OXSEMI_TORNADO_CPR_MIN 0x008 1052 #define OXSEMI_TORNADO_CPR_DEF 0x10f 1053 1054 /* 1055 * Determine the oversampling rate, the clock prescaler, and the clock 1056 * divisor for the requested baud rate. The clock rate is 62.5 MHz, 1057 * which is four times the baud base, and the prescaler increments in 1058 * steps of 1/8. Therefore to make calculations on integers we need 1059 * to use a scaled clock rate, which is the baud base multiplied by 32 1060 * (or our assumed UART clock rate multiplied by 2). 1061 * 1062 * The allowed oversampling rates are from 4 up to 16 inclusive (values 1063 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows 1064 * values between 1.000 and 63.875 inclusive (operation for values from 1065 * 0.000 to 0.875 has not been specified). The clock divisor is the usual 1066 * unsigned 16-bit integer. 1067 * 1068 * For the most accurate baud rate we use a table of predetermined 1069 * oversampling rates and clock prescalers that records all possible 1070 * products of the two parameters in the range from 4 up to 255 inclusive, 1071 * and additionally 335 for the 1500000bps rate, with the prescaler scaled 1072 * by 8. The table is sorted by the decreasing value of the oversampling 1073 * rate and ties are resolved by sorting by the decreasing value of the 1074 * product. This way preference is given to higher oversampling rates. 1075 * 1076 * We iterate over the table and choose the product of an oversampling 1077 * rate and a clock prescaler that gives the lowest integer division 1078 * result deviation, or if an exact integer divider is found we stop 1079 * looking for it right away. We do some fixup if the resulting clock 1080 * divisor required would be out of its unsigned 16-bit integer range. 1081 * 1082 * Finally we abuse the supposed fractional part returned to encode the 1083 * 4-bit value of the oversampling rate and the 9-bit value of the clock 1084 * prescaler which will end up in the TCR and CPR/CPR2 registers. 1085 */ 1086 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port, 1087 unsigned int baud, 1088 unsigned int *frac) 1089 { 1090 static u8 p[][2] = { 1091 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, }, 1092 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, }, 1093 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, }, 1094 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, }, 1095 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, }, 1096 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, }, 1097 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, }, 1098 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, }, 1099 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, }, 1100 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, }, 1101 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, }, 1102 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, }, 1103 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, }, 1104 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, }, 1105 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, }, 1106 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, }, 1107 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, }, 1108 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, }, 1109 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, }, 1110 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, }, 1111 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, }, 1112 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, }, 1113 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, }, 1114 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, }, 1115 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, }, 1116 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, }, 1117 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, }, 1118 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, }, 1119 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, }, 1120 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, }, 1121 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, }, 1122 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, }, 1123 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, }, 1124 { 4, 9, }, { 4, 8, }, 1125 }; 1126 /* Scale the quotient for comparison to get the fractional part. */ 1127 const unsigned int quot_scale = 65536; 1128 unsigned int sclk = port->uartclk * 2; 1129 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud); 1130 unsigned int best_squot; 1131 unsigned int squot; 1132 unsigned int quot; 1133 u16 cpr; 1134 u8 tcr; 1135 int i; 1136 1137 /* Old custom speed handling. */ 1138 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 1139 unsigned int cust_div = port->custom_divisor; 1140 1141 quot = cust_div & UART_DIV_MAX; 1142 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; 1143 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; 1144 if (cpr < OXSEMI_TORNADO_CPR_MIN) 1145 cpr = OXSEMI_TORNADO_CPR_DEF; 1146 } else { 1147 best_squot = quot_scale; 1148 for (i = 0; i < ARRAY_SIZE(p); i++) { 1149 unsigned int spre; 1150 unsigned int srem; 1151 u8 cp; 1152 u8 tc; 1153 1154 tc = p[i][0]; 1155 cp = p[i][1]; 1156 spre = tc * cp; 1157 1158 srem = sdiv % spre; 1159 if (srem > spre / 2) 1160 srem = spre - srem; 1161 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre); 1162 1163 if (srem == 0) { 1164 tcr = tc; 1165 cpr = cp; 1166 quot = sdiv / spre; 1167 break; 1168 } else if (squot < best_squot) { 1169 best_squot = squot; 1170 tcr = tc; 1171 cpr = cp; 1172 quot = DIV_ROUND_CLOSEST(sdiv, spre); 1173 } 1174 } 1175 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 1176 quot % 2 == 0) { 1177 quot >>= 1; 1178 tcr <<= 1; 1179 } 1180 while (quot > UART_DIV_MAX) { 1181 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 1182 quot >>= 1; 1183 tcr <<= 1; 1184 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 1185 quot >>= 1; 1186 cpr <<= 1; 1187 } else { 1188 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 1189 cpr = OXSEMI_TORNADO_CPR_MASK; 1190 } 1191 } 1192 } 1193 1194 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); 1195 return quot; 1196 } 1197 1198 /* 1199 * Set the oversampling rate in the transmitter clock cycle register (TCR), 1200 * the clock prescaler in the clock prescaler register (CPR and CPR2), and 1201 * the clock divisor in the divisor latch (DLL and DLM). Note that for 1202 * backwards compatibility any write to CPR clears CPR2 and therefore CPR 1203 * has to be written first, followed by CPR2, which occupies the location 1204 * of CKS used with earlier UART designs. 1205 */ 1206 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port, 1207 unsigned int baud, 1208 unsigned int quot, 1209 unsigned int quot_frac) 1210 { 1211 struct uart_8250_port *up = up_to_u8250p(port); 1212 u8 cpr2 = quot_frac >> 16; 1213 u8 cpr = quot_frac >> 8; 1214 u8 tcr = quot_frac; 1215 1216 serial_icr_write(up, UART_TCR, tcr); 1217 serial_icr_write(up, UART_CPR, cpr); 1218 serial_icr_write(up, UART_CKS, cpr2); 1219 serial8250_do_set_divisor(port, baud, quot, 0); 1220 } 1221 1222 /* 1223 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate 1224 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used. 1225 */ 1226 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port, 1227 unsigned int mctrl) 1228 { 1229 struct uart_8250_port *up = up_to_u8250p(port); 1230 1231 up->mcr |= UART_MCR_CLKSEL; 1232 serial8250_do_set_mctrl(port, mctrl); 1233 } 1234 1235 /* 1236 * We require EFR features for clock programming, so set UPF_FULL_PROBE 1237 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting. 1238 */ 1239 static int pci_oxsemi_tornado_setup(struct serial_private *priv, 1240 const struct pciserial_board *board, 1241 struct uart_8250_port *up, int idx) 1242 { 1243 struct pci_dev *dev = priv->dev; 1244 1245 if (pci_oxsemi_tornado_p(dev)) { 1246 up->port.flags |= UPF_FULL_PROBE; 1247 up->port.get_divisor = pci_oxsemi_tornado_get_divisor; 1248 up->port.set_divisor = pci_oxsemi_tornado_set_divisor; 1249 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl; 1250 } 1251 1252 return pci_default_setup(priv, board, up, idx); 1253 } 1254 1255 static int pci_asix_setup(struct serial_private *priv, 1256 const struct pciserial_board *board, 1257 struct uart_8250_port *port, int idx) 1258 { 1259 port->bugs |= UART_BUG_PARITY; 1260 return pci_default_setup(priv, board, port, idx); 1261 } 1262 1263 #define QPCR_TEST_FOR1 0x3F 1264 #define QPCR_TEST_GET1 0x00 1265 #define QPCR_TEST_FOR2 0x40 1266 #define QPCR_TEST_GET2 0x40 1267 #define QPCR_TEST_FOR3 0x80 1268 #define QPCR_TEST_GET3 0x40 1269 #define QPCR_TEST_FOR4 0xC0 1270 #define QPCR_TEST_GET4 0x80 1271 1272 #define QOPR_CLOCK_X1 0x0000 1273 #define QOPR_CLOCK_X2 0x0001 1274 #define QOPR_CLOCK_X4 0x0002 1275 #define QOPR_CLOCK_X8 0x0003 1276 #define QOPR_CLOCK_RATE_MASK 0x0003 1277 1278 /* Quatech devices have their own extra interface features */ 1279 static struct pci_device_id quatech_cards[] = { 1280 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) }, 1281 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) }, 1282 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) }, 1283 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) }, 1284 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) }, 1285 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) }, 1286 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) }, 1287 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) }, 1288 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) }, 1289 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) }, 1290 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) }, 1291 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) }, 1292 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) }, 1293 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) }, 1294 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) }, 1295 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) }, 1296 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) }, 1297 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) }, 1298 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) }, 1299 { 0, } 1300 }; 1301 1302 static int pci_quatech_rqopr(struct uart_8250_port *port) 1303 { 1304 unsigned long base = port->port.iobase; 1305 u8 LCR, val; 1306 1307 LCR = inb(base + UART_LCR); 1308 outb(0xBF, base + UART_LCR); 1309 val = inb(base + UART_SCR); 1310 outb(LCR, base + UART_LCR); 1311 return val; 1312 } 1313 1314 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1315 { 1316 unsigned long base = port->port.iobase; 1317 u8 LCR; 1318 1319 LCR = inb(base + UART_LCR); 1320 outb(0xBF, base + UART_LCR); 1321 inb(base + UART_SCR); 1322 outb(qopr, base + UART_SCR); 1323 outb(LCR, base + UART_LCR); 1324 } 1325 1326 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1327 { 1328 unsigned long base = port->port.iobase; 1329 u8 LCR, val, qmcr; 1330 1331 LCR = inb(base + UART_LCR); 1332 outb(0xBF, base + UART_LCR); 1333 val = inb(base + UART_SCR); 1334 outb(val | 0x10, base + UART_SCR); 1335 qmcr = inb(base + UART_MCR); 1336 outb(val, base + UART_SCR); 1337 outb(LCR, base + UART_LCR); 1338 1339 return qmcr; 1340 } 1341 1342 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1343 { 1344 unsigned long base = port->port.iobase; 1345 u8 LCR, val; 1346 1347 LCR = inb(base + UART_LCR); 1348 outb(0xBF, base + UART_LCR); 1349 val = inb(base + UART_SCR); 1350 outb(val | 0x10, base + UART_SCR); 1351 outb(qmcr, base + UART_MCR); 1352 outb(val, base + UART_SCR); 1353 outb(LCR, base + UART_LCR); 1354 } 1355 1356 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1357 { 1358 unsigned long base = port->port.iobase; 1359 u8 LCR, val; 1360 1361 LCR = inb(base + UART_LCR); 1362 outb(0xBF, base + UART_LCR); 1363 val = inb(base + UART_SCR); 1364 if (val & 0x20) { 1365 outb(0x80, UART_LCR); 1366 if (!(inb(UART_SCR) & 0x20)) { 1367 outb(LCR, base + UART_LCR); 1368 return 1; 1369 } 1370 } 1371 return 0; 1372 } 1373 1374 static int pci_quatech_test(struct uart_8250_port *port) 1375 { 1376 u8 reg, qopr; 1377 1378 qopr = pci_quatech_rqopr(port); 1379 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1380 reg = pci_quatech_rqopr(port) & 0xC0; 1381 if (reg != QPCR_TEST_GET1) 1382 return -EINVAL; 1383 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1384 reg = pci_quatech_rqopr(port) & 0xC0; 1385 if (reg != QPCR_TEST_GET2) 1386 return -EINVAL; 1387 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1388 reg = pci_quatech_rqopr(port) & 0xC0; 1389 if (reg != QPCR_TEST_GET3) 1390 return -EINVAL; 1391 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1392 reg = pci_quatech_rqopr(port) & 0xC0; 1393 if (reg != QPCR_TEST_GET4) 1394 return -EINVAL; 1395 1396 pci_quatech_wqopr(port, qopr); 1397 return 0; 1398 } 1399 1400 static int pci_quatech_clock(struct uart_8250_port *port) 1401 { 1402 u8 qopr, reg, set; 1403 unsigned long clock; 1404 1405 if (pci_quatech_test(port) < 0) 1406 return 1843200; 1407 1408 qopr = pci_quatech_rqopr(port); 1409 1410 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1411 reg = pci_quatech_rqopr(port); 1412 if (reg & QOPR_CLOCK_X8) { 1413 clock = 1843200; 1414 goto out; 1415 } 1416 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1417 reg = pci_quatech_rqopr(port); 1418 if (!(reg & QOPR_CLOCK_X8)) { 1419 clock = 1843200; 1420 goto out; 1421 } 1422 reg &= QOPR_CLOCK_X8; 1423 if (reg == QOPR_CLOCK_X2) { 1424 clock = 3685400; 1425 set = QOPR_CLOCK_X2; 1426 } else if (reg == QOPR_CLOCK_X4) { 1427 clock = 7372800; 1428 set = QOPR_CLOCK_X4; 1429 } else if (reg == QOPR_CLOCK_X8) { 1430 clock = 14745600; 1431 set = QOPR_CLOCK_X8; 1432 } else { 1433 clock = 1843200; 1434 set = QOPR_CLOCK_X1; 1435 } 1436 qopr &= ~QOPR_CLOCK_RATE_MASK; 1437 qopr |= set; 1438 1439 out: 1440 pci_quatech_wqopr(port, qopr); 1441 return clock; 1442 } 1443 1444 static int pci_quatech_rs422(struct uart_8250_port *port) 1445 { 1446 u8 qmcr; 1447 int rs422 = 0; 1448 1449 if (!pci_quatech_has_qmcr(port)) 1450 return 0; 1451 qmcr = pci_quatech_rqmcr(port); 1452 pci_quatech_wqmcr(port, 0xFF); 1453 if (pci_quatech_rqmcr(port)) 1454 rs422 = 1; 1455 pci_quatech_wqmcr(port, qmcr); 1456 return rs422; 1457 } 1458 1459 static int pci_quatech_init(struct pci_dev *dev) 1460 { 1461 const struct pci_device_id *match; 1462 bool amcc = false; 1463 1464 match = pci_match_id(quatech_cards, dev); 1465 if (match) 1466 amcc = match->driver_data; 1467 else 1468 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); 1469 1470 if (amcc) { 1471 unsigned long base = pci_resource_start(dev, 0); 1472 if (base) { 1473 u32 tmp; 1474 1475 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1476 tmp = inl(base + 0x3c); 1477 outl(tmp | 0x01000000, base + 0x3c); 1478 outl(tmp & ~0x01000000, base + 0x3c); 1479 } 1480 } 1481 return 0; 1482 } 1483 1484 static int pci_quatech_setup(struct serial_private *priv, 1485 const struct pciserial_board *board, 1486 struct uart_8250_port *port, int idx) 1487 { 1488 /* Needed by pci_quatech calls below */ 1489 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1490 /* Set up the clocking */ 1491 port->port.uartclk = pci_quatech_clock(port); 1492 /* For now just warn about RS422 */ 1493 if (pci_quatech_rs422(port)) 1494 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); 1495 return pci_default_setup(priv, board, port, idx); 1496 } 1497 1498 static int pci_default_setup(struct serial_private *priv, 1499 const struct pciserial_board *board, 1500 struct uart_8250_port *port, int idx) 1501 { 1502 unsigned int bar, offset = board->first_offset, maxnr; 1503 1504 bar = FL_GET_BASE(board->flags); 1505 if (board->flags & FL_BASE_BARS) 1506 bar += idx; 1507 else 1508 offset += idx * board->uart_offset; 1509 1510 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1511 (board->reg_shift + 3); 1512 1513 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1514 return 1; 1515 1516 return setup_port(priv, port, bar, offset, board->reg_shift); 1517 } 1518 1519 static int 1520 ce4100_serial_setup(struct serial_private *priv, 1521 const struct pciserial_board *board, 1522 struct uart_8250_port *port, int idx) 1523 { 1524 int ret; 1525 1526 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1527 port->port.iotype = UPIO_MEM32; 1528 port->port.type = PORT_XSCALE; 1529 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1530 port->port.regshift = 2; 1531 1532 return ret; 1533 } 1534 1535 static int 1536 pci_omegapci_setup(struct serial_private *priv, 1537 const struct pciserial_board *board, 1538 struct uart_8250_port *port, int idx) 1539 { 1540 return setup_port(priv, port, 2, idx * 8, 0); 1541 } 1542 1543 static int 1544 pci_brcm_trumanage_setup(struct serial_private *priv, 1545 const struct pciserial_board *board, 1546 struct uart_8250_port *port, int idx) 1547 { 1548 int ret = pci_default_setup(priv, board, port, idx); 1549 1550 port->port.type = PORT_BRCM_TRUMANAGE; 1551 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1552 return ret; 1553 } 1554 1555 /* RTS will control by MCR if this bit is 0 */ 1556 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1557 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1558 #define FINTEK_RTS_INVERT BIT(5) 1559 1560 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1561 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios, 1562 struct serial_rs485 *rs485) 1563 { 1564 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1565 u8 setting; 1566 u8 *index = (u8 *) port->private_data; 1567 1568 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1569 1570 if (rs485->flags & SER_RS485_ENABLED) { 1571 /* Enable RTS H/W control mode */ 1572 setting |= FINTEK_RTS_CONTROL_BY_HW; 1573 1574 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1575 /* RTS driving high on TX */ 1576 setting &= ~FINTEK_RTS_INVERT; 1577 } else { 1578 /* RTS driving low on TX */ 1579 setting |= FINTEK_RTS_INVERT; 1580 } 1581 } else { 1582 /* Disable RTS H/W control mode */ 1583 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1584 } 1585 1586 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1587 1588 return 0; 1589 } 1590 1591 static const struct serial_rs485 pci_fintek_rs485_supported = { 1592 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND, 1593 /* F81504/508/512 does not support RTS delay before or after send */ 1594 }; 1595 1596 static int pci_fintek_setup(struct serial_private *priv, 1597 const struct pciserial_board *board, 1598 struct uart_8250_port *port, int idx) 1599 { 1600 struct pci_dev *pdev = priv->dev; 1601 u8 *data; 1602 u8 config_base; 1603 u16 iobase; 1604 1605 config_base = 0x40 + 0x08 * idx; 1606 1607 /* Get the io address from configuration space */ 1608 pci_read_config_word(pdev, config_base + 4, &iobase); 1609 1610 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); 1611 1612 port->port.iotype = UPIO_PORT; 1613 port->port.iobase = iobase; 1614 port->port.rs485_config = pci_fintek_rs485_config; 1615 port->port.rs485_supported = pci_fintek_rs485_supported; 1616 1617 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1618 if (!data) 1619 return -ENOMEM; 1620 1621 /* preserve index in PCI configuration space */ 1622 *data = idx; 1623 port->port.private_data = data; 1624 1625 return 0; 1626 } 1627 1628 static int pci_fintek_init(struct pci_dev *dev) 1629 { 1630 unsigned long iobase; 1631 u32 max_port, i; 1632 resource_size_t bar_data[3]; 1633 u8 config_base; 1634 struct serial_private *priv = pci_get_drvdata(dev); 1635 1636 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1637 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1638 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1639 return -ENODEV; 1640 1641 switch (dev->device) { 1642 case 0x1104: /* 4 ports */ 1643 case 0x1108: /* 8 ports */ 1644 max_port = dev->device & 0xff; 1645 break; 1646 case 0x1112: /* 12 ports */ 1647 max_port = 12; 1648 break; 1649 default: 1650 return -EINVAL; 1651 } 1652 1653 /* Get the io address dispatch from the BIOS */ 1654 bar_data[0] = pci_resource_start(dev, 5); 1655 bar_data[1] = pci_resource_start(dev, 4); 1656 bar_data[2] = pci_resource_start(dev, 3); 1657 1658 for (i = 0; i < max_port; ++i) { 1659 /* UART0 configuration offset start from 0x40 */ 1660 config_base = 0x40 + 0x08 * i; 1661 1662 /* Calculate Real IO Port */ 1663 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1664 1665 /* Enable UART I/O port */ 1666 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1667 1668 /* Select 128-byte FIFO and 8x FIFO threshold */ 1669 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1670 1671 /* LSB UART */ 1672 pci_write_config_byte(dev, config_base + 0x04, 1673 (u8)(iobase & 0xff)); 1674 1675 /* MSB UART */ 1676 pci_write_config_byte(dev, config_base + 0x05, 1677 (u8)((iobase & 0xff00) >> 8)); 1678 1679 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1680 1681 if (!priv) { 1682 /* First init without port data 1683 * force init to RS232 Mode 1684 */ 1685 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1686 } 1687 } 1688 1689 return max_port; 1690 } 1691 1692 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1693 { 1694 struct f815xxa_data *data = p->private_data; 1695 unsigned long flags; 1696 1697 spin_lock_irqsave(&data->lock, flags); 1698 writeb(value, p->membase + offset); 1699 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1700 spin_unlock_irqrestore(&data->lock, flags); 1701 } 1702 1703 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1704 const struct pciserial_board *board, 1705 struct uart_8250_port *port, int idx) 1706 { 1707 struct pci_dev *pdev = priv->dev; 1708 struct f815xxa_data *data; 1709 1710 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1711 if (!data) 1712 return -ENOMEM; 1713 1714 data->idx = idx; 1715 spin_lock_init(&data->lock); 1716 1717 port->port.private_data = data; 1718 port->port.iotype = UPIO_MEM; 1719 port->port.flags |= UPF_IOREMAP; 1720 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1721 port->port.serial_out = f815xxa_mem_serial_out; 1722 1723 return 0; 1724 } 1725 1726 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1727 { 1728 u32 max_port, i; 1729 int config_base; 1730 1731 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1732 return -ENODEV; 1733 1734 switch (dev->device) { 1735 case 0x1204: /* 4 ports */ 1736 case 0x1208: /* 8 ports */ 1737 max_port = dev->device & 0xff; 1738 break; 1739 case 0x1212: /* 12 ports */ 1740 max_port = 12; 1741 break; 1742 default: 1743 return -EINVAL; 1744 } 1745 1746 /* Set to mmio decode */ 1747 pci_write_config_byte(dev, 0x209, 0x40); 1748 1749 for (i = 0; i < max_port; ++i) { 1750 /* UART0 configuration offset start from 0x2A0 */ 1751 config_base = 0x2A0 + 0x08 * i; 1752 1753 /* Select 128-byte FIFO and 8x FIFO threshold */ 1754 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1755 1756 /* Enable UART I/O port */ 1757 pci_write_config_byte(dev, config_base + 0, 0x01); 1758 } 1759 1760 return max_port; 1761 } 1762 1763 static int skip_tx_en_setup(struct serial_private *priv, 1764 const struct pciserial_board *board, 1765 struct uart_8250_port *port, int idx) 1766 { 1767 port->port.quirks |= UPQ_NO_TXEN_TEST; 1768 pci_dbg(priv->dev, 1769 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1770 priv->dev->vendor, priv->dev->device, 1771 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1772 1773 return pci_default_setup(priv, board, port, idx); 1774 } 1775 1776 static void kt_handle_break(struct uart_port *p) 1777 { 1778 struct uart_8250_port *up = up_to_u8250p(p); 1779 /* 1780 * On receipt of a BI, serial device in Intel ME (Intel 1781 * management engine) needs to have its fifos cleared for sane 1782 * SOL (Serial Over Lan) output. 1783 */ 1784 serial8250_clear_and_reinit_fifos(up); 1785 } 1786 1787 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1788 { 1789 struct uart_8250_port *up = up_to_u8250p(p); 1790 unsigned int val; 1791 1792 /* 1793 * When the Intel ME (management engine) gets reset its serial 1794 * port registers could return 0 momentarily. Functions like 1795 * serial8250_console_write, read and save the IER, perform 1796 * some operation and then restore it. In order to avoid 1797 * setting IER register inadvertently to 0, if the value read 1798 * is 0, double check with ier value in uart_8250_port and use 1799 * that instead. up->ier should be the same value as what is 1800 * currently configured. 1801 */ 1802 val = inb(p->iobase + offset); 1803 if (offset == UART_IER) { 1804 if (val == 0) 1805 val = up->ier; 1806 } 1807 return val; 1808 } 1809 1810 static int kt_serial_setup(struct serial_private *priv, 1811 const struct pciserial_board *board, 1812 struct uart_8250_port *port, int idx) 1813 { 1814 port->port.flags |= UPF_BUG_THRE; 1815 port->port.serial_in = kt_serial_in; 1816 port->port.handle_break = kt_handle_break; 1817 return skip_tx_en_setup(priv, board, port, idx); 1818 } 1819 1820 static int pci_eg20t_init(struct pci_dev *dev) 1821 { 1822 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1823 return -ENODEV; 1824 #else 1825 return 0; 1826 #endif 1827 } 1828 1829 static int 1830 pci_wch_ch353_setup(struct serial_private *priv, 1831 const struct pciserial_board *board, 1832 struct uart_8250_port *port, int idx) 1833 { 1834 port->port.flags |= UPF_FIXED_TYPE; 1835 port->port.type = PORT_16550A; 1836 return pci_default_setup(priv, board, port, idx); 1837 } 1838 1839 static int 1840 pci_wch_ch355_setup(struct serial_private *priv, 1841 const struct pciserial_board *board, 1842 struct uart_8250_port *port, int idx) 1843 { 1844 port->port.flags |= UPF_FIXED_TYPE; 1845 port->port.type = PORT_16550A; 1846 return pci_default_setup(priv, board, port, idx); 1847 } 1848 1849 static int 1850 pci_wch_ch38x_setup(struct serial_private *priv, 1851 const struct pciserial_board *board, 1852 struct uart_8250_port *port, int idx) 1853 { 1854 port->port.flags |= UPF_FIXED_TYPE; 1855 port->port.type = PORT_16850; 1856 return pci_default_setup(priv, board, port, idx); 1857 } 1858 1859 1860 #define CH384_XINT_ENABLE_REG 0xEB 1861 #define CH384_XINT_ENABLE_BIT 0x02 1862 1863 static int pci_wch_ch38x_init(struct pci_dev *dev) 1864 { 1865 int max_port; 1866 unsigned long iobase; 1867 1868 1869 switch (dev->device) { 1870 case 0x3853: /* 8 ports */ 1871 max_port = 8; 1872 break; 1873 default: 1874 return -EINVAL; 1875 } 1876 1877 iobase = pci_resource_start(dev, 0); 1878 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1879 1880 return max_port; 1881 } 1882 1883 static void pci_wch_ch38x_exit(struct pci_dev *dev) 1884 { 1885 unsigned long iobase; 1886 1887 iobase = pci_resource_start(dev, 0); 1888 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1889 } 1890 1891 1892 static int 1893 pci_sunix_setup(struct serial_private *priv, 1894 const struct pciserial_board *board, 1895 struct uart_8250_port *port, int idx) 1896 { 1897 int bar; 1898 int offset; 1899 1900 port->port.flags |= UPF_FIXED_TYPE; 1901 port->port.type = PORT_SUNIX; 1902 1903 if (idx < 4) { 1904 bar = 0; 1905 offset = idx * board->uart_offset; 1906 } else { 1907 bar = 1; 1908 idx -= 4; 1909 idx = div_s64_rem(idx, 4, &offset); 1910 offset = idx * 64 + offset * board->uart_offset; 1911 } 1912 1913 return setup_port(priv, port, bar, offset, 0); 1914 } 1915 1916 static int 1917 pci_moxa_setup(struct serial_private *priv, 1918 const struct pciserial_board *board, 1919 struct uart_8250_port *port, int idx) 1920 { 1921 unsigned int bar = FL_GET_BASE(board->flags); 1922 int offset; 1923 1924 if (board->num_ports == 4 && idx == 3) 1925 offset = 7 * board->uart_offset; 1926 else 1927 offset = idx * board->uart_offset; 1928 1929 return setup_port(priv, port, bar, offset, 0); 1930 } 1931 1932 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1933 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1934 #define PCI_DEVICE_ID_OCTPRO 0x0001 1935 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1936 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1937 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1938 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1939 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1940 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1941 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1942 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1943 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1944 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1945 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1946 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1947 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1948 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1949 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1950 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1951 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1952 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1953 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1954 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1955 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1956 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1957 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1958 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1959 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1960 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1961 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1962 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1963 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1964 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1965 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1966 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1967 #define PCI_VENDOR_ID_WCH 0x4348 1968 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1969 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1970 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1971 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1972 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1973 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1974 #define PCI_VENDOR_ID_AGESTAR 0x5372 1975 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1976 #define PCI_VENDOR_ID_ASIX 0x9710 1977 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1978 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1979 1980 #define PCIE_VENDOR_ID_WCH 0x1c00 1981 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1982 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1983 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 1984 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1985 1986 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 1987 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 1988 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 1989 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 1990 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 1991 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 1992 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 1993 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 1994 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 1995 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 1996 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 1997 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 1998 1999 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 2000 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 2001 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 2002 2003 /* 2004 * Master list of serial port init/setup/exit quirks. 2005 * This does not describe the general nature of the port. 2006 * (ie, baud base, number and location of ports, etc) 2007 * 2008 * This list is ordered alphabetically by vendor then device. 2009 * Specific entries must come before more generic entries. 2010 */ 2011 static struct pci_serial_quirk pci_serial_quirks[] = { 2012 /* 2013 * ADDI-DATA GmbH communication cards <info@addi-data.com> 2014 */ 2015 { 2016 .vendor = PCI_VENDOR_ID_AMCC, 2017 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 2018 .subvendor = PCI_ANY_ID, 2019 .subdevice = PCI_ANY_ID, 2020 .setup = addidata_apci7800_setup, 2021 }, 2022 /* 2023 * AFAVLAB cards - these may be called via parport_serial 2024 * It is not clear whether this applies to all products. 2025 */ 2026 { 2027 .vendor = PCI_VENDOR_ID_AFAVLAB, 2028 .device = PCI_ANY_ID, 2029 .subvendor = PCI_ANY_ID, 2030 .subdevice = PCI_ANY_ID, 2031 .setup = afavlab_setup, 2032 }, 2033 /* 2034 * HP Diva 2035 */ 2036 { 2037 .vendor = PCI_VENDOR_ID_HP, 2038 .device = PCI_DEVICE_ID_HP_DIVA, 2039 .subvendor = PCI_ANY_ID, 2040 .subdevice = PCI_ANY_ID, 2041 .init = pci_hp_diva_init, 2042 .setup = pci_hp_diva_setup, 2043 }, 2044 /* 2045 * HPE PCI serial device 2046 */ 2047 { 2048 .vendor = PCI_VENDOR_ID_HP_3PAR, 2049 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 2050 .subvendor = PCI_ANY_ID, 2051 .subdevice = PCI_ANY_ID, 2052 .setup = pci_hp_diva_setup, 2053 }, 2054 /* 2055 * Intel 2056 */ 2057 { 2058 .vendor = PCI_VENDOR_ID_INTEL, 2059 .device = PCI_DEVICE_ID_INTEL_80960_RP, 2060 .subvendor = 0xe4bf, 2061 .subdevice = PCI_ANY_ID, 2062 .init = pci_inteli960ni_init, 2063 .setup = pci_default_setup, 2064 }, 2065 { 2066 .vendor = PCI_VENDOR_ID_INTEL, 2067 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2068 .subvendor = PCI_ANY_ID, 2069 .subdevice = PCI_ANY_ID, 2070 .setup = skip_tx_en_setup, 2071 }, 2072 { 2073 .vendor = PCI_VENDOR_ID_INTEL, 2074 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2075 .subvendor = PCI_ANY_ID, 2076 .subdevice = PCI_ANY_ID, 2077 .setup = skip_tx_en_setup, 2078 }, 2079 { 2080 .vendor = PCI_VENDOR_ID_INTEL, 2081 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2082 .subvendor = PCI_ANY_ID, 2083 .subdevice = PCI_ANY_ID, 2084 .setup = skip_tx_en_setup, 2085 }, 2086 { 2087 .vendor = PCI_VENDOR_ID_INTEL, 2088 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2089 .subvendor = PCI_ANY_ID, 2090 .subdevice = PCI_ANY_ID, 2091 .setup = ce4100_serial_setup, 2092 }, 2093 { 2094 .vendor = PCI_VENDOR_ID_INTEL, 2095 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2096 .subvendor = PCI_ANY_ID, 2097 .subdevice = PCI_ANY_ID, 2098 .setup = kt_serial_setup, 2099 }, 2100 /* 2101 * ITE 2102 */ 2103 { 2104 .vendor = PCI_VENDOR_ID_ITE, 2105 .device = PCI_DEVICE_ID_ITE_8872, 2106 .subvendor = PCI_ANY_ID, 2107 .subdevice = PCI_ANY_ID, 2108 .init = pci_ite887x_init, 2109 .setup = pci_default_setup, 2110 .exit = pci_ite887x_exit, 2111 }, 2112 /* 2113 * National Instruments 2114 */ 2115 { 2116 .vendor = PCI_VENDOR_ID_NI, 2117 .device = PCI_DEVICE_ID_NI_PCI23216, 2118 .subvendor = PCI_ANY_ID, 2119 .subdevice = PCI_ANY_ID, 2120 .init = pci_ni8420_init, 2121 .setup = pci_default_setup, 2122 .exit = pci_ni8420_exit, 2123 }, 2124 { 2125 .vendor = PCI_VENDOR_ID_NI, 2126 .device = PCI_DEVICE_ID_NI_PCI2328, 2127 .subvendor = PCI_ANY_ID, 2128 .subdevice = PCI_ANY_ID, 2129 .init = pci_ni8420_init, 2130 .setup = pci_default_setup, 2131 .exit = pci_ni8420_exit, 2132 }, 2133 { 2134 .vendor = PCI_VENDOR_ID_NI, 2135 .device = PCI_DEVICE_ID_NI_PCI2324, 2136 .subvendor = PCI_ANY_ID, 2137 .subdevice = PCI_ANY_ID, 2138 .init = pci_ni8420_init, 2139 .setup = pci_default_setup, 2140 .exit = pci_ni8420_exit, 2141 }, 2142 { 2143 .vendor = PCI_VENDOR_ID_NI, 2144 .device = PCI_DEVICE_ID_NI_PCI2322, 2145 .subvendor = PCI_ANY_ID, 2146 .subdevice = PCI_ANY_ID, 2147 .init = pci_ni8420_init, 2148 .setup = pci_default_setup, 2149 .exit = pci_ni8420_exit, 2150 }, 2151 { 2152 .vendor = PCI_VENDOR_ID_NI, 2153 .device = PCI_DEVICE_ID_NI_PCI2324I, 2154 .subvendor = PCI_ANY_ID, 2155 .subdevice = PCI_ANY_ID, 2156 .init = pci_ni8420_init, 2157 .setup = pci_default_setup, 2158 .exit = pci_ni8420_exit, 2159 }, 2160 { 2161 .vendor = PCI_VENDOR_ID_NI, 2162 .device = PCI_DEVICE_ID_NI_PCI2322I, 2163 .subvendor = PCI_ANY_ID, 2164 .subdevice = PCI_ANY_ID, 2165 .init = pci_ni8420_init, 2166 .setup = pci_default_setup, 2167 .exit = pci_ni8420_exit, 2168 }, 2169 { 2170 .vendor = PCI_VENDOR_ID_NI, 2171 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2172 .subvendor = PCI_ANY_ID, 2173 .subdevice = PCI_ANY_ID, 2174 .init = pci_ni8420_init, 2175 .setup = pci_default_setup, 2176 .exit = pci_ni8420_exit, 2177 }, 2178 { 2179 .vendor = PCI_VENDOR_ID_NI, 2180 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2181 .subvendor = PCI_ANY_ID, 2182 .subdevice = PCI_ANY_ID, 2183 .init = pci_ni8420_init, 2184 .setup = pci_default_setup, 2185 .exit = pci_ni8420_exit, 2186 }, 2187 { 2188 .vendor = PCI_VENDOR_ID_NI, 2189 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2190 .subvendor = PCI_ANY_ID, 2191 .subdevice = PCI_ANY_ID, 2192 .init = pci_ni8420_init, 2193 .setup = pci_default_setup, 2194 .exit = pci_ni8420_exit, 2195 }, 2196 { 2197 .vendor = PCI_VENDOR_ID_NI, 2198 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2199 .subvendor = PCI_ANY_ID, 2200 .subdevice = PCI_ANY_ID, 2201 .init = pci_ni8420_init, 2202 .setup = pci_default_setup, 2203 .exit = pci_ni8420_exit, 2204 }, 2205 { 2206 .vendor = PCI_VENDOR_ID_NI, 2207 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2208 .subvendor = PCI_ANY_ID, 2209 .subdevice = PCI_ANY_ID, 2210 .init = pci_ni8420_init, 2211 .setup = pci_default_setup, 2212 .exit = pci_ni8420_exit, 2213 }, 2214 { 2215 .vendor = PCI_VENDOR_ID_NI, 2216 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2217 .subvendor = PCI_ANY_ID, 2218 .subdevice = PCI_ANY_ID, 2219 .init = pci_ni8420_init, 2220 .setup = pci_default_setup, 2221 .exit = pci_ni8420_exit, 2222 }, 2223 { 2224 .vendor = PCI_VENDOR_ID_NI, 2225 .device = PCI_ANY_ID, 2226 .subvendor = PCI_ANY_ID, 2227 .subdevice = PCI_ANY_ID, 2228 .init = pci_ni8430_init, 2229 .setup = pci_ni8430_setup, 2230 .exit = pci_ni8430_exit, 2231 }, 2232 /* Quatech */ 2233 { 2234 .vendor = PCI_VENDOR_ID_QUATECH, 2235 .device = PCI_ANY_ID, 2236 .subvendor = PCI_ANY_ID, 2237 .subdevice = PCI_ANY_ID, 2238 .init = pci_quatech_init, 2239 .setup = pci_quatech_setup, 2240 }, 2241 /* 2242 * Panacom 2243 */ 2244 { 2245 .vendor = PCI_VENDOR_ID_PANACOM, 2246 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2247 .subvendor = PCI_ANY_ID, 2248 .subdevice = PCI_ANY_ID, 2249 .init = pci_plx9050_init, 2250 .setup = pci_default_setup, 2251 .exit = pci_plx9050_exit, 2252 }, 2253 { 2254 .vendor = PCI_VENDOR_ID_PANACOM, 2255 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2256 .subvendor = PCI_ANY_ID, 2257 .subdevice = PCI_ANY_ID, 2258 .init = pci_plx9050_init, 2259 .setup = pci_default_setup, 2260 .exit = pci_plx9050_exit, 2261 }, 2262 /* 2263 * PLX 2264 */ 2265 { 2266 .vendor = PCI_VENDOR_ID_PLX, 2267 .device = PCI_DEVICE_ID_PLX_9050, 2268 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2269 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2270 .init = pci_plx9050_init, 2271 .setup = pci_default_setup, 2272 .exit = pci_plx9050_exit, 2273 }, 2274 { 2275 .vendor = PCI_VENDOR_ID_PLX, 2276 .device = PCI_DEVICE_ID_PLX_9050, 2277 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2278 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2279 .init = pci_plx9050_init, 2280 .setup = pci_default_setup, 2281 .exit = pci_plx9050_exit, 2282 }, 2283 { 2284 .vendor = PCI_VENDOR_ID_PLX, 2285 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2286 .subvendor = PCI_VENDOR_ID_PLX, 2287 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2288 .init = pci_plx9050_init, 2289 .setup = pci_default_setup, 2290 .exit = pci_plx9050_exit, 2291 }, 2292 /* 2293 * SBS Technologies, Inc., PMC-OCTALPRO 232 2294 */ 2295 { 2296 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2297 .device = PCI_DEVICE_ID_OCTPRO, 2298 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2299 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2300 .init = sbs_init, 2301 .setup = sbs_setup, 2302 .exit = sbs_exit, 2303 }, 2304 /* 2305 * SBS Technologies, Inc., PMC-OCTALPRO 422 2306 */ 2307 { 2308 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2309 .device = PCI_DEVICE_ID_OCTPRO, 2310 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2311 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2312 .init = sbs_init, 2313 .setup = sbs_setup, 2314 .exit = sbs_exit, 2315 }, 2316 /* 2317 * SBS Technologies, Inc., P-Octal 232 2318 */ 2319 { 2320 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2321 .device = PCI_DEVICE_ID_OCTPRO, 2322 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2323 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2324 .init = sbs_init, 2325 .setup = sbs_setup, 2326 .exit = sbs_exit, 2327 }, 2328 /* 2329 * SBS Technologies, Inc., P-Octal 422 2330 */ 2331 { 2332 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2333 .device = PCI_DEVICE_ID_OCTPRO, 2334 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2335 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2336 .init = sbs_init, 2337 .setup = sbs_setup, 2338 .exit = sbs_exit, 2339 }, 2340 /* 2341 * SIIG cards - these may be called via parport_serial 2342 */ 2343 { 2344 .vendor = PCI_VENDOR_ID_SIIG, 2345 .device = PCI_ANY_ID, 2346 .subvendor = PCI_ANY_ID, 2347 .subdevice = PCI_ANY_ID, 2348 .init = pci_siig_init, 2349 .setup = pci_siig_setup, 2350 }, 2351 /* 2352 * Titan cards 2353 */ 2354 { 2355 .vendor = PCI_VENDOR_ID_TITAN, 2356 .device = PCI_DEVICE_ID_TITAN_400L, 2357 .subvendor = PCI_ANY_ID, 2358 .subdevice = PCI_ANY_ID, 2359 .setup = titan_400l_800l_setup, 2360 }, 2361 { 2362 .vendor = PCI_VENDOR_ID_TITAN, 2363 .device = PCI_DEVICE_ID_TITAN_800L, 2364 .subvendor = PCI_ANY_ID, 2365 .subdevice = PCI_ANY_ID, 2366 .setup = titan_400l_800l_setup, 2367 }, 2368 /* 2369 * Timedia cards 2370 */ 2371 { 2372 .vendor = PCI_VENDOR_ID_TIMEDIA, 2373 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2374 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2375 .subdevice = PCI_ANY_ID, 2376 .probe = pci_timedia_probe, 2377 .init = pci_timedia_init, 2378 .setup = pci_timedia_setup, 2379 }, 2380 { 2381 .vendor = PCI_VENDOR_ID_TIMEDIA, 2382 .device = PCI_ANY_ID, 2383 .subvendor = PCI_ANY_ID, 2384 .subdevice = PCI_ANY_ID, 2385 .setup = pci_timedia_setup, 2386 }, 2387 /* 2388 * Sunix PCI serial boards 2389 */ 2390 { 2391 .vendor = PCI_VENDOR_ID_SUNIX, 2392 .device = PCI_DEVICE_ID_SUNIX_1999, 2393 .subvendor = PCI_VENDOR_ID_SUNIX, 2394 .subdevice = PCI_ANY_ID, 2395 .setup = pci_sunix_setup, 2396 }, 2397 /* 2398 * Xircom cards 2399 */ 2400 { 2401 .vendor = PCI_VENDOR_ID_XIRCOM, 2402 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2403 .subvendor = PCI_ANY_ID, 2404 .subdevice = PCI_ANY_ID, 2405 .init = pci_xircom_init, 2406 .setup = pci_default_setup, 2407 }, 2408 /* 2409 * Netmos cards - these may be called via parport_serial 2410 */ 2411 { 2412 .vendor = PCI_VENDOR_ID_NETMOS, 2413 .device = PCI_ANY_ID, 2414 .subvendor = PCI_ANY_ID, 2415 .subdevice = PCI_ANY_ID, 2416 .init = pci_netmos_init, 2417 .setup = pci_netmos_9900_setup, 2418 }, 2419 /* 2420 * EndRun Technologies 2421 */ 2422 { 2423 .vendor = PCI_VENDOR_ID_ENDRUN, 2424 .device = PCI_ANY_ID, 2425 .subvendor = PCI_ANY_ID, 2426 .subdevice = PCI_ANY_ID, 2427 .init = pci_oxsemi_tornado_init, 2428 .setup = pci_default_setup, 2429 }, 2430 /* 2431 * For Oxford Semiconductor Tornado based devices 2432 */ 2433 { 2434 .vendor = PCI_VENDOR_ID_OXSEMI, 2435 .device = PCI_ANY_ID, 2436 .subvendor = PCI_ANY_ID, 2437 .subdevice = PCI_ANY_ID, 2438 .init = pci_oxsemi_tornado_init, 2439 .setup = pci_oxsemi_tornado_setup, 2440 }, 2441 { 2442 .vendor = PCI_VENDOR_ID_MAINPINE, 2443 .device = PCI_ANY_ID, 2444 .subvendor = PCI_ANY_ID, 2445 .subdevice = PCI_ANY_ID, 2446 .init = pci_oxsemi_tornado_init, 2447 .setup = pci_oxsemi_tornado_setup, 2448 }, 2449 { 2450 .vendor = PCI_VENDOR_ID_DIGI, 2451 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2452 .subvendor = PCI_SUBVENDOR_ID_IBM, 2453 .subdevice = PCI_ANY_ID, 2454 .init = pci_oxsemi_tornado_init, 2455 .setup = pci_oxsemi_tornado_setup, 2456 }, 2457 { 2458 .vendor = PCI_VENDOR_ID_INTEL, 2459 .device = 0x8811, 2460 .subvendor = PCI_ANY_ID, 2461 .subdevice = PCI_ANY_ID, 2462 .init = pci_eg20t_init, 2463 .setup = pci_default_setup, 2464 }, 2465 { 2466 .vendor = PCI_VENDOR_ID_INTEL, 2467 .device = 0x8812, 2468 .subvendor = PCI_ANY_ID, 2469 .subdevice = PCI_ANY_ID, 2470 .init = pci_eg20t_init, 2471 .setup = pci_default_setup, 2472 }, 2473 { 2474 .vendor = PCI_VENDOR_ID_INTEL, 2475 .device = 0x8813, 2476 .subvendor = PCI_ANY_ID, 2477 .subdevice = PCI_ANY_ID, 2478 .init = pci_eg20t_init, 2479 .setup = pci_default_setup, 2480 }, 2481 { 2482 .vendor = PCI_VENDOR_ID_INTEL, 2483 .device = 0x8814, 2484 .subvendor = PCI_ANY_ID, 2485 .subdevice = PCI_ANY_ID, 2486 .init = pci_eg20t_init, 2487 .setup = pci_default_setup, 2488 }, 2489 { 2490 .vendor = 0x10DB, 2491 .device = 0x8027, 2492 .subvendor = PCI_ANY_ID, 2493 .subdevice = PCI_ANY_ID, 2494 .init = pci_eg20t_init, 2495 .setup = pci_default_setup, 2496 }, 2497 { 2498 .vendor = 0x10DB, 2499 .device = 0x8028, 2500 .subvendor = PCI_ANY_ID, 2501 .subdevice = PCI_ANY_ID, 2502 .init = pci_eg20t_init, 2503 .setup = pci_default_setup, 2504 }, 2505 { 2506 .vendor = 0x10DB, 2507 .device = 0x8029, 2508 .subvendor = PCI_ANY_ID, 2509 .subdevice = PCI_ANY_ID, 2510 .init = pci_eg20t_init, 2511 .setup = pci_default_setup, 2512 }, 2513 { 2514 .vendor = 0x10DB, 2515 .device = 0x800C, 2516 .subvendor = PCI_ANY_ID, 2517 .subdevice = PCI_ANY_ID, 2518 .init = pci_eg20t_init, 2519 .setup = pci_default_setup, 2520 }, 2521 { 2522 .vendor = 0x10DB, 2523 .device = 0x800D, 2524 .subvendor = PCI_ANY_ID, 2525 .subdevice = PCI_ANY_ID, 2526 .init = pci_eg20t_init, 2527 .setup = pci_default_setup, 2528 }, 2529 /* 2530 * Cronyx Omega PCI (PLX-chip based) 2531 */ 2532 { 2533 .vendor = PCI_VENDOR_ID_PLX, 2534 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2535 .subvendor = PCI_ANY_ID, 2536 .subdevice = PCI_ANY_ID, 2537 .setup = pci_omegapci_setup, 2538 }, 2539 /* WCH CH353 1S1P card (16550 clone) */ 2540 { 2541 .vendor = PCI_VENDOR_ID_WCH, 2542 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2543 .subvendor = PCI_ANY_ID, 2544 .subdevice = PCI_ANY_ID, 2545 .setup = pci_wch_ch353_setup, 2546 }, 2547 /* WCH CH353 2S1P card (16550 clone) */ 2548 { 2549 .vendor = PCI_VENDOR_ID_WCH, 2550 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2551 .subvendor = PCI_ANY_ID, 2552 .subdevice = PCI_ANY_ID, 2553 .setup = pci_wch_ch353_setup, 2554 }, 2555 /* WCH CH353 4S card (16550 clone) */ 2556 { 2557 .vendor = PCI_VENDOR_ID_WCH, 2558 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2559 .subvendor = PCI_ANY_ID, 2560 .subdevice = PCI_ANY_ID, 2561 .setup = pci_wch_ch353_setup, 2562 }, 2563 /* WCH CH353 2S1PF card (16550 clone) */ 2564 { 2565 .vendor = PCI_VENDOR_ID_WCH, 2566 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2567 .subvendor = PCI_ANY_ID, 2568 .subdevice = PCI_ANY_ID, 2569 .setup = pci_wch_ch353_setup, 2570 }, 2571 /* WCH CH352 2S card (16550 clone) */ 2572 { 2573 .vendor = PCI_VENDOR_ID_WCH, 2574 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2575 .subvendor = PCI_ANY_ID, 2576 .subdevice = PCI_ANY_ID, 2577 .setup = pci_wch_ch353_setup, 2578 }, 2579 /* WCH CH355 4S card (16550 clone) */ 2580 { 2581 .vendor = PCI_VENDOR_ID_WCH, 2582 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2583 .subvendor = PCI_ANY_ID, 2584 .subdevice = PCI_ANY_ID, 2585 .setup = pci_wch_ch355_setup, 2586 }, 2587 /* WCH CH382 2S card (16850 clone) */ 2588 { 2589 .vendor = PCIE_VENDOR_ID_WCH, 2590 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2591 .subvendor = PCI_ANY_ID, 2592 .subdevice = PCI_ANY_ID, 2593 .setup = pci_wch_ch38x_setup, 2594 }, 2595 /* WCH CH382 2S1P card (16850 clone) */ 2596 { 2597 .vendor = PCIE_VENDOR_ID_WCH, 2598 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2599 .subvendor = PCI_ANY_ID, 2600 .subdevice = PCI_ANY_ID, 2601 .setup = pci_wch_ch38x_setup, 2602 }, 2603 /* WCH CH384 4S card (16850 clone) */ 2604 { 2605 .vendor = PCIE_VENDOR_ID_WCH, 2606 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2607 .subvendor = PCI_ANY_ID, 2608 .subdevice = PCI_ANY_ID, 2609 .setup = pci_wch_ch38x_setup, 2610 }, 2611 /* WCH CH384 8S card (16850 clone) */ 2612 { 2613 .vendor = PCIE_VENDOR_ID_WCH, 2614 .device = PCIE_DEVICE_ID_WCH_CH384_8S, 2615 .subvendor = PCI_ANY_ID, 2616 .subdevice = PCI_ANY_ID, 2617 .init = pci_wch_ch38x_init, 2618 .exit = pci_wch_ch38x_exit, 2619 .setup = pci_wch_ch38x_setup, 2620 }, 2621 /* 2622 * ASIX devices with FIFO bug 2623 */ 2624 { 2625 .vendor = PCI_VENDOR_ID_ASIX, 2626 .device = PCI_ANY_ID, 2627 .subvendor = PCI_ANY_ID, 2628 .subdevice = PCI_ANY_ID, 2629 .setup = pci_asix_setup, 2630 }, 2631 /* 2632 * Broadcom TruManage (NetXtreme) 2633 */ 2634 { 2635 .vendor = PCI_VENDOR_ID_BROADCOM, 2636 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2637 .subvendor = PCI_ANY_ID, 2638 .subdevice = PCI_ANY_ID, 2639 .setup = pci_brcm_trumanage_setup, 2640 }, 2641 { 2642 .vendor = 0x1c29, 2643 .device = 0x1104, 2644 .subvendor = PCI_ANY_ID, 2645 .subdevice = PCI_ANY_ID, 2646 .setup = pci_fintek_setup, 2647 .init = pci_fintek_init, 2648 }, 2649 { 2650 .vendor = 0x1c29, 2651 .device = 0x1108, 2652 .subvendor = PCI_ANY_ID, 2653 .subdevice = PCI_ANY_ID, 2654 .setup = pci_fintek_setup, 2655 .init = pci_fintek_init, 2656 }, 2657 { 2658 .vendor = 0x1c29, 2659 .device = 0x1112, 2660 .subvendor = PCI_ANY_ID, 2661 .subdevice = PCI_ANY_ID, 2662 .setup = pci_fintek_setup, 2663 .init = pci_fintek_init, 2664 }, 2665 /* 2666 * MOXA 2667 */ 2668 { 2669 .vendor = PCI_VENDOR_ID_MOXA, 2670 .device = PCI_ANY_ID, 2671 .subvendor = PCI_ANY_ID, 2672 .subdevice = PCI_ANY_ID, 2673 .setup = pci_moxa_setup, 2674 }, 2675 { 2676 .vendor = 0x1c29, 2677 .device = 0x1204, 2678 .subvendor = PCI_ANY_ID, 2679 .subdevice = PCI_ANY_ID, 2680 .setup = pci_fintek_f815xxa_setup, 2681 .init = pci_fintek_f815xxa_init, 2682 }, 2683 { 2684 .vendor = 0x1c29, 2685 .device = 0x1208, 2686 .subvendor = PCI_ANY_ID, 2687 .subdevice = PCI_ANY_ID, 2688 .setup = pci_fintek_f815xxa_setup, 2689 .init = pci_fintek_f815xxa_init, 2690 }, 2691 { 2692 .vendor = 0x1c29, 2693 .device = 0x1212, 2694 .subvendor = PCI_ANY_ID, 2695 .subdevice = PCI_ANY_ID, 2696 .setup = pci_fintek_f815xxa_setup, 2697 .init = pci_fintek_f815xxa_init, 2698 }, 2699 2700 /* 2701 * Default "match everything" terminator entry 2702 */ 2703 { 2704 .vendor = PCI_ANY_ID, 2705 .device = PCI_ANY_ID, 2706 .subvendor = PCI_ANY_ID, 2707 .subdevice = PCI_ANY_ID, 2708 .setup = pci_default_setup, 2709 } 2710 }; 2711 2712 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2713 { 2714 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2715 } 2716 2717 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2718 { 2719 struct pci_serial_quirk *quirk; 2720 2721 for (quirk = pci_serial_quirks; ; quirk++) 2722 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2723 quirk_id_matches(quirk->device, dev->device) && 2724 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2725 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2726 break; 2727 return quirk; 2728 } 2729 2730 /* 2731 * This is the configuration table for all of the PCI serial boards 2732 * which we support. It is directly indexed by the pci_board_num_t enum 2733 * value, which is encoded in the pci_device_id PCI probe table's 2734 * driver_data member. 2735 * 2736 * The makeup of these names are: 2737 * pbn_bn{_bt}_n_baud{_offsetinhex} 2738 * 2739 * bn = PCI BAR number 2740 * bt = Index using PCI BARs 2741 * n = number of serial ports 2742 * baud = baud rate 2743 * offsetinhex = offset for each sequential port (in hex) 2744 * 2745 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2746 * 2747 * Please note: in theory if n = 1, _bt infix should make no difference. 2748 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2749 */ 2750 enum pci_board_num_t { 2751 pbn_default = 0, 2752 2753 pbn_b0_1_115200, 2754 pbn_b0_2_115200, 2755 pbn_b0_4_115200, 2756 pbn_b0_5_115200, 2757 pbn_b0_8_115200, 2758 2759 pbn_b0_1_921600, 2760 pbn_b0_2_921600, 2761 pbn_b0_4_921600, 2762 2763 pbn_b0_2_1130000, 2764 2765 pbn_b0_4_1152000, 2766 2767 pbn_b0_4_1250000, 2768 2769 pbn_b0_2_1843200, 2770 pbn_b0_4_1843200, 2771 2772 pbn_b0_1_15625000, 2773 2774 pbn_b0_bt_1_115200, 2775 pbn_b0_bt_2_115200, 2776 pbn_b0_bt_4_115200, 2777 pbn_b0_bt_8_115200, 2778 2779 pbn_b0_bt_1_460800, 2780 pbn_b0_bt_2_460800, 2781 pbn_b0_bt_4_460800, 2782 2783 pbn_b0_bt_1_921600, 2784 pbn_b0_bt_2_921600, 2785 pbn_b0_bt_4_921600, 2786 pbn_b0_bt_8_921600, 2787 2788 pbn_b1_1_115200, 2789 pbn_b1_2_115200, 2790 pbn_b1_4_115200, 2791 pbn_b1_8_115200, 2792 pbn_b1_16_115200, 2793 2794 pbn_b1_1_921600, 2795 pbn_b1_2_921600, 2796 pbn_b1_4_921600, 2797 pbn_b1_8_921600, 2798 2799 pbn_b1_2_1250000, 2800 2801 pbn_b1_bt_1_115200, 2802 pbn_b1_bt_2_115200, 2803 pbn_b1_bt_4_115200, 2804 2805 pbn_b1_bt_2_921600, 2806 2807 pbn_b1_1_1382400, 2808 pbn_b1_2_1382400, 2809 pbn_b1_4_1382400, 2810 pbn_b1_8_1382400, 2811 2812 pbn_b2_1_115200, 2813 pbn_b2_2_115200, 2814 pbn_b2_4_115200, 2815 pbn_b2_8_115200, 2816 2817 pbn_b2_1_460800, 2818 pbn_b2_4_460800, 2819 pbn_b2_8_460800, 2820 pbn_b2_16_460800, 2821 2822 pbn_b2_1_921600, 2823 pbn_b2_4_921600, 2824 pbn_b2_8_921600, 2825 2826 pbn_b2_8_1152000, 2827 2828 pbn_b2_bt_1_115200, 2829 pbn_b2_bt_2_115200, 2830 pbn_b2_bt_4_115200, 2831 2832 pbn_b2_bt_2_921600, 2833 pbn_b2_bt_4_921600, 2834 2835 pbn_b3_2_115200, 2836 pbn_b3_4_115200, 2837 pbn_b3_8_115200, 2838 2839 pbn_b4_bt_2_921600, 2840 pbn_b4_bt_4_921600, 2841 pbn_b4_bt_8_921600, 2842 2843 /* 2844 * Board-specific versions. 2845 */ 2846 pbn_panacom, 2847 pbn_panacom2, 2848 pbn_panacom4, 2849 pbn_plx_romulus, 2850 pbn_oxsemi, 2851 pbn_oxsemi_1_15625000, 2852 pbn_oxsemi_2_15625000, 2853 pbn_oxsemi_4_15625000, 2854 pbn_oxsemi_8_15625000, 2855 pbn_intel_i960, 2856 pbn_sgi_ioc3, 2857 pbn_computone_4, 2858 pbn_computone_6, 2859 pbn_computone_8, 2860 pbn_sbsxrsio, 2861 pbn_pasemi_1682M, 2862 pbn_ni8430_2, 2863 pbn_ni8430_4, 2864 pbn_ni8430_8, 2865 pbn_ni8430_16, 2866 pbn_ADDIDATA_PCIe_1_3906250, 2867 pbn_ADDIDATA_PCIe_2_3906250, 2868 pbn_ADDIDATA_PCIe_4_3906250, 2869 pbn_ADDIDATA_PCIe_8_3906250, 2870 pbn_ce4100_1_115200, 2871 pbn_omegapci, 2872 pbn_NETMOS9900_2s_115200, 2873 pbn_brcm_trumanage, 2874 pbn_fintek_4, 2875 pbn_fintek_8, 2876 pbn_fintek_12, 2877 pbn_fintek_F81504A, 2878 pbn_fintek_F81508A, 2879 pbn_fintek_F81512A, 2880 pbn_wch382_2, 2881 pbn_wch384_4, 2882 pbn_wch384_8, 2883 pbn_sunix_pci_1s, 2884 pbn_sunix_pci_2s, 2885 pbn_sunix_pci_4s, 2886 pbn_sunix_pci_8s, 2887 pbn_sunix_pci_16s, 2888 pbn_titan_1_4000000, 2889 pbn_titan_2_4000000, 2890 pbn_titan_4_4000000, 2891 pbn_titan_8_4000000, 2892 pbn_moxa8250_2p, 2893 pbn_moxa8250_4p, 2894 pbn_moxa8250_8p, 2895 }; 2896 2897 /* 2898 * uart_offset - the space between channels 2899 * reg_shift - describes how the UART registers are mapped 2900 * to PCI memory by the card. 2901 * For example IER register on SBS, Inc. PMC-OctPro is located at 2902 * offset 0x10 from the UART base, while UART_IER is defined as 1 2903 * in include/linux/serial_reg.h, 2904 * see first lines of serial_in() and serial_out() in 8250.c 2905 */ 2906 2907 static struct pciserial_board pci_boards[] = { 2908 [pbn_default] = { 2909 .flags = FL_BASE0, 2910 .num_ports = 1, 2911 .base_baud = 115200, 2912 .uart_offset = 8, 2913 }, 2914 [pbn_b0_1_115200] = { 2915 .flags = FL_BASE0, 2916 .num_ports = 1, 2917 .base_baud = 115200, 2918 .uart_offset = 8, 2919 }, 2920 [pbn_b0_2_115200] = { 2921 .flags = FL_BASE0, 2922 .num_ports = 2, 2923 .base_baud = 115200, 2924 .uart_offset = 8, 2925 }, 2926 [pbn_b0_4_115200] = { 2927 .flags = FL_BASE0, 2928 .num_ports = 4, 2929 .base_baud = 115200, 2930 .uart_offset = 8, 2931 }, 2932 [pbn_b0_5_115200] = { 2933 .flags = FL_BASE0, 2934 .num_ports = 5, 2935 .base_baud = 115200, 2936 .uart_offset = 8, 2937 }, 2938 [pbn_b0_8_115200] = { 2939 .flags = FL_BASE0, 2940 .num_ports = 8, 2941 .base_baud = 115200, 2942 .uart_offset = 8, 2943 }, 2944 [pbn_b0_1_921600] = { 2945 .flags = FL_BASE0, 2946 .num_ports = 1, 2947 .base_baud = 921600, 2948 .uart_offset = 8, 2949 }, 2950 [pbn_b0_2_921600] = { 2951 .flags = FL_BASE0, 2952 .num_ports = 2, 2953 .base_baud = 921600, 2954 .uart_offset = 8, 2955 }, 2956 [pbn_b0_4_921600] = { 2957 .flags = FL_BASE0, 2958 .num_ports = 4, 2959 .base_baud = 921600, 2960 .uart_offset = 8, 2961 }, 2962 2963 [pbn_b0_2_1130000] = { 2964 .flags = FL_BASE0, 2965 .num_ports = 2, 2966 .base_baud = 1130000, 2967 .uart_offset = 8, 2968 }, 2969 2970 [pbn_b0_4_1152000] = { 2971 .flags = FL_BASE0, 2972 .num_ports = 4, 2973 .base_baud = 1152000, 2974 .uart_offset = 8, 2975 }, 2976 2977 [pbn_b0_4_1250000] = { 2978 .flags = FL_BASE0, 2979 .num_ports = 4, 2980 .base_baud = 1250000, 2981 .uart_offset = 8, 2982 }, 2983 2984 [pbn_b0_2_1843200] = { 2985 .flags = FL_BASE0, 2986 .num_ports = 2, 2987 .base_baud = 1843200, 2988 .uart_offset = 8, 2989 }, 2990 [pbn_b0_4_1843200] = { 2991 .flags = FL_BASE0, 2992 .num_ports = 4, 2993 .base_baud = 1843200, 2994 .uart_offset = 8, 2995 }, 2996 2997 [pbn_b0_1_15625000] = { 2998 .flags = FL_BASE0, 2999 .num_ports = 1, 3000 .base_baud = 15625000, 3001 .uart_offset = 8, 3002 }, 3003 3004 [pbn_b0_bt_1_115200] = { 3005 .flags = FL_BASE0|FL_BASE_BARS, 3006 .num_ports = 1, 3007 .base_baud = 115200, 3008 .uart_offset = 8, 3009 }, 3010 [pbn_b0_bt_2_115200] = { 3011 .flags = FL_BASE0|FL_BASE_BARS, 3012 .num_ports = 2, 3013 .base_baud = 115200, 3014 .uart_offset = 8, 3015 }, 3016 [pbn_b0_bt_4_115200] = { 3017 .flags = FL_BASE0|FL_BASE_BARS, 3018 .num_ports = 4, 3019 .base_baud = 115200, 3020 .uart_offset = 8, 3021 }, 3022 [pbn_b0_bt_8_115200] = { 3023 .flags = FL_BASE0|FL_BASE_BARS, 3024 .num_ports = 8, 3025 .base_baud = 115200, 3026 .uart_offset = 8, 3027 }, 3028 3029 [pbn_b0_bt_1_460800] = { 3030 .flags = FL_BASE0|FL_BASE_BARS, 3031 .num_ports = 1, 3032 .base_baud = 460800, 3033 .uart_offset = 8, 3034 }, 3035 [pbn_b0_bt_2_460800] = { 3036 .flags = FL_BASE0|FL_BASE_BARS, 3037 .num_ports = 2, 3038 .base_baud = 460800, 3039 .uart_offset = 8, 3040 }, 3041 [pbn_b0_bt_4_460800] = { 3042 .flags = FL_BASE0|FL_BASE_BARS, 3043 .num_ports = 4, 3044 .base_baud = 460800, 3045 .uart_offset = 8, 3046 }, 3047 3048 [pbn_b0_bt_1_921600] = { 3049 .flags = FL_BASE0|FL_BASE_BARS, 3050 .num_ports = 1, 3051 .base_baud = 921600, 3052 .uart_offset = 8, 3053 }, 3054 [pbn_b0_bt_2_921600] = { 3055 .flags = FL_BASE0|FL_BASE_BARS, 3056 .num_ports = 2, 3057 .base_baud = 921600, 3058 .uart_offset = 8, 3059 }, 3060 [pbn_b0_bt_4_921600] = { 3061 .flags = FL_BASE0|FL_BASE_BARS, 3062 .num_ports = 4, 3063 .base_baud = 921600, 3064 .uart_offset = 8, 3065 }, 3066 [pbn_b0_bt_8_921600] = { 3067 .flags = FL_BASE0|FL_BASE_BARS, 3068 .num_ports = 8, 3069 .base_baud = 921600, 3070 .uart_offset = 8, 3071 }, 3072 3073 [pbn_b1_1_115200] = { 3074 .flags = FL_BASE1, 3075 .num_ports = 1, 3076 .base_baud = 115200, 3077 .uart_offset = 8, 3078 }, 3079 [pbn_b1_2_115200] = { 3080 .flags = FL_BASE1, 3081 .num_ports = 2, 3082 .base_baud = 115200, 3083 .uart_offset = 8, 3084 }, 3085 [pbn_b1_4_115200] = { 3086 .flags = FL_BASE1, 3087 .num_ports = 4, 3088 .base_baud = 115200, 3089 .uart_offset = 8, 3090 }, 3091 [pbn_b1_8_115200] = { 3092 .flags = FL_BASE1, 3093 .num_ports = 8, 3094 .base_baud = 115200, 3095 .uart_offset = 8, 3096 }, 3097 [pbn_b1_16_115200] = { 3098 .flags = FL_BASE1, 3099 .num_ports = 16, 3100 .base_baud = 115200, 3101 .uart_offset = 8, 3102 }, 3103 3104 [pbn_b1_1_921600] = { 3105 .flags = FL_BASE1, 3106 .num_ports = 1, 3107 .base_baud = 921600, 3108 .uart_offset = 8, 3109 }, 3110 [pbn_b1_2_921600] = { 3111 .flags = FL_BASE1, 3112 .num_ports = 2, 3113 .base_baud = 921600, 3114 .uart_offset = 8, 3115 }, 3116 [pbn_b1_4_921600] = { 3117 .flags = FL_BASE1, 3118 .num_ports = 4, 3119 .base_baud = 921600, 3120 .uart_offset = 8, 3121 }, 3122 [pbn_b1_8_921600] = { 3123 .flags = FL_BASE1, 3124 .num_ports = 8, 3125 .base_baud = 921600, 3126 .uart_offset = 8, 3127 }, 3128 [pbn_b1_2_1250000] = { 3129 .flags = FL_BASE1, 3130 .num_ports = 2, 3131 .base_baud = 1250000, 3132 .uart_offset = 8, 3133 }, 3134 3135 [pbn_b1_bt_1_115200] = { 3136 .flags = FL_BASE1|FL_BASE_BARS, 3137 .num_ports = 1, 3138 .base_baud = 115200, 3139 .uart_offset = 8, 3140 }, 3141 [pbn_b1_bt_2_115200] = { 3142 .flags = FL_BASE1|FL_BASE_BARS, 3143 .num_ports = 2, 3144 .base_baud = 115200, 3145 .uart_offset = 8, 3146 }, 3147 [pbn_b1_bt_4_115200] = { 3148 .flags = FL_BASE1|FL_BASE_BARS, 3149 .num_ports = 4, 3150 .base_baud = 115200, 3151 .uart_offset = 8, 3152 }, 3153 3154 [pbn_b1_bt_2_921600] = { 3155 .flags = FL_BASE1|FL_BASE_BARS, 3156 .num_ports = 2, 3157 .base_baud = 921600, 3158 .uart_offset = 8, 3159 }, 3160 3161 [pbn_b1_1_1382400] = { 3162 .flags = FL_BASE1, 3163 .num_ports = 1, 3164 .base_baud = 1382400, 3165 .uart_offset = 8, 3166 }, 3167 [pbn_b1_2_1382400] = { 3168 .flags = FL_BASE1, 3169 .num_ports = 2, 3170 .base_baud = 1382400, 3171 .uart_offset = 8, 3172 }, 3173 [pbn_b1_4_1382400] = { 3174 .flags = FL_BASE1, 3175 .num_ports = 4, 3176 .base_baud = 1382400, 3177 .uart_offset = 8, 3178 }, 3179 [pbn_b1_8_1382400] = { 3180 .flags = FL_BASE1, 3181 .num_ports = 8, 3182 .base_baud = 1382400, 3183 .uart_offset = 8, 3184 }, 3185 3186 [pbn_b2_1_115200] = { 3187 .flags = FL_BASE2, 3188 .num_ports = 1, 3189 .base_baud = 115200, 3190 .uart_offset = 8, 3191 }, 3192 [pbn_b2_2_115200] = { 3193 .flags = FL_BASE2, 3194 .num_ports = 2, 3195 .base_baud = 115200, 3196 .uart_offset = 8, 3197 }, 3198 [pbn_b2_4_115200] = { 3199 .flags = FL_BASE2, 3200 .num_ports = 4, 3201 .base_baud = 115200, 3202 .uart_offset = 8, 3203 }, 3204 [pbn_b2_8_115200] = { 3205 .flags = FL_BASE2, 3206 .num_ports = 8, 3207 .base_baud = 115200, 3208 .uart_offset = 8, 3209 }, 3210 3211 [pbn_b2_1_460800] = { 3212 .flags = FL_BASE2, 3213 .num_ports = 1, 3214 .base_baud = 460800, 3215 .uart_offset = 8, 3216 }, 3217 [pbn_b2_4_460800] = { 3218 .flags = FL_BASE2, 3219 .num_ports = 4, 3220 .base_baud = 460800, 3221 .uart_offset = 8, 3222 }, 3223 [pbn_b2_8_460800] = { 3224 .flags = FL_BASE2, 3225 .num_ports = 8, 3226 .base_baud = 460800, 3227 .uart_offset = 8, 3228 }, 3229 [pbn_b2_16_460800] = { 3230 .flags = FL_BASE2, 3231 .num_ports = 16, 3232 .base_baud = 460800, 3233 .uart_offset = 8, 3234 }, 3235 3236 [pbn_b2_1_921600] = { 3237 .flags = FL_BASE2, 3238 .num_ports = 1, 3239 .base_baud = 921600, 3240 .uart_offset = 8, 3241 }, 3242 [pbn_b2_4_921600] = { 3243 .flags = FL_BASE2, 3244 .num_ports = 4, 3245 .base_baud = 921600, 3246 .uart_offset = 8, 3247 }, 3248 [pbn_b2_8_921600] = { 3249 .flags = FL_BASE2, 3250 .num_ports = 8, 3251 .base_baud = 921600, 3252 .uart_offset = 8, 3253 }, 3254 3255 [pbn_b2_8_1152000] = { 3256 .flags = FL_BASE2, 3257 .num_ports = 8, 3258 .base_baud = 1152000, 3259 .uart_offset = 8, 3260 }, 3261 3262 [pbn_b2_bt_1_115200] = { 3263 .flags = FL_BASE2|FL_BASE_BARS, 3264 .num_ports = 1, 3265 .base_baud = 115200, 3266 .uart_offset = 8, 3267 }, 3268 [pbn_b2_bt_2_115200] = { 3269 .flags = FL_BASE2|FL_BASE_BARS, 3270 .num_ports = 2, 3271 .base_baud = 115200, 3272 .uart_offset = 8, 3273 }, 3274 [pbn_b2_bt_4_115200] = { 3275 .flags = FL_BASE2|FL_BASE_BARS, 3276 .num_ports = 4, 3277 .base_baud = 115200, 3278 .uart_offset = 8, 3279 }, 3280 3281 [pbn_b2_bt_2_921600] = { 3282 .flags = FL_BASE2|FL_BASE_BARS, 3283 .num_ports = 2, 3284 .base_baud = 921600, 3285 .uart_offset = 8, 3286 }, 3287 [pbn_b2_bt_4_921600] = { 3288 .flags = FL_BASE2|FL_BASE_BARS, 3289 .num_ports = 4, 3290 .base_baud = 921600, 3291 .uart_offset = 8, 3292 }, 3293 3294 [pbn_b3_2_115200] = { 3295 .flags = FL_BASE3, 3296 .num_ports = 2, 3297 .base_baud = 115200, 3298 .uart_offset = 8, 3299 }, 3300 [pbn_b3_4_115200] = { 3301 .flags = FL_BASE3, 3302 .num_ports = 4, 3303 .base_baud = 115200, 3304 .uart_offset = 8, 3305 }, 3306 [pbn_b3_8_115200] = { 3307 .flags = FL_BASE3, 3308 .num_ports = 8, 3309 .base_baud = 115200, 3310 .uart_offset = 8, 3311 }, 3312 3313 [pbn_b4_bt_2_921600] = { 3314 .flags = FL_BASE4, 3315 .num_ports = 2, 3316 .base_baud = 921600, 3317 .uart_offset = 8, 3318 }, 3319 [pbn_b4_bt_4_921600] = { 3320 .flags = FL_BASE4, 3321 .num_ports = 4, 3322 .base_baud = 921600, 3323 .uart_offset = 8, 3324 }, 3325 [pbn_b4_bt_8_921600] = { 3326 .flags = FL_BASE4, 3327 .num_ports = 8, 3328 .base_baud = 921600, 3329 .uart_offset = 8, 3330 }, 3331 3332 /* 3333 * Entries following this are board-specific. 3334 */ 3335 3336 /* 3337 * Panacom - IOMEM 3338 */ 3339 [pbn_panacom] = { 3340 .flags = FL_BASE2, 3341 .num_ports = 2, 3342 .base_baud = 921600, 3343 .uart_offset = 0x400, 3344 .reg_shift = 7, 3345 }, 3346 [pbn_panacom2] = { 3347 .flags = FL_BASE2|FL_BASE_BARS, 3348 .num_ports = 2, 3349 .base_baud = 921600, 3350 .uart_offset = 0x400, 3351 .reg_shift = 7, 3352 }, 3353 [pbn_panacom4] = { 3354 .flags = FL_BASE2|FL_BASE_BARS, 3355 .num_ports = 4, 3356 .base_baud = 921600, 3357 .uart_offset = 0x400, 3358 .reg_shift = 7, 3359 }, 3360 3361 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3362 [pbn_plx_romulus] = { 3363 .flags = FL_BASE2, 3364 .num_ports = 4, 3365 .base_baud = 921600, 3366 .uart_offset = 8 << 2, 3367 .reg_shift = 2, 3368 .first_offset = 0x03, 3369 }, 3370 3371 /* 3372 * This board uses the size of PCI Base region 0 to 3373 * signal now many ports are available 3374 */ 3375 [pbn_oxsemi] = { 3376 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3377 .num_ports = 32, 3378 .base_baud = 115200, 3379 .uart_offset = 8, 3380 }, 3381 [pbn_oxsemi_1_15625000] = { 3382 .flags = FL_BASE0, 3383 .num_ports = 1, 3384 .base_baud = 15625000, 3385 .uart_offset = 0x200, 3386 .first_offset = 0x1000, 3387 }, 3388 [pbn_oxsemi_2_15625000] = { 3389 .flags = FL_BASE0, 3390 .num_ports = 2, 3391 .base_baud = 15625000, 3392 .uart_offset = 0x200, 3393 .first_offset = 0x1000, 3394 }, 3395 [pbn_oxsemi_4_15625000] = { 3396 .flags = FL_BASE0, 3397 .num_ports = 4, 3398 .base_baud = 15625000, 3399 .uart_offset = 0x200, 3400 .first_offset = 0x1000, 3401 }, 3402 [pbn_oxsemi_8_15625000] = { 3403 .flags = FL_BASE0, 3404 .num_ports = 8, 3405 .base_baud = 15625000, 3406 .uart_offset = 0x200, 3407 .first_offset = 0x1000, 3408 }, 3409 3410 3411 /* 3412 * EKF addition for i960 Boards form EKF with serial port. 3413 * Max 256 ports. 3414 */ 3415 [pbn_intel_i960] = { 3416 .flags = FL_BASE0, 3417 .num_ports = 32, 3418 .base_baud = 921600, 3419 .uart_offset = 8 << 2, 3420 .reg_shift = 2, 3421 .first_offset = 0x10000, 3422 }, 3423 [pbn_sgi_ioc3] = { 3424 .flags = FL_BASE0|FL_NOIRQ, 3425 .num_ports = 1, 3426 .base_baud = 458333, 3427 .uart_offset = 8, 3428 .reg_shift = 0, 3429 .first_offset = 0x20178, 3430 }, 3431 3432 /* 3433 * Computone - uses IOMEM. 3434 */ 3435 [pbn_computone_4] = { 3436 .flags = FL_BASE0, 3437 .num_ports = 4, 3438 .base_baud = 921600, 3439 .uart_offset = 0x40, 3440 .reg_shift = 2, 3441 .first_offset = 0x200, 3442 }, 3443 [pbn_computone_6] = { 3444 .flags = FL_BASE0, 3445 .num_ports = 6, 3446 .base_baud = 921600, 3447 .uart_offset = 0x40, 3448 .reg_shift = 2, 3449 .first_offset = 0x200, 3450 }, 3451 [pbn_computone_8] = { 3452 .flags = FL_BASE0, 3453 .num_ports = 8, 3454 .base_baud = 921600, 3455 .uart_offset = 0x40, 3456 .reg_shift = 2, 3457 .first_offset = 0x200, 3458 }, 3459 [pbn_sbsxrsio] = { 3460 .flags = FL_BASE0, 3461 .num_ports = 8, 3462 .base_baud = 460800, 3463 .uart_offset = 256, 3464 .reg_shift = 4, 3465 }, 3466 /* 3467 * PA Semi PWRficient PA6T-1682M on-chip UART 3468 */ 3469 [pbn_pasemi_1682M] = { 3470 .flags = FL_BASE0, 3471 .num_ports = 1, 3472 .base_baud = 8333333, 3473 }, 3474 /* 3475 * National Instruments 843x 3476 */ 3477 [pbn_ni8430_16] = { 3478 .flags = FL_BASE0, 3479 .num_ports = 16, 3480 .base_baud = 3686400, 3481 .uart_offset = 0x10, 3482 .first_offset = 0x800, 3483 }, 3484 [pbn_ni8430_8] = { 3485 .flags = FL_BASE0, 3486 .num_ports = 8, 3487 .base_baud = 3686400, 3488 .uart_offset = 0x10, 3489 .first_offset = 0x800, 3490 }, 3491 [pbn_ni8430_4] = { 3492 .flags = FL_BASE0, 3493 .num_ports = 4, 3494 .base_baud = 3686400, 3495 .uart_offset = 0x10, 3496 .first_offset = 0x800, 3497 }, 3498 [pbn_ni8430_2] = { 3499 .flags = FL_BASE0, 3500 .num_ports = 2, 3501 .base_baud = 3686400, 3502 .uart_offset = 0x10, 3503 .first_offset = 0x800, 3504 }, 3505 /* 3506 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3507 */ 3508 [pbn_ADDIDATA_PCIe_1_3906250] = { 3509 .flags = FL_BASE0, 3510 .num_ports = 1, 3511 .base_baud = 3906250, 3512 .uart_offset = 0x200, 3513 .first_offset = 0x1000, 3514 }, 3515 [pbn_ADDIDATA_PCIe_2_3906250] = { 3516 .flags = FL_BASE0, 3517 .num_ports = 2, 3518 .base_baud = 3906250, 3519 .uart_offset = 0x200, 3520 .first_offset = 0x1000, 3521 }, 3522 [pbn_ADDIDATA_PCIe_4_3906250] = { 3523 .flags = FL_BASE0, 3524 .num_ports = 4, 3525 .base_baud = 3906250, 3526 .uart_offset = 0x200, 3527 .first_offset = 0x1000, 3528 }, 3529 [pbn_ADDIDATA_PCIe_8_3906250] = { 3530 .flags = FL_BASE0, 3531 .num_ports = 8, 3532 .base_baud = 3906250, 3533 .uart_offset = 0x200, 3534 .first_offset = 0x1000, 3535 }, 3536 [pbn_ce4100_1_115200] = { 3537 .flags = FL_BASE_BARS, 3538 .num_ports = 2, 3539 .base_baud = 921600, 3540 .reg_shift = 2, 3541 }, 3542 [pbn_omegapci] = { 3543 .flags = FL_BASE0, 3544 .num_ports = 8, 3545 .base_baud = 115200, 3546 .uart_offset = 0x200, 3547 }, 3548 [pbn_NETMOS9900_2s_115200] = { 3549 .flags = FL_BASE0, 3550 .num_ports = 2, 3551 .base_baud = 115200, 3552 }, 3553 [pbn_brcm_trumanage] = { 3554 .flags = FL_BASE0, 3555 .num_ports = 1, 3556 .reg_shift = 2, 3557 .base_baud = 115200, 3558 }, 3559 [pbn_fintek_4] = { 3560 .num_ports = 4, 3561 .uart_offset = 8, 3562 .base_baud = 115200, 3563 .first_offset = 0x40, 3564 }, 3565 [pbn_fintek_8] = { 3566 .num_ports = 8, 3567 .uart_offset = 8, 3568 .base_baud = 115200, 3569 .first_offset = 0x40, 3570 }, 3571 [pbn_fintek_12] = { 3572 .num_ports = 12, 3573 .uart_offset = 8, 3574 .base_baud = 115200, 3575 .first_offset = 0x40, 3576 }, 3577 [pbn_fintek_F81504A] = { 3578 .num_ports = 4, 3579 .uart_offset = 8, 3580 .base_baud = 115200, 3581 }, 3582 [pbn_fintek_F81508A] = { 3583 .num_ports = 8, 3584 .uart_offset = 8, 3585 .base_baud = 115200, 3586 }, 3587 [pbn_fintek_F81512A] = { 3588 .num_ports = 12, 3589 .uart_offset = 8, 3590 .base_baud = 115200, 3591 }, 3592 [pbn_wch382_2] = { 3593 .flags = FL_BASE0, 3594 .num_ports = 2, 3595 .base_baud = 115200, 3596 .uart_offset = 8, 3597 .first_offset = 0xC0, 3598 }, 3599 [pbn_wch384_4] = { 3600 .flags = FL_BASE0, 3601 .num_ports = 4, 3602 .base_baud = 115200, 3603 .uart_offset = 8, 3604 .first_offset = 0xC0, 3605 }, 3606 [pbn_wch384_8] = { 3607 .flags = FL_BASE0, 3608 .num_ports = 8, 3609 .base_baud = 115200, 3610 .uart_offset = 8, 3611 .first_offset = 0x00, 3612 }, 3613 [pbn_sunix_pci_1s] = { 3614 .num_ports = 1, 3615 .base_baud = 921600, 3616 .uart_offset = 0x8, 3617 }, 3618 [pbn_sunix_pci_2s] = { 3619 .num_ports = 2, 3620 .base_baud = 921600, 3621 .uart_offset = 0x8, 3622 }, 3623 [pbn_sunix_pci_4s] = { 3624 .num_ports = 4, 3625 .base_baud = 921600, 3626 .uart_offset = 0x8, 3627 }, 3628 [pbn_sunix_pci_8s] = { 3629 .num_ports = 8, 3630 .base_baud = 921600, 3631 .uart_offset = 0x8, 3632 }, 3633 [pbn_sunix_pci_16s] = { 3634 .num_ports = 16, 3635 .base_baud = 921600, 3636 .uart_offset = 0x8, 3637 }, 3638 [pbn_titan_1_4000000] = { 3639 .flags = FL_BASE0, 3640 .num_ports = 1, 3641 .base_baud = 4000000, 3642 .uart_offset = 0x200, 3643 .first_offset = 0x1000, 3644 }, 3645 [pbn_titan_2_4000000] = { 3646 .flags = FL_BASE0, 3647 .num_ports = 2, 3648 .base_baud = 4000000, 3649 .uart_offset = 0x200, 3650 .first_offset = 0x1000, 3651 }, 3652 [pbn_titan_4_4000000] = { 3653 .flags = FL_BASE0, 3654 .num_ports = 4, 3655 .base_baud = 4000000, 3656 .uart_offset = 0x200, 3657 .first_offset = 0x1000, 3658 }, 3659 [pbn_titan_8_4000000] = { 3660 .flags = FL_BASE0, 3661 .num_ports = 8, 3662 .base_baud = 4000000, 3663 .uart_offset = 0x200, 3664 .first_offset = 0x1000, 3665 }, 3666 [pbn_moxa8250_2p] = { 3667 .flags = FL_BASE1, 3668 .num_ports = 2, 3669 .base_baud = 921600, 3670 .uart_offset = 0x200, 3671 }, 3672 [pbn_moxa8250_4p] = { 3673 .flags = FL_BASE1, 3674 .num_ports = 4, 3675 .base_baud = 921600, 3676 .uart_offset = 0x200, 3677 }, 3678 [pbn_moxa8250_8p] = { 3679 .flags = FL_BASE1, 3680 .num_ports = 8, 3681 .base_baud = 921600, 3682 .uart_offset = 0x200, 3683 }, 3684 }; 3685 3686 #define REPORT_CONFIG(option) \ 3687 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option) 3688 #define REPORT_8250_CONFIG(option) \ 3689 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \ 3690 0 : (kernel_ulong_t)&"SERIAL_8250_"#option) 3691 3692 static const struct pci_device_id blacklist[] = { 3693 /* softmodems */ 3694 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3695 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3696 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3697 3698 /* multi-io cards handled by parport_serial */ 3699 /* WCH CH353 2S1P */ 3700 { PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3701 /* WCH CH353 1S1P */ 3702 { PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3703 /* WCH CH382 2S1P */ 3704 { PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3705 3706 /* Intel platforms with MID UART */ 3707 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), }, 3708 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), }, 3709 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), }, 3710 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), }, 3711 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), }, 3712 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), }, 3713 3714 /* Intel platforms with DesignWare UART */ 3715 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), }, 3716 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), }, 3717 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), }, 3718 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), }, 3719 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), }, 3720 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), }, 3721 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), }, 3722 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), }, 3723 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), }, 3724 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), }, 3725 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), }, 3726 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), }, 3727 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), }, 3728 3729 /* Exar devices */ 3730 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3731 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3732 3733 /* Pericom devices */ 3734 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3735 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3736 3737 /* End of the black list */ 3738 { } 3739 }; 3740 3741 static int serial_pci_is_class_communication(struct pci_dev *dev) 3742 { 3743 /* 3744 * If it is not a communications device or the programming 3745 * interface is greater than 6, give up. 3746 */ 3747 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3748 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3749 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3750 (dev->class & 0xff) > 6) 3751 return -ENODEV; 3752 3753 return 0; 3754 } 3755 3756 /* 3757 * Given a complete unknown PCI device, try to use some heuristics to 3758 * guess what the configuration might be, based on the pitiful PCI 3759 * serial specs. Returns 0 on success, -ENODEV on failure. 3760 */ 3761 static int 3762 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3763 { 3764 int num_iomem, num_port, first_port = -1, i; 3765 int rc; 3766 3767 rc = serial_pci_is_class_communication(dev); 3768 if (rc) 3769 return rc; 3770 3771 /* 3772 * Should we try to make guesses for multiport serial devices later? 3773 */ 3774 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3775 return -ENODEV; 3776 3777 num_iomem = num_port = 0; 3778 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3779 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3780 num_port++; 3781 if (first_port == -1) 3782 first_port = i; 3783 } 3784 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3785 num_iomem++; 3786 } 3787 3788 /* 3789 * If there is 1 or 0 iomem regions, and exactly one port, 3790 * use it. We guess the number of ports based on the IO 3791 * region size. 3792 */ 3793 if (num_iomem <= 1 && num_port == 1) { 3794 board->flags = first_port; 3795 board->num_ports = pci_resource_len(dev, first_port) / 8; 3796 return 0; 3797 } 3798 3799 /* 3800 * Now guess if we've got a board which indexes by BARs. 3801 * Each IO BAR should be 8 bytes, and they should follow 3802 * consecutively. 3803 */ 3804 first_port = -1; 3805 num_port = 0; 3806 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3807 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3808 pci_resource_len(dev, i) == 8 && 3809 (first_port == -1 || (first_port + num_port) == i)) { 3810 num_port++; 3811 if (first_port == -1) 3812 first_port = i; 3813 } 3814 } 3815 3816 if (num_port > 1) { 3817 board->flags = first_port | FL_BASE_BARS; 3818 board->num_ports = num_port; 3819 return 0; 3820 } 3821 3822 return -ENODEV; 3823 } 3824 3825 static inline int 3826 serial_pci_matches(const struct pciserial_board *board, 3827 const struct pciserial_board *guessed) 3828 { 3829 return 3830 board->num_ports == guessed->num_ports && 3831 board->base_baud == guessed->base_baud && 3832 board->uart_offset == guessed->uart_offset && 3833 board->reg_shift == guessed->reg_shift && 3834 board->first_offset == guessed->first_offset; 3835 } 3836 3837 struct serial_private * 3838 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3839 { 3840 struct uart_8250_port uart; 3841 struct serial_private *priv; 3842 struct pci_serial_quirk *quirk; 3843 int rc, nr_ports, i; 3844 3845 nr_ports = board->num_ports; 3846 3847 /* 3848 * Find an init and setup quirks. 3849 */ 3850 quirk = find_quirk(dev); 3851 3852 /* 3853 * Run the new-style initialization function. 3854 * The initialization function returns: 3855 * <0 - error 3856 * 0 - use board->num_ports 3857 * >0 - number of ports 3858 */ 3859 if (quirk->init) { 3860 rc = quirk->init(dev); 3861 if (rc < 0) { 3862 priv = ERR_PTR(rc); 3863 goto err_out; 3864 } 3865 if (rc) 3866 nr_ports = rc; 3867 } 3868 3869 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL); 3870 if (!priv) { 3871 priv = ERR_PTR(-ENOMEM); 3872 goto err_deinit; 3873 } 3874 3875 priv->dev = dev; 3876 priv->quirk = quirk; 3877 3878 memset(&uart, 0, sizeof(uart)); 3879 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3880 uart.port.uartclk = board->base_baud * 16; 3881 3882 if (board->flags & FL_NOIRQ) { 3883 uart.port.irq = 0; 3884 } else { 3885 if (pci_match_id(pci_use_msi, dev)) { 3886 pci_dbg(dev, "Using MSI(-X) interrupts\n"); 3887 pci_set_master(dev); 3888 uart.port.flags &= ~UPF_SHARE_IRQ; 3889 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 3890 } else { 3891 pci_dbg(dev, "Using legacy interrupts\n"); 3892 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 3893 } 3894 if (rc < 0) { 3895 kfree(priv); 3896 priv = ERR_PTR(rc); 3897 goto err_deinit; 3898 } 3899 3900 uart.port.irq = pci_irq_vector(dev, 0); 3901 } 3902 3903 uart.port.dev = &dev->dev; 3904 3905 for (i = 0; i < nr_ports; i++) { 3906 if (quirk->setup(priv, board, &uart, i)) 3907 break; 3908 3909 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3910 uart.port.iobase, uart.port.irq, uart.port.iotype); 3911 3912 priv->line[i] = serial8250_register_8250_port(&uart); 3913 if (priv->line[i] < 0) { 3914 pci_err(dev, 3915 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3916 uart.port.iobase, uart.port.irq, 3917 uart.port.iotype, priv->line[i]); 3918 break; 3919 } 3920 } 3921 priv->nr = i; 3922 priv->board = board; 3923 return priv; 3924 3925 err_deinit: 3926 if (quirk->exit) 3927 quirk->exit(dev); 3928 err_out: 3929 return priv; 3930 } 3931 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3932 3933 static void pciserial_detach_ports(struct serial_private *priv) 3934 { 3935 struct pci_serial_quirk *quirk; 3936 int i; 3937 3938 for (i = 0; i < priv->nr; i++) 3939 serial8250_unregister_port(priv->line[i]); 3940 3941 /* 3942 * Find the exit quirks. 3943 */ 3944 quirk = find_quirk(priv->dev); 3945 if (quirk->exit) 3946 quirk->exit(priv->dev); 3947 } 3948 3949 void pciserial_remove_ports(struct serial_private *priv) 3950 { 3951 pciserial_detach_ports(priv); 3952 kfree(priv); 3953 } 3954 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3955 3956 void pciserial_suspend_ports(struct serial_private *priv) 3957 { 3958 int i; 3959 3960 for (i = 0; i < priv->nr; i++) 3961 if (priv->line[i] >= 0) 3962 serial8250_suspend_port(priv->line[i]); 3963 3964 /* 3965 * Ensure that every init quirk is properly torn down 3966 */ 3967 if (priv->quirk->exit) 3968 priv->quirk->exit(priv->dev); 3969 } 3970 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3971 3972 void pciserial_resume_ports(struct serial_private *priv) 3973 { 3974 int i; 3975 3976 /* 3977 * Ensure that the board is correctly configured. 3978 */ 3979 if (priv->quirk->init) 3980 priv->quirk->init(priv->dev); 3981 3982 for (i = 0; i < priv->nr; i++) 3983 if (priv->line[i] >= 0) 3984 serial8250_resume_port(priv->line[i]); 3985 } 3986 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3987 3988 /* 3989 * Probe one serial board. Unfortunately, there is no rhyme nor reason 3990 * to the arrangement of serial ports on a PCI card. 3991 */ 3992 static int 3993 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 3994 { 3995 struct pci_serial_quirk *quirk; 3996 struct serial_private *priv; 3997 const struct pciserial_board *board; 3998 const struct pci_device_id *exclude; 3999 struct pciserial_board tmp; 4000 int rc; 4001 4002 quirk = find_quirk(dev); 4003 if (quirk->probe) { 4004 rc = quirk->probe(dev); 4005 if (rc) 4006 return rc; 4007 } 4008 4009 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4010 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); 4011 return -EINVAL; 4012 } 4013 4014 board = &pci_boards[ent->driver_data]; 4015 4016 exclude = pci_match_id(blacklist, dev); 4017 if (exclude) { 4018 if (exclude->driver_data) 4019 pci_warn(dev, "ignoring port, enable %s to handle\n", 4020 (const char *)exclude->driver_data); 4021 return -ENODEV; 4022 } 4023 4024 rc = pcim_enable_device(dev); 4025 pci_save_state(dev); 4026 if (rc) 4027 return rc; 4028 4029 if (ent->driver_data == pbn_default) { 4030 /* 4031 * Use a copy of the pci_board entry for this; 4032 * avoid changing entries in the table. 4033 */ 4034 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4035 board = &tmp; 4036 4037 /* 4038 * We matched one of our class entries. Try to 4039 * determine the parameters of this board. 4040 */ 4041 rc = serial_pci_guess_board(dev, &tmp); 4042 if (rc) 4043 return rc; 4044 } else { 4045 /* 4046 * We matched an explicit entry. If we are able to 4047 * detect this boards settings with our heuristic, 4048 * then we no longer need this entry. 4049 */ 4050 memcpy(&tmp, &pci_boards[pbn_default], 4051 sizeof(struct pciserial_board)); 4052 rc = serial_pci_guess_board(dev, &tmp); 4053 if (rc == 0 && serial_pci_matches(board, &tmp)) 4054 moan_device("Redundant entry in serial pci_table.", 4055 dev); 4056 } 4057 4058 priv = pciserial_init_ports(dev, board); 4059 if (IS_ERR(priv)) 4060 return PTR_ERR(priv); 4061 4062 pci_set_drvdata(dev, priv); 4063 return 0; 4064 } 4065 4066 static void pciserial_remove_one(struct pci_dev *dev) 4067 { 4068 struct serial_private *priv = pci_get_drvdata(dev); 4069 4070 pciserial_remove_ports(priv); 4071 } 4072 4073 #ifdef CONFIG_PM_SLEEP 4074 static int pciserial_suspend_one(struct device *dev) 4075 { 4076 struct serial_private *priv = dev_get_drvdata(dev); 4077 4078 if (priv) 4079 pciserial_suspend_ports(priv); 4080 4081 return 0; 4082 } 4083 4084 static int pciserial_resume_one(struct device *dev) 4085 { 4086 struct pci_dev *pdev = to_pci_dev(dev); 4087 struct serial_private *priv = pci_get_drvdata(pdev); 4088 int err; 4089 4090 if (priv) { 4091 /* 4092 * The device may have been disabled. Re-enable it. 4093 */ 4094 err = pci_enable_device(pdev); 4095 /* FIXME: We cannot simply error out here */ 4096 if (err) 4097 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); 4098 pciserial_resume_ports(priv); 4099 } 4100 return 0; 4101 } 4102 #endif 4103 4104 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4105 pciserial_resume_one); 4106 4107 static const struct pci_device_id serial_pci_tbl[] = { 4108 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4109 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4110 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4111 pbn_b2_8_921600 }, 4112 /* Advantech also use 0x3618 and 0xf618 */ 4113 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4114 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4115 pbn_b0_4_921600 }, 4116 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4117 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4118 pbn_b0_4_921600 }, 4119 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4120 PCI_SUBVENDOR_ID_CONNECT_TECH, 4121 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4122 pbn_b1_8_1382400 }, 4123 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4124 PCI_SUBVENDOR_ID_CONNECT_TECH, 4125 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4126 pbn_b1_4_1382400 }, 4127 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4128 PCI_SUBVENDOR_ID_CONNECT_TECH, 4129 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4130 pbn_b1_2_1382400 }, 4131 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4132 PCI_SUBVENDOR_ID_CONNECT_TECH, 4133 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4134 pbn_b1_8_1382400 }, 4135 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4136 PCI_SUBVENDOR_ID_CONNECT_TECH, 4137 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4138 pbn_b1_4_1382400 }, 4139 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4140 PCI_SUBVENDOR_ID_CONNECT_TECH, 4141 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4142 pbn_b1_2_1382400 }, 4143 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4144 PCI_SUBVENDOR_ID_CONNECT_TECH, 4145 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4146 pbn_b1_8_921600 }, 4147 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4148 PCI_SUBVENDOR_ID_CONNECT_TECH, 4149 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4150 pbn_b1_8_921600 }, 4151 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4152 PCI_SUBVENDOR_ID_CONNECT_TECH, 4153 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4154 pbn_b1_4_921600 }, 4155 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4156 PCI_SUBVENDOR_ID_CONNECT_TECH, 4157 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4158 pbn_b1_4_921600 }, 4159 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4160 PCI_SUBVENDOR_ID_CONNECT_TECH, 4161 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4162 pbn_b1_2_921600 }, 4163 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4164 PCI_SUBVENDOR_ID_CONNECT_TECH, 4165 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4166 pbn_b1_8_921600 }, 4167 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4168 PCI_SUBVENDOR_ID_CONNECT_TECH, 4169 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4170 pbn_b1_8_921600 }, 4171 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4172 PCI_SUBVENDOR_ID_CONNECT_TECH, 4173 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4174 pbn_b1_4_921600 }, 4175 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4176 PCI_SUBVENDOR_ID_CONNECT_TECH, 4177 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4178 pbn_b1_2_1250000 }, 4179 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4180 PCI_SUBVENDOR_ID_CONNECT_TECH, 4181 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4182 pbn_b0_2_1843200 }, 4183 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4184 PCI_SUBVENDOR_ID_CONNECT_TECH, 4185 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4186 pbn_b0_4_1843200 }, 4187 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4188 PCI_VENDOR_ID_AFAVLAB, 4189 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4190 pbn_b0_4_1152000 }, 4191 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4193 pbn_b2_bt_1_115200 }, 4194 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4196 pbn_b2_bt_2_115200 }, 4197 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4199 pbn_b2_bt_4_115200 }, 4200 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4202 pbn_b2_bt_2_115200 }, 4203 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4205 pbn_b2_bt_4_115200 }, 4206 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4208 pbn_b2_8_115200 }, 4209 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4211 pbn_b2_8_460800 }, 4212 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4214 pbn_b2_8_115200 }, 4215 4216 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4218 pbn_b2_bt_2_115200 }, 4219 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4221 pbn_b2_bt_2_921600 }, 4222 /* 4223 * VScom SPCOM800, from sl@s.pl 4224 */ 4225 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4227 pbn_b2_8_921600 }, 4228 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4230 pbn_b2_4_921600 }, 4231 /* Unknown card - subdevice 0x1584 */ 4232 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4233 PCI_VENDOR_ID_PLX, 4234 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4235 pbn_b2_4_115200 }, 4236 /* Unknown card - subdevice 0x1588 */ 4237 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4238 PCI_VENDOR_ID_PLX, 4239 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4240 pbn_b2_8_115200 }, 4241 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4242 PCI_SUBVENDOR_ID_KEYSPAN, 4243 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4244 pbn_panacom }, 4245 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4247 pbn_panacom4 }, 4248 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4250 pbn_panacom2 }, 4251 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4252 PCI_VENDOR_ID_ESDGMBH, 4253 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4254 pbn_b2_4_115200 }, 4255 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4256 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4257 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4258 pbn_b2_4_460800 }, 4259 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4260 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4261 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4262 pbn_b2_8_460800 }, 4263 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4264 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4265 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4266 pbn_b2_16_460800 }, 4267 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4268 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4269 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4270 pbn_b2_16_460800 }, 4271 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4272 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4273 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4274 pbn_b2_4_460800 }, 4275 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4276 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4277 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4278 pbn_b2_8_460800 }, 4279 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4280 PCI_SUBVENDOR_ID_EXSYS, 4281 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4282 pbn_b2_4_115200 }, 4283 /* 4284 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4285 * (Exoray@isys.ca) 4286 */ 4287 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4288 0x10b5, 0x106a, 0, 0, 4289 pbn_plx_romulus }, 4290 /* 4291 * Quatech cards. These actually have configurable clocks but for 4292 * now we just use the default. 4293 * 4294 * 100 series are RS232, 200 series RS422, 4295 */ 4296 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4298 pbn_b1_4_115200 }, 4299 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4301 pbn_b1_2_115200 }, 4302 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4303 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4304 pbn_b2_2_115200 }, 4305 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4307 pbn_b1_2_115200 }, 4308 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4310 pbn_b2_2_115200 }, 4311 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4313 pbn_b1_4_115200 }, 4314 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4315 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4316 pbn_b1_8_115200 }, 4317 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4319 pbn_b1_8_115200 }, 4320 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4322 pbn_b1_4_115200 }, 4323 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4325 pbn_b1_2_115200 }, 4326 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4327 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4328 pbn_b1_4_115200 }, 4329 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4331 pbn_b1_2_115200 }, 4332 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4333 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4334 pbn_b2_4_115200 }, 4335 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4337 pbn_b2_2_115200 }, 4338 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4339 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4340 pbn_b2_1_115200 }, 4341 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4343 pbn_b2_4_115200 }, 4344 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4345 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4346 pbn_b2_2_115200 }, 4347 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4349 pbn_b2_1_115200 }, 4350 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4352 pbn_b0_8_115200 }, 4353 4354 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4355 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4356 0, 0, 4357 pbn_b0_4_921600 }, 4358 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4359 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4360 0, 0, 4361 pbn_b0_4_1152000 }, 4362 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4364 pbn_b0_bt_2_921600 }, 4365 4366 /* 4367 * The below card is a little controversial since it is the 4368 * subject of a PCI vendor/device ID clash. (See 4369 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4370 * For now just used the hex ID 0x950a. 4371 */ 4372 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4373 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4374 0, 0, pbn_b0_2_115200 }, 4375 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4376 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4377 0, 0, pbn_b0_2_115200 }, 4378 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4379 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4380 pbn_b0_2_1130000 }, 4381 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4382 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4383 pbn_b0_1_921600 }, 4384 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4385 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4386 pbn_b0_4_115200 }, 4387 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4388 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4389 pbn_b0_bt_2_921600 }, 4390 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4391 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4392 pbn_b2_8_1152000 }, 4393 4394 /* 4395 * Oxford Semiconductor Inc. Tornado PCI express device range. 4396 */ 4397 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4398 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4399 pbn_b0_1_15625000 }, 4400 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4401 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4402 pbn_b0_1_15625000 }, 4403 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4404 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4405 pbn_oxsemi_1_15625000 }, 4406 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4407 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4408 pbn_oxsemi_1_15625000 }, 4409 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4410 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4411 pbn_b0_1_15625000 }, 4412 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4413 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4414 pbn_b0_1_15625000 }, 4415 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4416 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4417 pbn_oxsemi_1_15625000 }, 4418 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4419 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4420 pbn_oxsemi_1_15625000 }, 4421 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4422 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4423 pbn_b0_1_15625000 }, 4424 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4426 pbn_b0_1_15625000 }, 4427 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4429 pbn_b0_1_15625000 }, 4430 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4432 pbn_b0_1_15625000 }, 4433 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4435 pbn_oxsemi_2_15625000 }, 4436 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4437 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4438 pbn_oxsemi_2_15625000 }, 4439 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4441 pbn_oxsemi_4_15625000 }, 4442 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4444 pbn_oxsemi_4_15625000 }, 4445 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4447 pbn_oxsemi_8_15625000 }, 4448 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4449 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4450 pbn_oxsemi_8_15625000 }, 4451 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4452 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4453 pbn_oxsemi_1_15625000 }, 4454 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4456 pbn_oxsemi_1_15625000 }, 4457 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4459 pbn_oxsemi_1_15625000 }, 4460 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4462 pbn_oxsemi_1_15625000 }, 4463 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4465 pbn_oxsemi_1_15625000 }, 4466 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4468 pbn_oxsemi_1_15625000 }, 4469 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4471 pbn_oxsemi_1_15625000 }, 4472 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4474 pbn_oxsemi_1_15625000 }, 4475 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4477 pbn_oxsemi_1_15625000 }, 4478 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4480 pbn_oxsemi_1_15625000 }, 4481 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4483 pbn_oxsemi_1_15625000 }, 4484 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4486 pbn_oxsemi_1_15625000 }, 4487 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4489 pbn_oxsemi_1_15625000 }, 4490 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4492 pbn_oxsemi_1_15625000 }, 4493 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4495 pbn_oxsemi_1_15625000 }, 4496 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4498 pbn_oxsemi_1_15625000 }, 4499 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4501 pbn_oxsemi_1_15625000 }, 4502 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4504 pbn_oxsemi_1_15625000 }, 4505 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4507 pbn_oxsemi_1_15625000 }, 4508 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4510 pbn_oxsemi_1_15625000 }, 4511 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4513 pbn_oxsemi_1_15625000 }, 4514 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4516 pbn_oxsemi_1_15625000 }, 4517 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4519 pbn_oxsemi_1_15625000 }, 4520 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4521 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4522 pbn_oxsemi_1_15625000 }, 4523 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4525 pbn_oxsemi_1_15625000 }, 4526 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4527 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4528 pbn_oxsemi_1_15625000 }, 4529 /* 4530 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4531 */ 4532 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4533 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4534 pbn_oxsemi_1_15625000 }, 4535 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4536 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4537 pbn_oxsemi_2_15625000 }, 4538 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4539 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4540 pbn_oxsemi_4_15625000 }, 4541 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4542 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4543 pbn_oxsemi_8_15625000 }, 4544 4545 /* 4546 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4547 */ 4548 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4549 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4550 pbn_oxsemi_2_15625000 }, 4551 /* 4552 * EndRun Technologies. PCI express device range. 4553 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952. 4554 */ 4555 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4556 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4557 pbn_oxsemi_2_15625000 }, 4558 4559 /* 4560 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4561 * from skokodyn@yahoo.com 4562 */ 4563 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4564 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4565 pbn_sbsxrsio }, 4566 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4567 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4568 pbn_sbsxrsio }, 4569 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4570 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4571 pbn_sbsxrsio }, 4572 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4573 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4574 pbn_sbsxrsio }, 4575 4576 /* 4577 * Digitan DS560-558, from jimd@esoft.com 4578 */ 4579 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4581 pbn_b1_1_115200 }, 4582 4583 /* 4584 * Titan Electronic cards 4585 * The 400L and 800L have a custom setup quirk. 4586 */ 4587 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4589 pbn_b0_1_921600 }, 4590 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4592 pbn_b0_2_921600 }, 4593 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4595 pbn_b0_4_921600 }, 4596 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4598 pbn_b0_4_921600 }, 4599 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4601 pbn_b1_1_921600 }, 4602 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4604 pbn_b1_bt_2_921600 }, 4605 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4607 pbn_b0_bt_4_921600 }, 4608 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4610 pbn_b0_bt_8_921600 }, 4611 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4613 pbn_b4_bt_2_921600 }, 4614 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4616 pbn_b4_bt_4_921600 }, 4617 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4619 pbn_b4_bt_8_921600 }, 4620 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4622 pbn_b0_4_921600 }, 4623 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4625 pbn_b0_4_921600 }, 4626 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4628 pbn_b0_4_921600 }, 4629 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4631 pbn_titan_1_4000000 }, 4632 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4634 pbn_titan_2_4000000 }, 4635 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4637 pbn_titan_4_4000000 }, 4638 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4640 pbn_titan_8_4000000 }, 4641 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4643 pbn_titan_2_4000000 }, 4644 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4646 pbn_titan_2_4000000 }, 4647 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4649 pbn_b0_bt_2_921600 }, 4650 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4652 pbn_b0_4_921600 }, 4653 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4655 pbn_b0_4_921600 }, 4656 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4658 pbn_b0_4_921600 }, 4659 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4661 pbn_b0_4_921600 }, 4662 4663 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4664 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4665 pbn_b2_1_460800 }, 4666 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4667 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4668 pbn_b2_1_460800 }, 4669 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4670 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4671 pbn_b2_1_460800 }, 4672 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4674 pbn_b2_bt_2_921600 }, 4675 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4677 pbn_b2_bt_2_921600 }, 4678 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4680 pbn_b2_bt_2_921600 }, 4681 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4682 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4683 pbn_b2_bt_4_921600 }, 4684 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4686 pbn_b2_bt_4_921600 }, 4687 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4689 pbn_b2_bt_4_921600 }, 4690 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4692 pbn_b0_1_921600 }, 4693 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4695 pbn_b0_1_921600 }, 4696 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4698 pbn_b0_1_921600 }, 4699 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4701 pbn_b0_bt_2_921600 }, 4702 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4704 pbn_b0_bt_2_921600 }, 4705 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4707 pbn_b0_bt_2_921600 }, 4708 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4710 pbn_b0_bt_4_921600 }, 4711 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4713 pbn_b0_bt_4_921600 }, 4714 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4716 pbn_b0_bt_4_921600 }, 4717 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4719 pbn_b0_bt_8_921600 }, 4720 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4722 pbn_b0_bt_8_921600 }, 4723 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4725 pbn_b0_bt_8_921600 }, 4726 4727 /* 4728 * Computone devices submitted by Doug McNash dmcnash@computone.com 4729 */ 4730 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4731 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4732 0, 0, pbn_computone_4 }, 4733 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4734 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4735 0, 0, pbn_computone_8 }, 4736 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4737 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4738 0, 0, pbn_computone_6 }, 4739 4740 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4742 pbn_oxsemi }, 4743 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4744 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4745 pbn_b0_bt_1_921600 }, 4746 4747 /* 4748 * Sunix PCI serial boards 4749 */ 4750 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4751 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 4752 pbn_sunix_pci_1s }, 4753 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4754 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 4755 pbn_sunix_pci_2s }, 4756 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4757 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 4758 pbn_sunix_pci_4s }, 4759 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4760 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 4761 pbn_sunix_pci_4s }, 4762 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4763 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 4764 pbn_sunix_pci_8s }, 4765 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4766 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 4767 pbn_sunix_pci_8s }, 4768 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4769 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 4770 pbn_sunix_pci_16s }, 4771 4772 /* 4773 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4774 */ 4775 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4777 pbn_b0_bt_8_115200 }, 4778 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4780 pbn_b0_bt_8_115200 }, 4781 4782 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4784 pbn_b0_bt_2_115200 }, 4785 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4787 pbn_b0_bt_2_115200 }, 4788 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4790 pbn_b0_bt_2_115200 }, 4791 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4793 pbn_b0_bt_2_115200 }, 4794 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4796 pbn_b0_bt_2_115200 }, 4797 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4799 pbn_b0_bt_4_460800 }, 4800 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4802 pbn_b0_bt_4_460800 }, 4803 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4805 pbn_b0_bt_2_460800 }, 4806 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4808 pbn_b0_bt_2_460800 }, 4809 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4811 pbn_b0_bt_2_460800 }, 4812 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4814 pbn_b0_bt_1_115200 }, 4815 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4817 pbn_b0_bt_1_460800 }, 4818 4819 /* 4820 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4821 * Cards are identified by their subsystem vendor IDs, which 4822 * (in hex) match the model number. 4823 * 4824 * Note that JC140x are RS422/485 cards which require ox950 4825 * ACR = 0x10, and as such are not currently fully supported. 4826 */ 4827 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4828 0x1204, 0x0004, 0, 0, 4829 pbn_b0_4_921600 }, 4830 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4831 0x1208, 0x0004, 0, 0, 4832 pbn_b0_4_921600 }, 4833 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4834 0x1402, 0x0002, 0, 0, 4835 pbn_b0_2_921600 }, */ 4836 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4837 0x1404, 0x0004, 0, 0, 4838 pbn_b0_4_921600 }, */ 4839 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4840 0x1208, 0x0004, 0, 0, 4841 pbn_b0_4_921600 }, 4842 4843 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4844 0x1204, 0x0004, 0, 0, 4845 pbn_b0_4_921600 }, 4846 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4847 0x1208, 0x0004, 0, 0, 4848 pbn_b0_4_921600 }, 4849 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4850 0x1208, 0x0004, 0, 0, 4851 pbn_b0_4_921600 }, 4852 /* 4853 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4854 */ 4855 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4856 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4857 pbn_b1_1_1382400 }, 4858 4859 /* 4860 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4861 */ 4862 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4863 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4864 pbn_b1_1_1382400 }, 4865 4866 /* 4867 * RAStel 2 port modem, gerg@moreton.com.au 4868 */ 4869 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4870 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4871 pbn_b2_bt_2_115200 }, 4872 4873 /* 4874 * EKF addition for i960 Boards form EKF with serial port 4875 */ 4876 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4877 0xE4BF, PCI_ANY_ID, 0, 0, 4878 pbn_intel_i960 }, 4879 4880 /* 4881 * Xircom Cardbus/Ethernet combos 4882 */ 4883 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4884 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4885 pbn_b0_1_115200 }, 4886 /* 4887 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4888 */ 4889 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4890 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4891 pbn_b0_1_115200 }, 4892 4893 /* 4894 * Untested PCI modems, sent in from various folks... 4895 */ 4896 4897 /* 4898 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4899 */ 4900 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4901 0x1048, 0x1500, 0, 0, 4902 pbn_b1_1_115200 }, 4903 4904 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4905 0xFF00, 0, 0, 0, 4906 pbn_sgi_ioc3 }, 4907 4908 /* 4909 * HP Diva card 4910 */ 4911 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4912 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4913 pbn_b1_1_115200 }, 4914 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4915 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4916 pbn_b0_5_115200 }, 4917 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4918 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4919 pbn_b2_1_115200 }, 4920 /* HPE PCI serial device */ 4921 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 4922 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4923 pbn_b1_1_115200 }, 4924 4925 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4926 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4927 pbn_b3_2_115200 }, 4928 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4929 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4930 pbn_b3_4_115200 }, 4931 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4932 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4933 pbn_b3_8_115200 }, 4934 /* 4935 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 4936 */ 4937 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 4938 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4939 pbn_b0_1_115200 }, 4940 /* 4941 * ITE 4942 */ 4943 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 4944 PCI_ANY_ID, PCI_ANY_ID, 4945 0, 0, 4946 pbn_b1_bt_1_115200 }, 4947 4948 /* 4949 * IntaShield IS-200 4950 */ 4951 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 4952 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 4953 pbn_b2_2_115200 }, 4954 /* 4955 * IntaShield IS-400 4956 */ 4957 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 4959 pbn_b2_4_115200 }, 4960 /* Brainboxes Devices */ 4961 /* 4962 * Brainboxes UC-101 4963 */ 4964 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1, 4965 PCI_ANY_ID, PCI_ANY_ID, 4966 0, 0, 4967 pbn_b2_2_115200 }, 4968 /* 4969 * Brainboxes UC-235/246 4970 */ 4971 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1, 4972 PCI_ANY_ID, PCI_ANY_ID, 4973 0, 0, 4974 pbn_b2_1_115200 }, 4975 /* 4976 * Brainboxes UC-257 4977 */ 4978 { PCI_VENDOR_ID_INTASHIELD, 0x0861, 4979 PCI_ANY_ID, PCI_ANY_ID, 4980 0, 0, 4981 pbn_b2_2_115200 }, 4982 /* 4983 * Brainboxes UC-260/271/701/756 4984 */ 4985 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 4986 PCI_ANY_ID, PCI_ANY_ID, 4987 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4988 pbn_b2_4_115200 }, 4989 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 4990 PCI_ANY_ID, PCI_ANY_ID, 4991 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4992 pbn_b2_4_115200 }, 4993 /* 4994 * Brainboxes UC-268 4995 */ 4996 { PCI_VENDOR_ID_INTASHIELD, 0x0841, 4997 PCI_ANY_ID, PCI_ANY_ID, 4998 0, 0, 4999 pbn_b2_4_115200 }, 5000 /* 5001 * Brainboxes UC-275/279 5002 */ 5003 { PCI_VENDOR_ID_INTASHIELD, 0x0881, 5004 PCI_ANY_ID, PCI_ANY_ID, 5005 0, 0, 5006 pbn_b2_8_115200 }, 5007 /* 5008 * Brainboxes UC-302 5009 */ 5010 { PCI_VENDOR_ID_INTASHIELD, 0x08E1, 5011 PCI_ANY_ID, PCI_ANY_ID, 5012 0, 0, 5013 pbn_b2_2_115200 }, 5014 /* 5015 * Brainboxes UC-310 5016 */ 5017 { PCI_VENDOR_ID_INTASHIELD, 0x08C1, 5018 PCI_ANY_ID, PCI_ANY_ID, 5019 0, 0, 5020 pbn_b2_2_115200 }, 5021 /* 5022 * Brainboxes UC-313 5023 */ 5024 { PCI_VENDOR_ID_INTASHIELD, 0x08A3, 5025 PCI_ANY_ID, PCI_ANY_ID, 5026 0, 0, 5027 pbn_b2_2_115200 }, 5028 /* 5029 * Brainboxes UC-320/324 5030 */ 5031 { PCI_VENDOR_ID_INTASHIELD, 0x0A61, 5032 PCI_ANY_ID, PCI_ANY_ID, 5033 0, 0, 5034 pbn_b2_1_115200 }, 5035 /* 5036 * Brainboxes UC-346 5037 */ 5038 { PCI_VENDOR_ID_INTASHIELD, 0x0B02, 5039 PCI_ANY_ID, PCI_ANY_ID, 5040 0, 0, 5041 pbn_b2_4_115200 }, 5042 /* 5043 * Brainboxes UC-357 5044 */ 5045 { PCI_VENDOR_ID_INTASHIELD, 0x0A81, 5046 PCI_ANY_ID, PCI_ANY_ID, 5047 0, 0, 5048 pbn_b2_2_115200 }, 5049 { PCI_VENDOR_ID_INTASHIELD, 0x0A83, 5050 PCI_ANY_ID, PCI_ANY_ID, 5051 0, 0, 5052 pbn_b2_2_115200 }, 5053 /* 5054 * Brainboxes UC-368 5055 */ 5056 { PCI_VENDOR_ID_INTASHIELD, 0x0C41, 5057 PCI_ANY_ID, PCI_ANY_ID, 5058 0, 0, 5059 pbn_b2_4_115200 }, 5060 /* 5061 * Brainboxes UC-420/431 5062 */ 5063 { PCI_VENDOR_ID_INTASHIELD, 0x0921, 5064 PCI_ANY_ID, PCI_ANY_ID, 5065 0, 0, 5066 pbn_b2_4_115200 }, 5067 /* 5068 * Brainboxes PX-101 5069 */ 5070 { PCI_VENDOR_ID_INTASHIELD, 0x4005, 5071 PCI_ANY_ID, PCI_ANY_ID, 5072 0, 0, 5073 pbn_b0_2_115200 }, 5074 { PCI_VENDOR_ID_INTASHIELD, 0x4019, 5075 PCI_ANY_ID, PCI_ANY_ID, 5076 0, 0, 5077 pbn_oxsemi_2_15625000 }, 5078 /* 5079 * Brainboxes PX-235/246 5080 */ 5081 { PCI_VENDOR_ID_INTASHIELD, 0x4004, 5082 PCI_ANY_ID, PCI_ANY_ID, 5083 0, 0, 5084 pbn_b0_1_115200 }, 5085 { PCI_VENDOR_ID_INTASHIELD, 0x4016, 5086 PCI_ANY_ID, PCI_ANY_ID, 5087 0, 0, 5088 pbn_oxsemi_1_15625000 }, 5089 /* 5090 * Brainboxes PX-203/PX-257 5091 */ 5092 { PCI_VENDOR_ID_INTASHIELD, 0x4006, 5093 PCI_ANY_ID, PCI_ANY_ID, 5094 0, 0, 5095 pbn_b0_2_115200 }, 5096 { PCI_VENDOR_ID_INTASHIELD, 0x4015, 5097 PCI_ANY_ID, PCI_ANY_ID, 5098 0, 0, 5099 pbn_oxsemi_4_15625000 }, 5100 /* 5101 * Brainboxes PX-260/PX-701 5102 */ 5103 { PCI_VENDOR_ID_INTASHIELD, 0x400A, 5104 PCI_ANY_ID, PCI_ANY_ID, 5105 0, 0, 5106 pbn_oxsemi_4_15625000 }, 5107 /* 5108 * Brainboxes PX-310 5109 */ 5110 { PCI_VENDOR_ID_INTASHIELD, 0x400E, 5111 PCI_ANY_ID, PCI_ANY_ID, 5112 0, 0, 5113 pbn_oxsemi_2_15625000 }, 5114 /* 5115 * Brainboxes PX-313 5116 */ 5117 { PCI_VENDOR_ID_INTASHIELD, 0x400C, 5118 PCI_ANY_ID, PCI_ANY_ID, 5119 0, 0, 5120 pbn_oxsemi_2_15625000 }, 5121 /* 5122 * Brainboxes PX-320/324/PX-376/PX-387 5123 */ 5124 { PCI_VENDOR_ID_INTASHIELD, 0x400B, 5125 PCI_ANY_ID, PCI_ANY_ID, 5126 0, 0, 5127 pbn_oxsemi_1_15625000 }, 5128 /* 5129 * Brainboxes PX-335/346 5130 */ 5131 { PCI_VENDOR_ID_INTASHIELD, 0x400F, 5132 PCI_ANY_ID, PCI_ANY_ID, 5133 0, 0, 5134 pbn_oxsemi_4_15625000 }, 5135 /* 5136 * Brainboxes PX-368 5137 */ 5138 { PCI_VENDOR_ID_INTASHIELD, 0x4010, 5139 PCI_ANY_ID, PCI_ANY_ID, 5140 0, 0, 5141 pbn_oxsemi_4_15625000 }, 5142 /* 5143 * Brainboxes PX-420 5144 */ 5145 { PCI_VENDOR_ID_INTASHIELD, 0x4000, 5146 PCI_ANY_ID, PCI_ANY_ID, 5147 0, 0, 5148 pbn_b0_4_115200 }, 5149 { PCI_VENDOR_ID_INTASHIELD, 0x4011, 5150 PCI_ANY_ID, PCI_ANY_ID, 5151 0, 0, 5152 pbn_oxsemi_4_15625000 }, 5153 /* 5154 * Brainboxes PX-803 5155 */ 5156 { PCI_VENDOR_ID_INTASHIELD, 0x4009, 5157 PCI_ANY_ID, PCI_ANY_ID, 5158 0, 0, 5159 pbn_b0_1_115200 }, 5160 { PCI_VENDOR_ID_INTASHIELD, 0x401E, 5161 PCI_ANY_ID, PCI_ANY_ID, 5162 0, 0, 5163 pbn_oxsemi_1_15625000 }, 5164 /* 5165 * Brainboxes PX-846 5166 */ 5167 { PCI_VENDOR_ID_INTASHIELD, 0x4008, 5168 PCI_ANY_ID, PCI_ANY_ID, 5169 0, 0, 5170 pbn_b0_1_115200 }, 5171 { PCI_VENDOR_ID_INTASHIELD, 0x4017, 5172 PCI_ANY_ID, PCI_ANY_ID, 5173 0, 0, 5174 pbn_oxsemi_1_15625000 }, 5175 5176 /* 5177 * Perle PCI-RAS cards 5178 */ 5179 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5180 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5181 0, 0, pbn_b2_4_921600 }, 5182 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5183 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5184 0, 0, pbn_b2_8_921600 }, 5185 5186 /* 5187 * Mainpine series cards: Fairly standard layout but fools 5188 * parts of the autodetect in some cases and uses otherwise 5189 * unmatched communications subclasses in the PCI Express case 5190 */ 5191 5192 { /* RockForceDUO */ 5193 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5194 PCI_VENDOR_ID_MAINPINE, 0x0200, 5195 0, 0, pbn_b0_2_115200 }, 5196 { /* RockForceQUATRO */ 5197 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5198 PCI_VENDOR_ID_MAINPINE, 0x0300, 5199 0, 0, pbn_b0_4_115200 }, 5200 { /* RockForceDUO+ */ 5201 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5202 PCI_VENDOR_ID_MAINPINE, 0x0400, 5203 0, 0, pbn_b0_2_115200 }, 5204 { /* RockForceQUATRO+ */ 5205 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5206 PCI_VENDOR_ID_MAINPINE, 0x0500, 5207 0, 0, pbn_b0_4_115200 }, 5208 { /* RockForce+ */ 5209 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5210 PCI_VENDOR_ID_MAINPINE, 0x0600, 5211 0, 0, pbn_b0_2_115200 }, 5212 { /* RockForce+ */ 5213 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5214 PCI_VENDOR_ID_MAINPINE, 0x0700, 5215 0, 0, pbn_b0_4_115200 }, 5216 { /* RockForceOCTO+ */ 5217 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5218 PCI_VENDOR_ID_MAINPINE, 0x0800, 5219 0, 0, pbn_b0_8_115200 }, 5220 { /* RockForceDUO+ */ 5221 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5222 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5223 0, 0, pbn_b0_2_115200 }, 5224 { /* RockForceQUARTRO+ */ 5225 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5226 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5227 0, 0, pbn_b0_4_115200 }, 5228 { /* RockForceOCTO+ */ 5229 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5230 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5231 0, 0, pbn_b0_8_115200 }, 5232 { /* RockForceD1 */ 5233 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5234 PCI_VENDOR_ID_MAINPINE, 0x2000, 5235 0, 0, pbn_b0_1_115200 }, 5236 { /* RockForceF1 */ 5237 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5238 PCI_VENDOR_ID_MAINPINE, 0x2100, 5239 0, 0, pbn_b0_1_115200 }, 5240 { /* RockForceD2 */ 5241 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5242 PCI_VENDOR_ID_MAINPINE, 0x2200, 5243 0, 0, pbn_b0_2_115200 }, 5244 { /* RockForceF2 */ 5245 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5246 PCI_VENDOR_ID_MAINPINE, 0x2300, 5247 0, 0, pbn_b0_2_115200 }, 5248 { /* RockForceD4 */ 5249 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5250 PCI_VENDOR_ID_MAINPINE, 0x2400, 5251 0, 0, pbn_b0_4_115200 }, 5252 { /* RockForceF4 */ 5253 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5254 PCI_VENDOR_ID_MAINPINE, 0x2500, 5255 0, 0, pbn_b0_4_115200 }, 5256 { /* RockForceD8 */ 5257 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5258 PCI_VENDOR_ID_MAINPINE, 0x2600, 5259 0, 0, pbn_b0_8_115200 }, 5260 { /* RockForceF8 */ 5261 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5262 PCI_VENDOR_ID_MAINPINE, 0x2700, 5263 0, 0, pbn_b0_8_115200 }, 5264 { /* IQ Express D1 */ 5265 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5266 PCI_VENDOR_ID_MAINPINE, 0x3000, 5267 0, 0, pbn_b0_1_115200 }, 5268 { /* IQ Express F1 */ 5269 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5270 PCI_VENDOR_ID_MAINPINE, 0x3100, 5271 0, 0, pbn_b0_1_115200 }, 5272 { /* IQ Express D2 */ 5273 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5274 PCI_VENDOR_ID_MAINPINE, 0x3200, 5275 0, 0, pbn_b0_2_115200 }, 5276 { /* IQ Express F2 */ 5277 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5278 PCI_VENDOR_ID_MAINPINE, 0x3300, 5279 0, 0, pbn_b0_2_115200 }, 5280 { /* IQ Express D4 */ 5281 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5282 PCI_VENDOR_ID_MAINPINE, 0x3400, 5283 0, 0, pbn_b0_4_115200 }, 5284 { /* IQ Express F4 */ 5285 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5286 PCI_VENDOR_ID_MAINPINE, 0x3500, 5287 0, 0, pbn_b0_4_115200 }, 5288 { /* IQ Express D8 */ 5289 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5290 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5291 0, 0, pbn_b0_8_115200 }, 5292 { /* IQ Express F8 */ 5293 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5294 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5295 0, 0, pbn_b0_8_115200 }, 5296 5297 5298 /* 5299 * PA Semi PA6T-1682M on-chip UART 5300 */ 5301 { PCI_VENDOR_ID_PASEMI, 0xa004, 5302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5303 pbn_pasemi_1682M }, 5304 5305 /* 5306 * National Instruments 5307 */ 5308 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5310 pbn_b1_16_115200 }, 5311 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5313 pbn_b1_8_115200 }, 5314 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5315 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5316 pbn_b1_bt_4_115200 }, 5317 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5319 pbn_b1_bt_2_115200 }, 5320 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5322 pbn_b1_bt_4_115200 }, 5323 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5325 pbn_b1_bt_2_115200 }, 5326 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5327 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5328 pbn_b1_16_115200 }, 5329 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5331 pbn_b1_8_115200 }, 5332 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5333 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5334 pbn_b1_bt_4_115200 }, 5335 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5337 pbn_b1_bt_2_115200 }, 5338 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5339 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5340 pbn_b1_bt_4_115200 }, 5341 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5343 pbn_b1_bt_2_115200 }, 5344 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5345 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5346 pbn_ni8430_2 }, 5347 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5349 pbn_ni8430_2 }, 5350 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5352 pbn_ni8430_4 }, 5353 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5355 pbn_ni8430_4 }, 5356 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5358 pbn_ni8430_8 }, 5359 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5361 pbn_ni8430_8 }, 5362 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5364 pbn_ni8430_16 }, 5365 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5367 pbn_ni8430_16 }, 5368 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5369 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5370 pbn_ni8430_2 }, 5371 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5373 pbn_ni8430_2 }, 5374 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5375 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5376 pbn_ni8430_4 }, 5377 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5379 pbn_ni8430_4 }, 5380 5381 /* 5382 * MOXA 5383 */ 5384 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E, 5385 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5386 pbn_moxa8250_2p }, 5387 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL, 5388 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5389 pbn_moxa8250_2p }, 5390 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A, 5391 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5392 pbn_moxa8250_4p }, 5393 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL, 5394 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5395 pbn_moxa8250_4p }, 5396 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A, 5397 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5398 pbn_moxa8250_8p }, 5399 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B, 5400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5401 pbn_moxa8250_8p }, 5402 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A, 5403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5404 pbn_moxa8250_8p }, 5405 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I, 5406 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5407 pbn_moxa8250_8p }, 5408 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL, 5409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5410 pbn_moxa8250_2p }, 5411 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A, 5412 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5413 pbn_moxa8250_4p }, 5414 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A, 5415 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5416 pbn_moxa8250_8p }, 5417 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A, 5418 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5419 pbn_moxa8250_8p }, 5420 5421 /* 5422 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5423 */ 5424 { PCI_VENDOR_ID_ADDIDATA, 5425 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5426 PCI_ANY_ID, 5427 PCI_ANY_ID, 5428 0, 5429 0, 5430 pbn_b0_4_115200 }, 5431 5432 { PCI_VENDOR_ID_ADDIDATA, 5433 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5434 PCI_ANY_ID, 5435 PCI_ANY_ID, 5436 0, 5437 0, 5438 pbn_b0_2_115200 }, 5439 5440 { PCI_VENDOR_ID_ADDIDATA, 5441 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5442 PCI_ANY_ID, 5443 PCI_ANY_ID, 5444 0, 5445 0, 5446 pbn_b0_1_115200 }, 5447 5448 { PCI_VENDOR_ID_AMCC, 5449 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5450 PCI_ANY_ID, 5451 PCI_ANY_ID, 5452 0, 5453 0, 5454 pbn_b1_8_115200 }, 5455 5456 { PCI_VENDOR_ID_ADDIDATA, 5457 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5458 PCI_ANY_ID, 5459 PCI_ANY_ID, 5460 0, 5461 0, 5462 pbn_b0_4_115200 }, 5463 5464 { PCI_VENDOR_ID_ADDIDATA, 5465 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5466 PCI_ANY_ID, 5467 PCI_ANY_ID, 5468 0, 5469 0, 5470 pbn_b0_2_115200 }, 5471 5472 { PCI_VENDOR_ID_ADDIDATA, 5473 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5474 PCI_ANY_ID, 5475 PCI_ANY_ID, 5476 0, 5477 0, 5478 pbn_b0_1_115200 }, 5479 5480 { PCI_VENDOR_ID_ADDIDATA, 5481 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5482 PCI_ANY_ID, 5483 PCI_ANY_ID, 5484 0, 5485 0, 5486 pbn_b0_4_115200 }, 5487 5488 { PCI_VENDOR_ID_ADDIDATA, 5489 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5490 PCI_ANY_ID, 5491 PCI_ANY_ID, 5492 0, 5493 0, 5494 pbn_b0_2_115200 }, 5495 5496 { PCI_VENDOR_ID_ADDIDATA, 5497 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5498 PCI_ANY_ID, 5499 PCI_ANY_ID, 5500 0, 5501 0, 5502 pbn_b0_1_115200 }, 5503 5504 { PCI_VENDOR_ID_ADDIDATA, 5505 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5506 PCI_ANY_ID, 5507 PCI_ANY_ID, 5508 0, 5509 0, 5510 pbn_b0_8_115200 }, 5511 5512 { PCI_VENDOR_ID_ADDIDATA, 5513 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5514 PCI_ANY_ID, 5515 PCI_ANY_ID, 5516 0, 5517 0, 5518 pbn_ADDIDATA_PCIe_4_3906250 }, 5519 5520 { PCI_VENDOR_ID_ADDIDATA, 5521 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5522 PCI_ANY_ID, 5523 PCI_ANY_ID, 5524 0, 5525 0, 5526 pbn_ADDIDATA_PCIe_2_3906250 }, 5527 5528 { PCI_VENDOR_ID_ADDIDATA, 5529 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5530 PCI_ANY_ID, 5531 PCI_ANY_ID, 5532 0, 5533 0, 5534 pbn_ADDIDATA_PCIe_1_3906250 }, 5535 5536 { PCI_VENDOR_ID_ADDIDATA, 5537 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5538 PCI_ANY_ID, 5539 PCI_ANY_ID, 5540 0, 5541 0, 5542 pbn_ADDIDATA_PCIe_8_3906250 }, 5543 5544 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5545 PCI_VENDOR_ID_IBM, 0x0299, 5546 0, 0, pbn_b0_bt_2_115200 }, 5547 5548 /* 5549 * other NetMos 9835 devices are most likely handled by the 5550 * parport_serial driver, check drivers/parport/parport_serial.c 5551 * before adding them here. 5552 */ 5553 5554 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5555 0xA000, 0x1000, 5556 0, 0, pbn_b0_1_115200 }, 5557 5558 /* the 9901 is a rebranded 9912 */ 5559 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5560 0xA000, 0x1000, 5561 0, 0, pbn_b0_1_115200 }, 5562 5563 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5564 0xA000, 0x1000, 5565 0, 0, pbn_b0_1_115200 }, 5566 5567 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5568 0xA000, 0x1000, 5569 0, 0, pbn_b0_1_115200 }, 5570 5571 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5572 0xA000, 0x1000, 5573 0, 0, pbn_b0_1_115200 }, 5574 5575 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5576 0xA000, 0x3002, 5577 0, 0, pbn_NETMOS9900_2s_115200 }, 5578 5579 /* 5580 * Best Connectivity and Rosewill PCI Multi I/O cards 5581 */ 5582 5583 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5584 0xA000, 0x1000, 5585 0, 0, pbn_b0_1_115200 }, 5586 5587 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5588 0xA000, 0x3002, 5589 0, 0, pbn_b0_bt_2_115200 }, 5590 5591 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5592 0xA000, 0x3004, 5593 0, 0, pbn_b0_bt_4_115200 }, 5594 /* Intel CE4100 */ 5595 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5596 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5597 pbn_ce4100_1_115200 }, 5598 5599 /* 5600 * Cronyx Omega PCI 5601 */ 5602 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5603 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5604 pbn_omegapci }, 5605 5606 /* 5607 * Broadcom TruManage 5608 */ 5609 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5610 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5611 pbn_brcm_trumanage }, 5612 5613 /* 5614 * AgeStar as-prs2-009 5615 */ 5616 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5617 PCI_ANY_ID, PCI_ANY_ID, 5618 0, 0, pbn_b0_bt_2_115200 }, 5619 5620 /* 5621 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5622 * so not listed here. 5623 */ 5624 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5625 PCI_ANY_ID, PCI_ANY_ID, 5626 0, 0, pbn_b0_bt_4_115200 }, 5627 5628 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5629 PCI_ANY_ID, PCI_ANY_ID, 5630 0, 0, pbn_b0_bt_2_115200 }, 5631 5632 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5633 PCI_ANY_ID, PCI_ANY_ID, 5634 0, 0, pbn_b0_bt_4_115200 }, 5635 5636 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5637 PCI_ANY_ID, PCI_ANY_ID, 5638 0, 0, pbn_wch382_2 }, 5639 5640 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5641 PCI_ANY_ID, PCI_ANY_ID, 5642 0, 0, pbn_wch384_4 }, 5643 5644 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S, 5645 PCI_ANY_ID, PCI_ANY_ID, 5646 0, 0, pbn_wch384_8 }, 5647 /* 5648 * Realtek RealManage 5649 */ 5650 { PCI_VENDOR_ID_REALTEK, 0x816a, 5651 PCI_ANY_ID, PCI_ANY_ID, 5652 0, 0, pbn_b0_1_115200 }, 5653 5654 { PCI_VENDOR_ID_REALTEK, 0x816b, 5655 PCI_ANY_ID, PCI_ANY_ID, 5656 0, 0, pbn_b0_1_115200 }, 5657 5658 /* Fintek PCI serial cards */ 5659 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5660 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5661 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5662 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 5663 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 5664 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 5665 5666 /* MKS Tenta SCOM-080x serial cards */ 5667 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5668 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5669 5670 /* Amazon PCI serial device */ 5671 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5672 5673 /* 5674 * These entries match devices with class COMMUNICATION_SERIAL, 5675 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5676 */ 5677 { PCI_ANY_ID, PCI_ANY_ID, 5678 PCI_ANY_ID, PCI_ANY_ID, 5679 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5680 0xffff00, pbn_default }, 5681 { PCI_ANY_ID, PCI_ANY_ID, 5682 PCI_ANY_ID, PCI_ANY_ID, 5683 PCI_CLASS_COMMUNICATION_MODEM << 8, 5684 0xffff00, pbn_default }, 5685 { PCI_ANY_ID, PCI_ANY_ID, 5686 PCI_ANY_ID, PCI_ANY_ID, 5687 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5688 0xffff00, pbn_default }, 5689 { 0, } 5690 }; 5691 5692 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5693 pci_channel_state_t state) 5694 { 5695 struct serial_private *priv = pci_get_drvdata(dev); 5696 5697 if (state == pci_channel_io_perm_failure) 5698 return PCI_ERS_RESULT_DISCONNECT; 5699 5700 if (priv) 5701 pciserial_detach_ports(priv); 5702 5703 pci_disable_device(dev); 5704 5705 return PCI_ERS_RESULT_NEED_RESET; 5706 } 5707 5708 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5709 { 5710 int rc; 5711 5712 rc = pci_enable_device(dev); 5713 5714 if (rc) 5715 return PCI_ERS_RESULT_DISCONNECT; 5716 5717 pci_restore_state(dev); 5718 pci_save_state(dev); 5719 5720 return PCI_ERS_RESULT_RECOVERED; 5721 } 5722 5723 static void serial8250_io_resume(struct pci_dev *dev) 5724 { 5725 struct serial_private *priv = pci_get_drvdata(dev); 5726 struct serial_private *new; 5727 5728 if (!priv) 5729 return; 5730 5731 new = pciserial_init_ports(dev, priv->board); 5732 if (!IS_ERR(new)) { 5733 pci_set_drvdata(dev, new); 5734 kfree(priv); 5735 } 5736 } 5737 5738 static const struct pci_error_handlers serial8250_err_handler = { 5739 .error_detected = serial8250_io_error_detected, 5740 .slot_reset = serial8250_io_slot_reset, 5741 .resume = serial8250_io_resume, 5742 }; 5743 5744 static struct pci_driver serial_pci_driver = { 5745 .name = "serial", 5746 .probe = pciserial_init_one, 5747 .remove = pciserial_remove_one, 5748 .driver = { 5749 .pm = &pciserial_pm_ops, 5750 }, 5751 .id_table = serial_pci_tbl, 5752 .err_handler = &serial8250_err_handler, 5753 }; 5754 5755 module_pci_driver(serial_pci_driver); 5756 5757 MODULE_LICENSE("GPL"); 5758 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5759 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5760