1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <drm/drm_atomic_state_helper.h> 7 8 #include "intel_atomic.h" 9 #include "intel_bw.h" 10 #include "intel_cdclk.h" 11 #include "intel_display_types.h" 12 #include "intel_pm.h" 13 #include "intel_sideband.h" 14 15 /* Parameters for Qclk Geyserville (QGV) */ 16 struct intel_qgv_point { 17 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; 18 }; 19 20 struct intel_psf_gv_point { 21 u8 clk; /* clock in multiples of 16.6666 MHz */ 22 }; 23 24 struct intel_qgv_info { 25 struct intel_qgv_point points[I915_NUM_QGV_POINTS]; 26 struct intel_psf_gv_point psf_points[I915_NUM_PSF_GV_POINTS]; 27 u8 num_points; 28 u8 num_psf_points; 29 u8 t_bl; 30 }; 31 32 static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv, 33 struct intel_qgv_point *sp, 34 int point) 35 { 36 u32 dclk_ratio, dclk_reference; 37 u32 val; 38 39 val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC); 40 dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val); 41 if (val & DG1_QCLK_REFERENCE) 42 dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */ 43 else 44 dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */ 45 sp->dclk = dclk_ratio * dclk_reference; 46 47 val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); 48 if (val & DG1_GEAR_TYPE) 49 sp->dclk *= 2; 50 51 if (sp->dclk == 0) 52 return -EINVAL; 53 54 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR); 55 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val); 56 sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val); 57 58 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH); 59 sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val); 60 sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val); 61 62 sp->t_rc = sp->t_rp + sp->t_ras; 63 64 return 0; 65 } 66 67 static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, 68 struct intel_qgv_point *sp, 69 int point) 70 { 71 u32 val = 0, val2 = 0; 72 int ret; 73 74 ret = sandybridge_pcode_read(dev_priv, 75 ICL_PCODE_MEM_SUBSYSYSTEM_INFO | 76 ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point), 77 &val, &val2); 78 if (ret) 79 return ret; 80 81 sp->dclk = val & 0xffff; 82 sp->t_rp = (val & 0xff0000) >> 16; 83 sp->t_rcd = (val & 0xff000000) >> 24; 84 85 sp->t_rdpre = val2 & 0xff; 86 sp->t_ras = (val2 & 0xff00) >> 8; 87 88 sp->t_rc = sp->t_rp + sp->t_ras; 89 90 return 0; 91 } 92 93 static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv, 94 struct intel_psf_gv_point *points) 95 { 96 u32 val = 0; 97 int ret; 98 int i; 99 100 ret = sandybridge_pcode_read(dev_priv, 101 ICL_PCODE_MEM_SUBSYSYSTEM_INFO | 102 ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, 103 &val, NULL); 104 if (ret) 105 return ret; 106 107 for (i = 0; i < I915_NUM_PSF_GV_POINTS; i++) { 108 points[i].clk = val & 0xff; 109 val >>= 8; 110 } 111 112 return 0; 113 } 114 115 int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, 116 u32 points_mask) 117 { 118 int ret; 119 120 /* bspec says to keep retrying for at least 1 ms */ 121 ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG, 122 points_mask, 123 ICL_PCODE_POINTS_RESTRICTED_MASK, 124 ICL_PCODE_POINTS_RESTRICTED, 125 1); 126 127 if (ret < 0) { 128 drm_err(&dev_priv->drm, "Failed to disable qgv points (%d) points: 0x%x\n", ret, points_mask); 129 return ret; 130 } 131 132 return 0; 133 } 134 135 static int icl_get_qgv_points(struct drm_i915_private *dev_priv, 136 struct intel_qgv_info *qi) 137 { 138 const struct dram_info *dram_info = &dev_priv->dram_info; 139 int i, ret; 140 141 qi->num_points = dram_info->num_qgv_points; 142 qi->num_psf_points = dram_info->num_psf_gv_points; 143 144 if (DISPLAY_VER(dev_priv) == 12) 145 switch (dram_info->type) { 146 case INTEL_DRAM_DDR4: 147 qi->t_bl = 4; 148 break; 149 case INTEL_DRAM_DDR5: 150 qi->t_bl = 8; 151 break; 152 default: 153 qi->t_bl = 16; 154 break; 155 } 156 else if (DISPLAY_VER(dev_priv) == 11) 157 qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8; 158 159 if (drm_WARN_ON(&dev_priv->drm, 160 qi->num_points > ARRAY_SIZE(qi->points))) 161 qi->num_points = ARRAY_SIZE(qi->points); 162 163 for (i = 0; i < qi->num_points; i++) { 164 struct intel_qgv_point *sp = &qi->points[i]; 165 166 if (IS_DG1(dev_priv)) 167 ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i); 168 else 169 ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i); 170 171 if (ret) 172 return ret; 173 174 drm_dbg_kms(&dev_priv->drm, 175 "QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n", 176 i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras, 177 sp->t_rcd, sp->t_rc); 178 } 179 180 if (qi->num_psf_points > 0) { 181 ret = adls_pcode_read_psf_gv_point_info(dev_priv, qi->psf_points); 182 if (ret) { 183 drm_err(&dev_priv->drm, "Failed to read PSF point data; PSF points will not be considered in bandwidth calculations.\n"); 184 qi->num_psf_points = 0; 185 } 186 187 for (i = 0; i < qi->num_psf_points; i++) 188 drm_dbg_kms(&dev_priv->drm, 189 "PSF GV %d: CLK=%d \n", 190 i, qi->psf_points[i].clk); 191 } 192 193 return 0; 194 } 195 196 static int icl_calc_bw(int dclk, int num, int den) 197 { 198 /* multiples of 16.666MHz (100/6) */ 199 return DIV_ROUND_CLOSEST(num * dclk * 100, den * 6); 200 } 201 202 static int adl_calc_psf_bw(int clk) 203 { 204 /* 205 * clk is multiples of 16.666MHz (100/6) 206 * According to BSpec PSF GV bandwidth is 207 * calculated as BW = 64 * clk * 16.666Mhz 208 */ 209 return DIV_ROUND_CLOSEST(64 * clk * 100, 6); 210 } 211 212 static int icl_sagv_max_dclk(const struct intel_qgv_info *qi) 213 { 214 u16 dclk = 0; 215 int i; 216 217 for (i = 0; i < qi->num_points; i++) 218 dclk = max(dclk, qi->points[i].dclk); 219 220 return dclk; 221 } 222 223 struct intel_sa_info { 224 u16 displayrtids; 225 u8 deburst, deprogbwlimit, derating; 226 }; 227 228 static const struct intel_sa_info icl_sa_info = { 229 .deburst = 8, 230 .deprogbwlimit = 25, /* GB/s */ 231 .displayrtids = 128, 232 .derating = 10, 233 }; 234 235 static const struct intel_sa_info tgl_sa_info = { 236 .deburst = 16, 237 .deprogbwlimit = 34, /* GB/s */ 238 .displayrtids = 256, 239 .derating = 10, 240 }; 241 242 static const struct intel_sa_info rkl_sa_info = { 243 .deburst = 16, 244 .deprogbwlimit = 20, /* GB/s */ 245 .displayrtids = 128, 246 .derating = 10, 247 }; 248 249 static const struct intel_sa_info adls_sa_info = { 250 .deburst = 16, 251 .deprogbwlimit = 38, /* GB/s */ 252 .displayrtids = 256, 253 .derating = 10, 254 }; 255 256 static const struct intel_sa_info adlp_sa_info = { 257 .deburst = 16, 258 .deprogbwlimit = 38, /* GB/s */ 259 .displayrtids = 256, 260 .derating = 20, 261 }; 262 263 static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa) 264 { 265 struct intel_qgv_info qi = {}; 266 bool is_y_tile = true; /* assume y tile may be used */ 267 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels); 268 int deinterleave; 269 int ipqdepth, ipqdepthpch; 270 int dclk_max; 271 int maxdebw; 272 int i, ret; 273 274 ret = icl_get_qgv_points(dev_priv, &qi); 275 if (ret) { 276 drm_dbg_kms(&dev_priv->drm, 277 "Failed to get memory subsystem information, ignoring bandwidth limits"); 278 return ret; 279 } 280 281 deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2); 282 dclk_max = icl_sagv_max_dclk(&qi); 283 284 ipqdepthpch = 16; 285 286 maxdebw = min(sa->deprogbwlimit * 1000, 287 icl_calc_bw(dclk_max, 16, 1) * 6 / 10); /* 60% */ 288 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); 289 290 for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) { 291 struct intel_bw_info *bi = &dev_priv->max_bw[i]; 292 int clpchgroup; 293 int j; 294 295 clpchgroup = (sa->deburst * deinterleave / num_channels) << i; 296 bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1; 297 298 bi->num_qgv_points = qi.num_points; 299 bi->num_psf_gv_points = qi.num_psf_points; 300 301 for (j = 0; j < qi.num_points; j++) { 302 const struct intel_qgv_point *sp = &qi.points[j]; 303 int ct, bw; 304 305 /* 306 * Max row cycle time 307 * 308 * FIXME what is the logic behind the 309 * assumed burst length? 310 */ 311 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd + 312 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre); 313 bw = icl_calc_bw(sp->dclk, clpchgroup * 32 * num_channels, ct); 314 315 bi->deratedbw[j] = min(maxdebw, 316 bw * (100 - sa->derating) / 100); 317 318 drm_dbg_kms(&dev_priv->drm, 319 "BW%d / QGV %d: num_planes=%d deratedbw=%u\n", 320 i, j, bi->num_planes, bi->deratedbw[j]); 321 } 322 323 for (j = 0; j < qi.num_psf_points; j++) { 324 const struct intel_psf_gv_point *sp = &qi.psf_points[j]; 325 326 bi->psf_bw[j] = adl_calc_psf_bw(sp->clk); 327 328 drm_dbg_kms(&dev_priv->drm, 329 "BW%d / PSF GV %d: num_planes=%d bw=%u\n", 330 i, j, bi->num_planes, bi->psf_bw[j]); 331 } 332 333 if (bi->num_planes == 1) 334 break; 335 } 336 337 /* 338 * In case if SAGV is disabled in BIOS, we always get 1 339 * SAGV point, but we can't send PCode commands to restrict it 340 * as it will fail and pointless anyway. 341 */ 342 if (qi.num_points == 1) 343 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; 344 else 345 dev_priv->sagv_status = I915_SAGV_ENABLED; 346 347 return 0; 348 } 349 350 static void dg2_get_bw_info(struct drm_i915_private *i915) 351 { 352 struct intel_bw_info *bi = &i915->max_bw[0]; 353 354 /* 355 * DG2 doesn't have SAGV or QGV points, just a constant max bandwidth 356 * that doesn't depend on the number of planes enabled. Create a 357 * single dummy QGV point to reflect that. DG2-G10 platforms have a 358 * constant 50 GB/s bandwidth, whereas DG2-G11 platforms have 38 GB/s. 359 */ 360 bi->num_planes = 1; 361 bi->num_qgv_points = 1; 362 if (IS_DG2_G11(i915)) 363 bi->deratedbw[0] = 38000; 364 else 365 bi->deratedbw[0] = 50000; 366 367 i915->sagv_status = I915_SAGV_NOT_CONTROLLED; 368 } 369 370 static unsigned int icl_max_bw(struct drm_i915_private *dev_priv, 371 int num_planes, int qgv_point) 372 { 373 int i; 374 375 /* 376 * Let's return max bw for 0 planes 377 */ 378 num_planes = max(1, num_planes); 379 380 for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) { 381 const struct intel_bw_info *bi = 382 &dev_priv->max_bw[i]; 383 384 /* 385 * Pcode will not expose all QGV points when 386 * SAGV is forced to off/min/med/max. 387 */ 388 if (qgv_point >= bi->num_qgv_points) 389 return UINT_MAX; 390 391 if (num_planes >= bi->num_planes) 392 return bi->deratedbw[qgv_point]; 393 } 394 395 return 0; 396 } 397 398 static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv, 399 int psf_gv_point) 400 { 401 const struct intel_bw_info *bi = 402 &dev_priv->max_bw[0]; 403 404 return bi->psf_bw[psf_gv_point]; 405 } 406 407 void intel_bw_init_hw(struct drm_i915_private *dev_priv) 408 { 409 if (!HAS_DISPLAY(dev_priv)) 410 return; 411 412 if (IS_DG2(dev_priv)) 413 dg2_get_bw_info(dev_priv); 414 else if (IS_ALDERLAKE_P(dev_priv)) 415 icl_get_bw_info(dev_priv, &adlp_sa_info); 416 else if (IS_ALDERLAKE_S(dev_priv)) 417 icl_get_bw_info(dev_priv, &adls_sa_info); 418 else if (IS_ROCKETLAKE(dev_priv)) 419 icl_get_bw_info(dev_priv, &rkl_sa_info); 420 else if (DISPLAY_VER(dev_priv) == 12) 421 icl_get_bw_info(dev_priv, &tgl_sa_info); 422 else if (DISPLAY_VER(dev_priv) == 11) 423 icl_get_bw_info(dev_priv, &icl_sa_info); 424 } 425 426 static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state) 427 { 428 /* 429 * We assume cursors are small enough 430 * to not not cause bandwidth problems. 431 */ 432 return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR)); 433 } 434 435 static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state) 436 { 437 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 438 unsigned int data_rate = 0; 439 enum plane_id plane_id; 440 441 for_each_plane_id_on_crtc(crtc, plane_id) { 442 /* 443 * We assume cursors are small enough 444 * to not not cause bandwidth problems. 445 */ 446 if (plane_id == PLANE_CURSOR) 447 continue; 448 449 data_rate += crtc_state->data_rate[plane_id]; 450 } 451 452 return data_rate; 453 } 454 455 void intel_bw_crtc_update(struct intel_bw_state *bw_state, 456 const struct intel_crtc_state *crtc_state) 457 { 458 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 459 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 460 461 bw_state->data_rate[crtc->pipe] = 462 intel_bw_crtc_data_rate(crtc_state); 463 bw_state->num_active_planes[crtc->pipe] = 464 intel_bw_crtc_num_active_planes(crtc_state); 465 466 drm_dbg_kms(&i915->drm, "pipe %c data rate %u num active planes %u\n", 467 pipe_name(crtc->pipe), 468 bw_state->data_rate[crtc->pipe], 469 bw_state->num_active_planes[crtc->pipe]); 470 } 471 472 static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv, 473 const struct intel_bw_state *bw_state) 474 { 475 unsigned int num_active_planes = 0; 476 enum pipe pipe; 477 478 for_each_pipe(dev_priv, pipe) 479 num_active_planes += bw_state->num_active_planes[pipe]; 480 481 return num_active_planes; 482 } 483 484 static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv, 485 const struct intel_bw_state *bw_state) 486 { 487 unsigned int data_rate = 0; 488 enum pipe pipe; 489 490 for_each_pipe(dev_priv, pipe) 491 data_rate += bw_state->data_rate[pipe]; 492 493 if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active()) 494 data_rate = data_rate * 105 / 100; 495 496 return data_rate; 497 } 498 499 struct intel_bw_state * 500 intel_atomic_get_old_bw_state(struct intel_atomic_state *state) 501 { 502 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 503 struct intel_global_state *bw_state; 504 505 bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->bw_obj); 506 507 return to_intel_bw_state(bw_state); 508 } 509 510 struct intel_bw_state * 511 intel_atomic_get_new_bw_state(struct intel_atomic_state *state) 512 { 513 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 514 struct intel_global_state *bw_state; 515 516 bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->bw_obj); 517 518 return to_intel_bw_state(bw_state); 519 } 520 521 struct intel_bw_state * 522 intel_atomic_get_bw_state(struct intel_atomic_state *state) 523 { 524 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 525 struct intel_global_state *bw_state; 526 527 bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->bw_obj); 528 if (IS_ERR(bw_state)) 529 return ERR_CAST(bw_state); 530 531 return to_intel_bw_state(bw_state); 532 } 533 534 int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) 535 { 536 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 537 struct intel_bw_state *new_bw_state = NULL; 538 struct intel_bw_state *old_bw_state = NULL; 539 const struct intel_crtc_state *crtc_state; 540 struct intel_crtc *crtc; 541 int max_bw = 0; 542 enum pipe pipe; 543 int i; 544 545 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 546 enum plane_id plane_id; 547 struct intel_dbuf_bw *crtc_bw; 548 549 new_bw_state = intel_atomic_get_bw_state(state); 550 if (IS_ERR(new_bw_state)) 551 return PTR_ERR(new_bw_state); 552 553 old_bw_state = intel_atomic_get_old_bw_state(state); 554 555 crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe]; 556 557 memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw)); 558 559 if (!crtc_state->hw.active) 560 continue; 561 562 for_each_plane_id_on_crtc(crtc, plane_id) { 563 const struct skl_ddb_entry *plane_alloc = 564 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 565 const struct skl_ddb_entry *uv_plane_alloc = 566 &crtc_state->wm.skl.plane_ddb_uv[plane_id]; 567 unsigned int data_rate = crtc_state->data_rate[plane_id]; 568 unsigned int dbuf_mask = 0; 569 enum dbuf_slice slice; 570 571 dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, plane_alloc); 572 dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, uv_plane_alloc); 573 574 /* 575 * FIXME: To calculate that more properly we probably 576 * need to to split per plane data_rate into data_rate_y 577 * and data_rate_uv for multiplanar formats in order not 578 * to get accounted those twice if they happen to reside 579 * on different slices. 580 * However for pre-icl this would work anyway because 581 * we have only single slice and for icl+ uv plane has 582 * non-zero data rate. 583 * So in worst case those calculation are a bit 584 * pessimistic, which shouldn't pose any significant 585 * problem anyway. 586 */ 587 for_each_dbuf_slice_in_mask(dev_priv, slice, dbuf_mask) 588 crtc_bw->used_bw[slice] += data_rate; 589 } 590 } 591 592 if (!old_bw_state) 593 return 0; 594 595 for_each_pipe(dev_priv, pipe) { 596 struct intel_dbuf_bw *crtc_bw; 597 enum dbuf_slice slice; 598 599 crtc_bw = &new_bw_state->dbuf_bw[pipe]; 600 601 for_each_dbuf_slice(dev_priv, slice) { 602 /* 603 * Current experimental observations show that contrary 604 * to BSpec we get underruns once we exceed 64 * CDCLK 605 * for slices in total. 606 * As a temporary measure in order not to keep CDCLK 607 * bumped up all the time we calculate CDCLK according 608 * to this formula for overall bw consumed by slices. 609 */ 610 max_bw += crtc_bw->used_bw[slice]; 611 } 612 } 613 614 new_bw_state->min_cdclk = max_bw / 64; 615 616 if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { 617 int ret = intel_atomic_lock_global_state(&new_bw_state->base); 618 619 if (ret) 620 return ret; 621 } 622 623 return 0; 624 } 625 626 int intel_bw_calc_min_cdclk(struct intel_atomic_state *state) 627 { 628 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 629 struct intel_bw_state *new_bw_state = NULL; 630 struct intel_bw_state *old_bw_state = NULL; 631 const struct intel_crtc_state *crtc_state; 632 struct intel_crtc *crtc; 633 int min_cdclk = 0; 634 enum pipe pipe; 635 int i; 636 637 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 638 new_bw_state = intel_atomic_get_bw_state(state); 639 if (IS_ERR(new_bw_state)) 640 return PTR_ERR(new_bw_state); 641 642 old_bw_state = intel_atomic_get_old_bw_state(state); 643 } 644 645 if (!old_bw_state) 646 return 0; 647 648 for_each_pipe(dev_priv, pipe) { 649 struct intel_cdclk_state *cdclk_state; 650 651 cdclk_state = intel_atomic_get_new_cdclk_state(state); 652 if (!cdclk_state) 653 return 0; 654 655 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); 656 } 657 658 new_bw_state->min_cdclk = min_cdclk; 659 660 if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { 661 int ret = intel_atomic_lock_global_state(&new_bw_state->base); 662 663 if (ret) 664 return ret; 665 } 666 667 return 0; 668 } 669 670 int intel_bw_atomic_check(struct intel_atomic_state *state) 671 { 672 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 673 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 674 struct intel_bw_state *new_bw_state = NULL; 675 const struct intel_bw_state *old_bw_state = NULL; 676 unsigned int data_rate; 677 unsigned int num_active_planes; 678 struct intel_crtc *crtc; 679 int i, ret; 680 u32 allowed_points = 0; 681 unsigned int max_bw_point = 0, max_bw = 0; 682 unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points; 683 unsigned int num_psf_gv_points = dev_priv->max_bw[0].num_psf_gv_points; 684 u32 mask = 0; 685 686 /* FIXME earlier gens need some checks too */ 687 if (DISPLAY_VER(dev_priv) < 11) 688 return 0; 689 690 /* 691 * We can _not_ use the whole ADLS_QGV_PT_MASK here, as PCode rejects 692 * it with failure if we try masking any unadvertised points. 693 * So need to operate only with those returned from PCode. 694 */ 695 if (num_qgv_points > 0) 696 mask |= REG_GENMASK(num_qgv_points - 1, 0); 697 698 if (num_psf_gv_points > 0) 699 mask |= REG_GENMASK(num_psf_gv_points - 1, 0) << ADLS_PSF_PT_SHIFT; 700 701 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 702 new_crtc_state, i) { 703 unsigned int old_data_rate = 704 intel_bw_crtc_data_rate(old_crtc_state); 705 unsigned int new_data_rate = 706 intel_bw_crtc_data_rate(new_crtc_state); 707 unsigned int old_active_planes = 708 intel_bw_crtc_num_active_planes(old_crtc_state); 709 unsigned int new_active_planes = 710 intel_bw_crtc_num_active_planes(new_crtc_state); 711 712 /* 713 * Avoid locking the bw state when 714 * nothing significant has changed. 715 */ 716 if (old_data_rate == new_data_rate && 717 old_active_planes == new_active_planes) 718 continue; 719 720 new_bw_state = intel_atomic_get_bw_state(state); 721 if (IS_ERR(new_bw_state)) 722 return PTR_ERR(new_bw_state); 723 724 new_bw_state->data_rate[crtc->pipe] = new_data_rate; 725 new_bw_state->num_active_planes[crtc->pipe] = new_active_planes; 726 727 drm_dbg_kms(&dev_priv->drm, 728 "pipe %c data rate %u num active planes %u\n", 729 pipe_name(crtc->pipe), 730 new_bw_state->data_rate[crtc->pipe], 731 new_bw_state->num_active_planes[crtc->pipe]); 732 } 733 734 if (!new_bw_state) 735 return 0; 736 737 ret = intel_atomic_lock_global_state(&new_bw_state->base); 738 if (ret) 739 return ret; 740 741 data_rate = intel_bw_data_rate(dev_priv, new_bw_state); 742 data_rate = DIV_ROUND_UP(data_rate, 1000); 743 744 num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state); 745 746 for (i = 0; i < num_qgv_points; i++) { 747 unsigned int max_data_rate; 748 749 max_data_rate = icl_max_bw(dev_priv, num_active_planes, i); 750 /* 751 * We need to know which qgv point gives us 752 * maximum bandwidth in order to disable SAGV 753 * if we find that we exceed SAGV block time 754 * with watermarks. By that moment we already 755 * have those, as it is calculated earlier in 756 * intel_atomic_check, 757 */ 758 if (max_data_rate > max_bw) { 759 max_bw_point = i; 760 max_bw = max_data_rate; 761 } 762 if (max_data_rate >= data_rate) 763 allowed_points |= REG_FIELD_PREP(ADLS_QGV_PT_MASK, BIT(i)); 764 765 drm_dbg_kms(&dev_priv->drm, "QGV point %d: max bw %d required %d\n", 766 i, max_data_rate, data_rate); 767 } 768 769 for (i = 0; i < num_psf_gv_points; i++) { 770 unsigned int max_data_rate = adl_psf_bw(dev_priv, i); 771 772 if (max_data_rate >= data_rate) 773 allowed_points |= REG_FIELD_PREP(ADLS_PSF_PT_MASK, BIT(i)); 774 775 drm_dbg_kms(&dev_priv->drm, "PSF GV point %d: max bw %d" 776 " required %d\n", 777 i, max_data_rate, data_rate); 778 } 779 780 /* 781 * BSpec states that we always should have at least one allowed point 782 * left, so if we couldn't - simply reject the configuration for obvious 783 * reasons. 784 */ 785 if ((allowed_points & ADLS_QGV_PT_MASK) == 0) { 786 drm_dbg_kms(&dev_priv->drm, "No QGV points provide sufficient memory" 787 " bandwidth %d for display configuration(%d active planes).\n", 788 data_rate, num_active_planes); 789 return -EINVAL; 790 } 791 792 if (num_psf_gv_points > 0) { 793 if ((allowed_points & ADLS_PSF_PT_MASK) == 0) { 794 drm_dbg_kms(&dev_priv->drm, "No PSF GV points provide sufficient memory" 795 " bandwidth %d for display configuration(%d active planes).\n", 796 data_rate, num_active_planes); 797 return -EINVAL; 798 } 799 } 800 801 /* 802 * Leave only single point with highest bandwidth, if 803 * we can't enable SAGV due to the increased memory latency it may 804 * cause. 805 */ 806 if (!intel_can_enable_sagv(dev_priv, new_bw_state)) { 807 allowed_points = BIT(max_bw_point); 808 drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n", 809 max_bw_point); 810 } 811 /* 812 * We store the ones which need to be masked as that is what PCode 813 * actually accepts as a parameter. 814 */ 815 new_bw_state->qgv_points_mask = ~allowed_points & mask; 816 817 old_bw_state = intel_atomic_get_old_bw_state(state); 818 /* 819 * If the actual mask had changed we need to make sure that 820 * the commits are serialized(in case this is a nomodeset, nonblocking) 821 */ 822 if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) { 823 ret = intel_atomic_serialize_global_state(&new_bw_state->base); 824 if (ret) 825 return ret; 826 } 827 828 return 0; 829 } 830 831 static struct intel_global_state * 832 intel_bw_duplicate_state(struct intel_global_obj *obj) 833 { 834 struct intel_bw_state *state; 835 836 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 837 if (!state) 838 return NULL; 839 840 return &state->base; 841 } 842 843 static void intel_bw_destroy_state(struct intel_global_obj *obj, 844 struct intel_global_state *state) 845 { 846 kfree(state); 847 } 848 849 static const struct intel_global_state_funcs intel_bw_funcs = { 850 .atomic_duplicate_state = intel_bw_duplicate_state, 851 .atomic_destroy_state = intel_bw_destroy_state, 852 }; 853 854 int intel_bw_init(struct drm_i915_private *dev_priv) 855 { 856 struct intel_bw_state *state; 857 858 state = kzalloc(sizeof(*state), GFP_KERNEL); 859 if (!state) 860 return -ENOMEM; 861 862 intel_atomic_global_obj_init(dev_priv, &dev_priv->bw_obj, 863 &state->base, &intel_bw_funcs); 864 865 return 0; 866 } 867