1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // tegra210_ahub.c - Tegra210 AHUB driver 4 // 5 // Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/module.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <sound/soc.h> 15 #include "tegra210_ahub.h" 16 17 static int tegra_ahub_get_value_enum(struct snd_kcontrol *kctl, 18 struct snd_ctl_elem_value *uctl) 19 { 20 struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_component(kctl); 21 struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt); 22 struct soc_enum *e = (struct soc_enum *)kctl->private_value; 23 unsigned int reg, i, bit_pos = 0; 24 25 /* 26 * Find the bit position of current MUX input. 27 * If nothing is set, position would be 0 and it corresponds to 'None'. 28 */ 29 for (i = 0; i < ahub->soc_data->reg_count; i++) { 30 unsigned int reg_val; 31 32 reg = e->reg + (TEGRA210_XBAR_PART1_RX * i); 33 reg_val = snd_soc_component_read(cmpnt, reg); 34 reg_val &= ahub->soc_data->mask[i]; 35 36 if (reg_val) { 37 bit_pos = ffs(reg_val) + 38 (8 * cmpnt->val_bytes * i); 39 break; 40 } 41 } 42 43 /* Find index related to the item in array *_ahub_mux_texts[] */ 44 for (i = 0; i < e->items; i++) { 45 if (bit_pos == e->values[i]) { 46 uctl->value.enumerated.item[0] = i; 47 break; 48 } 49 } 50 51 return 0; 52 } 53 54 static int tegra_ahub_put_value_enum(struct snd_kcontrol *kctl, 55 struct snd_ctl_elem_value *uctl) 56 { 57 struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_component(kctl); 58 struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt); 59 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kctl); 60 struct soc_enum *e = (struct soc_enum *)kctl->private_value; 61 struct snd_soc_dapm_update update[TEGRA_XBAR_UPDATE_MAX_REG] = { }; 62 unsigned int *item = uctl->value.enumerated.item; 63 unsigned int value = e->values[item[0]]; 64 unsigned int i, bit_pos, reg_idx = 0, reg_val = 0; 65 int change = 0; 66 67 if (item[0] >= e->items) 68 return -EINVAL; 69 70 if (value) { 71 /* Get the register index and value to set */ 72 reg_idx = (value - 1) / (8 * cmpnt->val_bytes); 73 bit_pos = (value - 1) % (8 * cmpnt->val_bytes); 74 reg_val = BIT(bit_pos); 75 } 76 77 /* 78 * Run through all parts of a MUX register to find the state changes. 79 * There will be an additional update if new MUX input value is from 80 * different part of the MUX register. 81 */ 82 for (i = 0; i < ahub->soc_data->reg_count; i++) { 83 update[i].reg = e->reg + (TEGRA210_XBAR_PART1_RX * i); 84 update[i].val = (i == reg_idx) ? reg_val : 0; 85 update[i].mask = ahub->soc_data->mask[i]; 86 update[i].kcontrol = kctl; 87 88 /* Update widget power if state has changed */ 89 if (snd_soc_component_test_bits(cmpnt, update[i].reg, 90 update[i].mask, 91 update[i].val)) 92 change |= snd_soc_dapm_mux_update_power(dapm, kctl, 93 item[0], e, 94 &update[i]); 95 } 96 97 return change; 98 } 99 100 static struct snd_soc_dai_driver tegra210_ahub_dais[] = { 101 DAI(ADMAIF1), 102 DAI(ADMAIF2), 103 DAI(ADMAIF3), 104 DAI(ADMAIF4), 105 DAI(ADMAIF5), 106 DAI(ADMAIF6), 107 DAI(ADMAIF7), 108 DAI(ADMAIF8), 109 DAI(ADMAIF9), 110 DAI(ADMAIF10), 111 /* XBAR <-> I2S <-> Codec */ 112 DAI(I2S1), 113 DAI(I2S2), 114 DAI(I2S3), 115 DAI(I2S4), 116 DAI(I2S5), 117 /* XBAR <- DMIC <- Codec */ 118 DAI(DMIC1), 119 DAI(DMIC2), 120 DAI(DMIC3), 121 /* XBAR -> SFC -> XBAR */ 122 DAI(SFC1 RX), 123 DAI(SFC1 TX), 124 DAI(SFC2 RX), 125 DAI(SFC2 TX), 126 DAI(SFC3 RX), 127 DAI(SFC3 TX), 128 DAI(SFC4 RX), 129 DAI(SFC4 TX), 130 /* XBAR -> MVC -> XBAR */ 131 DAI(MVC1 RX), 132 DAI(MVC1 TX), 133 DAI(MVC2 RX), 134 DAI(MVC2 TX), 135 /* XBAR -> AMX(4:1) -> XBAR */ 136 DAI(AMX1 RX1), 137 DAI(AMX1 RX2), 138 DAI(AMX1 RX3), 139 DAI(AMX1 RX4), 140 DAI(AMX1), 141 DAI(AMX2 RX1), 142 DAI(AMX2 RX2), 143 DAI(AMX2 RX3), 144 DAI(AMX2 RX4), 145 DAI(AMX2), 146 /* XBAR -> ADX(1:4) -> XBAR */ 147 DAI(ADX1), 148 DAI(ADX1 TX1), 149 DAI(ADX1 TX2), 150 DAI(ADX1 TX3), 151 DAI(ADX1 TX4), 152 DAI(ADX2), 153 DAI(ADX2 TX1), 154 DAI(ADX2 TX2), 155 DAI(ADX2 TX3), 156 DAI(ADX2 TX4), 157 /* XBAR -> MIXER(10:5) -> XBAR */ 158 DAI(MIXER1 RX1), 159 DAI(MIXER1 RX2), 160 DAI(MIXER1 RX3), 161 DAI(MIXER1 RX4), 162 DAI(MIXER1 RX5), 163 DAI(MIXER1 RX6), 164 DAI(MIXER1 RX7), 165 DAI(MIXER1 RX8), 166 DAI(MIXER1 RX9), 167 DAI(MIXER1 RX10), 168 DAI(MIXER1 TX1), 169 DAI(MIXER1 TX2), 170 DAI(MIXER1 TX3), 171 DAI(MIXER1 TX4), 172 DAI(MIXER1 TX5), 173 }; 174 175 static struct snd_soc_dai_driver tegra186_ahub_dais[] = { 176 DAI(ADMAIF1), 177 DAI(ADMAIF2), 178 DAI(ADMAIF3), 179 DAI(ADMAIF4), 180 DAI(ADMAIF5), 181 DAI(ADMAIF6), 182 DAI(ADMAIF7), 183 DAI(ADMAIF8), 184 DAI(ADMAIF9), 185 DAI(ADMAIF10), 186 DAI(ADMAIF11), 187 DAI(ADMAIF12), 188 DAI(ADMAIF13), 189 DAI(ADMAIF14), 190 DAI(ADMAIF15), 191 DAI(ADMAIF16), 192 DAI(ADMAIF17), 193 DAI(ADMAIF18), 194 DAI(ADMAIF19), 195 DAI(ADMAIF20), 196 /* XBAR <-> I2S <-> Codec */ 197 DAI(I2S1), 198 DAI(I2S2), 199 DAI(I2S3), 200 DAI(I2S4), 201 DAI(I2S5), 202 DAI(I2S6), 203 /* XBAR <- DMIC <- Codec */ 204 DAI(DMIC1), 205 DAI(DMIC2), 206 DAI(DMIC3), 207 DAI(DMIC4), 208 /* XBAR -> DSPK -> Codec */ 209 DAI(DSPK1), 210 DAI(DSPK2), 211 /* XBAR -> SFC -> XBAR */ 212 DAI(SFC1 RX), 213 DAI(SFC1 TX), 214 DAI(SFC2 RX), 215 DAI(SFC2 TX), 216 DAI(SFC3 RX), 217 DAI(SFC3 TX), 218 DAI(SFC4 RX), 219 DAI(SFC4 TX), 220 /* XBAR -> MVC -> XBAR */ 221 DAI(MVC1 RX), 222 DAI(MVC1 TX), 223 DAI(MVC2 RX), 224 DAI(MVC2 TX), 225 /* XBAR -> AMX(4:1) -> XBAR */ 226 DAI(AMX1 RX1), 227 DAI(AMX1 RX2), 228 DAI(AMX1 RX3), 229 DAI(AMX1 RX4), 230 DAI(AMX1), 231 DAI(AMX2 RX1), 232 DAI(AMX2 RX2), 233 DAI(AMX2 RX3), 234 DAI(AMX2 RX4), 235 DAI(AMX2), 236 DAI(AMX3 RX1), 237 DAI(AMX3 RX2), 238 DAI(AMX3 RX3), 239 DAI(AMX3 RX4), 240 DAI(AMX3), 241 DAI(AMX4 RX1), 242 DAI(AMX4 RX2), 243 DAI(AMX4 RX3), 244 DAI(AMX4 RX4), 245 DAI(AMX4), 246 /* XBAR -> ADX(1:4) -> XBAR */ 247 DAI(ADX1), 248 DAI(ADX1 TX1), 249 DAI(ADX1 TX2), 250 DAI(ADX1 TX3), 251 DAI(ADX1 TX4), 252 DAI(ADX2), 253 DAI(ADX2 TX1), 254 DAI(ADX2 TX2), 255 DAI(ADX2 TX3), 256 DAI(ADX2 TX4), 257 DAI(ADX3), 258 DAI(ADX3 TX1), 259 DAI(ADX3 TX2), 260 DAI(ADX3 TX3), 261 DAI(ADX3 TX4), 262 DAI(ADX4), 263 DAI(ADX4 TX1), 264 DAI(ADX4 TX2), 265 DAI(ADX4 TX3), 266 DAI(ADX4 TX4), 267 /* XBAR -> MIXER1(10:5) -> XBAR */ 268 DAI(MIXER1 RX1), 269 DAI(MIXER1 RX2), 270 DAI(MIXER1 RX3), 271 DAI(MIXER1 RX4), 272 DAI(MIXER1 RX5), 273 DAI(MIXER1 RX6), 274 DAI(MIXER1 RX7), 275 DAI(MIXER1 RX8), 276 DAI(MIXER1 RX9), 277 DAI(MIXER1 RX10), 278 DAI(MIXER1 TX1), 279 DAI(MIXER1 TX2), 280 DAI(MIXER1 TX3), 281 DAI(MIXER1 TX4), 282 DAI(MIXER1 TX5), 283 }; 284 285 static const char * const tegra210_ahub_mux_texts[] = { 286 "None", 287 "ADMAIF1", 288 "ADMAIF2", 289 "ADMAIF3", 290 "ADMAIF4", 291 "ADMAIF5", 292 "ADMAIF6", 293 "ADMAIF7", 294 "ADMAIF8", 295 "ADMAIF9", 296 "ADMAIF10", 297 "I2S1", 298 "I2S2", 299 "I2S3", 300 "I2S4", 301 "I2S5", 302 "DMIC1", 303 "DMIC2", 304 "DMIC3", 305 "SFC1", 306 "SFC2", 307 "SFC3", 308 "SFC4", 309 "MVC1", 310 "MVC2", 311 "AMX1", 312 "AMX2", 313 "ADX1 TX1", 314 "ADX1 TX2", 315 "ADX1 TX3", 316 "ADX1 TX4", 317 "ADX2 TX1", 318 "ADX2 TX2", 319 "ADX2 TX3", 320 "ADX2 TX4", 321 "MIXER1 TX1", 322 "MIXER1 TX2", 323 "MIXER1 TX3", 324 "MIXER1 TX4", 325 "MIXER1 TX5", 326 }; 327 328 static const char * const tegra186_ahub_mux_texts[] = { 329 "None", 330 "ADMAIF1", 331 "ADMAIF2", 332 "ADMAIF3", 333 "ADMAIF4", 334 "ADMAIF5", 335 "ADMAIF6", 336 "ADMAIF7", 337 "ADMAIF8", 338 "ADMAIF9", 339 "ADMAIF10", 340 "ADMAIF11", 341 "ADMAIF12", 342 "ADMAIF13", 343 "ADMAIF14", 344 "ADMAIF15", 345 "ADMAIF16", 346 "I2S1", 347 "I2S2", 348 "I2S3", 349 "I2S4", 350 "I2S5", 351 "I2S6", 352 "ADMAIF17", 353 "ADMAIF18", 354 "ADMAIF19", 355 "ADMAIF20", 356 "DMIC1", 357 "DMIC2", 358 "DMIC3", 359 "DMIC4", 360 "SFC1", 361 "SFC2", 362 "SFC3", 363 "SFC4", 364 "MVC1", 365 "MVC2", 366 "AMX1", 367 "AMX2", 368 "AMX3", 369 "AMX4", 370 "ADX1 TX1", 371 "ADX1 TX2", 372 "ADX1 TX3", 373 "ADX1 TX4", 374 "ADX2 TX1", 375 "ADX2 TX2", 376 "ADX2 TX3", 377 "ADX2 TX4", 378 "ADX3 TX1", 379 "ADX3 TX2", 380 "ADX3 TX3", 381 "ADX3 TX4", 382 "ADX4 TX1", 383 "ADX4 TX2", 384 "ADX4 TX3", 385 "ADX4 TX4", 386 "MIXER1 TX1", 387 "MIXER1 TX2", 388 "MIXER1 TX3", 389 "MIXER1 TX4", 390 "MIXER1 TX5", 391 }; 392 393 static const unsigned int tegra210_ahub_mux_values[] = { 394 0, 395 /* ADMAIF */ 396 MUX_VALUE(0, 0), 397 MUX_VALUE(0, 1), 398 MUX_VALUE(0, 2), 399 MUX_VALUE(0, 3), 400 MUX_VALUE(0, 4), 401 MUX_VALUE(0, 5), 402 MUX_VALUE(0, 6), 403 MUX_VALUE(0, 7), 404 MUX_VALUE(0, 8), 405 MUX_VALUE(0, 9), 406 /* I2S */ 407 MUX_VALUE(0, 16), 408 MUX_VALUE(0, 17), 409 MUX_VALUE(0, 18), 410 MUX_VALUE(0, 19), 411 MUX_VALUE(0, 20), 412 /* DMIC */ 413 MUX_VALUE(2, 18), 414 MUX_VALUE(2, 19), 415 MUX_VALUE(2, 20), 416 /* SFC */ 417 MUX_VALUE(0, 24), 418 MUX_VALUE(0, 25), 419 MUX_VALUE(0, 26), 420 MUX_VALUE(0, 27), 421 /* MVC */ 422 MUX_VALUE(2, 8), 423 MUX_VALUE(2, 9), 424 /* AMX */ 425 MUX_VALUE(1, 8), 426 MUX_VALUE(1, 9), 427 /* ADX */ 428 MUX_VALUE(2, 24), 429 MUX_VALUE(2, 25), 430 MUX_VALUE(2, 26), 431 MUX_VALUE(2, 27), 432 MUX_VALUE(2, 28), 433 MUX_VALUE(2, 29), 434 MUX_VALUE(2, 30), 435 MUX_VALUE(2, 31), 436 /* MIXER */ 437 MUX_VALUE(1, 0), 438 MUX_VALUE(1, 1), 439 MUX_VALUE(1, 2), 440 MUX_VALUE(1, 3), 441 MUX_VALUE(1, 4), 442 }; 443 444 static const unsigned int tegra186_ahub_mux_values[] = { 445 0, 446 /* ADMAIF */ 447 MUX_VALUE(0, 0), 448 MUX_VALUE(0, 1), 449 MUX_VALUE(0, 2), 450 MUX_VALUE(0, 3), 451 MUX_VALUE(0, 4), 452 MUX_VALUE(0, 5), 453 MUX_VALUE(0, 6), 454 MUX_VALUE(0, 7), 455 MUX_VALUE(0, 8), 456 MUX_VALUE(0, 9), 457 MUX_VALUE(0, 10), 458 MUX_VALUE(0, 11), 459 MUX_VALUE(0, 12), 460 MUX_VALUE(0, 13), 461 MUX_VALUE(0, 14), 462 MUX_VALUE(0, 15), 463 /* I2S */ 464 MUX_VALUE(0, 16), 465 MUX_VALUE(0, 17), 466 MUX_VALUE(0, 18), 467 MUX_VALUE(0, 19), 468 MUX_VALUE(0, 20), 469 MUX_VALUE(0, 21), 470 /* ADMAIF */ 471 MUX_VALUE(3, 16), 472 MUX_VALUE(3, 17), 473 MUX_VALUE(3, 18), 474 MUX_VALUE(3, 19), 475 /* DMIC */ 476 MUX_VALUE(2, 18), 477 MUX_VALUE(2, 19), 478 MUX_VALUE(2, 20), 479 MUX_VALUE(2, 21), 480 /* SFC */ 481 MUX_VALUE(0, 24), 482 MUX_VALUE(0, 25), 483 MUX_VALUE(0, 26), 484 MUX_VALUE(0, 27), 485 /* MVC */ 486 MUX_VALUE(2, 8), 487 MUX_VALUE(2, 9), 488 /* AMX */ 489 MUX_VALUE(1, 8), 490 MUX_VALUE(1, 9), 491 MUX_VALUE(1, 10), 492 MUX_VALUE(1, 11), 493 /* ADX */ 494 MUX_VALUE(2, 24), 495 MUX_VALUE(2, 25), 496 MUX_VALUE(2, 26), 497 MUX_VALUE(2, 27), 498 MUX_VALUE(2, 28), 499 MUX_VALUE(2, 29), 500 MUX_VALUE(2, 30), 501 MUX_VALUE(2, 31), 502 MUX_VALUE(3, 0), 503 MUX_VALUE(3, 1), 504 MUX_VALUE(3, 2), 505 MUX_VALUE(3, 3), 506 MUX_VALUE(3, 4), 507 MUX_VALUE(3, 5), 508 MUX_VALUE(3, 6), 509 MUX_VALUE(3, 7), 510 /* MIXER */ 511 MUX_VALUE(1, 0), 512 MUX_VALUE(1, 1), 513 MUX_VALUE(1, 2), 514 MUX_VALUE(1, 3), 515 MUX_VALUE(1, 4), 516 }; 517 518 /* Controls for t210 */ 519 MUX_ENUM_CTRL_DECL(t210_admaif1_tx, 0x00); 520 MUX_ENUM_CTRL_DECL(t210_admaif2_tx, 0x01); 521 MUX_ENUM_CTRL_DECL(t210_admaif3_tx, 0x02); 522 MUX_ENUM_CTRL_DECL(t210_admaif4_tx, 0x03); 523 MUX_ENUM_CTRL_DECL(t210_admaif5_tx, 0x04); 524 MUX_ENUM_CTRL_DECL(t210_admaif6_tx, 0x05); 525 MUX_ENUM_CTRL_DECL(t210_admaif7_tx, 0x06); 526 MUX_ENUM_CTRL_DECL(t210_admaif8_tx, 0x07); 527 MUX_ENUM_CTRL_DECL(t210_admaif9_tx, 0x08); 528 MUX_ENUM_CTRL_DECL(t210_admaif10_tx, 0x09); 529 MUX_ENUM_CTRL_DECL(t210_i2s1_tx, 0x10); 530 MUX_ENUM_CTRL_DECL(t210_i2s2_tx, 0x11); 531 MUX_ENUM_CTRL_DECL(t210_i2s3_tx, 0x12); 532 MUX_ENUM_CTRL_DECL(t210_i2s4_tx, 0x13); 533 MUX_ENUM_CTRL_DECL(t210_i2s5_tx, 0x14); 534 MUX_ENUM_CTRL_DECL(t210_sfc1_tx, 0x18); 535 MUX_ENUM_CTRL_DECL(t210_sfc2_tx, 0x19); 536 MUX_ENUM_CTRL_DECL(t210_sfc3_tx, 0x1a); 537 MUX_ENUM_CTRL_DECL(t210_sfc4_tx, 0x1b); 538 MUX_ENUM_CTRL_DECL(t210_mvc1_tx, 0x48); 539 MUX_ENUM_CTRL_DECL(t210_mvc2_tx, 0x49); 540 MUX_ENUM_CTRL_DECL(t210_amx11_tx, 0x50); 541 MUX_ENUM_CTRL_DECL(t210_amx12_tx, 0x51); 542 MUX_ENUM_CTRL_DECL(t210_amx13_tx, 0x52); 543 MUX_ENUM_CTRL_DECL(t210_amx14_tx, 0x53); 544 MUX_ENUM_CTRL_DECL(t210_amx21_tx, 0x54); 545 MUX_ENUM_CTRL_DECL(t210_amx22_tx, 0x55); 546 MUX_ENUM_CTRL_DECL(t210_amx23_tx, 0x56); 547 MUX_ENUM_CTRL_DECL(t210_amx24_tx, 0x57); 548 MUX_ENUM_CTRL_DECL(t210_adx1_tx, 0x58); 549 MUX_ENUM_CTRL_DECL(t210_adx2_tx, 0x59); 550 MUX_ENUM_CTRL_DECL(t210_mixer11_tx, 0x20); 551 MUX_ENUM_CTRL_DECL(t210_mixer12_tx, 0x21); 552 MUX_ENUM_CTRL_DECL(t210_mixer13_tx, 0x22); 553 MUX_ENUM_CTRL_DECL(t210_mixer14_tx, 0x23); 554 MUX_ENUM_CTRL_DECL(t210_mixer15_tx, 0x24); 555 MUX_ENUM_CTRL_DECL(t210_mixer16_tx, 0x25); 556 MUX_ENUM_CTRL_DECL(t210_mixer17_tx, 0x26); 557 MUX_ENUM_CTRL_DECL(t210_mixer18_tx, 0x27); 558 MUX_ENUM_CTRL_DECL(t210_mixer19_tx, 0x28); 559 MUX_ENUM_CTRL_DECL(t210_mixer110_tx, 0x29); 560 561 /* Controls for t186 */ 562 MUX_ENUM_CTRL_DECL_186(t186_admaif1_tx, 0x00); 563 MUX_ENUM_CTRL_DECL_186(t186_admaif2_tx, 0x01); 564 MUX_ENUM_CTRL_DECL_186(t186_admaif3_tx, 0x02); 565 MUX_ENUM_CTRL_DECL_186(t186_admaif4_tx, 0x03); 566 MUX_ENUM_CTRL_DECL_186(t186_admaif5_tx, 0x04); 567 MUX_ENUM_CTRL_DECL_186(t186_admaif6_tx, 0x05); 568 MUX_ENUM_CTRL_DECL_186(t186_admaif7_tx, 0x06); 569 MUX_ENUM_CTRL_DECL_186(t186_admaif8_tx, 0x07); 570 MUX_ENUM_CTRL_DECL_186(t186_admaif9_tx, 0x08); 571 MUX_ENUM_CTRL_DECL_186(t186_admaif10_tx, 0x09); 572 MUX_ENUM_CTRL_DECL_186(t186_i2s1_tx, 0x10); 573 MUX_ENUM_CTRL_DECL_186(t186_i2s2_tx, 0x11); 574 MUX_ENUM_CTRL_DECL_186(t186_i2s3_tx, 0x12); 575 MUX_ENUM_CTRL_DECL_186(t186_i2s4_tx, 0x13); 576 MUX_ENUM_CTRL_DECL_186(t186_i2s5_tx, 0x14); 577 MUX_ENUM_CTRL_DECL_186(t186_admaif11_tx, 0x0a); 578 MUX_ENUM_CTRL_DECL_186(t186_admaif12_tx, 0x0b); 579 MUX_ENUM_CTRL_DECL_186(t186_admaif13_tx, 0x0c); 580 MUX_ENUM_CTRL_DECL_186(t186_admaif14_tx, 0x0d); 581 MUX_ENUM_CTRL_DECL_186(t186_admaif15_tx, 0x0e); 582 MUX_ENUM_CTRL_DECL_186(t186_admaif16_tx, 0x0f); 583 MUX_ENUM_CTRL_DECL_186(t186_i2s6_tx, 0x15); 584 MUX_ENUM_CTRL_DECL_186(t186_dspk1_tx, 0x30); 585 MUX_ENUM_CTRL_DECL_186(t186_dspk2_tx, 0x31); 586 MUX_ENUM_CTRL_DECL_186(t186_admaif17_tx, 0x68); 587 MUX_ENUM_CTRL_DECL_186(t186_admaif18_tx, 0x69); 588 MUX_ENUM_CTRL_DECL_186(t186_admaif19_tx, 0x6a); 589 MUX_ENUM_CTRL_DECL_186(t186_admaif20_tx, 0x6b); 590 MUX_ENUM_CTRL_DECL_186(t186_sfc1_tx, 0x18); 591 MUX_ENUM_CTRL_DECL_186(t186_sfc2_tx, 0x19); 592 MUX_ENUM_CTRL_DECL_186(t186_sfc3_tx, 0x1a); 593 MUX_ENUM_CTRL_DECL_186(t186_sfc4_tx, 0x1b); 594 MUX_ENUM_CTRL_DECL_186(t186_mvc1_tx, 0x48); 595 MUX_ENUM_CTRL_DECL_186(t186_mvc2_tx, 0x49); 596 MUX_ENUM_CTRL_DECL_186(t186_amx11_tx, 0x50); 597 MUX_ENUM_CTRL_DECL_186(t186_amx12_tx, 0x51); 598 MUX_ENUM_CTRL_DECL_186(t186_amx13_tx, 0x52); 599 MUX_ENUM_CTRL_DECL_186(t186_amx14_tx, 0x53); 600 MUX_ENUM_CTRL_DECL_186(t186_amx21_tx, 0x54); 601 MUX_ENUM_CTRL_DECL_186(t186_amx22_tx, 0x55); 602 MUX_ENUM_CTRL_DECL_186(t186_amx23_tx, 0x56); 603 MUX_ENUM_CTRL_DECL_186(t186_amx24_tx, 0x57); 604 MUX_ENUM_CTRL_DECL_186(t186_amx31_tx, 0x58); 605 MUX_ENUM_CTRL_DECL_186(t186_amx32_tx, 0x59); 606 MUX_ENUM_CTRL_DECL_186(t186_amx33_tx, 0x5a); 607 MUX_ENUM_CTRL_DECL_186(t186_amx34_tx, 0x5b); 608 MUX_ENUM_CTRL_DECL_186(t186_amx41_tx, 0x64); 609 MUX_ENUM_CTRL_DECL_186(t186_amx42_tx, 0x65); 610 MUX_ENUM_CTRL_DECL_186(t186_amx43_tx, 0x66); 611 MUX_ENUM_CTRL_DECL_186(t186_amx44_tx, 0x67); 612 MUX_ENUM_CTRL_DECL_186(t186_adx1_tx, 0x60); 613 MUX_ENUM_CTRL_DECL_186(t186_adx2_tx, 0x61); 614 MUX_ENUM_CTRL_DECL_186(t186_adx3_tx, 0x62); 615 MUX_ENUM_CTRL_DECL_186(t186_adx4_tx, 0x63); 616 MUX_ENUM_CTRL_DECL_186(t186_mixer11_tx, 0x20); 617 MUX_ENUM_CTRL_DECL_186(t186_mixer12_tx, 0x21); 618 MUX_ENUM_CTRL_DECL_186(t186_mixer13_tx, 0x22); 619 MUX_ENUM_CTRL_DECL_186(t186_mixer14_tx, 0x23); 620 MUX_ENUM_CTRL_DECL_186(t186_mixer15_tx, 0x24); 621 MUX_ENUM_CTRL_DECL_186(t186_mixer16_tx, 0x25); 622 MUX_ENUM_CTRL_DECL_186(t186_mixer17_tx, 0x26); 623 MUX_ENUM_CTRL_DECL_186(t186_mixer18_tx, 0x27); 624 MUX_ENUM_CTRL_DECL_186(t186_mixer19_tx, 0x28); 625 MUX_ENUM_CTRL_DECL_186(t186_mixer110_tx, 0x29); 626 627 /* Controls for t234 */ 628 MUX_ENUM_CTRL_DECL_234(t234_mvc1_tx, 0x44); 629 MUX_ENUM_CTRL_DECL_234(t234_mvc2_tx, 0x45); 630 MUX_ENUM_CTRL_DECL_234(t234_amx11_tx, 0x48); 631 MUX_ENUM_CTRL_DECL_234(t234_amx12_tx, 0x49); 632 MUX_ENUM_CTRL_DECL_234(t234_amx13_tx, 0x4a); 633 MUX_ENUM_CTRL_DECL_234(t234_amx14_tx, 0x4b); 634 MUX_ENUM_CTRL_DECL_234(t234_amx21_tx, 0x4c); 635 MUX_ENUM_CTRL_DECL_234(t234_amx22_tx, 0x4d); 636 MUX_ENUM_CTRL_DECL_234(t234_amx23_tx, 0x4e); 637 MUX_ENUM_CTRL_DECL_234(t234_amx24_tx, 0x4f); 638 MUX_ENUM_CTRL_DECL_234(t234_amx31_tx, 0x50); 639 MUX_ENUM_CTRL_DECL_234(t234_amx32_tx, 0x51); 640 MUX_ENUM_CTRL_DECL_234(t234_amx33_tx, 0x52); 641 MUX_ENUM_CTRL_DECL_234(t234_amx34_tx, 0x53); 642 MUX_ENUM_CTRL_DECL_234(t234_adx1_tx, 0x58); 643 MUX_ENUM_CTRL_DECL_234(t234_adx2_tx, 0x59); 644 MUX_ENUM_CTRL_DECL_234(t234_adx3_tx, 0x5a); 645 MUX_ENUM_CTRL_DECL_234(t234_adx4_tx, 0x5b); 646 MUX_ENUM_CTRL_DECL_234(t234_amx41_tx, 0x5c); 647 MUX_ENUM_CTRL_DECL_234(t234_amx42_tx, 0x5d); 648 MUX_ENUM_CTRL_DECL_234(t234_amx43_tx, 0x5e); 649 MUX_ENUM_CTRL_DECL_234(t234_amx44_tx, 0x5f); 650 MUX_ENUM_CTRL_DECL_234(t234_admaif17_tx, 0x60); 651 MUX_ENUM_CTRL_DECL_234(t234_admaif18_tx, 0x61); 652 MUX_ENUM_CTRL_DECL_234(t234_admaif19_tx, 0x62); 653 MUX_ENUM_CTRL_DECL_234(t234_admaif20_tx, 0x63); 654 655 /* 656 * The number of entries in, and order of, this array is closely tied to the 657 * calculation of tegra210_ahub_codec.num_dapm_widgets near the end of 658 * tegra210_ahub_probe() 659 */ 660 static const struct snd_soc_dapm_widget tegra210_ahub_widgets[] = { 661 WIDGETS("ADMAIF1", t210_admaif1_tx), 662 WIDGETS("ADMAIF2", t210_admaif2_tx), 663 WIDGETS("ADMAIF3", t210_admaif3_tx), 664 WIDGETS("ADMAIF4", t210_admaif4_tx), 665 WIDGETS("ADMAIF5", t210_admaif5_tx), 666 WIDGETS("ADMAIF6", t210_admaif6_tx), 667 WIDGETS("ADMAIF7", t210_admaif7_tx), 668 WIDGETS("ADMAIF8", t210_admaif8_tx), 669 WIDGETS("ADMAIF9", t210_admaif9_tx), 670 WIDGETS("ADMAIF10", t210_admaif10_tx), 671 WIDGETS("I2S1", t210_i2s1_tx), 672 WIDGETS("I2S2", t210_i2s2_tx), 673 WIDGETS("I2S3", t210_i2s3_tx), 674 WIDGETS("I2S4", t210_i2s4_tx), 675 WIDGETS("I2S5", t210_i2s5_tx), 676 TX_WIDGETS("DMIC1"), 677 TX_WIDGETS("DMIC2"), 678 TX_WIDGETS("DMIC3"), 679 WIDGETS("SFC1", t210_sfc1_tx), 680 WIDGETS("SFC2", t210_sfc2_tx), 681 WIDGETS("SFC3", t210_sfc3_tx), 682 WIDGETS("SFC4", t210_sfc4_tx), 683 WIDGETS("MVC1", t210_mvc1_tx), 684 WIDGETS("MVC2", t210_mvc2_tx), 685 WIDGETS("AMX1 RX1", t210_amx11_tx), 686 WIDGETS("AMX1 RX2", t210_amx12_tx), 687 WIDGETS("AMX1 RX3", t210_amx13_tx), 688 WIDGETS("AMX1 RX4", t210_amx14_tx), 689 WIDGETS("AMX2 RX1", t210_amx21_tx), 690 WIDGETS("AMX2 RX2", t210_amx22_tx), 691 WIDGETS("AMX2 RX3", t210_amx23_tx), 692 WIDGETS("AMX2 RX4", t210_amx24_tx), 693 TX_WIDGETS("AMX1"), 694 TX_WIDGETS("AMX2"), 695 WIDGETS("ADX1", t210_adx1_tx), 696 WIDGETS("ADX2", t210_adx2_tx), 697 TX_WIDGETS("ADX1 TX1"), 698 TX_WIDGETS("ADX1 TX2"), 699 TX_WIDGETS("ADX1 TX3"), 700 TX_WIDGETS("ADX1 TX4"), 701 TX_WIDGETS("ADX2 TX1"), 702 TX_WIDGETS("ADX2 TX2"), 703 TX_WIDGETS("ADX2 TX3"), 704 TX_WIDGETS("ADX2 TX4"), 705 WIDGETS("MIXER1 RX1", t210_mixer11_tx), 706 WIDGETS("MIXER1 RX2", t210_mixer12_tx), 707 WIDGETS("MIXER1 RX3", t210_mixer13_tx), 708 WIDGETS("MIXER1 RX4", t210_mixer14_tx), 709 WIDGETS("MIXER1 RX5", t210_mixer15_tx), 710 WIDGETS("MIXER1 RX6", t210_mixer16_tx), 711 WIDGETS("MIXER1 RX7", t210_mixer17_tx), 712 WIDGETS("MIXER1 RX8", t210_mixer18_tx), 713 WIDGETS("MIXER1 RX9", t210_mixer19_tx), 714 WIDGETS("MIXER1 RX10", t210_mixer110_tx), 715 TX_WIDGETS("MIXER1 TX1"), 716 TX_WIDGETS("MIXER1 TX2"), 717 TX_WIDGETS("MIXER1 TX3"), 718 TX_WIDGETS("MIXER1 TX4"), 719 TX_WIDGETS("MIXER1 TX5"), 720 }; 721 722 static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = { 723 WIDGETS("ADMAIF1", t186_admaif1_tx), 724 WIDGETS("ADMAIF2", t186_admaif2_tx), 725 WIDGETS("ADMAIF3", t186_admaif3_tx), 726 WIDGETS("ADMAIF4", t186_admaif4_tx), 727 WIDGETS("ADMAIF5", t186_admaif5_tx), 728 WIDGETS("ADMAIF6", t186_admaif6_tx), 729 WIDGETS("ADMAIF7", t186_admaif7_tx), 730 WIDGETS("ADMAIF8", t186_admaif8_tx), 731 WIDGETS("ADMAIF9", t186_admaif9_tx), 732 WIDGETS("ADMAIF10", t186_admaif10_tx), 733 WIDGETS("ADMAIF11", t186_admaif11_tx), 734 WIDGETS("ADMAIF12", t186_admaif12_tx), 735 WIDGETS("ADMAIF13", t186_admaif13_tx), 736 WIDGETS("ADMAIF14", t186_admaif14_tx), 737 WIDGETS("ADMAIF15", t186_admaif15_tx), 738 WIDGETS("ADMAIF16", t186_admaif16_tx), 739 WIDGETS("ADMAIF17", t186_admaif17_tx), 740 WIDGETS("ADMAIF18", t186_admaif18_tx), 741 WIDGETS("ADMAIF19", t186_admaif19_tx), 742 WIDGETS("ADMAIF20", t186_admaif20_tx), 743 WIDGETS("I2S1", t186_i2s1_tx), 744 WIDGETS("I2S2", t186_i2s2_tx), 745 WIDGETS("I2S3", t186_i2s3_tx), 746 WIDGETS("I2S4", t186_i2s4_tx), 747 WIDGETS("I2S5", t186_i2s5_tx), 748 WIDGETS("I2S6", t186_i2s6_tx), 749 TX_WIDGETS("DMIC1"), 750 TX_WIDGETS("DMIC2"), 751 TX_WIDGETS("DMIC3"), 752 TX_WIDGETS("DMIC4"), 753 WIDGETS("DSPK1", t186_dspk1_tx), 754 WIDGETS("DSPK2", t186_dspk2_tx), 755 WIDGETS("SFC1", t186_sfc1_tx), 756 WIDGETS("SFC2", t186_sfc2_tx), 757 WIDGETS("SFC3", t186_sfc3_tx), 758 WIDGETS("SFC4", t186_sfc4_tx), 759 WIDGETS("MVC1", t186_mvc1_tx), 760 WIDGETS("MVC2", t186_mvc2_tx), 761 WIDGETS("AMX1 RX1", t186_amx11_tx), 762 WIDGETS("AMX1 RX2", t186_amx12_tx), 763 WIDGETS("AMX1 RX3", t186_amx13_tx), 764 WIDGETS("AMX1 RX4", t186_amx14_tx), 765 WIDGETS("AMX2 RX1", t186_amx21_tx), 766 WIDGETS("AMX2 RX2", t186_amx22_tx), 767 WIDGETS("AMX2 RX3", t186_amx23_tx), 768 WIDGETS("AMX2 RX4", t186_amx24_tx), 769 WIDGETS("AMX3 RX1", t186_amx31_tx), 770 WIDGETS("AMX3 RX2", t186_amx32_tx), 771 WIDGETS("AMX3 RX3", t186_amx33_tx), 772 WIDGETS("AMX3 RX4", t186_amx34_tx), 773 WIDGETS("AMX4 RX1", t186_amx41_tx), 774 WIDGETS("AMX4 RX2", t186_amx42_tx), 775 WIDGETS("AMX4 RX3", t186_amx43_tx), 776 WIDGETS("AMX4 RX4", t186_amx44_tx), 777 TX_WIDGETS("AMX1"), 778 TX_WIDGETS("AMX2"), 779 TX_WIDGETS("AMX3"), 780 TX_WIDGETS("AMX4"), 781 WIDGETS("ADX1", t186_adx1_tx), 782 WIDGETS("ADX2", t186_adx2_tx), 783 WIDGETS("ADX3", t186_adx3_tx), 784 WIDGETS("ADX4", t186_adx4_tx), 785 TX_WIDGETS("ADX1 TX1"), 786 TX_WIDGETS("ADX1 TX2"), 787 TX_WIDGETS("ADX1 TX3"), 788 TX_WIDGETS("ADX1 TX4"), 789 TX_WIDGETS("ADX2 TX1"), 790 TX_WIDGETS("ADX2 TX2"), 791 TX_WIDGETS("ADX2 TX3"), 792 TX_WIDGETS("ADX2 TX4"), 793 TX_WIDGETS("ADX3 TX1"), 794 TX_WIDGETS("ADX3 TX2"), 795 TX_WIDGETS("ADX3 TX3"), 796 TX_WIDGETS("ADX3 TX4"), 797 TX_WIDGETS("ADX4 TX1"), 798 TX_WIDGETS("ADX4 TX2"), 799 TX_WIDGETS("ADX4 TX3"), 800 TX_WIDGETS("ADX4 TX4"), 801 WIDGETS("MIXER1 RX1", t186_mixer11_tx), 802 WIDGETS("MIXER1 RX2", t186_mixer12_tx), 803 WIDGETS("MIXER1 RX3", t186_mixer13_tx), 804 WIDGETS("MIXER1 RX4", t186_mixer14_tx), 805 WIDGETS("MIXER1 RX5", t186_mixer15_tx), 806 WIDGETS("MIXER1 RX6", t186_mixer16_tx), 807 WIDGETS("MIXER1 RX7", t186_mixer17_tx), 808 WIDGETS("MIXER1 RX8", t186_mixer18_tx), 809 WIDGETS("MIXER1 RX9", t186_mixer19_tx), 810 WIDGETS("MIXER1 RX10", t186_mixer110_tx), 811 TX_WIDGETS("MIXER1 TX1"), 812 TX_WIDGETS("MIXER1 TX2"), 813 TX_WIDGETS("MIXER1 TX3"), 814 TX_WIDGETS("MIXER1 TX4"), 815 TX_WIDGETS("MIXER1 TX5"), 816 }; 817 818 static const struct snd_soc_dapm_widget tegra234_ahub_widgets[] = { 819 WIDGETS("ADMAIF1", t186_admaif1_tx), 820 WIDGETS("ADMAIF2", t186_admaif2_tx), 821 WIDGETS("ADMAIF3", t186_admaif3_tx), 822 WIDGETS("ADMAIF4", t186_admaif4_tx), 823 WIDGETS("ADMAIF5", t186_admaif5_tx), 824 WIDGETS("ADMAIF6", t186_admaif6_tx), 825 WIDGETS("ADMAIF7", t186_admaif7_tx), 826 WIDGETS("ADMAIF8", t186_admaif8_tx), 827 WIDGETS("ADMAIF9", t186_admaif9_tx), 828 WIDGETS("ADMAIF10", t186_admaif10_tx), 829 WIDGETS("ADMAIF11", t186_admaif11_tx), 830 WIDGETS("ADMAIF12", t186_admaif12_tx), 831 WIDGETS("ADMAIF13", t186_admaif13_tx), 832 WIDGETS("ADMAIF14", t186_admaif14_tx), 833 WIDGETS("ADMAIF15", t186_admaif15_tx), 834 WIDGETS("ADMAIF16", t186_admaif16_tx), 835 WIDGETS("ADMAIF17", t234_admaif17_tx), 836 WIDGETS("ADMAIF18", t234_admaif18_tx), 837 WIDGETS("ADMAIF19", t234_admaif19_tx), 838 WIDGETS("ADMAIF20", t234_admaif20_tx), 839 WIDGETS("I2S1", t186_i2s1_tx), 840 WIDGETS("I2S2", t186_i2s2_tx), 841 WIDGETS("I2S3", t186_i2s3_tx), 842 WIDGETS("I2S4", t186_i2s4_tx), 843 WIDGETS("I2S5", t186_i2s5_tx), 844 WIDGETS("I2S6", t186_i2s6_tx), 845 TX_WIDGETS("DMIC1"), 846 TX_WIDGETS("DMIC2"), 847 TX_WIDGETS("DMIC3"), 848 TX_WIDGETS("DMIC4"), 849 WIDGETS("DSPK1", t186_dspk1_tx), 850 WIDGETS("DSPK2", t186_dspk2_tx), 851 WIDGETS("SFC1", t186_sfc1_tx), 852 WIDGETS("SFC2", t186_sfc2_tx), 853 WIDGETS("SFC3", t186_sfc3_tx), 854 WIDGETS("SFC4", t186_sfc4_tx), 855 WIDGETS("MVC1", t234_mvc1_tx), 856 WIDGETS("MVC2", t234_mvc2_tx), 857 WIDGETS("AMX1 RX1", t234_amx11_tx), 858 WIDGETS("AMX1 RX2", t234_amx12_tx), 859 WIDGETS("AMX1 RX3", t234_amx13_tx), 860 WIDGETS("AMX1 RX4", t234_amx14_tx), 861 WIDGETS("AMX2 RX1", t234_amx21_tx), 862 WIDGETS("AMX2 RX2", t234_amx22_tx), 863 WIDGETS("AMX2 RX3", t234_amx23_tx), 864 WIDGETS("AMX2 RX4", t234_amx24_tx), 865 WIDGETS("AMX3 RX1", t234_amx31_tx), 866 WIDGETS("AMX3 RX2", t234_amx32_tx), 867 WIDGETS("AMX3 RX3", t234_amx33_tx), 868 WIDGETS("AMX3 RX4", t234_amx34_tx), 869 WIDGETS("AMX4 RX1", t234_amx41_tx), 870 WIDGETS("AMX4 RX2", t234_amx42_tx), 871 WIDGETS("AMX4 RX3", t234_amx43_tx), 872 WIDGETS("AMX4 RX4", t234_amx44_tx), 873 TX_WIDGETS("AMX1"), 874 TX_WIDGETS("AMX2"), 875 TX_WIDGETS("AMX3"), 876 TX_WIDGETS("AMX4"), 877 WIDGETS("ADX1", t234_adx1_tx), 878 WIDGETS("ADX2", t234_adx2_tx), 879 WIDGETS("ADX3", t234_adx3_tx), 880 WIDGETS("ADX4", t234_adx4_tx), 881 TX_WIDGETS("ADX1 TX1"), 882 TX_WIDGETS("ADX1 TX2"), 883 TX_WIDGETS("ADX1 TX3"), 884 TX_WIDGETS("ADX1 TX4"), 885 TX_WIDGETS("ADX2 TX1"), 886 TX_WIDGETS("ADX2 TX2"), 887 TX_WIDGETS("ADX2 TX3"), 888 TX_WIDGETS("ADX2 TX4"), 889 TX_WIDGETS("ADX3 TX1"), 890 TX_WIDGETS("ADX3 TX2"), 891 TX_WIDGETS("ADX3 TX3"), 892 TX_WIDGETS("ADX3 TX4"), 893 TX_WIDGETS("ADX4 TX1"), 894 TX_WIDGETS("ADX4 TX2"), 895 TX_WIDGETS("ADX4 TX3"), 896 TX_WIDGETS("ADX4 TX4"), 897 WIDGETS("MIXER1 RX1", t186_mixer11_tx), 898 WIDGETS("MIXER1 RX2", t186_mixer12_tx), 899 WIDGETS("MIXER1 RX3", t186_mixer13_tx), 900 WIDGETS("MIXER1 RX4", t186_mixer14_tx), 901 WIDGETS("MIXER1 RX5", t186_mixer15_tx), 902 WIDGETS("MIXER1 RX6", t186_mixer16_tx), 903 WIDGETS("MIXER1 RX7", t186_mixer17_tx), 904 WIDGETS("MIXER1 RX8", t186_mixer18_tx), 905 WIDGETS("MIXER1 RX9", t186_mixer19_tx), 906 WIDGETS("MIXER1 RX10", t186_mixer110_tx), 907 TX_WIDGETS("MIXER1 TX1"), 908 TX_WIDGETS("MIXER1 TX2"), 909 TX_WIDGETS("MIXER1 TX3"), 910 TX_WIDGETS("MIXER1 TX4"), 911 TX_WIDGETS("MIXER1 TX5"), 912 }; 913 914 #define TEGRA_COMMON_MUX_ROUTES(name) \ 915 { name " XBAR-TX", NULL, name " Mux" }, \ 916 { name " Mux", "ADMAIF1", "ADMAIF1 XBAR-RX" }, \ 917 { name " Mux", "ADMAIF2", "ADMAIF2 XBAR-RX" }, \ 918 { name " Mux", "ADMAIF3", "ADMAIF3 XBAR-RX" }, \ 919 { name " Mux", "ADMAIF4", "ADMAIF4 XBAR-RX" }, \ 920 { name " Mux", "ADMAIF5", "ADMAIF5 XBAR-RX" }, \ 921 { name " Mux", "ADMAIF6", "ADMAIF6 XBAR-RX" }, \ 922 { name " Mux", "ADMAIF7", "ADMAIF7 XBAR-RX" }, \ 923 { name " Mux", "ADMAIF8", "ADMAIF8 XBAR-RX" }, \ 924 { name " Mux", "ADMAIF9", "ADMAIF9 XBAR-RX" }, \ 925 { name " Mux", "ADMAIF10", "ADMAIF10 XBAR-RX" }, \ 926 { name " Mux", "I2S1", "I2S1 XBAR-RX" }, \ 927 { name " Mux", "I2S2", "I2S2 XBAR-RX" }, \ 928 { name " Mux", "I2S3", "I2S3 XBAR-RX" }, \ 929 { name " Mux", "I2S4", "I2S4 XBAR-RX" }, \ 930 { name " Mux", "I2S5", "I2S5 XBAR-RX" }, \ 931 { name " Mux", "DMIC1", "DMIC1 XBAR-RX" }, \ 932 { name " Mux", "DMIC2", "DMIC2 XBAR-RX" }, \ 933 { name " Mux", "DMIC3", "DMIC3 XBAR-RX" }, \ 934 { name " Mux", "SFC1", "SFC1 XBAR-RX" }, \ 935 { name " Mux", "SFC2", "SFC2 XBAR-RX" }, \ 936 { name " Mux", "SFC3", "SFC3 XBAR-RX" }, \ 937 { name " Mux", "SFC4", "SFC4 XBAR-RX" }, \ 938 { name " Mux", "MVC1", "MVC1 XBAR-RX" }, \ 939 { name " Mux", "MVC2", "MVC2 XBAR-RX" }, \ 940 { name " Mux", "AMX1", "AMX1 XBAR-RX" }, \ 941 { name " Mux", "AMX2", "AMX2 XBAR-RX" }, \ 942 { name " Mux", "ADX1 TX1", "ADX1 TX1 XBAR-RX" }, \ 943 { name " Mux", "ADX1 TX2", "ADX1 TX2 XBAR-RX" }, \ 944 { name " Mux", "ADX1 TX3", "ADX1 TX3 XBAR-RX" }, \ 945 { name " Mux", "ADX1 TX4", "ADX1 TX4 XBAR-RX" }, \ 946 { name " Mux", "ADX2 TX1", "ADX2 TX1 XBAR-RX" }, \ 947 { name " Mux", "ADX2 TX2", "ADX2 TX2 XBAR-RX" }, \ 948 { name " Mux", "ADX2 TX3", "ADX2 TX3 XBAR-RX" }, \ 949 { name " Mux", "ADX2 TX4", "ADX2 TX4 XBAR-RX" }, \ 950 { name " Mux", "MIXER1 TX1", "MIXER1 TX1 XBAR-RX" }, \ 951 { name " Mux", "MIXER1 TX2", "MIXER1 TX2 XBAR-RX" }, \ 952 { name " Mux", "MIXER1 TX3", "MIXER1 TX3 XBAR-RX" }, \ 953 { name " Mux", "MIXER1 TX4", "MIXER1 TX4 XBAR-RX" }, \ 954 { name " Mux", "MIXER1 TX5", "MIXER1 TX5 XBAR-RX" }, 955 956 #define TEGRA186_ONLY_MUX_ROUTES(name) \ 957 { name " Mux", "ADMAIF11", "ADMAIF11 XBAR-RX" }, \ 958 { name " Mux", "ADMAIF12", "ADMAIF12 XBAR-RX" }, \ 959 { name " Mux", "ADMAIF13", "ADMAIF13 XBAR-RX" }, \ 960 { name " Mux", "ADMAIF14", "ADMAIF14 XBAR-RX" }, \ 961 { name " Mux", "ADMAIF15", "ADMAIF15 XBAR-RX" }, \ 962 { name " Mux", "ADMAIF16", "ADMAIF16 XBAR-RX" }, \ 963 { name " Mux", "ADMAIF17", "ADMAIF17 XBAR-RX" }, \ 964 { name " Mux", "ADMAIF18", "ADMAIF18 XBAR-RX" }, \ 965 { name " Mux", "ADMAIF19", "ADMAIF19 XBAR-RX" }, \ 966 { name " Mux", "ADMAIF20", "ADMAIF20 XBAR-RX" }, \ 967 { name " Mux", "I2S6", "I2S6 XBAR-RX" }, \ 968 { name " Mux", "DMIC4", "DMIC4 XBAR-RX" }, \ 969 { name " Mux", "AMX3", "AMX3 XBAR-RX" }, \ 970 { name " Mux", "AMX4", "AMX4 XBAR-RX" }, \ 971 { name " Mux", "ADX3 TX1", "ADX3 TX1 XBAR-RX" }, \ 972 { name " Mux", "ADX3 TX2", "ADX3 TX2 XBAR-RX" }, \ 973 { name " Mux", "ADX3 TX3", "ADX3 TX3 XBAR-RX" }, \ 974 { name " Mux", "ADX3 TX4", "ADX3 TX4 XBAR-RX" }, \ 975 { name " Mux", "ADX4 TX1", "ADX4 TX1 XBAR-RX" }, \ 976 { name " Mux", "ADX4 TX2", "ADX4 TX2 XBAR-RX" }, \ 977 { name " Mux", "ADX4 TX3", "ADX4 TX3 XBAR-RX" }, \ 978 { name " Mux", "ADX4 TX4", "ADX4 TX4 XBAR-RX" }, 979 980 #define TEGRA210_MUX_ROUTES(name) \ 981 TEGRA_COMMON_MUX_ROUTES(name) 982 983 #define TEGRA186_MUX_ROUTES(name) \ 984 TEGRA_COMMON_MUX_ROUTES(name) \ 985 TEGRA186_ONLY_MUX_ROUTES(name) 986 987 /* Connect FEs with XBAR */ 988 #define TEGRA_FE_ROUTES(name) \ 989 { name " XBAR-Playback", NULL, name " Playback" }, \ 990 { name " XBAR-RX", NULL, name " XBAR-Playback"}, \ 991 { name " XBAR-Capture", NULL, name " XBAR-TX" }, \ 992 { name " Capture", NULL, name " XBAR-Capture" }, 993 994 /* 995 * The number of entries in, and order of, this array is closely tied to the 996 * calculation of tegra210_ahub_codec.num_dapm_routes near the end of 997 * tegra210_ahub_probe() 998 */ 999 static const struct snd_soc_dapm_route tegra210_ahub_routes[] = { 1000 TEGRA_FE_ROUTES("ADMAIF1") 1001 TEGRA_FE_ROUTES("ADMAIF2") 1002 TEGRA_FE_ROUTES("ADMAIF3") 1003 TEGRA_FE_ROUTES("ADMAIF4") 1004 TEGRA_FE_ROUTES("ADMAIF5") 1005 TEGRA_FE_ROUTES("ADMAIF6") 1006 TEGRA_FE_ROUTES("ADMAIF7") 1007 TEGRA_FE_ROUTES("ADMAIF8") 1008 TEGRA_FE_ROUTES("ADMAIF9") 1009 TEGRA_FE_ROUTES("ADMAIF10") 1010 TEGRA210_MUX_ROUTES("ADMAIF1") 1011 TEGRA210_MUX_ROUTES("ADMAIF2") 1012 TEGRA210_MUX_ROUTES("ADMAIF3") 1013 TEGRA210_MUX_ROUTES("ADMAIF4") 1014 TEGRA210_MUX_ROUTES("ADMAIF5") 1015 TEGRA210_MUX_ROUTES("ADMAIF6") 1016 TEGRA210_MUX_ROUTES("ADMAIF7") 1017 TEGRA210_MUX_ROUTES("ADMAIF8") 1018 TEGRA210_MUX_ROUTES("ADMAIF9") 1019 TEGRA210_MUX_ROUTES("ADMAIF10") 1020 TEGRA210_MUX_ROUTES("I2S1") 1021 TEGRA210_MUX_ROUTES("I2S2") 1022 TEGRA210_MUX_ROUTES("I2S3") 1023 TEGRA210_MUX_ROUTES("I2S4") 1024 TEGRA210_MUX_ROUTES("I2S5") 1025 TEGRA210_MUX_ROUTES("SFC1") 1026 TEGRA210_MUX_ROUTES("SFC2") 1027 TEGRA210_MUX_ROUTES("SFC3") 1028 TEGRA210_MUX_ROUTES("SFC4") 1029 TEGRA210_MUX_ROUTES("MVC1") 1030 TEGRA210_MUX_ROUTES("MVC2") 1031 TEGRA210_MUX_ROUTES("AMX1 RX1") 1032 TEGRA210_MUX_ROUTES("AMX1 RX2") 1033 TEGRA210_MUX_ROUTES("AMX1 RX3") 1034 TEGRA210_MUX_ROUTES("AMX1 RX4") 1035 TEGRA210_MUX_ROUTES("AMX2 RX1") 1036 TEGRA210_MUX_ROUTES("AMX2 RX2") 1037 TEGRA210_MUX_ROUTES("AMX2 RX3") 1038 TEGRA210_MUX_ROUTES("AMX2 RX4") 1039 TEGRA210_MUX_ROUTES("ADX1") 1040 TEGRA210_MUX_ROUTES("ADX2") 1041 TEGRA210_MUX_ROUTES("MIXER1 RX1") 1042 TEGRA210_MUX_ROUTES("MIXER1 RX2") 1043 TEGRA210_MUX_ROUTES("MIXER1 RX3") 1044 TEGRA210_MUX_ROUTES("MIXER1 RX4") 1045 TEGRA210_MUX_ROUTES("MIXER1 RX5") 1046 TEGRA210_MUX_ROUTES("MIXER1 RX6") 1047 TEGRA210_MUX_ROUTES("MIXER1 RX7") 1048 TEGRA210_MUX_ROUTES("MIXER1 RX8") 1049 TEGRA210_MUX_ROUTES("MIXER1 RX9") 1050 TEGRA210_MUX_ROUTES("MIXER1 RX10") 1051 }; 1052 1053 static const struct snd_soc_dapm_route tegra186_ahub_routes[] = { 1054 TEGRA_FE_ROUTES("ADMAIF1") 1055 TEGRA_FE_ROUTES("ADMAIF2") 1056 TEGRA_FE_ROUTES("ADMAIF3") 1057 TEGRA_FE_ROUTES("ADMAIF4") 1058 TEGRA_FE_ROUTES("ADMAIF5") 1059 TEGRA_FE_ROUTES("ADMAIF6") 1060 TEGRA_FE_ROUTES("ADMAIF7") 1061 TEGRA_FE_ROUTES("ADMAIF8") 1062 TEGRA_FE_ROUTES("ADMAIF9") 1063 TEGRA_FE_ROUTES("ADMAIF10") 1064 TEGRA_FE_ROUTES("ADMAIF11") 1065 TEGRA_FE_ROUTES("ADMAIF12") 1066 TEGRA_FE_ROUTES("ADMAIF13") 1067 TEGRA_FE_ROUTES("ADMAIF14") 1068 TEGRA_FE_ROUTES("ADMAIF15") 1069 TEGRA_FE_ROUTES("ADMAIF16") 1070 TEGRA_FE_ROUTES("ADMAIF17") 1071 TEGRA_FE_ROUTES("ADMAIF18") 1072 TEGRA_FE_ROUTES("ADMAIF19") 1073 TEGRA_FE_ROUTES("ADMAIF20") 1074 TEGRA186_MUX_ROUTES("ADMAIF1") 1075 TEGRA186_MUX_ROUTES("ADMAIF2") 1076 TEGRA186_MUX_ROUTES("ADMAIF3") 1077 TEGRA186_MUX_ROUTES("ADMAIF4") 1078 TEGRA186_MUX_ROUTES("ADMAIF5") 1079 TEGRA186_MUX_ROUTES("ADMAIF6") 1080 TEGRA186_MUX_ROUTES("ADMAIF7") 1081 TEGRA186_MUX_ROUTES("ADMAIF8") 1082 TEGRA186_MUX_ROUTES("ADMAIF9") 1083 TEGRA186_MUX_ROUTES("ADMAIF10") 1084 TEGRA186_MUX_ROUTES("ADMAIF11") 1085 TEGRA186_MUX_ROUTES("ADMAIF12") 1086 TEGRA186_MUX_ROUTES("ADMAIF13") 1087 TEGRA186_MUX_ROUTES("ADMAIF14") 1088 TEGRA186_MUX_ROUTES("ADMAIF15") 1089 TEGRA186_MUX_ROUTES("ADMAIF16") 1090 TEGRA186_MUX_ROUTES("ADMAIF17") 1091 TEGRA186_MUX_ROUTES("ADMAIF18") 1092 TEGRA186_MUX_ROUTES("ADMAIF19") 1093 TEGRA186_MUX_ROUTES("ADMAIF20") 1094 TEGRA186_MUX_ROUTES("I2S1") 1095 TEGRA186_MUX_ROUTES("I2S2") 1096 TEGRA186_MUX_ROUTES("I2S3") 1097 TEGRA186_MUX_ROUTES("I2S4") 1098 TEGRA186_MUX_ROUTES("I2S5") 1099 TEGRA186_MUX_ROUTES("I2S6") 1100 TEGRA186_MUX_ROUTES("DSPK1") 1101 TEGRA186_MUX_ROUTES("DSPK2") 1102 TEGRA186_MUX_ROUTES("SFC1") 1103 TEGRA186_MUX_ROUTES("SFC2") 1104 TEGRA186_MUX_ROUTES("SFC3") 1105 TEGRA186_MUX_ROUTES("SFC4") 1106 TEGRA186_MUX_ROUTES("MVC1") 1107 TEGRA186_MUX_ROUTES("MVC2") 1108 TEGRA186_MUX_ROUTES("AMX1 RX1") 1109 TEGRA186_MUX_ROUTES("AMX1 RX2") 1110 TEGRA186_MUX_ROUTES("AMX1 RX3") 1111 TEGRA186_MUX_ROUTES("AMX1 RX4") 1112 TEGRA186_MUX_ROUTES("AMX2 RX1") 1113 TEGRA186_MUX_ROUTES("AMX2 RX2") 1114 TEGRA186_MUX_ROUTES("AMX2 RX3") 1115 TEGRA186_MUX_ROUTES("AMX2 RX4") 1116 TEGRA186_MUX_ROUTES("AMX3 RX1") 1117 TEGRA186_MUX_ROUTES("AMX3 RX2") 1118 TEGRA186_MUX_ROUTES("AMX3 RX3") 1119 TEGRA186_MUX_ROUTES("AMX3 RX4") 1120 TEGRA186_MUX_ROUTES("AMX4 RX1") 1121 TEGRA186_MUX_ROUTES("AMX4 RX2") 1122 TEGRA186_MUX_ROUTES("AMX4 RX3") 1123 TEGRA186_MUX_ROUTES("AMX4 RX4") 1124 TEGRA186_MUX_ROUTES("ADX1") 1125 TEGRA186_MUX_ROUTES("ADX2") 1126 TEGRA186_MUX_ROUTES("ADX3") 1127 TEGRA186_MUX_ROUTES("ADX4") 1128 TEGRA186_MUX_ROUTES("MIXER1 RX1") 1129 TEGRA186_MUX_ROUTES("MIXER1 RX2") 1130 TEGRA186_MUX_ROUTES("MIXER1 RX3") 1131 TEGRA186_MUX_ROUTES("MIXER1 RX4") 1132 TEGRA186_MUX_ROUTES("MIXER1 RX5") 1133 TEGRA186_MUX_ROUTES("MIXER1 RX6") 1134 TEGRA186_MUX_ROUTES("MIXER1 RX7") 1135 TEGRA186_MUX_ROUTES("MIXER1 RX8") 1136 TEGRA186_MUX_ROUTES("MIXER1 RX9") 1137 TEGRA186_MUX_ROUTES("MIXER1 RX10") 1138 }; 1139 1140 static const struct snd_soc_component_driver tegra210_ahub_component = { 1141 .dapm_widgets = tegra210_ahub_widgets, 1142 .num_dapm_widgets = ARRAY_SIZE(tegra210_ahub_widgets), 1143 .dapm_routes = tegra210_ahub_routes, 1144 .num_dapm_routes = ARRAY_SIZE(tegra210_ahub_routes), 1145 }; 1146 1147 static const struct snd_soc_component_driver tegra186_ahub_component = { 1148 .dapm_widgets = tegra186_ahub_widgets, 1149 .num_dapm_widgets = ARRAY_SIZE(tegra186_ahub_widgets), 1150 .dapm_routes = tegra186_ahub_routes, 1151 .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes), 1152 }; 1153 1154 static const struct snd_soc_component_driver tegra234_ahub_component = { 1155 .dapm_widgets = tegra234_ahub_widgets, 1156 .num_dapm_widgets = ARRAY_SIZE(tegra234_ahub_widgets), 1157 .dapm_routes = tegra186_ahub_routes, 1158 .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes), 1159 }; 1160 1161 static const struct regmap_config tegra210_ahub_regmap_config = { 1162 .reg_bits = 32, 1163 .val_bits = 32, 1164 .reg_stride = 4, 1165 .max_register = TEGRA210_MAX_REGISTER_ADDR, 1166 .cache_type = REGCACHE_FLAT, 1167 }; 1168 1169 static const struct regmap_config tegra186_ahub_regmap_config = { 1170 .reg_bits = 32, 1171 .val_bits = 32, 1172 .reg_stride = 4, 1173 .max_register = TEGRA186_MAX_REGISTER_ADDR, 1174 .cache_type = REGCACHE_FLAT, 1175 }; 1176 1177 static const struct tegra_ahub_soc_data soc_data_tegra210 = { 1178 .cmpnt_drv = &tegra210_ahub_component, 1179 .dai_drv = tegra210_ahub_dais, 1180 .num_dais = ARRAY_SIZE(tegra210_ahub_dais), 1181 .regmap_config = &tegra210_ahub_regmap_config, 1182 .mask[0] = TEGRA210_XBAR_REG_MASK_0, 1183 .mask[1] = TEGRA210_XBAR_REG_MASK_1, 1184 .mask[2] = TEGRA210_XBAR_REG_MASK_2, 1185 .mask[3] = TEGRA210_XBAR_REG_MASK_3, 1186 .reg_count = TEGRA210_XBAR_UPDATE_MAX_REG, 1187 }; 1188 1189 static const struct tegra_ahub_soc_data soc_data_tegra186 = { 1190 .cmpnt_drv = &tegra186_ahub_component, 1191 .dai_drv = tegra186_ahub_dais, 1192 .num_dais = ARRAY_SIZE(tegra186_ahub_dais), 1193 .regmap_config = &tegra186_ahub_regmap_config, 1194 .mask[0] = TEGRA186_XBAR_REG_MASK_0, 1195 .mask[1] = TEGRA186_XBAR_REG_MASK_1, 1196 .mask[2] = TEGRA186_XBAR_REG_MASK_2, 1197 .mask[3] = TEGRA186_XBAR_REG_MASK_3, 1198 .reg_count = TEGRA186_XBAR_UPDATE_MAX_REG, 1199 }; 1200 1201 static const struct tegra_ahub_soc_data soc_data_tegra234 = { 1202 .cmpnt_drv = &tegra234_ahub_component, 1203 .dai_drv = tegra186_ahub_dais, 1204 .num_dais = ARRAY_SIZE(tegra186_ahub_dais), 1205 .regmap_config = &tegra186_ahub_regmap_config, 1206 .mask[0] = TEGRA186_XBAR_REG_MASK_0, 1207 .mask[1] = TEGRA186_XBAR_REG_MASK_1, 1208 .mask[2] = TEGRA186_XBAR_REG_MASK_2, 1209 .mask[3] = TEGRA186_XBAR_REG_MASK_3, 1210 .reg_count = TEGRA186_XBAR_UPDATE_MAX_REG, 1211 }; 1212 1213 static const struct of_device_id tegra_ahub_of_match[] = { 1214 { .compatible = "nvidia,tegra210-ahub", .data = &soc_data_tegra210 }, 1215 { .compatible = "nvidia,tegra186-ahub", .data = &soc_data_tegra186 }, 1216 { .compatible = "nvidia,tegra234-ahub", .data = &soc_data_tegra234 }, 1217 {}, 1218 }; 1219 MODULE_DEVICE_TABLE(of, tegra_ahub_of_match); 1220 1221 static int __maybe_unused tegra_ahub_runtime_suspend(struct device *dev) 1222 { 1223 struct tegra_ahub *ahub = dev_get_drvdata(dev); 1224 1225 regcache_cache_only(ahub->regmap, true); 1226 regcache_mark_dirty(ahub->regmap); 1227 1228 clk_disable_unprepare(ahub->clk); 1229 1230 return 0; 1231 } 1232 1233 static int __maybe_unused tegra_ahub_runtime_resume(struct device *dev) 1234 { 1235 struct tegra_ahub *ahub = dev_get_drvdata(dev); 1236 int err; 1237 1238 err = clk_prepare_enable(ahub->clk); 1239 if (err) { 1240 dev_err(dev, "failed to enable AHUB clock, err: %d\n", err); 1241 return err; 1242 } 1243 1244 regcache_cache_only(ahub->regmap, false); 1245 regcache_sync(ahub->regmap); 1246 1247 return 0; 1248 } 1249 1250 static int tegra_ahub_probe(struct platform_device *pdev) 1251 { 1252 struct tegra_ahub *ahub; 1253 void __iomem *regs; 1254 int err; 1255 1256 ahub = devm_kzalloc(&pdev->dev, sizeof(*ahub), GFP_KERNEL); 1257 if (!ahub) 1258 return -ENOMEM; 1259 1260 ahub->soc_data = of_device_get_match_data(&pdev->dev); 1261 1262 platform_set_drvdata(pdev, ahub); 1263 1264 ahub->clk = devm_clk_get(&pdev->dev, "ahub"); 1265 if (IS_ERR(ahub->clk)) { 1266 dev_err(&pdev->dev, "can't retrieve AHUB clock\n"); 1267 return PTR_ERR(ahub->clk); 1268 } 1269 1270 regs = devm_platform_ioremap_resource(pdev, 0); 1271 if (IS_ERR(regs)) 1272 return PTR_ERR(regs); 1273 1274 ahub->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 1275 ahub->soc_data->regmap_config); 1276 if (IS_ERR(ahub->regmap)) { 1277 dev_err(&pdev->dev, "regmap init failed\n"); 1278 return PTR_ERR(ahub->regmap); 1279 } 1280 1281 regcache_cache_only(ahub->regmap, true); 1282 1283 err = devm_snd_soc_register_component(&pdev->dev, 1284 ahub->soc_data->cmpnt_drv, 1285 ahub->soc_data->dai_drv, 1286 ahub->soc_data->num_dais); 1287 if (err) { 1288 dev_err(&pdev->dev, "can't register AHUB component, err: %d\n", 1289 err); 1290 return err; 1291 } 1292 1293 err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 1294 if (err) 1295 return err; 1296 1297 pm_runtime_enable(&pdev->dev); 1298 1299 return 0; 1300 } 1301 1302 static int tegra_ahub_remove(struct platform_device *pdev) 1303 { 1304 pm_runtime_disable(&pdev->dev); 1305 1306 return 0; 1307 } 1308 1309 static const struct dev_pm_ops tegra_ahub_pm_ops = { 1310 SET_RUNTIME_PM_OPS(tegra_ahub_runtime_suspend, 1311 tegra_ahub_runtime_resume, NULL) 1312 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1313 pm_runtime_force_resume) 1314 }; 1315 1316 static struct platform_driver tegra_ahub_driver = { 1317 .probe = tegra_ahub_probe, 1318 .remove = tegra_ahub_remove, 1319 .driver = { 1320 .name = "tegra210-ahub", 1321 .of_match_table = tegra_ahub_of_match, 1322 .pm = &tegra_ahub_pm_ops, 1323 }, 1324 }; 1325 module_platform_driver(tegra_ahub_driver); 1326 1327 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 1328 MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>"); 1329 MODULE_DESCRIPTION("Tegra210 ASoC AHUB driver"); 1330 MODULE_LICENSE("GPL v2"); 1331