1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (c) 2005-2016 Advanced Micro Devices, Inc. 4 * 5 * Written by Jacob Shin - AMD, Inc. 6 * Maintained by: Borislav Petkov <bp@alien8.de> 7 * 8 * All MC4_MISCi registers are shared between cores on a node. 9 */ 10 #include <linux/interrupt.h> 11 #include <linux/notifier.h> 12 #include <linux/kobject.h> 13 #include <linux/percpu.h> 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/sysfs.h> 17 #include <linux/slab.h> 18 #include <linux/init.h> 19 #include <linux/cpu.h> 20 #include <linux/smp.h> 21 #include <linux/string.h> 22 23 #include <asm/amd_nb.h> 24 #include <asm/traps.h> 25 #include <asm/apic.h> 26 #include <asm/mce.h> 27 #include <asm/msr.h> 28 #include <asm/trace/irq_vectors.h> 29 30 #include "internal.h" 31 32 #define NR_BLOCKS 5 33 #define THRESHOLD_MAX 0xFFF 34 #define INT_TYPE_APIC 0x00020000 35 #define MASK_VALID_HI 0x80000000 36 #define MASK_CNTP_HI 0x40000000 37 #define MASK_LOCKED_HI 0x20000000 38 #define MASK_LVTOFF_HI 0x00F00000 39 #define MASK_COUNT_EN_HI 0x00080000 40 #define MASK_INT_TYPE_HI 0x00060000 41 #define MASK_OVERFLOW_HI 0x00010000 42 #define MASK_ERR_COUNT_HI 0x00000FFF 43 #define MASK_BLKPTR_LO 0xFF000000 44 #define MCG_XBLK_ADDR 0xC0000400 45 46 /* Deferred error settings */ 47 #define MSR_CU_DEF_ERR 0xC0000410 48 #define MASK_DEF_LVTOFF 0x000000F0 49 #define MASK_DEF_INT_TYPE 0x00000006 50 #define DEF_LVT_OFF 0x2 51 #define DEF_INT_TYPE_APIC 0x2 52 53 /* Scalable MCA: */ 54 55 /* Threshold LVT offset is at MSR0xC0000410[15:12] */ 56 #define SMCA_THR_LVT_OFF 0xF000 57 58 static bool thresholding_irq_en; 59 60 static const char * const th_names[] = { 61 "load_store", 62 "insn_fetch", 63 "combined_unit", 64 "decode_unit", 65 "northbridge", 66 "execution_unit", 67 }; 68 69 static const char * const smca_umc_block_names[] = { 70 "dram_ecc", 71 "misc_umc" 72 }; 73 74 #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype)) 75 76 struct smca_hwid { 77 unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */ 78 u32 hwid_mcatype; /* (hwid,mcatype) tuple */ 79 }; 80 81 struct smca_bank { 82 const struct smca_hwid *hwid; 83 u32 id; /* Value of MCA_IPID[InstanceId]. */ 84 u8 sysfs_id; /* Value used for sysfs name. */ 85 }; 86 87 static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks); 88 static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts); 89 90 struct smca_bank_name { 91 const char *name; /* Short name for sysfs */ 92 const char *long_name; /* Long name for pretty-printing */ 93 }; 94 95 static struct smca_bank_name smca_names[] = { 96 [SMCA_LS ... SMCA_LS_V2] = { "load_store", "Load Store Unit" }, 97 [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, 98 [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, 99 [SMCA_DE] = { "decode_unit", "Decode Unit" }, 100 [SMCA_RESERVED] = { "reserved", "Reserved" }, 101 [SMCA_EX] = { "execution_unit", "Execution Unit" }, 102 [SMCA_FP] = { "floating_point", "Floating Point Unit" }, 103 [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, 104 [SMCA_CS ... SMCA_CS_V2] = { "coherent_slave", "Coherent Slave" }, 105 [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, 106 107 /* UMC v2 is separate because both of them can exist in a single system. */ 108 [SMCA_UMC] = { "umc", "Unified Memory Controller" }, 109 [SMCA_UMC_V2] = { "umc_v2", "Unified Memory Controller v2" }, 110 [SMCA_PB] = { "param_block", "Parameter Block" }, 111 [SMCA_PSP ... SMCA_PSP_V2] = { "psp", "Platform Security Processor" }, 112 [SMCA_SMU ... SMCA_SMU_V2] = { "smu", "System Management Unit" }, 113 [SMCA_MP5] = { "mp5", "Microprocessor 5 Unit" }, 114 [SMCA_MPDMA] = { "mpdma", "MPDMA Unit" }, 115 [SMCA_NBIO] = { "nbio", "Northbridge IO Unit" }, 116 [SMCA_PCIE ... SMCA_PCIE_V2] = { "pcie", "PCI Express Unit" }, 117 [SMCA_XGMI_PCS] = { "xgmi_pcs", "Ext Global Memory Interconnect PCS Unit" }, 118 [SMCA_NBIF] = { "nbif", "NBIF Unit" }, 119 [SMCA_SHUB] = { "shub", "System Hub Unit" }, 120 [SMCA_SATA] = { "sata", "SATA Unit" }, 121 [SMCA_USB] = { "usb", "USB Unit" }, 122 [SMCA_GMI_PCS] = { "gmi_pcs", "Global Memory Interconnect PCS Unit" }, 123 [SMCA_XGMI_PHY] = { "xgmi_phy", "Ext Global Memory Interconnect PHY Unit" }, 124 [SMCA_WAFL_PHY] = { "wafl_phy", "WAFL PHY Unit" }, 125 [SMCA_GMI_PHY] = { "gmi_phy", "Global Memory Interconnect PHY Unit" }, 126 }; 127 128 static const char *smca_get_name(enum smca_bank_types t) 129 { 130 if (t >= N_SMCA_BANK_TYPES) 131 return NULL; 132 133 return smca_names[t].name; 134 } 135 136 const char *smca_get_long_name(enum smca_bank_types t) 137 { 138 if (t >= N_SMCA_BANK_TYPES) 139 return NULL; 140 141 return smca_names[t].long_name; 142 } 143 EXPORT_SYMBOL_GPL(smca_get_long_name); 144 145 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) 146 { 147 struct smca_bank *b; 148 149 if (bank >= MAX_NR_BANKS) 150 return N_SMCA_BANK_TYPES; 151 152 b = &per_cpu(smca_banks, cpu)[bank]; 153 if (!b->hwid) 154 return N_SMCA_BANK_TYPES; 155 156 return b->hwid->bank_type; 157 } 158 EXPORT_SYMBOL_GPL(smca_get_bank_type); 159 160 static const struct smca_hwid smca_hwid_mcatypes[] = { 161 /* { bank_type, hwid_mcatype } */ 162 163 /* Reserved type */ 164 { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) }, 165 166 /* ZN Core (HWID=0xB0) MCA types */ 167 { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) }, 168 { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) }, 169 { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) }, 170 { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) }, 171 { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) }, 172 /* HWID 0xB0 MCATYPE 0x4 is Reserved */ 173 { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) }, 174 { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) }, 175 { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) }, 176 177 /* Data Fabric MCA types */ 178 { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, 179 { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, 180 { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, 181 182 /* Unified Memory Controller MCA type */ 183 { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, 184 { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) }, 185 186 /* Parameter Block MCA type */ 187 { SMCA_PB, HWID_MCATYPE(0x05, 0x0) }, 188 189 /* Platform Security Processor MCA type */ 190 { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) }, 191 { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) }, 192 193 /* System Management Unit MCA type */ 194 { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) }, 195 { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) }, 196 197 /* Microprocessor 5 Unit MCA type */ 198 { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) }, 199 200 /* MPDMA MCA type */ 201 { SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) }, 202 203 /* Northbridge IO Unit MCA type */ 204 { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) }, 205 206 /* PCI Express Unit MCA type */ 207 { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) }, 208 { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) }, 209 210 { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) }, 211 { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) }, 212 { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) }, 213 { SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) }, 214 { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) }, 215 { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) }, 216 { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) }, 217 { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) }, 218 { SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) }, 219 }; 220 221 /* 222 * In SMCA enabled processors, we can have multiple banks for a given IP type. 223 * So to define a unique name for each bank, we use a temp c-string to append 224 * the MCA_IPID[InstanceId] to type's name in get_name(). 225 * 226 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN 227 * is greater than 8 plus 1 (for underscore) plus length of longest type name. 228 */ 229 #define MAX_MCATYPE_NAME_LEN 30 230 static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; 231 232 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); 233 234 /* 235 * A list of the banks enabled on each logical CPU. Controls which respective 236 * descriptors to initialize later in mce_threshold_create_device(). 237 */ 238 static DEFINE_PER_CPU(unsigned int, bank_map); 239 240 /* Map of banks that have more than MCA_MISC0 available. */ 241 static DEFINE_PER_CPU(u32, smca_misc_banks_map); 242 243 static void amd_threshold_interrupt(void); 244 static void amd_deferred_error_interrupt(void); 245 246 static void default_deferred_error_interrupt(void) 247 { 248 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); 249 } 250 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; 251 252 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) 253 { 254 u32 low, high; 255 256 /* 257 * For SMCA enabled processors, BLKPTR field of the first MISC register 258 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). 259 */ 260 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) 261 return; 262 263 if (!(low & MCI_CONFIG_MCAX)) 264 return; 265 266 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) 267 return; 268 269 if (low & MASK_BLKPTR_LO) 270 per_cpu(smca_misc_banks_map, cpu) |= BIT(bank); 271 272 } 273 274 static void smca_configure(unsigned int bank, unsigned int cpu) 275 { 276 u8 *bank_counts = this_cpu_ptr(smca_bank_counts); 277 const struct smca_hwid *s_hwid; 278 unsigned int i, hwid_mcatype; 279 u32 high, low; 280 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); 281 282 /* Set appropriate bits in MCA_CONFIG */ 283 if (!rdmsr_safe(smca_config, &low, &high)) { 284 /* 285 * OS is required to set the MCAX bit to acknowledge that it is 286 * now using the new MSR ranges and new registers under each 287 * bank. It also means that the OS will configure deferred 288 * errors in the new MCx_CONFIG register. If the bit is not set, 289 * uncorrectable errors will cause a system panic. 290 * 291 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) 292 */ 293 high |= BIT(0); 294 295 /* 296 * SMCA sets the Deferred Error Interrupt type per bank. 297 * 298 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us 299 * if the DeferredIntType bit field is available. 300 * 301 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the 302 * high portion of the MSR). OS should set this to 0x1 to enable 303 * APIC based interrupt. First, check that no interrupt has been 304 * set. 305 */ 306 if ((low & BIT(5)) && !((high >> 5) & 0x3)) 307 high |= BIT(5); 308 309 wrmsr(smca_config, low, high); 310 } 311 312 smca_set_misc_banks_map(bank, cpu); 313 314 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { 315 pr_warn("Failed to read MCA_IPID for bank %d\n", bank); 316 return; 317 } 318 319 hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, 320 (high & MCI_IPID_MCATYPE) >> 16); 321 322 for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { 323 s_hwid = &smca_hwid_mcatypes[i]; 324 325 if (hwid_mcatype == s_hwid->hwid_mcatype) { 326 this_cpu_ptr(smca_banks)[bank].hwid = s_hwid; 327 this_cpu_ptr(smca_banks)[bank].id = low; 328 this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++; 329 break; 330 } 331 } 332 } 333 334 struct thresh_restart { 335 struct threshold_block *b; 336 int reset; 337 int set_lvt_off; 338 int lvt_off; 339 u16 old_limit; 340 }; 341 342 static inline bool is_shared_bank(int bank) 343 { 344 /* 345 * Scalable MCA provides for only one core to have access to the MSRs of 346 * a shared bank. 347 */ 348 if (mce_flags.smca) 349 return false; 350 351 /* Bank 4 is for northbridge reporting and is thus shared */ 352 return (bank == 4); 353 } 354 355 static const char *bank4_names(const struct threshold_block *b) 356 { 357 switch (b->address) { 358 /* MSR4_MISC0 */ 359 case 0x00000413: 360 return "dram"; 361 362 case 0xc0000408: 363 return "ht_links"; 364 365 case 0xc0000409: 366 return "l3_cache"; 367 368 default: 369 WARN(1, "Funny MSR: 0x%08x\n", b->address); 370 return ""; 371 } 372 }; 373 374 375 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) 376 { 377 /* 378 * bank 4 supports APIC LVT interrupts implicitly since forever. 379 */ 380 if (bank == 4) 381 return true; 382 383 /* 384 * IntP: interrupt present; if this bit is set, the thresholding 385 * bank can generate APIC LVT interrupts 386 */ 387 return msr_high_bits & BIT(28); 388 } 389 390 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) 391 { 392 int msr = (hi & MASK_LVTOFF_HI) >> 20; 393 394 if (apic < 0) { 395 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " 396 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, 397 b->bank, b->block, b->address, hi, lo); 398 return 0; 399 } 400 401 if (apic != msr) { 402 /* 403 * On SMCA CPUs, LVT offset is programmed at a different MSR, and 404 * the BIOS provides the value. The original field where LVT offset 405 * was set is reserved. Return early here: 406 */ 407 if (mce_flags.smca) 408 return 0; 409 410 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " 411 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", 412 b->cpu, apic, b->bank, b->block, b->address, hi, lo); 413 return 0; 414 } 415 416 return 1; 417 }; 418 419 /* Reprogram MCx_MISC MSR behind this threshold bank. */ 420 static void threshold_restart_bank(void *_tr) 421 { 422 struct thresh_restart *tr = _tr; 423 u32 hi, lo; 424 425 /* sysfs write might race against an offline operation */ 426 if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off) 427 return; 428 429 rdmsr(tr->b->address, lo, hi); 430 431 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) 432 tr->reset = 1; /* limit cannot be lower than err count */ 433 434 if (tr->reset) { /* reset err count and overflow bit */ 435 hi = 436 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | 437 (THRESHOLD_MAX - tr->b->threshold_limit); 438 } else if (tr->old_limit) { /* change limit w/o reset */ 439 int new_count = (hi & THRESHOLD_MAX) + 440 (tr->old_limit - tr->b->threshold_limit); 441 442 hi = (hi & ~MASK_ERR_COUNT_HI) | 443 (new_count & THRESHOLD_MAX); 444 } 445 446 /* clear IntType */ 447 hi &= ~MASK_INT_TYPE_HI; 448 449 if (!tr->b->interrupt_capable) 450 goto done; 451 452 if (tr->set_lvt_off) { 453 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { 454 /* set new lvt offset */ 455 hi &= ~MASK_LVTOFF_HI; 456 hi |= tr->lvt_off << 20; 457 } 458 } 459 460 if (tr->b->interrupt_enable) 461 hi |= INT_TYPE_APIC; 462 463 done: 464 465 hi |= MASK_COUNT_EN_HI; 466 wrmsr(tr->b->address, lo, hi); 467 } 468 469 static void mce_threshold_block_init(struct threshold_block *b, int offset) 470 { 471 struct thresh_restart tr = { 472 .b = b, 473 .set_lvt_off = 1, 474 .lvt_off = offset, 475 }; 476 477 b->threshold_limit = THRESHOLD_MAX; 478 threshold_restart_bank(&tr); 479 }; 480 481 static int setup_APIC_mce_threshold(int reserved, int new) 482 { 483 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, 484 APIC_EILVT_MSG_FIX, 0)) 485 return new; 486 487 return reserved; 488 } 489 490 static int setup_APIC_deferred_error(int reserved, int new) 491 { 492 if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, 493 APIC_EILVT_MSG_FIX, 0)) 494 return new; 495 496 return reserved; 497 } 498 499 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) 500 { 501 u32 low = 0, high = 0; 502 int def_offset = -1, def_new; 503 504 if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) 505 return; 506 507 def_new = (low & MASK_DEF_LVTOFF) >> 4; 508 if (!(low & MASK_DEF_LVTOFF)) { 509 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); 510 def_new = DEF_LVT_OFF; 511 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); 512 } 513 514 def_offset = setup_APIC_deferred_error(def_offset, def_new); 515 if ((def_offset == def_new) && 516 (deferred_error_int_vector != amd_deferred_error_interrupt)) 517 deferred_error_int_vector = amd_deferred_error_interrupt; 518 519 if (!mce_flags.smca) 520 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; 521 522 wrmsr(MSR_CU_DEF_ERR, low, high); 523 } 524 525 static u32 smca_get_block_address(unsigned int bank, unsigned int block, 526 unsigned int cpu) 527 { 528 if (!block) 529 return MSR_AMD64_SMCA_MCx_MISC(bank); 530 531 if (!(per_cpu(smca_misc_banks_map, cpu) & BIT(bank))) 532 return 0; 533 534 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); 535 } 536 537 static u32 get_block_address(u32 current_addr, u32 low, u32 high, 538 unsigned int bank, unsigned int block, 539 unsigned int cpu) 540 { 541 u32 addr = 0, offset = 0; 542 543 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) 544 return addr; 545 546 if (mce_flags.smca) 547 return smca_get_block_address(bank, block, cpu); 548 549 /* Fall back to method we used for older processors: */ 550 switch (block) { 551 case 0: 552 addr = mca_msr_reg(bank, MCA_MISC); 553 break; 554 case 1: 555 offset = ((low & MASK_BLKPTR_LO) >> 21); 556 if (offset) 557 addr = MCG_XBLK_ADDR + offset; 558 break; 559 default: 560 addr = ++current_addr; 561 } 562 return addr; 563 } 564 565 static int 566 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 567 int offset, u32 misc_high) 568 { 569 unsigned int cpu = smp_processor_id(); 570 u32 smca_low, smca_high; 571 struct threshold_block b; 572 int new; 573 574 if (!block) 575 per_cpu(bank_map, cpu) |= (1 << bank); 576 577 memset(&b, 0, sizeof(b)); 578 b.cpu = cpu; 579 b.bank = bank; 580 b.block = block; 581 b.address = addr; 582 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); 583 584 if (!b.interrupt_capable) 585 goto done; 586 587 b.interrupt_enable = 1; 588 589 if (!mce_flags.smca) { 590 new = (misc_high & MASK_LVTOFF_HI) >> 20; 591 goto set_offset; 592 } 593 594 /* Gather LVT offset for thresholding: */ 595 if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) 596 goto out; 597 598 new = (smca_low & SMCA_THR_LVT_OFF) >> 12; 599 600 set_offset: 601 offset = setup_APIC_mce_threshold(offset, new); 602 if (offset == new) 603 thresholding_irq_en = true; 604 605 done: 606 mce_threshold_block_init(&b, offset); 607 608 out: 609 return offset; 610 } 611 612 bool amd_filter_mce(struct mce *m) 613 { 614 enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); 615 struct cpuinfo_x86 *c = &boot_cpu_data; 616 617 /* See Family 17h Models 10h-2Fh Erratum #1114. */ 618 if (c->x86 == 0x17 && 619 c->x86_model >= 0x10 && c->x86_model <= 0x2F && 620 bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10) 621 return true; 622 623 /* NB GART TLB error reporting is disabled by default. */ 624 if (c->x86 < 0x17) { 625 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5) 626 return true; 627 } 628 629 return false; 630 } 631 632 /* 633 * Turn off thresholding banks for the following conditions: 634 * - MC4_MISC thresholding is not supported on Family 0x15. 635 * - Prevent possible spurious interrupts from the IF bank on Family 0x17 636 * Models 0x10-0x2F due to Erratum #1114. 637 */ 638 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) 639 { 640 int i, num_msrs; 641 u64 hwcr; 642 bool need_toggle; 643 u32 msrs[NR_BLOCKS]; 644 645 if (c->x86 == 0x15 && bank == 4) { 646 msrs[0] = 0x00000413; /* MC4_MISC0 */ 647 msrs[1] = 0xc0000408; /* MC4_MISC1 */ 648 num_msrs = 2; 649 } else if (c->x86 == 0x17 && 650 (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { 651 652 if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF) 653 return; 654 655 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); 656 num_msrs = 1; 657 } else { 658 return; 659 } 660 661 rdmsrl(MSR_K7_HWCR, hwcr); 662 663 /* McStatusWrEn has to be set */ 664 need_toggle = !(hwcr & BIT(18)); 665 if (need_toggle) 666 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); 667 668 /* Clear CntP bit safely */ 669 for (i = 0; i < num_msrs; i++) 670 msr_clear_bit(msrs[i], 62); 671 672 /* restore old settings */ 673 if (need_toggle) 674 wrmsrl(MSR_K7_HWCR, hwcr); 675 } 676 677 /* cpu init entry point, called from mce.c with preempt off */ 678 void mce_amd_feature_init(struct cpuinfo_x86 *c) 679 { 680 unsigned int bank, block, cpu = smp_processor_id(); 681 u32 low = 0, high = 0, address = 0; 682 int offset = -1; 683 684 685 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 686 if (mce_flags.smca) 687 smca_configure(bank, cpu); 688 689 disable_err_thresholding(c, bank); 690 691 for (block = 0; block < NR_BLOCKS; ++block) { 692 address = get_block_address(address, low, high, bank, block, cpu); 693 if (!address) 694 break; 695 696 if (rdmsr_safe(address, &low, &high)) 697 break; 698 699 if (!(high & MASK_VALID_HI)) 700 continue; 701 702 if (!(high & MASK_CNTP_HI) || 703 (high & MASK_LOCKED_HI)) 704 continue; 705 706 offset = prepare_threshold_block(bank, block, address, offset, high); 707 } 708 } 709 710 if (mce_flags.succor) 711 deferred_error_interrupt_enable(c); 712 } 713 714 bool amd_mce_is_memory_error(struct mce *m) 715 { 716 /* ErrCodeExt[20:16] */ 717 u8 xec = (m->status >> 16) & 0x1f; 718 719 if (mce_flags.smca) 720 return smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC && xec == 0x0; 721 722 return m->bank == 4 && xec == 0x8; 723 } 724 725 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) 726 { 727 struct mce m; 728 729 mce_setup(&m); 730 731 m.status = status; 732 m.misc = misc; 733 m.bank = bank; 734 m.tsc = rdtsc(); 735 736 if (m.status & MCI_STATUS_ADDRV) { 737 m.addr = addr; 738 739 /* 740 * Extract [55:<lsb>] where lsb is the least significant 741 * *valid* bit of the address bits. 742 */ 743 if (mce_flags.smca) { 744 u8 lsb = (m.addr >> 56) & 0x3f; 745 746 m.addr &= GENMASK_ULL(55, lsb); 747 } 748 } 749 750 if (mce_flags.smca) { 751 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); 752 753 if (m.status & MCI_STATUS_SYNDV) 754 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); 755 } 756 757 mce_log(&m); 758 } 759 760 DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) 761 { 762 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); 763 inc_irq_stat(irq_deferred_error_count); 764 deferred_error_int_vector(); 765 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); 766 ack_APIC_irq(); 767 } 768 769 /* 770 * Returns true if the logged error is deferred. False, otherwise. 771 */ 772 static inline bool 773 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) 774 { 775 u64 status, addr = 0; 776 777 rdmsrl(msr_stat, status); 778 if (!(status & MCI_STATUS_VAL)) 779 return false; 780 781 if (status & MCI_STATUS_ADDRV) 782 rdmsrl(msr_addr, addr); 783 784 __log_error(bank, status, addr, misc); 785 786 wrmsrl(msr_stat, 0); 787 788 return status & MCI_STATUS_DEFERRED; 789 } 790 791 /* 792 * We have three scenarios for checking for Deferred errors: 793 * 794 * 1) Non-SMCA systems check MCA_STATUS and log error if found. 795 * 2) SMCA systems check MCA_STATUS. If error is found then log it and also 796 * clear MCA_DESTAT. 797 * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and 798 * log it. 799 */ 800 static void log_error_deferred(unsigned int bank) 801 { 802 bool defrd; 803 804 defrd = _log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), 805 mca_msr_reg(bank, MCA_ADDR), 0); 806 807 if (!mce_flags.smca) 808 return; 809 810 /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */ 811 if (defrd) { 812 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); 813 return; 814 } 815 816 /* 817 * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check 818 * for a valid error. 819 */ 820 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), 821 MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); 822 } 823 824 /* APIC interrupt handler for deferred errors */ 825 static void amd_deferred_error_interrupt(void) 826 { 827 unsigned int bank; 828 829 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) 830 log_error_deferred(bank); 831 } 832 833 static void log_error_thresholding(unsigned int bank, u64 misc) 834 { 835 _log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), mca_msr_reg(bank, MCA_ADDR), misc); 836 } 837 838 static void log_and_reset_block(struct threshold_block *block) 839 { 840 struct thresh_restart tr; 841 u32 low = 0, high = 0; 842 843 if (!block) 844 return; 845 846 if (rdmsr_safe(block->address, &low, &high)) 847 return; 848 849 if (!(high & MASK_OVERFLOW_HI)) 850 return; 851 852 /* Log the MCE which caused the threshold event. */ 853 log_error_thresholding(block->bank, ((u64)high << 32) | low); 854 855 /* Reset threshold block after logging error. */ 856 memset(&tr, 0, sizeof(tr)); 857 tr.b = block; 858 threshold_restart_bank(&tr); 859 } 860 861 /* 862 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt 863 * goes off when error_count reaches threshold_limit. 864 */ 865 static void amd_threshold_interrupt(void) 866 { 867 struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; 868 struct threshold_bank **bp = this_cpu_read(threshold_banks); 869 unsigned int bank, cpu = smp_processor_id(); 870 871 /* 872 * Validate that the threshold bank has been initialized already. The 873 * handler is installed at boot time, but on a hotplug event the 874 * interrupt might fire before the data has been initialized. 875 */ 876 if (!bp) 877 return; 878 879 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 880 if (!(per_cpu(bank_map, cpu) & (1 << bank))) 881 continue; 882 883 first_block = bp[bank]->blocks; 884 if (!first_block) 885 continue; 886 887 /* 888 * The first block is also the head of the list. Check it first 889 * before iterating over the rest. 890 */ 891 log_and_reset_block(first_block); 892 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) 893 log_and_reset_block(block); 894 } 895 } 896 897 /* 898 * Sysfs Interface 899 */ 900 901 struct threshold_attr { 902 struct attribute attr; 903 ssize_t (*show) (struct threshold_block *, char *); 904 ssize_t (*store) (struct threshold_block *, const char *, size_t count); 905 }; 906 907 #define SHOW_FIELDS(name) \ 908 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ 909 { \ 910 return sprintf(buf, "%lu\n", (unsigned long) b->name); \ 911 } 912 SHOW_FIELDS(interrupt_enable) 913 SHOW_FIELDS(threshold_limit) 914 915 static ssize_t 916 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) 917 { 918 struct thresh_restart tr; 919 unsigned long new; 920 921 if (!b->interrupt_capable) 922 return -EINVAL; 923 924 if (kstrtoul(buf, 0, &new) < 0) 925 return -EINVAL; 926 927 b->interrupt_enable = !!new; 928 929 memset(&tr, 0, sizeof(tr)); 930 tr.b = b; 931 932 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 933 return -ENODEV; 934 935 return size; 936 } 937 938 static ssize_t 939 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) 940 { 941 struct thresh_restart tr; 942 unsigned long new; 943 944 if (kstrtoul(buf, 0, &new) < 0) 945 return -EINVAL; 946 947 if (new > THRESHOLD_MAX) 948 new = THRESHOLD_MAX; 949 if (new < 1) 950 new = 1; 951 952 memset(&tr, 0, sizeof(tr)); 953 tr.old_limit = b->threshold_limit; 954 b->threshold_limit = new; 955 tr.b = b; 956 957 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 958 return -ENODEV; 959 960 return size; 961 } 962 963 static ssize_t show_error_count(struct threshold_block *b, char *buf) 964 { 965 u32 lo, hi; 966 967 /* CPU might be offline by now */ 968 if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi)) 969 return -ENODEV; 970 971 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - 972 (THRESHOLD_MAX - b->threshold_limit))); 973 } 974 975 static struct threshold_attr error_count = { 976 .attr = {.name = __stringify(error_count), .mode = 0444 }, 977 .show = show_error_count, 978 }; 979 980 #define RW_ATTR(val) \ 981 static struct threshold_attr val = { \ 982 .attr = {.name = __stringify(val), .mode = 0644 }, \ 983 .show = show_## val, \ 984 .store = store_## val, \ 985 }; 986 987 RW_ATTR(interrupt_enable); 988 RW_ATTR(threshold_limit); 989 990 static struct attribute *default_attrs[] = { 991 &threshold_limit.attr, 992 &error_count.attr, 993 NULL, /* possibly interrupt_enable if supported, see below */ 994 NULL, 995 }; 996 ATTRIBUTE_GROUPS(default); 997 998 #define to_block(k) container_of(k, struct threshold_block, kobj) 999 #define to_attr(a) container_of(a, struct threshold_attr, attr) 1000 1001 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) 1002 { 1003 struct threshold_block *b = to_block(kobj); 1004 struct threshold_attr *a = to_attr(attr); 1005 ssize_t ret; 1006 1007 ret = a->show ? a->show(b, buf) : -EIO; 1008 1009 return ret; 1010 } 1011 1012 static ssize_t store(struct kobject *kobj, struct attribute *attr, 1013 const char *buf, size_t count) 1014 { 1015 struct threshold_block *b = to_block(kobj); 1016 struct threshold_attr *a = to_attr(attr); 1017 ssize_t ret; 1018 1019 ret = a->store ? a->store(b, buf, count) : -EIO; 1020 1021 return ret; 1022 } 1023 1024 static const struct sysfs_ops threshold_ops = { 1025 .show = show, 1026 .store = store, 1027 }; 1028 1029 static void threshold_block_release(struct kobject *kobj); 1030 1031 static struct kobj_type threshold_ktype = { 1032 .sysfs_ops = &threshold_ops, 1033 .default_groups = default_groups, 1034 .release = threshold_block_release, 1035 }; 1036 1037 static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b) 1038 { 1039 enum smca_bank_types bank_type; 1040 1041 if (!mce_flags.smca) { 1042 if (b && bank == 4) 1043 return bank4_names(b); 1044 1045 return th_names[bank]; 1046 } 1047 1048 bank_type = smca_get_bank_type(cpu, bank); 1049 if (bank_type >= N_SMCA_BANK_TYPES) 1050 return NULL; 1051 1052 if (b && bank_type == SMCA_UMC) { 1053 if (b->block < ARRAY_SIZE(smca_umc_block_names)) 1054 return smca_umc_block_names[b->block]; 1055 return NULL; 1056 } 1057 1058 if (per_cpu(smca_bank_counts, cpu)[bank_type] == 1) 1059 return smca_get_name(bank_type); 1060 1061 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, 1062 "%s_%u", smca_get_name(bank_type), 1063 per_cpu(smca_banks, cpu)[bank].sysfs_id); 1064 return buf_mcatype; 1065 } 1066 1067 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb, 1068 unsigned int bank, unsigned int block, 1069 u32 address) 1070 { 1071 struct threshold_block *b = NULL; 1072 u32 low, high; 1073 int err; 1074 1075 if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS)) 1076 return 0; 1077 1078 if (rdmsr_safe(address, &low, &high)) 1079 return 0; 1080 1081 if (!(high & MASK_VALID_HI)) { 1082 if (block) 1083 goto recurse; 1084 else 1085 return 0; 1086 } 1087 1088 if (!(high & MASK_CNTP_HI) || 1089 (high & MASK_LOCKED_HI)) 1090 goto recurse; 1091 1092 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); 1093 if (!b) 1094 return -ENOMEM; 1095 1096 b->block = block; 1097 b->bank = bank; 1098 b->cpu = cpu; 1099 b->address = address; 1100 b->interrupt_enable = 0; 1101 b->interrupt_capable = lvt_interrupt_supported(bank, high); 1102 b->threshold_limit = THRESHOLD_MAX; 1103 1104 if (b->interrupt_capable) { 1105 default_attrs[2] = &interrupt_enable.attr; 1106 b->interrupt_enable = 1; 1107 } else { 1108 default_attrs[2] = NULL; 1109 } 1110 1111 INIT_LIST_HEAD(&b->miscj); 1112 1113 /* This is safe as @tb is not visible yet */ 1114 if (tb->blocks) 1115 list_add(&b->miscj, &tb->blocks->miscj); 1116 else 1117 tb->blocks = b; 1118 1119 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b)); 1120 if (err) 1121 goto out_free; 1122 recurse: 1123 address = get_block_address(address, low, high, bank, ++block, cpu); 1124 if (!address) 1125 return 0; 1126 1127 err = allocate_threshold_blocks(cpu, tb, bank, block, address); 1128 if (err) 1129 goto out_free; 1130 1131 if (b) 1132 kobject_uevent(&b->kobj, KOBJ_ADD); 1133 1134 return 0; 1135 1136 out_free: 1137 if (b) { 1138 list_del(&b->miscj); 1139 kobject_put(&b->kobj); 1140 } 1141 return err; 1142 } 1143 1144 static int __threshold_add_blocks(struct threshold_bank *b) 1145 { 1146 struct list_head *head = &b->blocks->miscj; 1147 struct threshold_block *pos = NULL; 1148 struct threshold_block *tmp = NULL; 1149 int err = 0; 1150 1151 err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); 1152 if (err) 1153 return err; 1154 1155 list_for_each_entry_safe(pos, tmp, head, miscj) { 1156 1157 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); 1158 if (err) { 1159 list_for_each_entry_safe_reverse(pos, tmp, head, miscj) 1160 kobject_del(&pos->kobj); 1161 1162 return err; 1163 } 1164 } 1165 return err; 1166 } 1167 1168 static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu, 1169 unsigned int bank) 1170 { 1171 struct device *dev = this_cpu_read(mce_device); 1172 struct amd_northbridge *nb = NULL; 1173 struct threshold_bank *b = NULL; 1174 const char *name = get_name(cpu, bank, NULL); 1175 int err = 0; 1176 1177 if (!dev) 1178 return -ENODEV; 1179 1180 if (is_shared_bank(bank)) { 1181 nb = node_to_amd_nb(topology_die_id(cpu)); 1182 1183 /* threshold descriptor already initialized on this node? */ 1184 if (nb && nb->bank4) { 1185 /* yes, use it */ 1186 b = nb->bank4; 1187 err = kobject_add(b->kobj, &dev->kobj, name); 1188 if (err) 1189 goto out; 1190 1191 bp[bank] = b; 1192 refcount_inc(&b->cpus); 1193 1194 err = __threshold_add_blocks(b); 1195 1196 goto out; 1197 } 1198 } 1199 1200 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); 1201 if (!b) { 1202 err = -ENOMEM; 1203 goto out; 1204 } 1205 1206 /* Associate the bank with the per-CPU MCE device */ 1207 b->kobj = kobject_create_and_add(name, &dev->kobj); 1208 if (!b->kobj) { 1209 err = -EINVAL; 1210 goto out_free; 1211 } 1212 1213 if (is_shared_bank(bank)) { 1214 b->shared = 1; 1215 refcount_set(&b->cpus, 1); 1216 1217 /* nb is already initialized, see above */ 1218 if (nb) { 1219 WARN_ON(nb->bank4); 1220 nb->bank4 = b; 1221 } 1222 } 1223 1224 err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC)); 1225 if (err) 1226 goto out_kobj; 1227 1228 bp[bank] = b; 1229 return 0; 1230 1231 out_kobj: 1232 kobject_put(b->kobj); 1233 out_free: 1234 kfree(b); 1235 out: 1236 return err; 1237 } 1238 1239 static void threshold_block_release(struct kobject *kobj) 1240 { 1241 kfree(to_block(kobj)); 1242 } 1243 1244 static void deallocate_threshold_blocks(struct threshold_bank *bank) 1245 { 1246 struct threshold_block *pos, *tmp; 1247 1248 list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) { 1249 list_del(&pos->miscj); 1250 kobject_put(&pos->kobj); 1251 } 1252 1253 kobject_put(&bank->blocks->kobj); 1254 } 1255 1256 static void __threshold_remove_blocks(struct threshold_bank *b) 1257 { 1258 struct threshold_block *pos = NULL; 1259 struct threshold_block *tmp = NULL; 1260 1261 kobject_del(b->kobj); 1262 1263 list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) 1264 kobject_del(&pos->kobj); 1265 } 1266 1267 static void threshold_remove_bank(struct threshold_bank *bank) 1268 { 1269 struct amd_northbridge *nb; 1270 1271 if (!bank->blocks) 1272 goto out_free; 1273 1274 if (!bank->shared) 1275 goto out_dealloc; 1276 1277 if (!refcount_dec_and_test(&bank->cpus)) { 1278 __threshold_remove_blocks(bank); 1279 return; 1280 } else { 1281 /* 1282 * The last CPU on this node using the shared bank is going 1283 * away, remove that bank now. 1284 */ 1285 nb = node_to_amd_nb(topology_die_id(smp_processor_id())); 1286 nb->bank4 = NULL; 1287 } 1288 1289 out_dealloc: 1290 deallocate_threshold_blocks(bank); 1291 1292 out_free: 1293 kobject_put(bank->kobj); 1294 kfree(bank); 1295 } 1296 1297 int mce_threshold_remove_device(unsigned int cpu) 1298 { 1299 struct threshold_bank **bp = this_cpu_read(threshold_banks); 1300 unsigned int bank, numbanks = this_cpu_read(mce_num_banks); 1301 1302 if (!bp) 1303 return 0; 1304 1305 /* 1306 * Clear the pointer before cleaning up, so that the interrupt won't 1307 * touch anything of this. 1308 */ 1309 this_cpu_write(threshold_banks, NULL); 1310 1311 for (bank = 0; bank < numbanks; bank++) { 1312 if (bp[bank]) { 1313 threshold_remove_bank(bp[bank]); 1314 bp[bank] = NULL; 1315 } 1316 } 1317 kfree(bp); 1318 return 0; 1319 } 1320 1321 /** 1322 * mce_threshold_create_device - Create the per-CPU MCE threshold device 1323 * @cpu: The plugged in CPU 1324 * 1325 * Create directories and files for all valid threshold banks. 1326 * 1327 * This is invoked from the CPU hotplug callback which was installed in 1328 * mcheck_init_device(). The invocation happens in context of the hotplug 1329 * thread running on @cpu. The callback is invoked on all CPUs which are 1330 * online when the callback is installed or during a real hotplug event. 1331 */ 1332 int mce_threshold_create_device(unsigned int cpu) 1333 { 1334 unsigned int numbanks, bank; 1335 struct threshold_bank **bp; 1336 int err; 1337 1338 if (!mce_flags.amd_threshold) 1339 return 0; 1340 1341 bp = this_cpu_read(threshold_banks); 1342 if (bp) 1343 return 0; 1344 1345 numbanks = this_cpu_read(mce_num_banks); 1346 bp = kcalloc(numbanks, sizeof(*bp), GFP_KERNEL); 1347 if (!bp) 1348 return -ENOMEM; 1349 1350 for (bank = 0; bank < numbanks; ++bank) { 1351 if (!(this_cpu_read(bank_map) & (1 << bank))) 1352 continue; 1353 err = threshold_create_bank(bp, cpu, bank); 1354 if (err) 1355 goto out_err; 1356 } 1357 this_cpu_write(threshold_banks, bp); 1358 1359 if (thresholding_irq_en) 1360 mce_threshold_vector = amd_threshold_interrupt; 1361 return 0; 1362 out_err: 1363 mce_threshold_remove_device(cpu); 1364 return err; 1365 } 1366