1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * linux/arch/arm/kernel/entry-armv.S 4 * 5 * Copyright (C) 1996,1997,1998 Russell King. 6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 7 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 8 * 9 * Low-level vector interface routines 10 * 11 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 12 * that causes it to save wrong values... Be aware! 13 */ 14 15#include <linux/init.h> 16 17#include <asm/assembler.h> 18#include <asm/memory.h> 19#include <asm/glue-df.h> 20#include <asm/glue-pf.h> 21#include <asm/vfpmacros.h> 22#include <asm/thread_notify.h> 23#include <asm/unwind.h> 24#include <asm/unistd.h> 25#include <asm/tls.h> 26#include <asm/system_info.h> 27#include <asm/uaccess-asm.h> 28 29#include "entry-header.S" 30#include <asm/probes.h> 31 32/* 33 * Interrupt handling. 34 */ 35 .macro irq_handler, from_user:req 36 mov r1, sp 37 ldr_this_cpu r2, irq_stack_ptr, r2, r3 38 .if \from_user == 0 39 @ 40 @ If we took the interrupt while running in the kernel, we may already 41 @ be using the IRQ stack, so revert to the original value in that case. 42 @ 43 subs r3, r2, r1 @ SP above bottom of IRQ stack? 44 rsbscs r3, r3, #THREAD_SIZE @ ... and below the top? 45#ifdef CONFIG_VMAP_STACK 46 ldr_va r3, high_memory, cc @ End of the linear region 47 cmpcc r3, r1 @ Stack pointer was below it? 48#endif 49 bcc 0f @ If not, switch to the IRQ stack 50 mov r0, r1 51 bl generic_handle_arch_irq 52 b 1f 530: 54 .endif 55 56 mov_l r0, generic_handle_arch_irq 57 bl call_with_stack 581: 59 .endm 60 61 .macro pabt_helper 62 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 63#ifdef MULTI_PABORT 64 ldr ip, .LCprocfns 65 mov lr, pc 66 ldr pc, [ip, #PROCESSOR_PABT_FUNC] 67#else 68 bl CPU_PABORT_HANDLER 69#endif 70 .endm 71 72 .macro dabt_helper 73 74 @ 75 @ Call the processor-specific abort handler: 76 @ 77 @ r2 - pt_regs 78 @ r4 - aborted context pc 79 @ r5 - aborted context psr 80 @ 81 @ The abort handler must return the aborted address in r0, and 82 @ the fault status register in r1. r9 must be preserved. 83 @ 84#ifdef MULTI_DABORT 85 ldr ip, .LCprocfns 86 mov lr, pc 87 ldr pc, [ip, #PROCESSOR_DABT_FUNC] 88#else 89 bl CPU_DABORT_HANDLER 90#endif 91 .endm 92 93 .section .entry.text,"ax",%progbits 94 95/* 96 * Invalid mode handlers 97 */ 98 .macro inv_entry, reason 99 sub sp, sp, #PT_REGS_SIZE 100 ARM( stmib sp, {r1 - lr} ) 101 THUMB( stmia sp, {r0 - r12} ) 102 THUMB( str sp, [sp, #S_SP] ) 103 THUMB( str lr, [sp, #S_LR] ) 104 mov r1, #\reason 105 .endm 106 107__pabt_invalid: 108 inv_entry BAD_PREFETCH 109 b common_invalid 110ENDPROC(__pabt_invalid) 111 112__dabt_invalid: 113 inv_entry BAD_DATA 114 b common_invalid 115ENDPROC(__dabt_invalid) 116 117__irq_invalid: 118 inv_entry BAD_IRQ 119 b common_invalid 120ENDPROC(__irq_invalid) 121 122__und_invalid: 123 inv_entry BAD_UNDEFINSTR 124 125 @ 126 @ XXX fall through to common_invalid 127 @ 128 129@ 130@ common_invalid - generic code for failed exception (re-entrant version of handlers) 131@ 132common_invalid: 133 zero_fp 134 135 ldmia r0, {r4 - r6} 136 add r0, sp, #S_PC @ here for interlock avoidance 137 mov r7, #-1 @ "" "" "" "" 138 str r4, [sp] @ save preserved r0 139 stmia r0, {r5 - r7} @ lr_<exception>, 140 @ cpsr_<exception>, "old_r0" 141 142 mov r0, sp 143 b bad_mode 144ENDPROC(__und_invalid) 145 146/* 147 * SVC mode handlers 148 */ 149 150#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 151#define SPFIX(code...) code 152#else 153#define SPFIX(code...) 154#endif 155 156 .macro svc_entry, stack_hole=0, trace=1, uaccess=1, overflow_check=1 157 UNWIND(.fnstart ) 158 sub sp, sp, #(SVC_REGS_SIZE + \stack_hole) 159 THUMB( add sp, r1 ) @ get SP in a GPR without 160 THUMB( sub r1, sp, r1 ) @ using a temp register 161 162 .if \overflow_check 163 UNWIND(.save {r0 - pc} ) 164 do_overflow_check (SVC_REGS_SIZE + \stack_hole) 165 .endif 166 167#ifdef CONFIG_THUMB2_KERNEL 168 tst r1, #4 @ test stack pointer alignment 169 sub r1, sp, r1 @ restore original R1 170 sub sp, r1 @ restore original SP 171#else 172 SPFIX( tst sp, #4 ) 173#endif 174 SPFIX( subne sp, sp, #4 ) 175 176 ARM( stmib sp, {r1 - r12} ) 177 THUMB( stmia sp, {r0 - r12} ) @ No STMIB in Thumb-2 178 179 ldmia r0, {r3 - r5} 180 add r7, sp, #S_SP @ here for interlock avoidance 181 mov r6, #-1 @ "" "" "" "" 182 add r2, sp, #(SVC_REGS_SIZE + \stack_hole) 183 SPFIX( addne r2, r2, #4 ) 184 str r3, [sp] @ save the "real" r0 copied 185 @ from the exception stack 186 187 mov r3, lr 188 189 @ 190 @ We are now ready to fill in the remaining blanks on the stack: 191 @ 192 @ r2 - sp_svc 193 @ r3 - lr_svc 194 @ r4 - lr_<exception>, already fixed up for correct return/restart 195 @ r5 - spsr_<exception> 196 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 197 @ 198 stmia r7, {r2 - r6} 199 200 get_thread_info tsk 201 uaccess_entry tsk, r0, r1, r2, \uaccess 202 203 .if \trace 204#ifdef CONFIG_TRACE_IRQFLAGS 205 bl trace_hardirqs_off 206#endif 207 .endif 208 .endm 209 210 .align 5 211__dabt_svc: 212 svc_entry uaccess=0 213 mov r2, sp 214 dabt_helper 215 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR 216 svc_exit r5 @ return from exception 217 UNWIND(.fnend ) 218ENDPROC(__dabt_svc) 219 220 .align 5 221__irq_svc: 222 svc_entry 223 irq_handler from_user=0 224 225#ifdef CONFIG_PREEMPTION 226 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 227 ldr r0, [tsk, #TI_FLAGS] @ get flags 228 teq r8, #0 @ if preempt count != 0 229 movne r0, #0 @ force flags to 0 230 tst r0, #_TIF_NEED_RESCHED 231 blne svc_preempt 232#endif 233 234 svc_exit r5, irq = 1 @ return from exception 235 UNWIND(.fnend ) 236ENDPROC(__irq_svc) 237 238 .ltorg 239 240#ifdef CONFIG_PREEMPTION 241svc_preempt: 242 mov r8, lr 2431: bl preempt_schedule_irq @ irq en/disable is done inside 244 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 245 tst r0, #_TIF_NEED_RESCHED 246 reteq r8 @ go again 247 b 1b 248#endif 249 250__und_fault: 251 @ Correct the PC such that it is pointing at the instruction 252 @ which caused the fault. If the faulting instruction was ARM 253 @ the PC will be pointing at the next instruction, and have to 254 @ subtract 4. Otherwise, it is Thumb, and the PC will be 255 @ pointing at the second half of the Thumb instruction. We 256 @ have to subtract 2. 257 ldr r2, [r0, #S_PC] 258 sub r2, r2, r1 259 str r2, [r0, #S_PC] 260 b do_undefinstr 261ENDPROC(__und_fault) 262 263 .align 5 264__und_svc: 265#ifdef CONFIG_KPROBES 266 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 267 @ it obviously needs free stack space which then will belong to 268 @ the saved context. 269 svc_entry MAX_STACK_SIZE 270#else 271 svc_entry 272#endif 273 274 mov r1, #4 @ PC correction to apply 275 THUMB( tst r5, #PSR_T_BIT ) @ exception taken in Thumb mode? 276 THUMB( movne r1, #2 ) @ if so, fix up PC correction 277 mov r0, sp @ struct pt_regs *regs 278 bl __und_fault 279 280__und_svc_finish: 281 get_thread_info tsk 282 ldr r5, [sp, #S_PSR] @ Get SVC cpsr 283 svc_exit r5 @ return from exception 284 UNWIND(.fnend ) 285ENDPROC(__und_svc) 286 287 .align 5 288__pabt_svc: 289 svc_entry 290 mov r2, sp @ regs 291 pabt_helper 292 svc_exit r5 @ return from exception 293 UNWIND(.fnend ) 294ENDPROC(__pabt_svc) 295 296 .align 5 297__fiq_svc: 298 svc_entry trace=0 299 mov r0, sp @ struct pt_regs *regs 300 bl handle_fiq_as_nmi 301 svc_exit_via_fiq 302 UNWIND(.fnend ) 303ENDPROC(__fiq_svc) 304 305 .align 5 306.LCcralign: 307 .word cr_alignment 308#ifdef MULTI_DABORT 309.LCprocfns: 310 .word processor 311#endif 312.LCfp: 313 .word fp_enter 314 315/* 316 * Abort mode handlers 317 */ 318 319@ 320@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode 321@ and reuses the same macros. However in abort mode we must also 322@ save/restore lr_abt and spsr_abt to make nested aborts safe. 323@ 324 .align 5 325__fiq_abt: 326 svc_entry trace=0 327 328 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 329 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 330 THUMB( msr cpsr_c, r0 ) 331 mov r1, lr @ Save lr_abt 332 mrs r2, spsr @ Save spsr_abt, abort is now safe 333 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 334 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 335 THUMB( msr cpsr_c, r0 ) 336 stmfd sp!, {r1 - r2} 337 338 add r0, sp, #8 @ struct pt_regs *regs 339 bl handle_fiq_as_nmi 340 341 ldmfd sp!, {r1 - r2} 342 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 343 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 344 THUMB( msr cpsr_c, r0 ) 345 mov lr, r1 @ Restore lr_abt, abort is unsafe 346 msr spsr_cxsf, r2 @ Restore spsr_abt 347 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 348 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 349 THUMB( msr cpsr_c, r0 ) 350 351 svc_exit_via_fiq 352 UNWIND(.fnend ) 353ENDPROC(__fiq_abt) 354 355/* 356 * User mode handlers 357 * 358 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE 359 */ 360 361#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (PT_REGS_SIZE & 7) 362#error "sizeof(struct pt_regs) must be a multiple of 8" 363#endif 364 365 .macro usr_entry, trace=1, uaccess=1 366 UNWIND(.fnstart ) 367 UNWIND(.cantunwind ) @ don't unwind the user space 368 sub sp, sp, #PT_REGS_SIZE 369 ARM( stmib sp, {r1 - r12} ) 370 THUMB( stmia sp, {r0 - r12} ) 371 372 ATRAP( mrc p15, 0, r7, c1, c0, 0) 373 ATRAP( ldr r8, .LCcralign) 374 375 ldmia r0, {r3 - r5} 376 add r0, sp, #S_PC @ here for interlock avoidance 377 mov r6, #-1 @ "" "" "" "" 378 379 str r3, [sp] @ save the "real" r0 copied 380 @ from the exception stack 381 382 ATRAP( ldr r8, [r8, #0]) 383 384 @ 385 @ We are now ready to fill in the remaining blanks on the stack: 386 @ 387 @ r4 - lr_<exception>, already fixed up for correct return/restart 388 @ r5 - spsr_<exception> 389 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 390 @ 391 @ Also, separately save sp_usr and lr_usr 392 @ 393 stmia r0, {r4 - r6} 394 ARM( stmdb r0, {sp, lr}^ ) 395 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 396 397 .if \uaccess 398 uaccess_disable ip 399 .endif 400 401 @ Enable the alignment trap while in kernel mode 402 ATRAP( teq r8, r7) 403 ATRAP( mcrne p15, 0, r8, c1, c0, 0) 404 405 reload_current r7, r8 406 407 @ 408 @ Clear FP to mark the first stack frame 409 @ 410 zero_fp 411 412 .if \trace 413#ifdef CONFIG_TRACE_IRQFLAGS 414 bl trace_hardirqs_off 415#endif 416 ct_user_exit save = 0 417 .endif 418 .endm 419 420 .macro kuser_cmpxchg_check 421#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) 422#ifndef CONFIG_MMU 423#warning "NPTL on non MMU needs fixing" 424#else 425 @ Make sure our user space atomic helper is restarted 426 @ if it was interrupted in a critical region. Here we 427 @ perform a quick test inline since it should be false 428 @ 99.9999% of the time. The rest is done out of line. 429 ldr r0, =TASK_SIZE 430 cmp r4, r0 431 blhs kuser_cmpxchg64_fixup 432#endif 433#endif 434 .endm 435 436 .align 5 437__dabt_usr: 438 usr_entry uaccess=0 439 kuser_cmpxchg_check 440 mov r2, sp 441 dabt_helper 442 b ret_from_exception 443 UNWIND(.fnend ) 444ENDPROC(__dabt_usr) 445 446 .align 5 447__irq_usr: 448 usr_entry 449 kuser_cmpxchg_check 450 irq_handler from_user=1 451 get_thread_info tsk 452 mov why, #0 453 b ret_to_user_from_irq 454 UNWIND(.fnend ) 455ENDPROC(__irq_usr) 456 457 .ltorg 458 459 .align 5 460__und_usr: 461 usr_entry uaccess=0 462 463 mov r2, r4 464 mov r3, r5 465 466 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the 467 @ faulting instruction depending on Thumb mode. 468 @ r3 = regs->ARM_cpsr 469 @ 470 @ The emulation code returns using r9 if it has emulated the 471 @ instruction, or the more conventional lr if we are to treat 472 @ this as a real undefined instruction 473 @ 474 badr r9, ret_from_exception 475 476 @ IRQs must be enabled before attempting to read the instruction from 477 @ user space since that could cause a page/translation fault if the 478 @ page table was modified by another CPU. 479 enable_irq 480 481 tst r3, #PSR_T_BIT @ Thumb mode? 482 bne __und_usr_thumb 483 sub r4, r2, #4 @ ARM instr at LR - 4 4841: ldrt r0, [r4] 485 ARM_BE8(rev r0, r0) @ little endian instruction 486 487 uaccess_disable ip 488 489 @ r0 = 32-bit ARM instruction which caused the exception 490 @ r2 = PC value for the following instruction (:= regs->ARM_pc) 491 @ r4 = PC value for the faulting instruction 492 @ lr = 32-bit undefined instruction function 493 badr lr, __und_usr_fault_32 494 b call_fpe 495 496__und_usr_thumb: 497 @ Thumb instruction 498 sub r4, r2, #2 @ First half of thumb instr at LR - 2 499#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 500/* 501 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms 502 * can never be supported in a single kernel, this code is not applicable at 503 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be 504 * made about .arch directives. 505 */ 506#if __LINUX_ARM_ARCH__ < 7 507/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ 508#define NEED_CPU_ARCHITECTURE 509 ldr r5, .LCcpu_architecture 510 ldr r5, [r5] 511 cmp r5, #CPU_ARCH_ARMv7 512 blo __und_usr_fault_16 @ 16bit undefined instruction 513/* 514 * The following code won't get run unless the running CPU really is v7, so 515 * coding round the lack of ldrht on older arches is pointless. Temporarily 516 * override the assembler target arch with the minimum required instead: 517 */ 518 .arch armv6t2 519#endif 5202: ldrht r5, [r4] 521ARM_BE8(rev16 r5, r5) @ little endian instruction 522 cmp r5, #0xe800 @ 32bit instruction if xx != 0 523 blo __und_usr_fault_16_pan @ 16bit undefined instruction 5243: ldrht r0, [r2] 525ARM_BE8(rev16 r0, r0) @ little endian instruction 526 uaccess_disable ip 527 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 528 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update 529 orr r0, r0, r5, lsl #16 530 badr lr, __und_usr_fault_32 531 @ r0 = the two 16-bit Thumb instructions which caused the exception 532 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) 533 @ r4 = PC value for the first 16-bit Thumb instruction 534 @ lr = 32bit undefined instruction function 535 536#if __LINUX_ARM_ARCH__ < 7 537/* If the target arch was overridden, change it back: */ 538#ifdef CONFIG_CPU_32v6K 539 .arch armv6k 540#else 541 .arch armv6 542#endif 543#endif /* __LINUX_ARM_ARCH__ < 7 */ 544#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ 545 b __und_usr_fault_16 546#endif 547 UNWIND(.fnend) 548ENDPROC(__und_usr) 549 550/* 551 * The out of line fixup for the ldrt instructions above. 552 */ 553 .pushsection .text.fixup, "ax" 554 .align 2 5554: str r4, [sp, #S_PC] @ retry current instruction 556 ret r9 557 .popsection 558 .pushsection __ex_table,"a" 559 .long 1b, 4b 560#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 561 .long 2b, 4b 562 .long 3b, 4b 563#endif 564 .popsection 565 566/* 567 * Check whether the instruction is a co-processor instruction. 568 * If yes, we need to call the relevant co-processor handler. 569 * 570 * Note that we don't do a full check here for the co-processor 571 * instructions; all instructions with bit 27 set are well 572 * defined. The only instructions that should fault are the 573 * co-processor instructions. However, we have to watch out 574 * for the ARM6/ARM7 SWI bug. 575 * 576 * NEON is a special case that has to be handled here. Not all 577 * NEON instructions are co-processor instructions, so we have 578 * to make a special case of checking for them. Plus, there's 579 * five groups of them, so we have a table of mask/opcode pairs 580 * to check against, and if any match then we branch off into the 581 * NEON handler code. 582 * 583 * Emulators may wish to make use of the following registers: 584 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) 585 * r2 = PC value to resume execution after successful emulation 586 * r9 = normal "successful" return address 587 * r10 = this threads thread_info structure 588 * lr = unrecognised instruction return address 589 * IRQs enabled, FIQs enabled. 590 */ 591 @ 592 @ Fall-through from Thumb-2 __und_usr 593 @ 594#ifdef CONFIG_NEON 595 get_thread_info r10 @ get current thread 596 adr r6, .LCneon_thumb_opcodes 597 b 2f 598#endif 599call_fpe: 600 get_thread_info r10 @ get current thread 601#ifdef CONFIG_NEON 602 adr r6, .LCneon_arm_opcodes 6032: ldr r5, [r6], #4 @ mask value 604 ldr r7, [r6], #4 @ opcode bits matching in mask 605 cmp r5, #0 @ end mask? 606 beq 1f 607 and r8, r0, r5 608 cmp r8, r7 @ NEON instruction? 609 bne 2b 610 mov r7, #1 611 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 612 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 613 b do_vfp @ let VFP handler handle this 6141: 615#endif 616 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 617 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 618 reteq lr 619 and r8, r0, #0x00000f00 @ mask out CP number 620 mov r7, #1 621 add r6, r10, r8, lsr #8 @ add used_cp[] array offset first 622 strb r7, [r6, #TI_USED_CP] @ set appropriate used_cp[] 623#ifdef CONFIG_IWMMXT 624 @ Test if we need to give access to iWMMXt coprocessors 625 ldr r5, [r10, #TI_FLAGS] 626 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 627 movscs r7, r5, lsr #(TIF_USING_IWMMXT + 1) 628 bcs iwmmxt_task_enable 629#endif 630 ARM( add pc, pc, r8, lsr #6 ) 631 THUMB( lsr r8, r8, #6 ) 632 THUMB( add pc, r8 ) 633 nop 634 635 ret.w lr @ CP#0 636 W(b) do_fpe @ CP#1 (FPE) 637 W(b) do_fpe @ CP#2 (FPE) 638 ret.w lr @ CP#3 639 ret.w lr @ CP#4 640 ret.w lr @ CP#5 641 ret.w lr @ CP#6 642 ret.w lr @ CP#7 643 ret.w lr @ CP#8 644 ret.w lr @ CP#9 645#ifdef CONFIG_VFP 646 W(b) do_vfp @ CP#10 (VFP) 647 W(b) do_vfp @ CP#11 (VFP) 648#else 649 ret.w lr @ CP#10 (VFP) 650 ret.w lr @ CP#11 (VFP) 651#endif 652 ret.w lr @ CP#12 653 ret.w lr @ CP#13 654 ret.w lr @ CP#14 (Debug) 655 ret.w lr @ CP#15 (Control) 656 657#ifdef NEED_CPU_ARCHITECTURE 658 .align 2 659.LCcpu_architecture: 660 .word __cpu_architecture 661#endif 662 663#ifdef CONFIG_NEON 664 .align 6 665 666.LCneon_arm_opcodes: 667 .word 0xfe000000 @ mask 668 .word 0xf2000000 @ opcode 669 670 .word 0xff100000 @ mask 671 .word 0xf4000000 @ opcode 672 673 .word 0x00000000 @ mask 674 .word 0x00000000 @ opcode 675 676.LCneon_thumb_opcodes: 677 .word 0xef000000 @ mask 678 .word 0xef000000 @ opcode 679 680 .word 0xff100000 @ mask 681 .word 0xf9000000 @ opcode 682 683 .word 0x00000000 @ mask 684 .word 0x00000000 @ opcode 685#endif 686 687do_fpe: 688 ldr r4, .LCfp 689 add r10, r10, #TI_FPSTATE @ r10 = workspace 690 ldr pc, [r4] @ Call FP module USR entry point 691 692/* 693 * The FP module is called with these registers set: 694 * r0 = instruction 695 * r2 = PC+4 696 * r9 = normal "successful" return address 697 * r10 = FP workspace 698 * lr = unrecognised FP instruction return address 699 */ 700 701 .pushsection .data 702 .align 2 703ENTRY(fp_enter) 704 .word no_fp 705 .popsection 706 707ENTRY(no_fp) 708 ret lr 709ENDPROC(no_fp) 710 711__und_usr_fault_32: 712 mov r1, #4 713 b 1f 714__und_usr_fault_16_pan: 715 uaccess_disable ip 716__und_usr_fault_16: 717 mov r1, #2 7181: mov r0, sp 719 badr lr, ret_from_exception 720 b __und_fault 721ENDPROC(__und_usr_fault_32) 722ENDPROC(__und_usr_fault_16) 723 724 .align 5 725__pabt_usr: 726 usr_entry 727 mov r2, sp @ regs 728 pabt_helper 729 UNWIND(.fnend ) 730 /* fall through */ 731/* 732 * This is the return code to user mode for abort handlers 733 */ 734ENTRY(ret_from_exception) 735 UNWIND(.fnstart ) 736 UNWIND(.cantunwind ) 737 get_thread_info tsk 738 mov why, #0 739 b ret_to_user 740 UNWIND(.fnend ) 741ENDPROC(__pabt_usr) 742ENDPROC(ret_from_exception) 743 744 .align 5 745__fiq_usr: 746 usr_entry trace=0 747 kuser_cmpxchg_check 748 mov r0, sp @ struct pt_regs *regs 749 bl handle_fiq_as_nmi 750 get_thread_info tsk 751 restore_user_regs fast = 0, offset = 0 752 UNWIND(.fnend ) 753ENDPROC(__fiq_usr) 754 755/* 756 * Register switch for ARMv3 and ARMv4 processors 757 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 758 * previous and next are guaranteed not to be the same. 759 */ 760ENTRY(__switch_to) 761 UNWIND(.fnstart ) 762 UNWIND(.cantunwind ) 763 add ip, r1, #TI_CPU_SAVE 764 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack 765 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack 766 THUMB( str sp, [ip], #4 ) 767 THUMB( str lr, [ip], #4 ) 768 ldr r4, [r2, #TI_TP_VALUE] 769 ldr r5, [r2, #TI_TP_VALUE + 4] 770#ifdef CONFIG_CPU_USE_DOMAINS 771 mrc p15, 0, r6, c3, c0, 0 @ Get domain register 772 str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register 773 ldr r6, [r2, #TI_CPU_DOMAIN] 774#endif 775 switch_tls r1, r4, r5, r3, r7 776#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) && \ 777 !defined(CONFIG_STACKPROTECTOR_PER_TASK) 778 ldr r8, =__stack_chk_guard 779 .if (TSK_STACK_CANARY > IMM12_MASK) 780 add r9, r2, #TSK_STACK_CANARY & ~IMM12_MASK 781 ldr r9, [r9, #TSK_STACK_CANARY & IMM12_MASK] 782 .else 783 ldr r9, [r2, #TSK_STACK_CANARY & IMM12_MASK] 784 .endif 785#endif 786 mov r7, r2 @ Preserve 'next' 787#ifdef CONFIG_CPU_USE_DOMAINS 788 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 789#endif 790 mov r5, r0 791 add r4, r2, #TI_CPU_SAVE 792 ldr r0, =thread_notify_head 793 mov r1, #THREAD_NOTIFY_SWITCH 794 bl atomic_notifier_call_chain 795#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) && \ 796 !defined(CONFIG_STACKPROTECTOR_PER_TASK) 797 str r9, [r8] 798#endif 799 mov r0, r5 800#if !defined(CONFIG_THUMB2_KERNEL) && !defined(CONFIG_VMAP_STACK) 801 set_current r7, r8 802 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously 803#else 804 mov r1, r7 805 ldmia r4, {r4 - sl, fp, ip, lr} @ Load all regs saved previously 806#ifdef CONFIG_VMAP_STACK 807 @ 808 @ Do a dummy read from the new stack while running from the old one so 809 @ that we can rely on do_translation_fault() to fix up any stale PMD 810 @ entries covering the vmalloc region. 811 @ 812 ldr r2, [ip] 813#endif 814 815 @ When CONFIG_THREAD_INFO_IN_TASK=n, the update of SP itself is what 816 @ effectuates the task switch, as that is what causes the observable 817 @ values of current and current_thread_info to change. When 818 @ CONFIG_THREAD_INFO_IN_TASK=y, setting current (and therefore 819 @ current_thread_info) is done explicitly, and the update of SP just 820 @ switches us to another stack, with few other side effects. In order 821 @ to prevent this distinction from causing any inconsistencies, let's 822 @ keep the 'set_current' call as close as we can to the update of SP. 823 set_current r1, r2 824 mov sp, ip 825 ret lr 826#endif 827 UNWIND(.fnend ) 828ENDPROC(__switch_to) 829 830#ifdef CONFIG_VMAP_STACK 831 .text 832 .align 2 833__bad_stack: 834 @ 835 @ We've just detected an overflow. We need to load the address of this 836 @ CPU's overflow stack into the stack pointer register. We have only one 837 @ scratch register so let's use a sequence of ADDs including one 838 @ involving the PC, and decorate them with PC-relative group 839 @ relocations. As these are ARM only, switch to ARM mode first. 840 @ 841 @ We enter here with IP clobbered and its value stashed on the mode 842 @ stack. 843 @ 844THUMB( bx pc ) 845THUMB( nop ) 846THUMB( .arm ) 847 ldr_this_cpu_armv6 ip, overflow_stack_ptr 848 849 str sp, [ip, #-4]! @ Preserve original SP value 850 mov sp, ip @ Switch to overflow stack 851 pop {ip} @ Original SP in IP 852 853#if defined(CONFIG_UNWINDER_FRAME_POINTER) && defined(CONFIG_CC_IS_GCC) 854 mov ip, ip @ mov expected by unwinder 855 push {fp, ip, lr, pc} @ GCC flavor frame record 856#else 857 str ip, [sp, #-8]! @ store original SP 858 push {fpreg, lr} @ Clang flavor frame record 859#endif 860UNWIND( ldr ip, [r0, #4] ) @ load exception LR 861UNWIND( str ip, [sp, #12] ) @ store in the frame record 862 ldr ip, [r0, #12] @ reload IP 863 864 @ Store the original GPRs to the new stack. 865 svc_entry uaccess=0, overflow_check=0 866 867UNWIND( .save {sp, pc} ) 868UNWIND( .save {fpreg, lr} ) 869UNWIND( .setfp fpreg, sp ) 870 871 ldr fpreg, [sp, #S_SP] @ Add our frame record 872 @ to the linked list 873#if defined(CONFIG_UNWINDER_FRAME_POINTER) && defined(CONFIG_CC_IS_GCC) 874 ldr r1, [fp, #4] @ reload SP at entry 875 add fp, fp, #12 876#else 877 ldr r1, [fpreg, #8] 878#endif 879 str r1, [sp, #S_SP] @ store in pt_regs 880 881 @ Stash the regs for handle_bad_stack 882 mov r0, sp 883 884 @ Time to die 885 bl handle_bad_stack 886 nop 887UNWIND( .fnend ) 888ENDPROC(__bad_stack) 889#endif 890 891 __INIT 892 893/* 894 * User helpers. 895 * 896 * Each segment is 32-byte aligned and will be moved to the top of the high 897 * vector page. New segments (if ever needed) must be added in front of 898 * existing ones. This mechanism should be used only for things that are 899 * really small and justified, and not be abused freely. 900 * 901 * See Documentation/arm/kernel_user_helpers.rst for formal definitions. 902 */ 903 THUMB( .arm ) 904 905 .macro usr_ret, reg 906#ifdef CONFIG_ARM_THUMB 907 bx \reg 908#else 909 ret \reg 910#endif 911 .endm 912 913 .macro kuser_pad, sym, size 914 .if (. - \sym) & 3 915 .rept 4 - (. - \sym) & 3 916 .byte 0 917 .endr 918 .endif 919 .rept (\size - (. - \sym)) / 4 920 .word 0xe7fddef1 921 .endr 922 .endm 923 924#ifdef CONFIG_KUSER_HELPERS 925 .align 5 926 .globl __kuser_helper_start 927__kuser_helper_start: 928 929/* 930 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular 931 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. 932 */ 933 934__kuser_cmpxchg64: @ 0xffff0f60 935 936#if defined(CONFIG_CPU_32v6K) 937 938 stmfd sp!, {r4, r5, r6, r7} 939 ldrd r4, r5, [r0] @ load old val 940 ldrd r6, r7, [r1] @ load new val 941 smp_dmb arm 9421: ldrexd r0, r1, [r2] @ load current val 943 eors r3, r0, r4 @ compare with oldval (1) 944 eorseq r3, r1, r5 @ compare with oldval (2) 945 strexdeq r3, r6, r7, [r2] @ store newval if eq 946 teqeq r3, #1 @ success? 947 beq 1b @ if no then retry 948 smp_dmb arm 949 rsbs r0, r3, #0 @ set returned val and C flag 950 ldmfd sp!, {r4, r5, r6, r7} 951 usr_ret lr 952 953#elif !defined(CONFIG_SMP) 954 955#ifdef CONFIG_MMU 956 957 /* 958 * The only thing that can break atomicity in this cmpxchg64 959 * implementation is either an IRQ or a data abort exception 960 * causing another process/thread to be scheduled in the middle of 961 * the critical sequence. The same strategy as for cmpxchg is used. 962 */ 963 stmfd sp!, {r4, r5, r6, lr} 964 ldmia r0, {r4, r5} @ load old val 965 ldmia r1, {r6, lr} @ load new val 9661: ldmia r2, {r0, r1} @ load current val 967 eors r3, r0, r4 @ compare with oldval (1) 968 eorseq r3, r1, r5 @ compare with oldval (2) 9692: stmiaeq r2, {r6, lr} @ store newval if eq 970 rsbs r0, r3, #0 @ set return val and C flag 971 ldmfd sp!, {r4, r5, r6, pc} 972 973 .text 974kuser_cmpxchg64_fixup: 975 @ Called from kuser_cmpxchg_fixup. 976 @ r4 = address of interrupted insn (must be preserved). 977 @ sp = saved regs. r7 and r8 are clobbered. 978 @ 1b = first critical insn, 2b = last critical insn. 979 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 980 mov r7, #0xffff0fff 981 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) 982 subs r8, r4, r7 983 rsbscs r8, r8, #(2b - 1b) 984 strcs r7, [sp, #S_PC] 985#if __LINUX_ARM_ARCH__ < 6 986 bcc kuser_cmpxchg32_fixup 987#endif 988 ret lr 989 .previous 990 991#else 992#warning "NPTL on non MMU needs fixing" 993 mov r0, #-1 994 adds r0, r0, #0 995 usr_ret lr 996#endif 997 998#else 999#error "incoherent kernel configuration" 1000#endif 1001 1002 kuser_pad __kuser_cmpxchg64, 64 1003 1004__kuser_memory_barrier: @ 0xffff0fa0 1005 smp_dmb arm 1006 usr_ret lr 1007 1008 kuser_pad __kuser_memory_barrier, 32 1009 1010__kuser_cmpxchg: @ 0xffff0fc0 1011 1012#if __LINUX_ARM_ARCH__ < 6 1013 1014#ifdef CONFIG_MMU 1015 1016 /* 1017 * The only thing that can break atomicity in this cmpxchg 1018 * implementation is either an IRQ or a data abort exception 1019 * causing another process/thread to be scheduled in the middle 1020 * of the critical sequence. To prevent this, code is added to 1021 * the IRQ and data abort exception handlers to set the pc back 1022 * to the beginning of the critical section if it is found to be 1023 * within that critical section (see kuser_cmpxchg_fixup). 1024 */ 10251: ldr r3, [r2] @ load current val 1026 subs r3, r3, r0 @ compare with oldval 10272: streq r1, [r2] @ store newval if eq 1028 rsbs r0, r3, #0 @ set return val and C flag 1029 usr_ret lr 1030 1031 .text 1032kuser_cmpxchg32_fixup: 1033 @ Called from kuser_cmpxchg_check macro. 1034 @ r4 = address of interrupted insn (must be preserved). 1035 @ sp = saved regs. r7 and r8 are clobbered. 1036 @ 1b = first critical insn, 2b = last critical insn. 1037 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 1038 mov r7, #0xffff0fff 1039 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 1040 subs r8, r4, r7 1041 rsbscs r8, r8, #(2b - 1b) 1042 strcs r7, [sp, #S_PC] 1043 ret lr 1044 .previous 1045 1046#else 1047#warning "NPTL on non MMU needs fixing" 1048 mov r0, #-1 1049 adds r0, r0, #0 1050 usr_ret lr 1051#endif 1052 1053#else 1054 1055 smp_dmb arm 10561: ldrex r3, [r2] 1057 subs r3, r3, r0 1058 strexeq r3, r1, [r2] 1059 teqeq r3, #1 1060 beq 1b 1061 rsbs r0, r3, #0 1062 /* beware -- each __kuser slot must be 8 instructions max */ 1063 ALT_SMP(b __kuser_memory_barrier) 1064 ALT_UP(usr_ret lr) 1065 1066#endif 1067 1068 kuser_pad __kuser_cmpxchg, 32 1069 1070__kuser_get_tls: @ 0xffff0fe0 1071 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init 1072 usr_ret lr 1073 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code 1074 kuser_pad __kuser_get_tls, 16 1075 .rep 3 1076 .word 0 @ 0xffff0ff0 software TLS value, then 1077 .endr @ pad up to __kuser_helper_version 1078 1079__kuser_helper_version: @ 0xffff0ffc 1080 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 1081 1082 .globl __kuser_helper_end 1083__kuser_helper_end: 1084 1085#endif 1086 1087 THUMB( .thumb ) 1088 1089/* 1090 * Vector stubs. 1091 * 1092 * This code is copied to 0xffff1000 so we can use branches in the 1093 * vectors, rather than ldr's. Note that this code must not exceed 1094 * a page size. 1095 * 1096 * Common stub entry macro: 1097 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1098 * 1099 * SP points to a minimal amount of processor-private memory, the address 1100 * of which is copied into r0 for the mode specific abort handler. 1101 */ 1102 .macro vector_stub, name, mode, correction=0 1103 .align 5 1104 1105vector_\name: 1106 .if \correction 1107 sub lr, lr, #\correction 1108 .endif 1109 1110 @ Save r0, lr_<exception> (parent PC) 1111 stmia sp, {r0, lr} @ save r0, lr 1112 1113 @ Save spsr_<exception> (parent CPSR) 11142: mrs lr, spsr 1115 str lr, [sp, #8] @ save spsr 1116 1117 @ 1118 @ Prepare for SVC32 mode. IRQs remain disabled. 1119 @ 1120 mrs r0, cpsr 1121 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) 1122 msr spsr_cxsf, r0 1123 1124 @ 1125 @ the branch table must immediately follow this code 1126 @ 1127 and lr, lr, #0x0f 1128 THUMB( adr r0, 1f ) 1129 THUMB( ldr lr, [r0, lr, lsl #2] ) 1130 mov r0, sp 1131 ARM( ldr lr, [pc, lr, lsl #2] ) 1132 movs pc, lr @ branch to handler in SVC mode 1133ENDPROC(vector_\name) 1134 1135#ifdef CONFIG_HARDEN_BRANCH_HISTORY 1136 .subsection 1 1137 .align 5 1138vector_bhb_loop8_\name: 1139 .if \correction 1140 sub lr, lr, #\correction 1141 .endif 1142 1143 @ Save r0, lr_<exception> (parent PC) 1144 stmia sp, {r0, lr} 1145 1146 @ bhb workaround 1147 mov r0, #8 11483: b . + 4 1149 subs r0, r0, #1 1150 bne 3b 1151 dsb 1152 isb 1153 b 2b 1154ENDPROC(vector_bhb_loop8_\name) 1155 1156vector_bhb_bpiall_\name: 1157 .if \correction 1158 sub lr, lr, #\correction 1159 .endif 1160 1161 @ Save r0, lr_<exception> (parent PC) 1162 stmia sp, {r0, lr} 1163 1164 @ bhb workaround 1165 mcr p15, 0, r0, c7, c5, 6 @ BPIALL 1166 @ isb not needed due to "movs pc, lr" in the vector stub 1167 @ which gives a "context synchronisation". 1168 b 2b 1169ENDPROC(vector_bhb_bpiall_\name) 1170 .previous 1171#endif 1172 1173 .align 2 1174 @ handler addresses follow this label 11751: 1176 .endm 1177 1178 .section .stubs, "ax", %progbits 1179 @ This must be the first word 1180 .word vector_swi 1181#ifdef CONFIG_HARDEN_BRANCH_HISTORY 1182 .word vector_bhb_loop8_swi 1183 .word vector_bhb_bpiall_swi 1184#endif 1185 1186vector_rst: 1187 ARM( swi SYS_ERROR0 ) 1188 THUMB( svc #0 ) 1189 THUMB( nop ) 1190 b vector_und 1191 1192/* 1193 * Interrupt dispatcher 1194 */ 1195 vector_stub irq, IRQ_MODE, 4 1196 1197 .long __irq_usr @ 0 (USR_26 / USR_32) 1198 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1199 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 1200 .long __irq_svc @ 3 (SVC_26 / SVC_32) 1201 .long __irq_invalid @ 4 1202 .long __irq_invalid @ 5 1203 .long __irq_invalid @ 6 1204 .long __irq_invalid @ 7 1205 .long __irq_invalid @ 8 1206 .long __irq_invalid @ 9 1207 .long __irq_invalid @ a 1208 .long __irq_invalid @ b 1209 .long __irq_invalid @ c 1210 .long __irq_invalid @ d 1211 .long __irq_invalid @ e 1212 .long __irq_invalid @ f 1213 1214/* 1215 * Data abort dispatcher 1216 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1217 */ 1218 vector_stub dabt, ABT_MODE, 8 1219 1220 .long __dabt_usr @ 0 (USR_26 / USR_32) 1221 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 1222 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 1223 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 1224 .long __dabt_invalid @ 4 1225 .long __dabt_invalid @ 5 1226 .long __dabt_invalid @ 6 1227 .long __dabt_invalid @ 7 1228 .long __dabt_invalid @ 8 1229 .long __dabt_invalid @ 9 1230 .long __dabt_invalid @ a 1231 .long __dabt_invalid @ b 1232 .long __dabt_invalid @ c 1233 .long __dabt_invalid @ d 1234 .long __dabt_invalid @ e 1235 .long __dabt_invalid @ f 1236 1237/* 1238 * Prefetch abort dispatcher 1239 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1240 */ 1241 vector_stub pabt, ABT_MODE, 4 1242 1243 .long __pabt_usr @ 0 (USR_26 / USR_32) 1244 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 1245 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 1246 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 1247 .long __pabt_invalid @ 4 1248 .long __pabt_invalid @ 5 1249 .long __pabt_invalid @ 6 1250 .long __pabt_invalid @ 7 1251 .long __pabt_invalid @ 8 1252 .long __pabt_invalid @ 9 1253 .long __pabt_invalid @ a 1254 .long __pabt_invalid @ b 1255 .long __pabt_invalid @ c 1256 .long __pabt_invalid @ d 1257 .long __pabt_invalid @ e 1258 .long __pabt_invalid @ f 1259 1260/* 1261 * Undef instr entry dispatcher 1262 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1263 */ 1264 vector_stub und, UND_MODE 1265 1266 .long __und_usr @ 0 (USR_26 / USR_32) 1267 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1268 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1269 .long __und_svc @ 3 (SVC_26 / SVC_32) 1270 .long __und_invalid @ 4 1271 .long __und_invalid @ 5 1272 .long __und_invalid @ 6 1273 .long __und_invalid @ 7 1274 .long __und_invalid @ 8 1275 .long __und_invalid @ 9 1276 .long __und_invalid @ a 1277 .long __und_invalid @ b 1278 .long __und_invalid @ c 1279 .long __und_invalid @ d 1280 .long __und_invalid @ e 1281 .long __und_invalid @ f 1282 1283 .align 5 1284 1285/*============================================================================= 1286 * Address exception handler 1287 *----------------------------------------------------------------------------- 1288 * These aren't too critical. 1289 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1290 */ 1291 1292vector_addrexcptn: 1293 b vector_addrexcptn 1294 1295/*============================================================================= 1296 * FIQ "NMI" handler 1297 *----------------------------------------------------------------------------- 1298 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 1299 * systems. This must be the last vector stub, so lets place it in its own 1300 * subsection. 1301 */ 1302 .subsection 2 1303 vector_stub fiq, FIQ_MODE, 4 1304 1305 .long __fiq_usr @ 0 (USR_26 / USR_32) 1306 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32) 1307 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32) 1308 .long __fiq_svc @ 3 (SVC_26 / SVC_32) 1309 .long __fiq_svc @ 4 1310 .long __fiq_svc @ 5 1311 .long __fiq_svc @ 6 1312 .long __fiq_abt @ 7 1313 .long __fiq_svc @ 8 1314 .long __fiq_svc @ 9 1315 .long __fiq_svc @ a 1316 .long __fiq_svc @ b 1317 .long __fiq_svc @ c 1318 .long __fiq_svc @ d 1319 .long __fiq_svc @ e 1320 .long __fiq_svc @ f 1321 1322 .globl vector_fiq 1323 1324 .section .vectors, "ax", %progbits 1325.L__vectors_start: 1326 W(b) vector_rst 1327 W(b) vector_und 1328 W(ldr) pc, .L__vectors_start + 0x1000 1329 W(b) vector_pabt 1330 W(b) vector_dabt 1331 W(b) vector_addrexcptn 1332 W(b) vector_irq 1333 W(b) vector_fiq 1334 1335#ifdef CONFIG_HARDEN_BRANCH_HISTORY 1336 .section .vectors.bhb.loop8, "ax", %progbits 1337.L__vectors_bhb_loop8_start: 1338 W(b) vector_rst 1339 W(b) vector_bhb_loop8_und 1340 W(ldr) pc, .L__vectors_bhb_loop8_start + 0x1004 1341 W(b) vector_bhb_loop8_pabt 1342 W(b) vector_bhb_loop8_dabt 1343 W(b) vector_addrexcptn 1344 W(b) vector_bhb_loop8_irq 1345 W(b) vector_bhb_loop8_fiq 1346 1347 .section .vectors.bhb.bpiall, "ax", %progbits 1348.L__vectors_bhb_bpiall_start: 1349 W(b) vector_rst 1350 W(b) vector_bhb_bpiall_und 1351 W(ldr) pc, .L__vectors_bhb_bpiall_start + 0x1008 1352 W(b) vector_bhb_bpiall_pabt 1353 W(b) vector_bhb_bpiall_dabt 1354 W(b) vector_addrexcptn 1355 W(b) vector_bhb_bpiall_irq 1356 W(b) vector_bhb_bpiall_fiq 1357#endif 1358 1359 .data 1360 .align 2 1361 1362 .globl cr_alignment 1363cr_alignment: 1364 .space 4 1365