1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MPC5200 General Purpose Timer device driver 4 * 5 * Copyright (c) 2009 Secret Lab Technologies Ltd. 6 * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix 7 * 8 * This file is a driver for the General Purpose Timer (gpt) devices 9 * found on the MPC5200 SoC. Each timer has an IO pin which can be used 10 * for GPIO or can be used to raise interrupts. The timer function can 11 * be used independently from the IO pin, or it can be used to control 12 * output signals or measure input signals. 13 * 14 * This driver supports the GPIO and IRQ controller functions of the GPT 15 * device. Timer functions are not yet supported. 16 * 17 * The timer gpt0 can be used as watchdog (wdt). If the wdt mode is used, 18 * this prevents the use of any gpt0 gpt function (i.e. they will fail with 19 * -EBUSY). Thus, the safety wdt function always has precedence over the gpt 20 * function. If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT, 21 * this means that gpt0 is locked in wdt mode until the next reboot - this 22 * may be a requirement in safety applications. 23 * 24 * To use the GPIO function, the following two properties must be added 25 * to the device tree node for the gpt device (typically in the .dts file 26 * for the board): 27 * gpio-controller; 28 * #gpio-cells = < 2 >; 29 * This driver will register the GPIO pin if it finds the gpio-controller 30 * property in the device tree. 31 * 32 * To use the IRQ controller function, the following two properties must 33 * be added to the device tree node for the gpt device: 34 * interrupt-controller; 35 * #interrupt-cells = < 1 >; 36 * The IRQ controller binding only uses one cell to specify the interrupt, 37 * and the IRQ flags are encoded in the cell. A cell is not used to encode 38 * the IRQ number because the GPT only has a single IRQ source. For flags, 39 * a value of '1' means rising edge sensitive and '2' means falling edge. 40 * 41 * The GPIO and the IRQ controller functions can be used at the same time, 42 * but in this use case the IO line will only work as an input. Trying to 43 * use it as a GPIO output will not work. 44 * 45 * When using the GPIO line as an output, it can either be driven as normal 46 * IO, or it can be an Open Collector (OC) output. At the moment it is the 47 * responsibility of either the bootloader or the platform setup code to set 48 * the output mode. This driver does not change the output mode setting. 49 */ 50 51 #include <linux/device.h> 52 #include <linux/irq.h> 53 #include <linux/interrupt.h> 54 #include <linux/io.h> 55 #include <linux/list.h> 56 #include <linux/mutex.h> 57 #include <linux/of.h> 58 #include <linux/of_address.h> 59 #include <linux/of_irq.h> 60 #include <linux/of_platform.h> 61 #include <linux/of_gpio.h> 62 #include <linux/kernel.h> 63 #include <linux/slab.h> 64 #include <linux/fs.h> 65 #include <linux/watchdog.h> 66 #include <linux/miscdevice.h> 67 #include <linux/uaccess.h> 68 #include <linux/module.h> 69 #include <asm/div64.h> 70 #include <asm/mpc52xx.h> 71 72 MODULE_DESCRIPTION("Freescale MPC52xx gpt driver"); 73 MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß"); 74 MODULE_LICENSE("GPL"); 75 76 /** 77 * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver 78 * @dev: pointer to device structure 79 * @regs: virtual address of GPT registers 80 * @lock: spinlock to coordinate between different functions. 81 * @gc: gpio_chip instance structure; used when GPIO is enabled 82 * @irqhost: Pointer to irq_domain instance; used when IRQ mode is supported 83 * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates 84 * if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates 85 * if the timer is actively used as wdt which blocks gpt functions 86 */ 87 struct mpc52xx_gpt_priv { 88 struct list_head list; /* List of all GPT devices */ 89 struct device *dev; 90 struct mpc52xx_gpt __iomem *regs; 91 raw_spinlock_t lock; 92 struct irq_domain *irqhost; 93 u32 ipb_freq; 94 u8 wdt_mode; 95 96 #if defined(CONFIG_GPIOLIB) 97 struct gpio_chip gc; 98 #endif 99 }; 100 101 LIST_HEAD(mpc52xx_gpt_list); 102 DEFINE_MUTEX(mpc52xx_gpt_list_mutex); 103 104 #define MPC52xx_GPT_MODE_MS_MASK (0x07) 105 #define MPC52xx_GPT_MODE_MS_IC (0x01) 106 #define MPC52xx_GPT_MODE_MS_OC (0x02) 107 #define MPC52xx_GPT_MODE_MS_PWM (0x03) 108 #define MPC52xx_GPT_MODE_MS_GPIO (0x04) 109 110 #define MPC52xx_GPT_MODE_GPIO_MASK (0x30) 111 #define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20) 112 #define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30) 113 114 #define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000) 115 #define MPC52xx_GPT_MODE_CONTINUOUS (0x0400) 116 #define MPC52xx_GPT_MODE_OPEN_DRAIN (0x0200) 117 #define MPC52xx_GPT_MODE_IRQ_EN (0x0100) 118 #define MPC52xx_GPT_MODE_WDT_EN (0x8000) 119 120 #define MPC52xx_GPT_MODE_ICT_MASK (0x030000) 121 #define MPC52xx_GPT_MODE_ICT_RISING (0x010000) 122 #define MPC52xx_GPT_MODE_ICT_FALLING (0x020000) 123 #define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000) 124 125 #define MPC52xx_GPT_MODE_WDT_PING (0xa5) 126 127 #define MPC52xx_GPT_STATUS_IRQMASK (0x000f) 128 129 #define MPC52xx_GPT_CAN_WDT (1 << 0) 130 #define MPC52xx_GPT_IS_WDT (1 << 1) 131 132 133 /* --------------------------------------------------------------------- 134 * Cascaded interrupt controller hooks 135 */ 136 137 static void mpc52xx_gpt_irq_unmask(struct irq_data *d) 138 { 139 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); 140 unsigned long flags; 141 142 raw_spin_lock_irqsave(&gpt->lock, flags); 143 setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); 144 raw_spin_unlock_irqrestore(&gpt->lock, flags); 145 } 146 147 static void mpc52xx_gpt_irq_mask(struct irq_data *d) 148 { 149 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); 150 unsigned long flags; 151 152 raw_spin_lock_irqsave(&gpt->lock, flags); 153 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); 154 raw_spin_unlock_irqrestore(&gpt->lock, flags); 155 } 156 157 static void mpc52xx_gpt_irq_ack(struct irq_data *d) 158 { 159 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); 160 161 out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK); 162 } 163 164 static int mpc52xx_gpt_irq_set_type(struct irq_data *d, unsigned int flow_type) 165 { 166 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); 167 unsigned long flags; 168 u32 reg; 169 170 dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type); 171 172 raw_spin_lock_irqsave(&gpt->lock, flags); 173 reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK; 174 if (flow_type & IRQF_TRIGGER_RISING) 175 reg |= MPC52xx_GPT_MODE_ICT_RISING; 176 if (flow_type & IRQF_TRIGGER_FALLING) 177 reg |= MPC52xx_GPT_MODE_ICT_FALLING; 178 out_be32(&gpt->regs->mode, reg); 179 raw_spin_unlock_irqrestore(&gpt->lock, flags); 180 181 return 0; 182 } 183 184 static struct irq_chip mpc52xx_gpt_irq_chip = { 185 .name = "MPC52xx GPT", 186 .irq_unmask = mpc52xx_gpt_irq_unmask, 187 .irq_mask = mpc52xx_gpt_irq_mask, 188 .irq_ack = mpc52xx_gpt_irq_ack, 189 .irq_set_type = mpc52xx_gpt_irq_set_type, 190 }; 191 192 static void mpc52xx_gpt_irq_cascade(struct irq_desc *desc) 193 { 194 struct mpc52xx_gpt_priv *gpt = irq_desc_get_handler_data(desc); 195 u32 status; 196 197 status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK; 198 if (status) 199 generic_handle_domain_irq(gpt->irqhost, 0); 200 } 201 202 static int mpc52xx_gpt_irq_map(struct irq_domain *h, unsigned int virq, 203 irq_hw_number_t hw) 204 { 205 struct mpc52xx_gpt_priv *gpt = h->host_data; 206 207 dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq); 208 irq_set_chip_data(virq, gpt); 209 irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq); 210 211 return 0; 212 } 213 214 static int mpc52xx_gpt_irq_xlate(struct irq_domain *h, struct device_node *ct, 215 const u32 *intspec, unsigned int intsize, 216 irq_hw_number_t *out_hwirq, 217 unsigned int *out_flags) 218 { 219 struct mpc52xx_gpt_priv *gpt = h->host_data; 220 221 dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]); 222 223 if ((intsize < 1) || (intspec[0] > 3)) { 224 dev_err(gpt->dev, "bad irq specifier in %pOF\n", ct); 225 return -EINVAL; 226 } 227 228 *out_hwirq = 0; /* The GPT only has 1 IRQ line */ 229 *out_flags = intspec[0]; 230 231 return 0; 232 } 233 234 static const struct irq_domain_ops mpc52xx_gpt_irq_ops = { 235 .map = mpc52xx_gpt_irq_map, 236 .xlate = mpc52xx_gpt_irq_xlate, 237 }; 238 239 static void 240 mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node) 241 { 242 int cascade_virq; 243 unsigned long flags; 244 u32 mode; 245 246 cascade_virq = irq_of_parse_and_map(node, 0); 247 if (!cascade_virq) 248 return; 249 250 gpt->irqhost = irq_domain_add_linear(node, 1, &mpc52xx_gpt_irq_ops, gpt); 251 if (!gpt->irqhost) { 252 dev_err(gpt->dev, "irq_domain_add_linear() failed\n"); 253 return; 254 } 255 256 irq_set_handler_data(cascade_virq, gpt); 257 irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade); 258 259 /* If the GPT is currently disabled, then change it to be in Input 260 * Capture mode. If the mode is non-zero, then the pin could be 261 * already in use for something. */ 262 raw_spin_lock_irqsave(&gpt->lock, flags); 263 mode = in_be32(&gpt->regs->mode); 264 if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0) 265 out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC); 266 raw_spin_unlock_irqrestore(&gpt->lock, flags); 267 268 dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq); 269 } 270 271 272 /* --------------------------------------------------------------------- 273 * GPIOLIB hooks 274 */ 275 #if defined(CONFIG_GPIOLIB) 276 static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio) 277 { 278 struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc); 279 280 return (in_be32(&gpt->regs->status) >> 8) & 1; 281 } 282 283 static void 284 mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v) 285 { 286 struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc); 287 unsigned long flags; 288 u32 r; 289 290 dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v); 291 r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW; 292 293 raw_spin_lock_irqsave(&gpt->lock, flags); 294 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r); 295 raw_spin_unlock_irqrestore(&gpt->lock, flags); 296 } 297 298 static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 299 { 300 struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc); 301 unsigned long flags; 302 303 dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio); 304 305 raw_spin_lock_irqsave(&gpt->lock, flags); 306 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK); 307 raw_spin_unlock_irqrestore(&gpt->lock, flags); 308 309 return 0; 310 } 311 312 static int 313 mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 314 { 315 mpc52xx_gpt_gpio_set(gc, gpio, val); 316 return 0; 317 } 318 319 static void 320 mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node) 321 { 322 int rc; 323 324 /* Only setup GPIO if the device tree claims the GPT is 325 * a GPIO controller */ 326 if (!of_find_property(node, "gpio-controller", NULL)) 327 return; 328 329 gpt->gc.label = kasprintf(GFP_KERNEL, "%pOF", node); 330 if (!gpt->gc.label) { 331 dev_err(gpt->dev, "out of memory\n"); 332 return; 333 } 334 335 gpt->gc.ngpio = 1; 336 gpt->gc.direction_input = mpc52xx_gpt_gpio_dir_in; 337 gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out; 338 gpt->gc.get = mpc52xx_gpt_gpio_get; 339 gpt->gc.set = mpc52xx_gpt_gpio_set; 340 gpt->gc.base = -1; 341 gpt->gc.of_node = node; 342 343 /* Setup external pin in GPIO mode */ 344 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK, 345 MPC52xx_GPT_MODE_MS_GPIO); 346 347 rc = gpiochip_add_data(&gpt->gc, gpt); 348 if (rc) 349 dev_err(gpt->dev, "gpiochip_add_data() failed; rc=%i\n", rc); 350 351 dev_dbg(gpt->dev, "%s() complete.\n", __func__); 352 } 353 #else /* defined(CONFIG_GPIOLIB) */ 354 static void 355 mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { } 356 #endif /* defined(CONFIG_GPIOLIB) */ 357 358 /*********************************************************************** 359 * Timer API 360 */ 361 362 /** 363 * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number 364 * @irq: irq of timer. 365 */ 366 struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq) 367 { 368 struct mpc52xx_gpt_priv *gpt; 369 struct list_head *pos; 370 371 /* Iterate over the list of timers looking for a matching device */ 372 mutex_lock(&mpc52xx_gpt_list_mutex); 373 list_for_each(pos, &mpc52xx_gpt_list) { 374 gpt = container_of(pos, struct mpc52xx_gpt_priv, list); 375 if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) { 376 mutex_unlock(&mpc52xx_gpt_list_mutex); 377 return gpt; 378 } 379 } 380 mutex_unlock(&mpc52xx_gpt_list_mutex); 381 382 return NULL; 383 } 384 EXPORT_SYMBOL(mpc52xx_gpt_from_irq); 385 386 static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period, 387 int continuous, int as_wdt) 388 { 389 u32 clear, set; 390 u64 clocks; 391 u32 prescale; 392 unsigned long flags; 393 394 clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS; 395 set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE; 396 if (as_wdt) { 397 clear |= MPC52xx_GPT_MODE_IRQ_EN; 398 set |= MPC52xx_GPT_MODE_WDT_EN; 399 } else if (continuous) 400 set |= MPC52xx_GPT_MODE_CONTINUOUS; 401 402 /* Determine the number of clocks in the requested period. 64 bit 403 * arithmetic is done here to preserve the precision until the value 404 * is scaled back down into the u32 range. Period is in 'ns', bus 405 * frequency is in Hz. */ 406 clocks = period * (u64)gpt->ipb_freq; 407 do_div(clocks, 1000000000); /* Scale it down to ns range */ 408 409 /* This device cannot handle a clock count greater than 32 bits */ 410 if (clocks > 0xffffffff) 411 return -EINVAL; 412 413 /* Calculate the prescaler and count values from the clocks value. 414 * 'clocks' is the number of clock ticks in the period. The timer 415 * has 16 bit precision and a 16 bit prescaler. Prescaler is 416 * calculated by integer dividing the clocks by 0x10000 (shifting 417 * down 16 bits) to obtain the smallest possible divisor for clocks 418 * to get a 16 bit count value. 419 * 420 * Note: the prescale register is '1' based, not '0' based. ie. a 421 * value of '1' means divide the clock by one. 0xffff divides the 422 * clock by 0xffff. '0x0000' does not divide by zero, but wraps 423 * around and divides by 0x10000. That is why prescale must be 424 * a u32 variable, not a u16, for this calculation. */ 425 prescale = (clocks >> 16) + 1; 426 do_div(clocks, prescale); 427 if (clocks > 0xffff) { 428 pr_err("calculation error; prescale:%x clocks:%llx\n", 429 prescale, clocks); 430 return -EINVAL; 431 } 432 433 /* Set and enable the timer, reject an attempt to use a wdt as gpt */ 434 raw_spin_lock_irqsave(&gpt->lock, flags); 435 if (as_wdt) 436 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT; 437 else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) { 438 raw_spin_unlock_irqrestore(&gpt->lock, flags); 439 return -EBUSY; 440 } 441 out_be32(&gpt->regs->count, prescale << 16 | clocks); 442 clrsetbits_be32(&gpt->regs->mode, clear, set); 443 raw_spin_unlock_irqrestore(&gpt->lock, flags); 444 445 return 0; 446 } 447 448 /** 449 * mpc52xx_gpt_start_timer - Set and enable the GPT timer 450 * @gpt: Pointer to gpt private data structure 451 * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock 452 * @continuous: set to 1 to make timer continuous free running 453 * 454 * An interrupt will be generated every time the timer fires 455 */ 456 int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period, 457 int continuous) 458 { 459 return mpc52xx_gpt_do_start(gpt, period, continuous, 0); 460 } 461 EXPORT_SYMBOL(mpc52xx_gpt_start_timer); 462 463 /** 464 * mpc52xx_gpt_stop_timer - Stop a gpt 465 * @gpt: Pointer to gpt private data structure 466 * 467 * Returns an error if attempting to stop a wdt 468 */ 469 int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt) 470 { 471 unsigned long flags; 472 473 /* reject the operation if the timer is used as watchdog (gpt 0 only) */ 474 raw_spin_lock_irqsave(&gpt->lock, flags); 475 if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) { 476 raw_spin_unlock_irqrestore(&gpt->lock, flags); 477 return -EBUSY; 478 } 479 480 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE); 481 raw_spin_unlock_irqrestore(&gpt->lock, flags); 482 return 0; 483 } 484 EXPORT_SYMBOL(mpc52xx_gpt_stop_timer); 485 486 /** 487 * mpc52xx_gpt_timer_period - Read the timer period 488 * @gpt: Pointer to gpt private data structure 489 * 490 * Returns the timer period in ns 491 */ 492 u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt) 493 { 494 u64 period; 495 u64 prescale; 496 unsigned long flags; 497 498 raw_spin_lock_irqsave(&gpt->lock, flags); 499 period = in_be32(&gpt->regs->count); 500 raw_spin_unlock_irqrestore(&gpt->lock, flags); 501 502 prescale = period >> 16; 503 period &= 0xffff; 504 if (prescale == 0) 505 prescale = 0x10000; 506 period = period * prescale * 1000000000ULL; 507 do_div(period, gpt->ipb_freq); 508 return period; 509 } 510 EXPORT_SYMBOL(mpc52xx_gpt_timer_period); 511 512 #if defined(CONFIG_MPC5200_WDT) 513 /*********************************************************************** 514 * Watchdog API for gpt0 515 */ 516 517 #define WDT_IDENTITY "mpc52xx watchdog on GPT0" 518 519 /* wdt_is_active stores whether or not the /dev/watchdog device is opened */ 520 static unsigned long wdt_is_active; 521 522 /* wdt-capable gpt */ 523 static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt; 524 525 /* low-level wdt functions */ 526 static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt) 527 { 528 unsigned long flags; 529 530 raw_spin_lock_irqsave(&gpt_wdt->lock, flags); 531 out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING); 532 raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags); 533 } 534 535 /* wdt misc device api */ 536 static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data, 537 size_t len, loff_t *ppos) 538 { 539 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data; 540 mpc52xx_gpt_wdt_ping(gpt_wdt); 541 return 0; 542 } 543 544 static const struct watchdog_info mpc5200_wdt_info = { 545 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, 546 .identity = WDT_IDENTITY, 547 }; 548 549 static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd, 550 unsigned long arg) 551 { 552 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data; 553 int __user *data = (int __user *)arg; 554 int timeout; 555 u64 real_timeout; 556 int ret = 0; 557 558 switch (cmd) { 559 case WDIOC_GETSUPPORT: 560 ret = copy_to_user(data, &mpc5200_wdt_info, 561 sizeof(mpc5200_wdt_info)); 562 if (ret) 563 ret = -EFAULT; 564 break; 565 566 case WDIOC_GETSTATUS: 567 case WDIOC_GETBOOTSTATUS: 568 ret = put_user(0, data); 569 break; 570 571 case WDIOC_KEEPALIVE: 572 mpc52xx_gpt_wdt_ping(gpt_wdt); 573 break; 574 575 case WDIOC_SETTIMEOUT: 576 ret = get_user(timeout, data); 577 if (ret) 578 break; 579 real_timeout = (u64) timeout * 1000000000ULL; 580 ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1); 581 if (ret) 582 break; 583 /* fall through and return the timeout */ 584 fallthrough; 585 586 case WDIOC_GETTIMEOUT: 587 /* we need to round here as to avoid e.g. the following 588 * situation: 589 * - timeout requested is 1 second; 590 * - real timeout @33MHz is 999997090ns 591 * - the int divide by 10^9 will return 0. 592 */ 593 real_timeout = 594 mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL; 595 do_div(real_timeout, 1000000000ULL); 596 timeout = (int) real_timeout; 597 ret = put_user(timeout, data); 598 break; 599 600 default: 601 ret = -ENOTTY; 602 } 603 return ret; 604 } 605 606 static int mpc52xx_wdt_open(struct inode *inode, struct file *file) 607 { 608 int ret; 609 610 /* sanity check */ 611 if (!mpc52xx_gpt_wdt) 612 return -ENODEV; 613 614 /* /dev/watchdog can only be opened once */ 615 if (test_and_set_bit(0, &wdt_is_active)) 616 return -EBUSY; 617 618 /* Set and activate the watchdog with 30 seconds timeout */ 619 ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL, 620 0, 1); 621 if (ret) { 622 clear_bit(0, &wdt_is_active); 623 return ret; 624 } 625 626 file->private_data = mpc52xx_gpt_wdt; 627 return stream_open(inode, file); 628 } 629 630 static int mpc52xx_wdt_release(struct inode *inode, struct file *file) 631 { 632 /* note: releasing the wdt in NOWAYOUT-mode does not stop it */ 633 #if !defined(CONFIG_WATCHDOG_NOWAYOUT) 634 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data; 635 unsigned long flags; 636 637 raw_spin_lock_irqsave(&gpt_wdt->lock, flags); 638 clrbits32(&gpt_wdt->regs->mode, 639 MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN); 640 gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT; 641 raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags); 642 #endif 643 clear_bit(0, &wdt_is_active); 644 return 0; 645 } 646 647 648 static const struct file_operations mpc52xx_wdt_fops = { 649 .owner = THIS_MODULE, 650 .llseek = no_llseek, 651 .write = mpc52xx_wdt_write, 652 .unlocked_ioctl = mpc52xx_wdt_ioctl, 653 .compat_ioctl = compat_ptr_ioctl, 654 .open = mpc52xx_wdt_open, 655 .release = mpc52xx_wdt_release, 656 }; 657 658 static struct miscdevice mpc52xx_wdt_miscdev = { 659 .minor = WATCHDOG_MINOR, 660 .name = "watchdog", 661 .fops = &mpc52xx_wdt_fops, 662 }; 663 664 static int mpc52xx_gpt_wdt_init(void) 665 { 666 int err; 667 668 /* try to register the watchdog misc device */ 669 err = misc_register(&mpc52xx_wdt_miscdev); 670 if (err) 671 pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY); 672 else 673 pr_info("%s: watchdog device registered\n", WDT_IDENTITY); 674 return err; 675 } 676 677 static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt, 678 const u32 *period) 679 { 680 u64 real_timeout; 681 682 /* remember the gpt for the wdt operation */ 683 mpc52xx_gpt_wdt = gpt; 684 685 /* configure the wdt if the device tree contained a timeout */ 686 if (!period || *period == 0) 687 return 0; 688 689 real_timeout = (u64) *period * 1000000000ULL; 690 if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1)) 691 dev_warn(gpt->dev, "starting as wdt failed\n"); 692 else 693 dev_info(gpt->dev, "watchdog set to %us timeout\n", *period); 694 return 0; 695 } 696 697 #else 698 699 static int mpc52xx_gpt_wdt_init(void) 700 { 701 return 0; 702 } 703 704 static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt, 705 const u32 *period) 706 { 707 return 0; 708 } 709 710 #endif /* CONFIG_MPC5200_WDT */ 711 712 /* --------------------------------------------------------------------- 713 * of_platform bus binding code 714 */ 715 static int mpc52xx_gpt_probe(struct platform_device *ofdev) 716 { 717 struct mpc52xx_gpt_priv *gpt; 718 719 gpt = devm_kzalloc(&ofdev->dev, sizeof *gpt, GFP_KERNEL); 720 if (!gpt) 721 return -ENOMEM; 722 723 raw_spin_lock_init(&gpt->lock); 724 gpt->dev = &ofdev->dev; 725 gpt->ipb_freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); 726 gpt->regs = of_iomap(ofdev->dev.of_node, 0); 727 if (!gpt->regs) 728 return -ENOMEM; 729 730 dev_set_drvdata(&ofdev->dev, gpt); 731 732 mpc52xx_gpt_gpio_setup(gpt, ofdev->dev.of_node); 733 mpc52xx_gpt_irq_setup(gpt, ofdev->dev.of_node); 734 735 mutex_lock(&mpc52xx_gpt_list_mutex); 736 list_add(&gpt->list, &mpc52xx_gpt_list); 737 mutex_unlock(&mpc52xx_gpt_list_mutex); 738 739 /* check if this device could be a watchdog */ 740 if (of_get_property(ofdev->dev.of_node, "fsl,has-wdt", NULL) || 741 of_get_property(ofdev->dev.of_node, "has-wdt", NULL)) { 742 const u32 *on_boot_wdt; 743 744 gpt->wdt_mode = MPC52xx_GPT_CAN_WDT; 745 on_boot_wdt = of_get_property(ofdev->dev.of_node, 746 "fsl,wdt-on-boot", NULL); 747 if (on_boot_wdt) { 748 dev_info(gpt->dev, "used as watchdog\n"); 749 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT; 750 } else 751 dev_info(gpt->dev, "can function as watchdog\n"); 752 mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt); 753 } 754 755 return 0; 756 } 757 758 static int mpc52xx_gpt_remove(struct platform_device *ofdev) 759 { 760 return -EBUSY; 761 } 762 763 static const struct of_device_id mpc52xx_gpt_match[] = { 764 { .compatible = "fsl,mpc5200-gpt", }, 765 766 /* Depreciated compatible values; don't use for new dts files */ 767 { .compatible = "fsl,mpc5200-gpt-gpio", }, 768 { .compatible = "mpc5200-gpt", }, 769 {} 770 }; 771 772 static struct platform_driver mpc52xx_gpt_driver = { 773 .driver = { 774 .name = "mpc52xx-gpt", 775 .of_match_table = mpc52xx_gpt_match, 776 }, 777 .probe = mpc52xx_gpt_probe, 778 .remove = mpc52xx_gpt_remove, 779 }; 780 781 static int __init mpc52xx_gpt_init(void) 782 { 783 return platform_driver_register(&mpc52xx_gpt_driver); 784 } 785 786 /* Make sure GPIOs and IRQs get set up before anyone tries to use them */ 787 subsys_initcall(mpc52xx_gpt_init); 788 device_initcall(mpc52xx_gpt_wdt_init); 789