1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/iopoll.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/of_address.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 #include <linux/soc/mediatek/mtk-mmsys.h> 14 #include <linux/soc/mediatek/mtk-mutex.h> 15 #include <linux/soc/mediatek/mtk-cmdq.h> 16 17 #define MTK_MUTEX_MAX_HANDLES 10 18 19 #define MT2701_MUTEX0_MOD0 0x2c 20 #define MT2701_MUTEX0_SOF0 0x30 21 #define MT8183_MUTEX0_MOD0 0x30 22 #define MT8183_MUTEX0_SOF0 0x2c 23 24 #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) 25 #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) 26 #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) 27 #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) 28 #define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20 * (n) + 0x4) 29 #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) 30 #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) 31 32 #define INT_MUTEX BIT(1) 33 34 #define MT8186_MUTEX_MOD_DISP_OVL0 0 35 #define MT8186_MUTEX_MOD_DISP_OVL0_2L 1 36 #define MT8186_MUTEX_MOD_DISP_RDMA0 2 37 #define MT8186_MUTEX_MOD_DISP_COLOR0 4 38 #define MT8186_MUTEX_MOD_DISP_CCORR0 5 39 #define MT8186_MUTEX_MOD_DISP_AAL0 7 40 #define MT8186_MUTEX_MOD_DISP_GAMMA0 8 41 #define MT8186_MUTEX_MOD_DISP_POSTMASK0 9 42 #define MT8186_MUTEX_MOD_DISP_DITHER0 10 43 #define MT8186_MUTEX_MOD_DISP_RDMA1 17 44 45 #define MT8186_MUTEX_SOF_SINGLE_MODE 0 46 #define MT8186_MUTEX_SOF_DSI0 1 47 #define MT8186_MUTEX_SOF_DPI0 2 48 #define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6) 49 #define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6) 50 51 #define MT8167_MUTEX_MOD_DISP_PWM 1 52 #define MT8167_MUTEX_MOD_DISP_OVL0 6 53 #define MT8167_MUTEX_MOD_DISP_OVL1 7 54 #define MT8167_MUTEX_MOD_DISP_RDMA0 8 55 #define MT8167_MUTEX_MOD_DISP_RDMA1 9 56 #define MT8167_MUTEX_MOD_DISP_WDMA0 10 57 #define MT8167_MUTEX_MOD_DISP_CCORR 11 58 #define MT8167_MUTEX_MOD_DISP_COLOR 12 59 #define MT8167_MUTEX_MOD_DISP_AAL 13 60 #define MT8167_MUTEX_MOD_DISP_GAMMA 14 61 #define MT8167_MUTEX_MOD_DISP_DITHER 15 62 #define MT8167_MUTEX_MOD_DISP_UFOE 16 63 64 #define MT8192_MUTEX_MOD_DISP_OVL0 0 65 #define MT8192_MUTEX_MOD_DISP_OVL0_2L 1 66 #define MT8192_MUTEX_MOD_DISP_RDMA0 2 67 #define MT8192_MUTEX_MOD_DISP_COLOR0 4 68 #define MT8192_MUTEX_MOD_DISP_CCORR0 5 69 #define MT8192_MUTEX_MOD_DISP_AAL0 6 70 #define MT8192_MUTEX_MOD_DISP_GAMMA0 7 71 #define MT8192_MUTEX_MOD_DISP_POSTMASK0 8 72 #define MT8192_MUTEX_MOD_DISP_DITHER0 9 73 #define MT8192_MUTEX_MOD_DISP_OVL2_2L 16 74 #define MT8192_MUTEX_MOD_DISP_RDMA4 17 75 76 #define MT8183_MUTEX_MOD_DISP_RDMA0 0 77 #define MT8183_MUTEX_MOD_DISP_RDMA1 1 78 #define MT8183_MUTEX_MOD_DISP_OVL0 9 79 #define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 80 #define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 81 #define MT8183_MUTEX_MOD_DISP_WDMA0 12 82 #define MT8183_MUTEX_MOD_DISP_COLOR0 13 83 #define MT8183_MUTEX_MOD_DISP_CCORR0 14 84 #define MT8183_MUTEX_MOD_DISP_AAL0 15 85 #define MT8183_MUTEX_MOD_DISP_GAMMA0 16 86 #define MT8183_MUTEX_MOD_DISP_DITHER0 17 87 88 #define MT8183_MUTEX_MOD_MDP_RDMA0 2 89 #define MT8183_MUTEX_MOD_MDP_RSZ0 4 90 #define MT8183_MUTEX_MOD_MDP_RSZ1 5 91 #define MT8183_MUTEX_MOD_MDP_TDSHP0 6 92 #define MT8183_MUTEX_MOD_MDP_WROT0 7 93 #define MT8183_MUTEX_MOD_MDP_WDMA 8 94 #define MT8183_MUTEX_MOD_MDP_AAL0 23 95 #define MT8183_MUTEX_MOD_MDP_CCORR0 24 96 97 #define MT8186_MUTEX_MOD_MDP_RDMA0 0 98 #define MT8186_MUTEX_MOD_MDP_AAL0 2 99 #define MT8186_MUTEX_MOD_MDP_HDR0 4 100 #define MT8186_MUTEX_MOD_MDP_RSZ0 5 101 #define MT8186_MUTEX_MOD_MDP_RSZ1 6 102 #define MT8186_MUTEX_MOD_MDP_WROT0 7 103 #define MT8186_MUTEX_MOD_MDP_TDSHP0 9 104 #define MT8186_MUTEX_MOD_MDP_COLOR0 14 105 106 #define MT8173_MUTEX_MOD_DISP_OVL0 11 107 #define MT8173_MUTEX_MOD_DISP_OVL1 12 108 #define MT8173_MUTEX_MOD_DISP_RDMA0 13 109 #define MT8173_MUTEX_MOD_DISP_RDMA1 14 110 #define MT8173_MUTEX_MOD_DISP_RDMA2 15 111 #define MT8173_MUTEX_MOD_DISP_WDMA0 16 112 #define MT8173_MUTEX_MOD_DISP_WDMA1 17 113 #define MT8173_MUTEX_MOD_DISP_COLOR0 18 114 #define MT8173_MUTEX_MOD_DISP_COLOR1 19 115 #define MT8173_MUTEX_MOD_DISP_AAL 20 116 #define MT8173_MUTEX_MOD_DISP_GAMMA 21 117 #define MT8173_MUTEX_MOD_DISP_UFOE 22 118 #define MT8173_MUTEX_MOD_DISP_PWM0 23 119 #define MT8173_MUTEX_MOD_DISP_PWM1 24 120 #define MT8173_MUTEX_MOD_DISP_OD 25 121 122 #define MT8188_MUTEX_MOD_DISP_OVL0 0 123 #define MT8188_MUTEX_MOD_DISP_WDMA0 1 124 #define MT8188_MUTEX_MOD_DISP_RDMA0 2 125 #define MT8188_MUTEX_MOD_DISP_COLOR0 3 126 #define MT8188_MUTEX_MOD_DISP_CCORR0 4 127 #define MT8188_MUTEX_MOD_DISP_AAL0 5 128 #define MT8188_MUTEX_MOD_DISP_GAMMA0 6 129 #define MT8188_MUTEX_MOD_DISP_DITHER0 7 130 #define MT8188_MUTEX_MOD_DISP_DSI0 8 131 #define MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 132 #define MT8188_MUTEX_MOD_DISP_VPP_MERGE 20 133 #define MT8188_MUTEX_MOD_DISP_DP_INTF0 21 134 #define MT8188_MUTEX_MOD_DISP_POSTMASK0 24 135 #define MT8188_MUTEX_MOD2_DISP_PWM0 33 136 137 #define MT8195_MUTEX_MOD_DISP_OVL0 0 138 #define MT8195_MUTEX_MOD_DISP_WDMA0 1 139 #define MT8195_MUTEX_MOD_DISP_RDMA0 2 140 #define MT8195_MUTEX_MOD_DISP_COLOR0 3 141 #define MT8195_MUTEX_MOD_DISP_CCORR0 4 142 #define MT8195_MUTEX_MOD_DISP_AAL0 5 143 #define MT8195_MUTEX_MOD_DISP_GAMMA0 6 144 #define MT8195_MUTEX_MOD_DISP_DITHER0 7 145 #define MT8195_MUTEX_MOD_DISP_DSI0 8 146 #define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 147 #define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 148 #define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 149 #define MT8195_MUTEX_MOD_DISP_PWM0 27 150 151 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 0 152 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 1 153 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 2 154 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 3 155 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 4 156 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 5 157 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 6 158 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 7 159 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 8 160 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 9 161 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 10 162 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 11 163 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 12 164 #define MT8195_MUTEX_MOD_DISP1_DISP_MIXER 18 165 #define MT8195_MUTEX_MOD_DISP1_DPI0 25 166 #define MT8195_MUTEX_MOD_DISP1_DPI1 26 167 #define MT8195_MUTEX_MOD_DISP1_DP_INTF0 27 168 169 /* VPPSYS0 */ 170 #define MT8195_MUTEX_MOD_MDP_RDMA0 0 171 #define MT8195_MUTEX_MOD_MDP_FG0 1 172 #define MT8195_MUTEX_MOD_MDP_STITCH0 2 173 #define MT8195_MUTEX_MOD_MDP_HDR0 3 174 #define MT8195_MUTEX_MOD_MDP_AAL0 4 175 #define MT8195_MUTEX_MOD_MDP_RSZ0 5 176 #define MT8195_MUTEX_MOD_MDP_TDSHP0 6 177 #define MT8195_MUTEX_MOD_MDP_COLOR0 7 178 #define MT8195_MUTEX_MOD_MDP_OVL0 8 179 #define MT8195_MUTEX_MOD_MDP_PAD0 9 180 #define MT8195_MUTEX_MOD_MDP_TCC0 10 181 #define MT8195_MUTEX_MOD_MDP_WROT0 11 182 183 /* VPPSYS1 */ 184 #define MT8195_MUTEX_MOD_MDP_TCC1 3 185 #define MT8195_MUTEX_MOD_MDP_RDMA1 4 186 #define MT8195_MUTEX_MOD_MDP_RDMA2 5 187 #define MT8195_MUTEX_MOD_MDP_RDMA3 6 188 #define MT8195_MUTEX_MOD_MDP_FG1 7 189 #define MT8195_MUTEX_MOD_MDP_FG2 8 190 #define MT8195_MUTEX_MOD_MDP_FG3 9 191 #define MT8195_MUTEX_MOD_MDP_HDR1 10 192 #define MT8195_MUTEX_MOD_MDP_HDR2 11 193 #define MT8195_MUTEX_MOD_MDP_HDR3 12 194 #define MT8195_MUTEX_MOD_MDP_AAL1 13 195 #define MT8195_MUTEX_MOD_MDP_AAL2 14 196 #define MT8195_MUTEX_MOD_MDP_AAL3 15 197 #define MT8195_MUTEX_MOD_MDP_RSZ1 16 198 #define MT8195_MUTEX_MOD_MDP_RSZ2 17 199 #define MT8195_MUTEX_MOD_MDP_RSZ3 18 200 #define MT8195_MUTEX_MOD_MDP_TDSHP1 19 201 #define MT8195_MUTEX_MOD_MDP_TDSHP2 20 202 #define MT8195_MUTEX_MOD_MDP_TDSHP3 21 203 #define MT8195_MUTEX_MOD_MDP_MERGE2 22 204 #define MT8195_MUTEX_MOD_MDP_MERGE3 23 205 #define MT8195_MUTEX_MOD_MDP_COLOR1 24 206 #define MT8195_MUTEX_MOD_MDP_COLOR2 25 207 #define MT8195_MUTEX_MOD_MDP_COLOR3 26 208 #define MT8195_MUTEX_MOD_MDP_OVL1 27 209 #define MT8195_MUTEX_MOD_MDP_PAD1 28 210 #define MT8195_MUTEX_MOD_MDP_PAD2 29 211 #define MT8195_MUTEX_MOD_MDP_PAD3 30 212 #define MT8195_MUTEX_MOD_MDP_WROT1 31 213 #define MT8195_MUTEX_MOD_MDP_WROT2 32 214 #define MT8195_MUTEX_MOD_MDP_WROT3 33 215 216 #define MT8365_MUTEX_MOD_DISP_OVL0 7 217 #define MT8365_MUTEX_MOD_DISP_OVL0_2L 8 218 #define MT8365_MUTEX_MOD_DISP_RDMA0 9 219 #define MT8365_MUTEX_MOD_DISP_RDMA1 10 220 #define MT8365_MUTEX_MOD_DISP_WDMA0 11 221 #define MT8365_MUTEX_MOD_DISP_COLOR0 12 222 #define MT8365_MUTEX_MOD_DISP_CCORR 13 223 #define MT8365_MUTEX_MOD_DISP_AAL 14 224 #define MT8365_MUTEX_MOD_DISP_GAMMA 15 225 #define MT8365_MUTEX_MOD_DISP_DITHER 16 226 #define MT8365_MUTEX_MOD_DISP_DSI0 17 227 #define MT8365_MUTEX_MOD_DISP_PWM0 20 228 #define MT8365_MUTEX_MOD_DISP_DPI0 22 229 230 #define MT2712_MUTEX_MOD_DISP_PWM2 10 231 #define MT2712_MUTEX_MOD_DISP_OVL0 11 232 #define MT2712_MUTEX_MOD_DISP_OVL1 12 233 #define MT2712_MUTEX_MOD_DISP_RDMA0 13 234 #define MT2712_MUTEX_MOD_DISP_RDMA1 14 235 #define MT2712_MUTEX_MOD_DISP_RDMA2 15 236 #define MT2712_MUTEX_MOD_DISP_WDMA0 16 237 #define MT2712_MUTEX_MOD_DISP_WDMA1 17 238 #define MT2712_MUTEX_MOD_DISP_COLOR0 18 239 #define MT2712_MUTEX_MOD_DISP_COLOR1 19 240 #define MT2712_MUTEX_MOD_DISP_AAL0 20 241 #define MT2712_MUTEX_MOD_DISP_UFOE 22 242 #define MT2712_MUTEX_MOD_DISP_PWM0 23 243 #define MT2712_MUTEX_MOD_DISP_PWM1 24 244 #define MT2712_MUTEX_MOD_DISP_OD0 25 245 #define MT2712_MUTEX_MOD2_DISP_AAL1 33 246 #define MT2712_MUTEX_MOD2_DISP_OD1 34 247 248 #define MT2701_MUTEX_MOD_DISP_OVL 3 249 #define MT2701_MUTEX_MOD_DISP_WDMA 6 250 #define MT2701_MUTEX_MOD_DISP_COLOR 7 251 #define MT2701_MUTEX_MOD_DISP_BLS 9 252 #define MT2701_MUTEX_MOD_DISP_RDMA0 10 253 #define MT2701_MUTEX_MOD_DISP_RDMA1 12 254 255 #define MT2712_MUTEX_SOF_SINGLE_MODE 0 256 #define MT2712_MUTEX_SOF_DSI0 1 257 #define MT2712_MUTEX_SOF_DSI1 2 258 #define MT2712_MUTEX_SOF_DPI0 3 259 #define MT2712_MUTEX_SOF_DPI1 4 260 #define MT2712_MUTEX_SOF_DSI2 5 261 #define MT2712_MUTEX_SOF_DSI3 6 262 #define MT8167_MUTEX_SOF_DPI0 2 263 #define MT8167_MUTEX_SOF_DPI1 3 264 #define MT8183_MUTEX_SOF_DSI0 1 265 #define MT8183_MUTEX_SOF_DPI0 2 266 #define MT8188_MUTEX_SOF_DSI0 1 267 #define MT8188_MUTEX_SOF_DP_INTF0 3 268 #define MT8195_MUTEX_SOF_DSI0 1 269 #define MT8195_MUTEX_SOF_DSI1 2 270 #define MT8195_MUTEX_SOF_DP_INTF0 3 271 #define MT8195_MUTEX_SOF_DP_INTF1 4 272 #define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */ 273 #define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */ 274 275 #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) 276 #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) 277 #define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7) 278 #define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7) 279 #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7) 280 #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7) 281 #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7) 282 #define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7) 283 #define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7) 284 #define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7) 285 286 struct mtk_mutex { 287 u8 id; 288 bool claimed; 289 }; 290 291 enum mtk_mutex_sof_id { 292 MUTEX_SOF_SINGLE_MODE, 293 MUTEX_SOF_DSI0, 294 MUTEX_SOF_DSI1, 295 MUTEX_SOF_DPI0, 296 MUTEX_SOF_DPI1, 297 MUTEX_SOF_DSI2, 298 MUTEX_SOF_DSI3, 299 MUTEX_SOF_DP_INTF0, 300 MUTEX_SOF_DP_INTF1, 301 DDP_MUTEX_SOF_MAX, 302 }; 303 304 struct mtk_mutex_data { 305 const unsigned int *mutex_mod; 306 const unsigned int *mutex_sof; 307 const unsigned int mutex_mod_reg; 308 const unsigned int mutex_sof_reg; 309 const unsigned int *mutex_table_mod; 310 const bool no_clk; 311 }; 312 313 struct mtk_mutex_ctx { 314 struct device *dev; 315 struct clk *clk; 316 void __iomem *regs; 317 struct mtk_mutex mutex[MTK_MUTEX_MAX_HANDLES]; 318 const struct mtk_mutex_data *data; 319 phys_addr_t addr; 320 struct cmdq_client_reg cmdq_reg; 321 }; 322 323 static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { 324 [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, 325 [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, 326 [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, 327 [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0, 328 [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1, 329 [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, 330 }; 331 332 static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { 333 [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, 334 [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, 335 [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, 336 [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, 337 [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, 338 [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, 339 [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, 340 [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, 341 [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, 342 [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, 343 [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, 344 [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, 345 [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, 346 [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, 347 [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, 348 [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, 349 [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, 350 }; 351 352 static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { 353 [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, 354 [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, 355 [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR, 356 [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER, 357 [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA, 358 [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0, 359 [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1, 360 [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM, 361 [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0, 362 [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1, 363 [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE, 364 [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0, 365 }; 366 367 static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { 368 [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, 369 [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, 370 [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, 371 [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, 372 [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, 373 [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, 374 [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, 375 [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, 376 [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1, 377 [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0, 378 [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1, 379 [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2, 380 [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE, 381 [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0, 382 [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, 383 }; 384 385 static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { 386 [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, 387 [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, 388 [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, 389 [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0, 390 [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, 391 [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, 392 [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, 393 [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, 394 [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, 395 [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, 396 [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, 397 }; 398 399 static const unsigned int mt8183_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { 400 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0, 401 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0, 402 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1, 403 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0, 404 [MUTEX_MOD_IDX_MDP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0, 405 [MUTEX_MOD_IDX_MDP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA, 406 [MUTEX_MOD_IDX_MDP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0, 407 [MUTEX_MOD_IDX_MDP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0, 408 }; 409 410 static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = { 411 [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0, 412 [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0, 413 [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0, 414 [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0, 415 [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0, 416 [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0, 417 [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L, 418 [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0, 419 [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0, 420 [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1, 421 }; 422 423 static const unsigned int mt8186_mdp_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { 424 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8186_MUTEX_MOD_MDP_RDMA0, 425 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8186_MUTEX_MOD_MDP_RSZ0, 426 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8186_MUTEX_MOD_MDP_RSZ1, 427 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8186_MUTEX_MOD_MDP_TDSHP0, 428 [MUTEX_MOD_IDX_MDP_WROT0] = MT8186_MUTEX_MOD_MDP_WROT0, 429 [MUTEX_MOD_IDX_MDP_HDR0] = MT8186_MUTEX_MOD_MDP_HDR0, 430 [MUTEX_MOD_IDX_MDP_AAL0] = MT8186_MUTEX_MOD_MDP_AAL0, 431 [MUTEX_MOD_IDX_MDP_COLOR0] = MT8186_MUTEX_MOD_MDP_COLOR0, 432 }; 433 434 static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = { 435 [DDP_COMPONENT_OVL0] = MT8188_MUTEX_MOD_DISP_OVL0, 436 [DDP_COMPONENT_WDMA0] = MT8188_MUTEX_MOD_DISP_WDMA0, 437 [DDP_COMPONENT_RDMA0] = MT8188_MUTEX_MOD_DISP_RDMA0, 438 [DDP_COMPONENT_COLOR0] = MT8188_MUTEX_MOD_DISP_COLOR0, 439 [DDP_COMPONENT_CCORR] = MT8188_MUTEX_MOD_DISP_CCORR0, 440 [DDP_COMPONENT_AAL0] = MT8188_MUTEX_MOD_DISP_AAL0, 441 [DDP_COMPONENT_GAMMA] = MT8188_MUTEX_MOD_DISP_GAMMA0, 442 [DDP_COMPONENT_POSTMASK0] = MT8188_MUTEX_MOD_DISP_POSTMASK0, 443 [DDP_COMPONENT_DITHER0] = MT8188_MUTEX_MOD_DISP_DITHER0, 444 [DDP_COMPONENT_MERGE0] = MT8188_MUTEX_MOD_DISP_VPP_MERGE, 445 [DDP_COMPONENT_DSC0] = MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, 446 [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0, 447 [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0, 448 [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0, 449 }; 450 451 static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { 452 [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, 453 [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, 454 [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0, 455 [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0, 456 [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0, 457 [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0, 458 [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0, 459 [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L, 460 [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L, 461 [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0, 462 [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4, 463 }; 464 465 static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { 466 [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0, 467 [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0, 468 [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0, 469 [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0, 470 [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0, 471 [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0, 472 [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0, 473 [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0, 474 [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE, 475 [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, 476 [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, 477 [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, 478 [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, 479 [DDP_COMPONENT_MDP_RDMA0] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0, 480 [DDP_COMPONENT_MDP_RDMA1] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA1, 481 [DDP_COMPONENT_MDP_RDMA2] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA2, 482 [DDP_COMPONENT_MDP_RDMA3] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA3, 483 [DDP_COMPONENT_MDP_RDMA4] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA4, 484 [DDP_COMPONENT_MDP_RDMA5] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA5, 485 [DDP_COMPONENT_MDP_RDMA6] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA6, 486 [DDP_COMPONENT_MDP_RDMA7] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA7, 487 [DDP_COMPONENT_MERGE1] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE0, 488 [DDP_COMPONENT_MERGE2] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE1, 489 [DDP_COMPONENT_MERGE3] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE2, 490 [DDP_COMPONENT_MERGE4] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE3, 491 [DDP_COMPONENT_ETHDR_MIXER] = MT8195_MUTEX_MOD_DISP1_DISP_MIXER, 492 [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4, 493 [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0, 494 }; 495 496 static const unsigned int mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { 497 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8195_MUTEX_MOD_MDP_RDMA0, 498 [MUTEX_MOD_IDX_MDP_RDMA1] = MT8195_MUTEX_MOD_MDP_RDMA1, 499 [MUTEX_MOD_IDX_MDP_RDMA2] = MT8195_MUTEX_MOD_MDP_RDMA2, 500 [MUTEX_MOD_IDX_MDP_RDMA3] = MT8195_MUTEX_MOD_MDP_RDMA3, 501 [MUTEX_MOD_IDX_MDP_STITCH0] = MT8195_MUTEX_MOD_MDP_STITCH0, 502 [MUTEX_MOD_IDX_MDP_FG0] = MT8195_MUTEX_MOD_MDP_FG0, 503 [MUTEX_MOD_IDX_MDP_FG1] = MT8195_MUTEX_MOD_MDP_FG1, 504 [MUTEX_MOD_IDX_MDP_FG2] = MT8195_MUTEX_MOD_MDP_FG2, 505 [MUTEX_MOD_IDX_MDP_FG3] = MT8195_MUTEX_MOD_MDP_FG3, 506 [MUTEX_MOD_IDX_MDP_HDR0] = MT8195_MUTEX_MOD_MDP_HDR0, 507 [MUTEX_MOD_IDX_MDP_HDR1] = MT8195_MUTEX_MOD_MDP_HDR1, 508 [MUTEX_MOD_IDX_MDP_HDR2] = MT8195_MUTEX_MOD_MDP_HDR2, 509 [MUTEX_MOD_IDX_MDP_HDR3] = MT8195_MUTEX_MOD_MDP_HDR3, 510 [MUTEX_MOD_IDX_MDP_AAL0] = MT8195_MUTEX_MOD_MDP_AAL0, 511 [MUTEX_MOD_IDX_MDP_AAL1] = MT8195_MUTEX_MOD_MDP_AAL1, 512 [MUTEX_MOD_IDX_MDP_AAL2] = MT8195_MUTEX_MOD_MDP_AAL2, 513 [MUTEX_MOD_IDX_MDP_AAL3] = MT8195_MUTEX_MOD_MDP_AAL3, 514 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8195_MUTEX_MOD_MDP_RSZ0, 515 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8195_MUTEX_MOD_MDP_RSZ1, 516 [MUTEX_MOD_IDX_MDP_RSZ2] = MT8195_MUTEX_MOD_MDP_RSZ2, 517 [MUTEX_MOD_IDX_MDP_RSZ3] = MT8195_MUTEX_MOD_MDP_RSZ3, 518 [MUTEX_MOD_IDX_MDP_MERGE2] = MT8195_MUTEX_MOD_MDP_MERGE2, 519 [MUTEX_MOD_IDX_MDP_MERGE3] = MT8195_MUTEX_MOD_MDP_MERGE3, 520 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8195_MUTEX_MOD_MDP_TDSHP0, 521 [MUTEX_MOD_IDX_MDP_TDSHP1] = MT8195_MUTEX_MOD_MDP_TDSHP1, 522 [MUTEX_MOD_IDX_MDP_TDSHP2] = MT8195_MUTEX_MOD_MDP_TDSHP2, 523 [MUTEX_MOD_IDX_MDP_TDSHP3] = MT8195_MUTEX_MOD_MDP_TDSHP3, 524 [MUTEX_MOD_IDX_MDP_COLOR0] = MT8195_MUTEX_MOD_MDP_COLOR0, 525 [MUTEX_MOD_IDX_MDP_COLOR1] = MT8195_MUTEX_MOD_MDP_COLOR1, 526 [MUTEX_MOD_IDX_MDP_COLOR2] = MT8195_MUTEX_MOD_MDP_COLOR2, 527 [MUTEX_MOD_IDX_MDP_COLOR3] = MT8195_MUTEX_MOD_MDP_COLOR3, 528 [MUTEX_MOD_IDX_MDP_OVL0] = MT8195_MUTEX_MOD_MDP_OVL0, 529 [MUTEX_MOD_IDX_MDP_OVL1] = MT8195_MUTEX_MOD_MDP_OVL1, 530 [MUTEX_MOD_IDX_MDP_PAD0] = MT8195_MUTEX_MOD_MDP_PAD0, 531 [MUTEX_MOD_IDX_MDP_PAD1] = MT8195_MUTEX_MOD_MDP_PAD1, 532 [MUTEX_MOD_IDX_MDP_PAD2] = MT8195_MUTEX_MOD_MDP_PAD2, 533 [MUTEX_MOD_IDX_MDP_PAD3] = MT8195_MUTEX_MOD_MDP_PAD3, 534 [MUTEX_MOD_IDX_MDP_TCC0] = MT8195_MUTEX_MOD_MDP_TCC0, 535 [MUTEX_MOD_IDX_MDP_TCC1] = MT8195_MUTEX_MOD_MDP_TCC1, 536 [MUTEX_MOD_IDX_MDP_WROT0] = MT8195_MUTEX_MOD_MDP_WROT0, 537 [MUTEX_MOD_IDX_MDP_WROT1] = MT8195_MUTEX_MOD_MDP_WROT1, 538 [MUTEX_MOD_IDX_MDP_WROT2] = MT8195_MUTEX_MOD_MDP_WROT2, 539 [MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3, 540 }; 541 542 static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = { 543 [DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL, 544 [DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR, 545 [DDP_COMPONENT_COLOR0] = MT8365_MUTEX_MOD_DISP_COLOR0, 546 [DDP_COMPONENT_DITHER0] = MT8365_MUTEX_MOD_DISP_DITHER, 547 [DDP_COMPONENT_DPI0] = MT8365_MUTEX_MOD_DISP_DPI0, 548 [DDP_COMPONENT_DSI0] = MT8365_MUTEX_MOD_DISP_DSI0, 549 [DDP_COMPONENT_GAMMA] = MT8365_MUTEX_MOD_DISP_GAMMA, 550 [DDP_COMPONENT_OVL0] = MT8365_MUTEX_MOD_DISP_OVL0, 551 [DDP_COMPONENT_OVL_2L0] = MT8365_MUTEX_MOD_DISP_OVL0_2L, 552 [DDP_COMPONENT_PWM0] = MT8365_MUTEX_MOD_DISP_PWM0, 553 [DDP_COMPONENT_RDMA0] = MT8365_MUTEX_MOD_DISP_RDMA0, 554 [DDP_COMPONENT_RDMA1] = MT8365_MUTEX_MOD_DISP_RDMA1, 555 [DDP_COMPONENT_WDMA0] = MT8365_MUTEX_MOD_DISP_WDMA0, 556 }; 557 558 static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { 559 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 560 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, 561 [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, 562 [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, 563 [MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1, 564 [MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2, 565 [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, 566 }; 567 568 static const unsigned int mt6795_mutex_sof[DDP_MUTEX_SOF_MAX] = { 569 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 570 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, 571 [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, 572 [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, 573 }; 574 575 static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = { 576 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 577 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, 578 [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, 579 [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, 580 }; 581 582 /* Add EOF setting so overlay hardware can receive frame done irq */ 583 static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = { 584 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 585 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, 586 [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, 587 }; 588 589 static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = { 590 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 591 [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0, 592 [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0, 593 }; 594 595 /* 596 * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should 597 * select the EOF source and configure the EOF plus timing from the 598 * module that provides the timing signal. 599 * So that MUTEX can not only send a STREAM_DONE event to GCE 600 * but also detect the error at end of frame(EAEOF) when EOF signal 601 * arrives. 602 */ 603 static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = { 604 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 605 [MUTEX_SOF_DSI0] = 606 MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0, 607 [MUTEX_SOF_DP_INTF0] = 608 MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0, 609 }; 610 611 static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = { 612 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 613 [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0, 614 [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1, 615 [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0, 616 [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1, 617 [MUTEX_SOF_DP_INTF0] = 618 MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0, 619 [MUTEX_SOF_DP_INTF1] = 620 MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1, 621 }; 622 623 static const struct mtk_mutex_data mt2701_mutex_driver_data = { 624 .mutex_mod = mt2701_mutex_mod, 625 .mutex_sof = mt2712_mutex_sof, 626 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 627 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 628 }; 629 630 static const struct mtk_mutex_data mt2712_mutex_driver_data = { 631 .mutex_mod = mt2712_mutex_mod, 632 .mutex_sof = mt2712_mutex_sof, 633 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 634 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 635 }; 636 637 static const struct mtk_mutex_data mt6795_mutex_driver_data = { 638 .mutex_mod = mt8173_mutex_mod, 639 .mutex_sof = mt6795_mutex_sof, 640 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 641 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 642 }; 643 644 static const struct mtk_mutex_data mt8167_mutex_driver_data = { 645 .mutex_mod = mt8167_mutex_mod, 646 .mutex_sof = mt8167_mutex_sof, 647 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 648 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 649 .no_clk = true, 650 }; 651 652 static const struct mtk_mutex_data mt8173_mutex_driver_data = { 653 .mutex_mod = mt8173_mutex_mod, 654 .mutex_sof = mt2712_mutex_sof, 655 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 656 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 657 }; 658 659 static const struct mtk_mutex_data mt8183_mutex_driver_data = { 660 .mutex_mod = mt8183_mutex_mod, 661 .mutex_sof = mt8183_mutex_sof, 662 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 663 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 664 .mutex_table_mod = mt8183_mutex_table_mod, 665 .no_clk = true, 666 }; 667 668 static const struct mtk_mutex_data mt8186_mdp_mutex_driver_data = { 669 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 670 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 671 .mutex_table_mod = mt8186_mdp_mutex_table_mod, 672 }; 673 674 static const struct mtk_mutex_data mt8186_mutex_driver_data = { 675 .mutex_mod = mt8186_mutex_mod, 676 .mutex_sof = mt8186_mutex_sof, 677 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 678 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 679 }; 680 681 static const struct mtk_mutex_data mt8188_mutex_driver_data = { 682 .mutex_mod = mt8188_mutex_mod, 683 .mutex_sof = mt8188_mutex_sof, 684 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 685 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 686 }; 687 688 static const struct mtk_mutex_data mt8192_mutex_driver_data = { 689 .mutex_mod = mt8192_mutex_mod, 690 .mutex_sof = mt8183_mutex_sof, 691 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 692 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 693 }; 694 695 static const struct mtk_mutex_data mt8195_mutex_driver_data = { 696 .mutex_mod = mt8195_mutex_mod, 697 .mutex_sof = mt8195_mutex_sof, 698 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 699 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 700 }; 701 702 static const struct mtk_mutex_data mt8195_vpp_mutex_driver_data = { 703 .mutex_sof = mt8195_mutex_sof, 704 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 705 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 706 .mutex_table_mod = mt8195_mutex_table_mod, 707 }; 708 709 static const struct mtk_mutex_data mt8365_mutex_driver_data = { 710 .mutex_mod = mt8365_mutex_mod, 711 .mutex_sof = mt8183_mutex_sof, 712 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 713 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 714 .no_clk = true, 715 }; 716 717 struct mtk_mutex *mtk_mutex_get(struct device *dev) 718 { 719 struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); 720 int i; 721 722 for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++) 723 if (!mtx->mutex[i].claimed) { 724 mtx->mutex[i].claimed = true; 725 return &mtx->mutex[i]; 726 } 727 728 return ERR_PTR(-EBUSY); 729 } 730 EXPORT_SYMBOL_GPL(mtk_mutex_get); 731 732 void mtk_mutex_put(struct mtk_mutex *mutex) 733 { 734 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 735 mutex[mutex->id]); 736 737 WARN_ON(&mtx->mutex[mutex->id] != mutex); 738 739 mutex->claimed = false; 740 } 741 EXPORT_SYMBOL_GPL(mtk_mutex_put); 742 743 int mtk_mutex_prepare(struct mtk_mutex *mutex) 744 { 745 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 746 mutex[mutex->id]); 747 return clk_prepare_enable(mtx->clk); 748 } 749 EXPORT_SYMBOL_GPL(mtk_mutex_prepare); 750 751 void mtk_mutex_unprepare(struct mtk_mutex *mutex) 752 { 753 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 754 mutex[mutex->id]); 755 clk_disable_unprepare(mtx->clk); 756 } 757 EXPORT_SYMBOL_GPL(mtk_mutex_unprepare); 758 759 void mtk_mutex_add_comp(struct mtk_mutex *mutex, 760 enum mtk_ddp_comp_id id) 761 { 762 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 763 mutex[mutex->id]); 764 unsigned int reg; 765 unsigned int sof_id; 766 unsigned int offset; 767 768 WARN_ON(&mtx->mutex[mutex->id] != mutex); 769 770 switch (id) { 771 case DDP_COMPONENT_DSI0: 772 sof_id = MUTEX_SOF_DSI0; 773 break; 774 case DDP_COMPONENT_DSI1: 775 sof_id = MUTEX_SOF_DSI0; 776 break; 777 case DDP_COMPONENT_DSI2: 778 sof_id = MUTEX_SOF_DSI2; 779 break; 780 case DDP_COMPONENT_DSI3: 781 sof_id = MUTEX_SOF_DSI3; 782 break; 783 case DDP_COMPONENT_DPI0: 784 sof_id = MUTEX_SOF_DPI0; 785 break; 786 case DDP_COMPONENT_DPI1: 787 sof_id = MUTEX_SOF_DPI1; 788 break; 789 case DDP_COMPONENT_DP_INTF0: 790 sof_id = MUTEX_SOF_DP_INTF0; 791 break; 792 case DDP_COMPONENT_DP_INTF1: 793 sof_id = MUTEX_SOF_DP_INTF1; 794 break; 795 default: 796 if (mtx->data->mutex_mod[id] < 32) { 797 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, 798 mutex->id); 799 reg = readl_relaxed(mtx->regs + offset); 800 reg |= 1 << mtx->data->mutex_mod[id]; 801 writel_relaxed(reg, mtx->regs + offset); 802 } else { 803 offset = DISP_REG_MUTEX_MOD2(mutex->id); 804 reg = readl_relaxed(mtx->regs + offset); 805 reg |= 1 << (mtx->data->mutex_mod[id] - 32); 806 writel_relaxed(reg, mtx->regs + offset); 807 } 808 return; 809 } 810 811 writel_relaxed(mtx->data->mutex_sof[sof_id], 812 mtx->regs + 813 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); 814 } 815 EXPORT_SYMBOL_GPL(mtk_mutex_add_comp); 816 817 void mtk_mutex_remove_comp(struct mtk_mutex *mutex, 818 enum mtk_ddp_comp_id id) 819 { 820 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 821 mutex[mutex->id]); 822 unsigned int reg; 823 unsigned int offset; 824 825 WARN_ON(&mtx->mutex[mutex->id] != mutex); 826 827 switch (id) { 828 case DDP_COMPONENT_DSI0: 829 case DDP_COMPONENT_DSI1: 830 case DDP_COMPONENT_DSI2: 831 case DDP_COMPONENT_DSI3: 832 case DDP_COMPONENT_DPI0: 833 case DDP_COMPONENT_DPI1: 834 case DDP_COMPONENT_DP_INTF0: 835 case DDP_COMPONENT_DP_INTF1: 836 writel_relaxed(MUTEX_SOF_SINGLE_MODE, 837 mtx->regs + 838 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, 839 mutex->id)); 840 break; 841 default: 842 if (mtx->data->mutex_mod[id] < 32) { 843 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, 844 mutex->id); 845 reg = readl_relaxed(mtx->regs + offset); 846 reg &= ~(1 << mtx->data->mutex_mod[id]); 847 writel_relaxed(reg, mtx->regs + offset); 848 } else { 849 offset = DISP_REG_MUTEX_MOD2(mutex->id); 850 reg = readl_relaxed(mtx->regs + offset); 851 reg &= ~(1 << (mtx->data->mutex_mod[id] - 32)); 852 writel_relaxed(reg, mtx->regs + offset); 853 } 854 break; 855 } 856 } 857 EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp); 858 859 void mtk_mutex_enable(struct mtk_mutex *mutex) 860 { 861 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 862 mutex[mutex->id]); 863 864 WARN_ON(&mtx->mutex[mutex->id] != mutex); 865 866 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); 867 } 868 EXPORT_SYMBOL_GPL(mtk_mutex_enable); 869 870 int mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex, void *pkt) 871 { 872 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 873 mutex[mutex->id]); 874 struct cmdq_pkt *cmdq_pkt = (struct cmdq_pkt *)pkt; 875 876 WARN_ON(&mtx->mutex[mutex->id] != mutex); 877 878 if (!mtx->cmdq_reg.size) { 879 dev_err(mtx->dev, "mediatek,gce-client-reg hasn't been set"); 880 return -ENODEV; 881 } 882 883 cmdq_pkt_write(cmdq_pkt, mtx->cmdq_reg.subsys, 884 mtx->addr + DISP_REG_MUTEX_EN(mutex->id), 1); 885 return 0; 886 } 887 EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq); 888 889 void mtk_mutex_disable(struct mtk_mutex *mutex) 890 { 891 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 892 mutex[mutex->id]); 893 894 WARN_ON(&mtx->mutex[mutex->id] != mutex); 895 896 writel(0, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); 897 } 898 EXPORT_SYMBOL_GPL(mtk_mutex_disable); 899 900 void mtk_mutex_acquire(struct mtk_mutex *mutex) 901 { 902 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 903 mutex[mutex->id]); 904 u32 tmp; 905 906 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); 907 writel(1, mtx->regs + DISP_REG_MUTEX(mutex->id)); 908 if (readl_poll_timeout_atomic(mtx->regs + DISP_REG_MUTEX(mutex->id), 909 tmp, tmp & INT_MUTEX, 1, 10000)) 910 pr_err("could not acquire mutex %d\n", mutex->id); 911 } 912 EXPORT_SYMBOL_GPL(mtk_mutex_acquire); 913 914 void mtk_mutex_release(struct mtk_mutex *mutex) 915 { 916 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 917 mutex[mutex->id]); 918 919 writel(0, mtx->regs + DISP_REG_MUTEX(mutex->id)); 920 } 921 EXPORT_SYMBOL_GPL(mtk_mutex_release); 922 923 int mtk_mutex_write_mod(struct mtk_mutex *mutex, 924 enum mtk_mutex_mod_index idx, bool clear) 925 { 926 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 927 mutex[mutex->id]); 928 unsigned int reg; 929 u32 reg_offset, id_offset = 0; 930 931 WARN_ON(&mtx->mutex[mutex->id] != mutex); 932 933 if (idx < MUTEX_MOD_IDX_MDP_RDMA0 || 934 idx >= MUTEX_MOD_IDX_MAX) { 935 dev_err(mtx->dev, "Not supported MOD table index : %d", idx); 936 return -EINVAL; 937 } 938 939 /* 940 * Some SoCs may have multiple MUTEX_MOD registers as more than 32 mods 941 * are present, hence requiring multiple 32-bits registers. 942 * 943 * The mutex_table_mod fully represents that by defining the number of 944 * the mod sequentially, later used as a bit number, which can be more 945 * than 0..31. 946 * 947 * In order to retain compatibility with older SoCs, we perform R/W on 948 * the single 32 bits registers, but this requires us to translate the 949 * mutex ID bit accordingly. 950 */ 951 if (mtx->data->mutex_table_mod[idx] < 32) { 952 reg_offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, 953 mutex->id); 954 } else { 955 reg_offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg, 956 mutex->id); 957 id_offset = 32; 958 } 959 960 reg = readl_relaxed(mtx->regs + reg_offset); 961 if (clear) 962 reg &= ~BIT(mtx->data->mutex_table_mod[idx] - id_offset); 963 else 964 reg |= BIT(mtx->data->mutex_table_mod[idx] - id_offset); 965 966 writel_relaxed(reg, mtx->regs + reg_offset); 967 968 return 0; 969 } 970 EXPORT_SYMBOL_GPL(mtk_mutex_write_mod); 971 972 int mtk_mutex_write_sof(struct mtk_mutex *mutex, 973 enum mtk_mutex_sof_index idx) 974 { 975 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 976 mutex[mutex->id]); 977 978 WARN_ON(&mtx->mutex[mutex->id] != mutex); 979 980 if (idx < MUTEX_SOF_IDX_SINGLE_MODE || 981 idx >= MUTEX_SOF_IDX_MAX) { 982 dev_err(mtx->dev, "Not supported SOF index : %d", idx); 983 return -EINVAL; 984 } 985 986 writel_relaxed(idx, mtx->regs + 987 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); 988 989 return 0; 990 } 991 EXPORT_SYMBOL_GPL(mtk_mutex_write_sof); 992 993 static int mtk_mutex_probe(struct platform_device *pdev) 994 { 995 struct device *dev = &pdev->dev; 996 struct mtk_mutex_ctx *mtx; 997 struct resource *regs; 998 int i, ret; 999 1000 mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL); 1001 if (!mtx) 1002 return -ENOMEM; 1003 1004 for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++) 1005 mtx->mutex[i].id = i; 1006 1007 mtx->data = of_device_get_match_data(dev); 1008 1009 if (!mtx->data->no_clk) { 1010 mtx->clk = devm_clk_get(dev, NULL); 1011 if (IS_ERR(mtx->clk)) 1012 return dev_err_probe(dev, PTR_ERR(mtx->clk), "Failed to get clock\n"); 1013 } 1014 1015 mtx->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); 1016 if (IS_ERR(mtx->regs)) { 1017 dev_err(dev, "Failed to map mutex registers\n"); 1018 return PTR_ERR(mtx->regs); 1019 } 1020 mtx->addr = regs->start; 1021 1022 /* CMDQ is optional */ 1023 ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0); 1024 if (ret) 1025 dev_dbg(dev, "No mediatek,gce-client-reg!\n"); 1026 1027 platform_set_drvdata(pdev, mtx); 1028 1029 return 0; 1030 } 1031 1032 static const struct of_device_id mutex_driver_dt_match[] = { 1033 { .compatible = "mediatek,mt2701-disp-mutex", .data = &mt2701_mutex_driver_data }, 1034 { .compatible = "mediatek,mt2712-disp-mutex", .data = &mt2712_mutex_driver_data }, 1035 { .compatible = "mediatek,mt6795-disp-mutex", .data = &mt6795_mutex_driver_data }, 1036 { .compatible = "mediatek,mt8167-disp-mutex", .data = &mt8167_mutex_driver_data }, 1037 { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_mutex_driver_data }, 1038 { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data }, 1039 { .compatible = "mediatek,mt8186-disp-mutex", .data = &mt8186_mutex_driver_data }, 1040 { .compatible = "mediatek,mt8186-mdp3-mutex", .data = &mt8186_mdp_mutex_driver_data }, 1041 { .compatible = "mediatek,mt8188-disp-mutex", .data = &mt8188_mutex_driver_data }, 1042 { .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data }, 1043 { .compatible = "mediatek,mt8195-disp-mutex", .data = &mt8195_mutex_driver_data }, 1044 { .compatible = "mediatek,mt8195-vpp-mutex", .data = &mt8195_vpp_mutex_driver_data }, 1045 { .compatible = "mediatek,mt8365-disp-mutex", .data = &mt8365_mutex_driver_data }, 1046 { /* sentinel */ }, 1047 }; 1048 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); 1049 1050 static struct platform_driver mtk_mutex_driver = { 1051 .probe = mtk_mutex_probe, 1052 .driver = { 1053 .name = "mediatek-mutex", 1054 .owner = THIS_MODULE, 1055 .of_match_table = mutex_driver_dt_match, 1056 }, 1057 }; 1058 module_platform_driver(mtk_mutex_driver); 1059 1060 MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>"); 1061 MODULE_DESCRIPTION("MediaTek SoC MUTEX driver"); 1062 MODULE_LICENSE("GPL"); 1063