1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Core of Xen paravirt_ops implementation. 4 * 5 * This file contains the xen_paravirt_ops structure itself, and the 6 * implementations for: 7 * - privileged instructions 8 * - interrupt flags 9 * - segment operations 10 * - booting and setup 11 * 12 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 13 */ 14 15 #include <linux/cpu.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/smp.h> 19 #include <linux/preempt.h> 20 #include <linux/hardirq.h> 21 #include <linux/percpu.h> 22 #include <linux/delay.h> 23 #include <linux/start_kernel.h> 24 #include <linux/sched.h> 25 #include <linux/kprobes.h> 26 #include <linux/memblock.h> 27 #include <linux/export.h> 28 #include <linux/mm.h> 29 #include <linux/page-flags.h> 30 #include <linux/pci.h> 31 #include <linux/gfp.h> 32 #include <linux/edd.h> 33 #include <linux/objtool.h> 34 35 #include <xen/xen.h> 36 #include <xen/events.h> 37 #include <xen/interface/xen.h> 38 #include <xen/interface/version.h> 39 #include <xen/interface/physdev.h> 40 #include <xen/interface/vcpu.h> 41 #include <xen/interface/memory.h> 42 #include <xen/interface/nmi.h> 43 #include <xen/interface/xen-mca.h> 44 #include <xen/features.h> 45 #include <xen/page.h> 46 #include <xen/hvc-console.h> 47 #include <xen/acpi.h> 48 49 #include <asm/paravirt.h> 50 #include <asm/apic.h> 51 #include <asm/page.h> 52 #include <asm/xen/pci.h> 53 #include <asm/xen/hypercall.h> 54 #include <asm/xen/hypervisor.h> 55 #include <asm/xen/cpuid.h> 56 #include <asm/fixmap.h> 57 #include <asm/processor.h> 58 #include <asm/proto.h> 59 #include <asm/msr-index.h> 60 #include <asm/traps.h> 61 #include <asm/setup.h> 62 #include <asm/desc.h> 63 #include <asm/pgalloc.h> 64 #include <asm/tlbflush.h> 65 #include <asm/reboot.h> 66 #include <asm/stackprotector.h> 67 #include <asm/hypervisor.h> 68 #include <asm/mach_traps.h> 69 #include <asm/mwait.h> 70 #include <asm/pci_x86.h> 71 #include <asm/cpu.h> 72 #ifdef CONFIG_X86_IOPL_IOPERM 73 #include <asm/io_bitmap.h> 74 #endif 75 76 #ifdef CONFIG_ACPI 77 #include <linux/acpi.h> 78 #include <asm/acpi.h> 79 #include <acpi/pdc_intel.h> 80 #include <acpi/processor.h> 81 #include <xen/interface/platform.h> 82 #endif 83 84 #include "xen-ops.h" 85 #include "mmu.h" 86 #include "smp.h" 87 #include "multicalls.h" 88 #include "pmu.h" 89 90 #include "../kernel/cpu/cpu.h" /* get_cpu_cap() */ 91 92 void *xen_initial_gdt; 93 94 static int xen_cpu_up_prepare_pv(unsigned int cpu); 95 static int xen_cpu_dead_pv(unsigned int cpu); 96 97 struct tls_descs { 98 struct desc_struct desc[3]; 99 }; 100 101 /* 102 * Updating the 3 TLS descriptors in the GDT on every task switch is 103 * surprisingly expensive so we avoid updating them if they haven't 104 * changed. Since Xen writes different descriptors than the one 105 * passed in the update_descriptor hypercall we keep shadow copies to 106 * compare against. 107 */ 108 static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc); 109 110 static void __init xen_pv_init_platform(void) 111 { 112 populate_extra_pte(fix_to_virt(FIX_PARAVIRT_BOOTMAP)); 113 114 set_fixmap(FIX_PARAVIRT_BOOTMAP, xen_start_info->shared_info); 115 HYPERVISOR_shared_info = (void *)fix_to_virt(FIX_PARAVIRT_BOOTMAP); 116 117 /* xen clock uses per-cpu vcpu_info, need to init it for boot cpu */ 118 xen_vcpu_info_reset(0); 119 120 /* pvclock is in shared info area */ 121 xen_init_time_ops(); 122 } 123 124 static void __init xen_pv_guest_late_init(void) 125 { 126 #ifndef CONFIG_SMP 127 /* Setup shared vcpu info for non-smp configurations */ 128 xen_setup_vcpu_info_placement(); 129 #endif 130 } 131 132 static __read_mostly unsigned int cpuid_leaf5_ecx_val; 133 static __read_mostly unsigned int cpuid_leaf5_edx_val; 134 135 static void xen_cpuid(unsigned int *ax, unsigned int *bx, 136 unsigned int *cx, unsigned int *dx) 137 { 138 unsigned maskebx = ~0; 139 140 /* 141 * Mask out inconvenient features, to try and disable as many 142 * unsupported kernel subsystems as possible. 143 */ 144 switch (*ax) { 145 case CPUID_MWAIT_LEAF: 146 /* Synthesize the values.. */ 147 *ax = 0; 148 *bx = 0; 149 *cx = cpuid_leaf5_ecx_val; 150 *dx = cpuid_leaf5_edx_val; 151 return; 152 153 case 0xb: 154 /* Suppress extended topology stuff */ 155 maskebx = 0; 156 break; 157 } 158 159 asm(XEN_EMULATE_PREFIX "cpuid" 160 : "=a" (*ax), 161 "=b" (*bx), 162 "=c" (*cx), 163 "=d" (*dx) 164 : "0" (*ax), "2" (*cx)); 165 166 *bx &= maskebx; 167 } 168 STACK_FRAME_NON_STANDARD(xen_cpuid); /* XEN_EMULATE_PREFIX */ 169 170 static bool __init xen_check_mwait(void) 171 { 172 #ifdef CONFIG_ACPI 173 struct xen_platform_op op = { 174 .cmd = XENPF_set_processor_pminfo, 175 .u.set_pminfo.id = -1, 176 .u.set_pminfo.type = XEN_PM_PDC, 177 }; 178 uint32_t buf[3]; 179 unsigned int ax, bx, cx, dx; 180 unsigned int mwait_mask; 181 182 /* We need to determine whether it is OK to expose the MWAIT 183 * capability to the kernel to harvest deeper than C3 states from ACPI 184 * _CST using the processor_harvest_xen.c module. For this to work, we 185 * need to gather the MWAIT_LEAF values (which the cstate.c code 186 * checks against). The hypervisor won't expose the MWAIT flag because 187 * it would break backwards compatibility; so we will find out directly 188 * from the hardware and hypercall. 189 */ 190 if (!xen_initial_domain()) 191 return false; 192 193 /* 194 * When running under platform earlier than Xen4.2, do not expose 195 * mwait, to avoid the risk of loading native acpi pad driver 196 */ 197 if (!xen_running_on_version_or_later(4, 2)) 198 return false; 199 200 ax = 1; 201 cx = 0; 202 203 native_cpuid(&ax, &bx, &cx, &dx); 204 205 mwait_mask = (1 << (X86_FEATURE_EST % 32)) | 206 (1 << (X86_FEATURE_MWAIT % 32)); 207 208 if ((cx & mwait_mask) != mwait_mask) 209 return false; 210 211 /* We need to emulate the MWAIT_LEAF and for that we need both 212 * ecx and edx. The hypercall provides only partial information. 213 */ 214 215 ax = CPUID_MWAIT_LEAF; 216 bx = 0; 217 cx = 0; 218 dx = 0; 219 220 native_cpuid(&ax, &bx, &cx, &dx); 221 222 /* Ask the Hypervisor whether to clear ACPI_PDC_C_C2C3_FFH. If so, 223 * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3. 224 */ 225 buf[0] = ACPI_PDC_REVISION_ID; 226 buf[1] = 1; 227 buf[2] = (ACPI_PDC_C_CAPABILITY_SMP | ACPI_PDC_EST_CAPABILITY_SWSMP); 228 229 set_xen_guest_handle(op.u.set_pminfo.pdc, buf); 230 231 if ((HYPERVISOR_platform_op(&op) == 0) && 232 (buf[2] & (ACPI_PDC_C_C1_FFH | ACPI_PDC_C_C2C3_FFH))) { 233 cpuid_leaf5_ecx_val = cx; 234 cpuid_leaf5_edx_val = dx; 235 } 236 return true; 237 #else 238 return false; 239 #endif 240 } 241 242 static bool __init xen_check_xsave(void) 243 { 244 unsigned int cx, xsave_mask; 245 246 cx = cpuid_ecx(1); 247 248 xsave_mask = (1 << (X86_FEATURE_XSAVE % 32)) | 249 (1 << (X86_FEATURE_OSXSAVE % 32)); 250 251 /* Xen will set CR4.OSXSAVE if supported and not disabled by force */ 252 return (cx & xsave_mask) == xsave_mask; 253 } 254 255 static void __init xen_init_capabilities(void) 256 { 257 setup_force_cpu_cap(X86_FEATURE_XENPV); 258 setup_clear_cpu_cap(X86_FEATURE_DCA); 259 setup_clear_cpu_cap(X86_FEATURE_APERFMPERF); 260 setup_clear_cpu_cap(X86_FEATURE_MTRR); 261 setup_clear_cpu_cap(X86_FEATURE_ACC); 262 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 263 setup_clear_cpu_cap(X86_FEATURE_SME); 264 265 /* 266 * Xen PV would need some work to support PCID: CR3 handling as well 267 * as xen_flush_tlb_others() would need updating. 268 */ 269 setup_clear_cpu_cap(X86_FEATURE_PCID); 270 271 if (!xen_initial_domain()) 272 setup_clear_cpu_cap(X86_FEATURE_ACPI); 273 274 if (xen_check_mwait()) 275 setup_force_cpu_cap(X86_FEATURE_MWAIT); 276 else 277 setup_clear_cpu_cap(X86_FEATURE_MWAIT); 278 279 if (!xen_check_xsave()) { 280 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 281 setup_clear_cpu_cap(X86_FEATURE_OSXSAVE); 282 } 283 } 284 285 static noinstr void xen_set_debugreg(int reg, unsigned long val) 286 { 287 HYPERVISOR_set_debugreg(reg, val); 288 } 289 290 static noinstr unsigned long xen_get_debugreg(int reg) 291 { 292 return HYPERVISOR_get_debugreg(reg); 293 } 294 295 static void xen_end_context_switch(struct task_struct *next) 296 { 297 xen_mc_flush(); 298 paravirt_end_context_switch(next); 299 } 300 301 static unsigned long xen_store_tr(void) 302 { 303 return 0; 304 } 305 306 /* 307 * Set the page permissions for a particular virtual address. If the 308 * address is a vmalloc mapping (or other non-linear mapping), then 309 * find the linear mapping of the page and also set its protections to 310 * match. 311 */ 312 static void set_aliased_prot(void *v, pgprot_t prot) 313 { 314 int level; 315 pte_t *ptep; 316 pte_t pte; 317 unsigned long pfn; 318 unsigned char dummy; 319 void *va; 320 321 ptep = lookup_address((unsigned long)v, &level); 322 BUG_ON(ptep == NULL); 323 324 pfn = pte_pfn(*ptep); 325 pte = pfn_pte(pfn, prot); 326 327 /* 328 * Careful: update_va_mapping() will fail if the virtual address 329 * we're poking isn't populated in the page tables. We don't 330 * need to worry about the direct map (that's always in the page 331 * tables), but we need to be careful about vmap space. In 332 * particular, the top level page table can lazily propagate 333 * entries between processes, so if we've switched mms since we 334 * vmapped the target in the first place, we might not have the 335 * top-level page table entry populated. 336 * 337 * We disable preemption because we want the same mm active when 338 * we probe the target and when we issue the hypercall. We'll 339 * have the same nominal mm, but if we're a kernel thread, lazy 340 * mm dropping could change our pgd. 341 * 342 * Out of an abundance of caution, this uses __get_user() to fault 343 * in the target address just in case there's some obscure case 344 * in which the target address isn't readable. 345 */ 346 347 preempt_disable(); 348 349 copy_from_kernel_nofault(&dummy, v, 1); 350 351 if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0)) 352 BUG(); 353 354 va = __va(PFN_PHYS(pfn)); 355 356 if (va != v && HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 357 BUG(); 358 359 preempt_enable(); 360 } 361 362 static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries) 363 { 364 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 365 int i; 366 367 /* 368 * We need to mark the all aliases of the LDT pages RO. We 369 * don't need to call vm_flush_aliases(), though, since that's 370 * only responsible for flushing aliases out the TLBs, not the 371 * page tables, and Xen will flush the TLB for us if needed. 372 * 373 * To avoid confusing future readers: none of this is necessary 374 * to load the LDT. The hypervisor only checks this when the 375 * LDT is faulted in due to subsequent descriptor access. 376 */ 377 378 for (i = 0; i < entries; i += entries_per_page) 379 set_aliased_prot(ldt + i, PAGE_KERNEL_RO); 380 } 381 382 static void xen_free_ldt(struct desc_struct *ldt, unsigned entries) 383 { 384 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 385 int i; 386 387 for (i = 0; i < entries; i += entries_per_page) 388 set_aliased_prot(ldt + i, PAGE_KERNEL); 389 } 390 391 static void xen_set_ldt(const void *addr, unsigned entries) 392 { 393 struct mmuext_op *op; 394 struct multicall_space mcs = xen_mc_entry(sizeof(*op)); 395 396 trace_xen_cpu_set_ldt(addr, entries); 397 398 op = mcs.args; 399 op->cmd = MMUEXT_SET_LDT; 400 op->arg1.linear_addr = (unsigned long)addr; 401 op->arg2.nr_ents = entries; 402 403 MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF); 404 405 xen_mc_issue(PARAVIRT_LAZY_CPU); 406 } 407 408 static void xen_load_gdt(const struct desc_ptr *dtr) 409 { 410 unsigned long va = dtr->address; 411 unsigned int size = dtr->size + 1; 412 unsigned long pfn, mfn; 413 int level; 414 pte_t *ptep; 415 void *virt; 416 417 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 418 BUG_ON(size > PAGE_SIZE); 419 BUG_ON(va & ~PAGE_MASK); 420 421 /* 422 * The GDT is per-cpu and is in the percpu data area. 423 * That can be virtually mapped, so we need to do a 424 * page-walk to get the underlying MFN for the 425 * hypercall. The page can also be in the kernel's 426 * linear range, so we need to RO that mapping too. 427 */ 428 ptep = lookup_address(va, &level); 429 BUG_ON(ptep == NULL); 430 431 pfn = pte_pfn(*ptep); 432 mfn = pfn_to_mfn(pfn); 433 virt = __va(PFN_PHYS(pfn)); 434 435 make_lowmem_page_readonly((void *)va); 436 make_lowmem_page_readonly(virt); 437 438 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 439 BUG(); 440 } 441 442 /* 443 * load_gdt for early boot, when the gdt is only mapped once 444 */ 445 static void __init xen_load_gdt_boot(const struct desc_ptr *dtr) 446 { 447 unsigned long va = dtr->address; 448 unsigned int size = dtr->size + 1; 449 unsigned long pfn, mfn; 450 pte_t pte; 451 452 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 453 BUG_ON(size > PAGE_SIZE); 454 BUG_ON(va & ~PAGE_MASK); 455 456 pfn = virt_to_pfn(va); 457 mfn = pfn_to_mfn(pfn); 458 459 pte = pfn_pte(pfn, PAGE_KERNEL_RO); 460 461 if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 462 BUG(); 463 464 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 465 BUG(); 466 } 467 468 static inline bool desc_equal(const struct desc_struct *d1, 469 const struct desc_struct *d2) 470 { 471 return !memcmp(d1, d2, sizeof(*d1)); 472 } 473 474 static void load_TLS_descriptor(struct thread_struct *t, 475 unsigned int cpu, unsigned int i) 476 { 477 struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i]; 478 struct desc_struct *gdt; 479 xmaddr_t maddr; 480 struct multicall_space mc; 481 482 if (desc_equal(shadow, &t->tls_array[i])) 483 return; 484 485 *shadow = t->tls_array[i]; 486 487 gdt = get_cpu_gdt_rw(cpu); 488 maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]); 489 mc = __xen_mc_entry(0); 490 491 MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]); 492 } 493 494 static void xen_load_tls(struct thread_struct *t, unsigned int cpu) 495 { 496 /* 497 * In lazy mode we need to zero %fs, otherwise we may get an 498 * exception between the new %fs descriptor being loaded and 499 * %fs being effectively cleared at __switch_to(). 500 */ 501 if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU) 502 loadsegment(fs, 0); 503 504 xen_mc_batch(); 505 506 load_TLS_descriptor(t, cpu, 0); 507 load_TLS_descriptor(t, cpu, 1); 508 load_TLS_descriptor(t, cpu, 2); 509 510 xen_mc_issue(PARAVIRT_LAZY_CPU); 511 } 512 513 static void xen_load_gs_index(unsigned int idx) 514 { 515 if (HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, idx)) 516 BUG(); 517 } 518 519 static void xen_write_ldt_entry(struct desc_struct *dt, int entrynum, 520 const void *ptr) 521 { 522 xmaddr_t mach_lp = arbitrary_virt_to_machine(&dt[entrynum]); 523 u64 entry = *(u64 *)ptr; 524 525 trace_xen_cpu_write_ldt_entry(dt, entrynum, entry); 526 527 preempt_disable(); 528 529 xen_mc_flush(); 530 if (HYPERVISOR_update_descriptor(mach_lp.maddr, entry)) 531 BUG(); 532 533 preempt_enable(); 534 } 535 536 void noist_exc_debug(struct pt_regs *regs); 537 538 DEFINE_IDTENTRY_RAW(xenpv_exc_nmi) 539 { 540 /* On Xen PV, NMI doesn't use IST. The C part is the same as native. */ 541 exc_nmi(regs); 542 } 543 544 DEFINE_IDTENTRY_RAW_ERRORCODE(xenpv_exc_double_fault) 545 { 546 /* On Xen PV, DF doesn't use IST. The C part is the same as native. */ 547 exc_double_fault(regs, error_code); 548 } 549 550 DEFINE_IDTENTRY_RAW(xenpv_exc_debug) 551 { 552 /* 553 * There's no IST on Xen PV, but we still need to dispatch 554 * to the correct handler. 555 */ 556 if (user_mode(regs)) 557 noist_exc_debug(regs); 558 else 559 exc_debug(regs); 560 } 561 562 DEFINE_IDTENTRY_RAW(exc_xen_unknown_trap) 563 { 564 /* This should never happen and there is no way to handle it. */ 565 instrumentation_begin(); 566 pr_err("Unknown trap in Xen PV mode."); 567 BUG(); 568 instrumentation_end(); 569 } 570 571 #ifdef CONFIG_X86_MCE 572 DEFINE_IDTENTRY_RAW(xenpv_exc_machine_check) 573 { 574 /* 575 * There's no IST on Xen PV, but we still need to dispatch 576 * to the correct handler. 577 */ 578 if (user_mode(regs)) 579 noist_exc_machine_check(regs); 580 else 581 exc_machine_check(regs); 582 } 583 #endif 584 585 struct trap_array_entry { 586 void (*orig)(void); 587 void (*xen)(void); 588 bool ist_okay; 589 }; 590 591 #define TRAP_ENTRY(func, ist_ok) { \ 592 .orig = asm_##func, \ 593 .xen = xen_asm_##func, \ 594 .ist_okay = ist_ok } 595 596 #define TRAP_ENTRY_REDIR(func, ist_ok) { \ 597 .orig = asm_##func, \ 598 .xen = xen_asm_xenpv_##func, \ 599 .ist_okay = ist_ok } 600 601 static struct trap_array_entry trap_array[] = { 602 TRAP_ENTRY_REDIR(exc_debug, true ), 603 TRAP_ENTRY_REDIR(exc_double_fault, true ), 604 #ifdef CONFIG_X86_MCE 605 TRAP_ENTRY_REDIR(exc_machine_check, true ), 606 #endif 607 TRAP_ENTRY_REDIR(exc_nmi, true ), 608 TRAP_ENTRY(exc_int3, false ), 609 TRAP_ENTRY(exc_overflow, false ), 610 #ifdef CONFIG_IA32_EMULATION 611 { entry_INT80_compat, xen_entry_INT80_compat, false }, 612 #endif 613 TRAP_ENTRY(exc_page_fault, false ), 614 TRAP_ENTRY(exc_divide_error, false ), 615 TRAP_ENTRY(exc_bounds, false ), 616 TRAP_ENTRY(exc_invalid_op, false ), 617 TRAP_ENTRY(exc_device_not_available, false ), 618 TRAP_ENTRY(exc_coproc_segment_overrun, false ), 619 TRAP_ENTRY(exc_invalid_tss, false ), 620 TRAP_ENTRY(exc_segment_not_present, false ), 621 TRAP_ENTRY(exc_stack_segment, false ), 622 TRAP_ENTRY(exc_general_protection, false ), 623 TRAP_ENTRY(exc_spurious_interrupt_bug, false ), 624 TRAP_ENTRY(exc_coprocessor_error, false ), 625 TRAP_ENTRY(exc_alignment_check, false ), 626 TRAP_ENTRY(exc_simd_coprocessor_error, false ), 627 }; 628 629 static bool __ref get_trap_addr(void **addr, unsigned int ist) 630 { 631 unsigned int nr; 632 bool ist_okay = false; 633 bool found = false; 634 635 /* 636 * Replace trap handler addresses by Xen specific ones. 637 * Check for known traps using IST and whitelist them. 638 * The debugger ones are the only ones we care about. 639 * Xen will handle faults like double_fault, so we should never see 640 * them. Warn if there's an unexpected IST-using fault handler. 641 */ 642 for (nr = 0; nr < ARRAY_SIZE(trap_array); nr++) { 643 struct trap_array_entry *entry = trap_array + nr; 644 645 if (*addr == entry->orig) { 646 *addr = entry->xen; 647 ist_okay = entry->ist_okay; 648 found = true; 649 break; 650 } 651 } 652 653 if (nr == ARRAY_SIZE(trap_array) && 654 *addr >= (void *)early_idt_handler_array[0] && 655 *addr < (void *)early_idt_handler_array[NUM_EXCEPTION_VECTORS]) { 656 nr = (*addr - (void *)early_idt_handler_array[0]) / 657 EARLY_IDT_HANDLER_SIZE; 658 *addr = (void *)xen_early_idt_handler_array[nr]; 659 found = true; 660 } 661 662 if (!found) 663 *addr = (void *)xen_asm_exc_xen_unknown_trap; 664 665 if (WARN_ON(found && ist != 0 && !ist_okay)) 666 return false; 667 668 return true; 669 } 670 671 static int cvt_gate_to_trap(int vector, const gate_desc *val, 672 struct trap_info *info) 673 { 674 unsigned long addr; 675 676 if (val->bits.type != GATE_TRAP && val->bits.type != GATE_INTERRUPT) 677 return 0; 678 679 info->vector = vector; 680 681 addr = gate_offset(val); 682 if (!get_trap_addr((void **)&addr, val->bits.ist)) 683 return 0; 684 info->address = addr; 685 686 info->cs = gate_segment(val); 687 info->flags = val->bits.dpl; 688 /* interrupt gates clear IF */ 689 if (val->bits.type == GATE_INTERRUPT) 690 info->flags |= 1 << 2; 691 692 return 1; 693 } 694 695 /* Locations of each CPU's IDT */ 696 static DEFINE_PER_CPU(struct desc_ptr, idt_desc); 697 698 /* Set an IDT entry. If the entry is part of the current IDT, then 699 also update Xen. */ 700 static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g) 701 { 702 unsigned long p = (unsigned long)&dt[entrynum]; 703 unsigned long start, end; 704 705 trace_xen_cpu_write_idt_entry(dt, entrynum, g); 706 707 preempt_disable(); 708 709 start = __this_cpu_read(idt_desc.address); 710 end = start + __this_cpu_read(idt_desc.size) + 1; 711 712 xen_mc_flush(); 713 714 native_write_idt_entry(dt, entrynum, g); 715 716 if (p >= start && (p + 8) <= end) { 717 struct trap_info info[2]; 718 719 info[1].address = 0; 720 721 if (cvt_gate_to_trap(entrynum, g, &info[0])) 722 if (HYPERVISOR_set_trap_table(info)) 723 BUG(); 724 } 725 726 preempt_enable(); 727 } 728 729 static unsigned xen_convert_trap_info(const struct desc_ptr *desc, 730 struct trap_info *traps, bool full) 731 { 732 unsigned in, out, count; 733 734 count = (desc->size+1) / sizeof(gate_desc); 735 BUG_ON(count > 256); 736 737 for (in = out = 0; in < count; in++) { 738 gate_desc *entry = (gate_desc *)(desc->address) + in; 739 740 if (cvt_gate_to_trap(in, entry, &traps[out]) || full) 741 out++; 742 } 743 744 return out; 745 } 746 747 void xen_copy_trap_info(struct trap_info *traps) 748 { 749 const struct desc_ptr *desc = this_cpu_ptr(&idt_desc); 750 751 xen_convert_trap_info(desc, traps, true); 752 } 753 754 /* Load a new IDT into Xen. In principle this can be per-CPU, so we 755 hold a spinlock to protect the static traps[] array (static because 756 it avoids allocation, and saves stack space). */ 757 static void xen_load_idt(const struct desc_ptr *desc) 758 { 759 static DEFINE_SPINLOCK(lock); 760 static struct trap_info traps[257]; 761 unsigned out; 762 763 trace_xen_cpu_load_idt(desc); 764 765 spin_lock(&lock); 766 767 memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc)); 768 769 out = xen_convert_trap_info(desc, traps, false); 770 memset(&traps[out], 0, sizeof(traps[0])); 771 772 xen_mc_flush(); 773 if (HYPERVISOR_set_trap_table(traps)) 774 BUG(); 775 776 spin_unlock(&lock); 777 } 778 779 /* Write a GDT descriptor entry. Ignore LDT descriptors, since 780 they're handled differently. */ 781 static void xen_write_gdt_entry(struct desc_struct *dt, int entry, 782 const void *desc, int type) 783 { 784 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 785 786 preempt_disable(); 787 788 switch (type) { 789 case DESC_LDT: 790 case DESC_TSS: 791 /* ignore */ 792 break; 793 794 default: { 795 xmaddr_t maddr = arbitrary_virt_to_machine(&dt[entry]); 796 797 xen_mc_flush(); 798 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 799 BUG(); 800 } 801 802 } 803 804 preempt_enable(); 805 } 806 807 /* 808 * Version of write_gdt_entry for use at early boot-time needed to 809 * update an entry as simply as possible. 810 */ 811 static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry, 812 const void *desc, int type) 813 { 814 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 815 816 switch (type) { 817 case DESC_LDT: 818 case DESC_TSS: 819 /* ignore */ 820 break; 821 822 default: { 823 xmaddr_t maddr = virt_to_machine(&dt[entry]); 824 825 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 826 dt[entry] = *(struct desc_struct *)desc; 827 } 828 829 } 830 } 831 832 static void xen_load_sp0(unsigned long sp0) 833 { 834 struct multicall_space mcs; 835 836 mcs = xen_mc_entry(0); 837 MULTI_stack_switch(mcs.mc, __KERNEL_DS, sp0); 838 xen_mc_issue(PARAVIRT_LAZY_CPU); 839 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 840 } 841 842 #ifdef CONFIG_X86_IOPL_IOPERM 843 static void xen_invalidate_io_bitmap(void) 844 { 845 struct physdev_set_iobitmap iobitmap = { 846 .bitmap = NULL, 847 .nr_ports = 0, 848 }; 849 850 native_tss_invalidate_io_bitmap(); 851 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 852 } 853 854 static void xen_update_io_bitmap(void) 855 { 856 struct physdev_set_iobitmap iobitmap; 857 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 858 859 native_tss_update_io_bitmap(); 860 861 iobitmap.bitmap = (uint8_t *)(&tss->x86_tss) + 862 tss->x86_tss.io_bitmap_base; 863 if (tss->x86_tss.io_bitmap_base == IO_BITMAP_OFFSET_INVALID) 864 iobitmap.nr_ports = 0; 865 else 866 iobitmap.nr_ports = IO_BITMAP_BITS; 867 868 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 869 } 870 #endif 871 872 static void xen_io_delay(void) 873 { 874 } 875 876 static DEFINE_PER_CPU(unsigned long, xen_cr0_value); 877 878 static unsigned long xen_read_cr0(void) 879 { 880 unsigned long cr0 = this_cpu_read(xen_cr0_value); 881 882 if (unlikely(cr0 == 0)) { 883 cr0 = native_read_cr0(); 884 this_cpu_write(xen_cr0_value, cr0); 885 } 886 887 return cr0; 888 } 889 890 static void xen_write_cr0(unsigned long cr0) 891 { 892 struct multicall_space mcs; 893 894 this_cpu_write(xen_cr0_value, cr0); 895 896 /* Only pay attention to cr0.TS; everything else is 897 ignored. */ 898 mcs = xen_mc_entry(0); 899 900 MULTI_fpu_taskswitch(mcs.mc, (cr0 & X86_CR0_TS) != 0); 901 902 xen_mc_issue(PARAVIRT_LAZY_CPU); 903 } 904 905 static void xen_write_cr4(unsigned long cr4) 906 { 907 cr4 &= ~(X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PCE); 908 909 native_write_cr4(cr4); 910 } 911 912 static u64 xen_read_msr_safe(unsigned int msr, int *err) 913 { 914 u64 val; 915 916 if (pmu_msr_read(msr, &val, err)) 917 return val; 918 919 val = native_read_msr_safe(msr, err); 920 switch (msr) { 921 case MSR_IA32_APICBASE: 922 val &= ~X2APIC_ENABLE; 923 break; 924 } 925 return val; 926 } 927 928 static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high) 929 { 930 int ret; 931 unsigned int which; 932 u64 base; 933 934 ret = 0; 935 936 switch (msr) { 937 case MSR_FS_BASE: which = SEGBASE_FS; goto set; 938 case MSR_KERNEL_GS_BASE: which = SEGBASE_GS_USER; goto set; 939 case MSR_GS_BASE: which = SEGBASE_GS_KERNEL; goto set; 940 941 set: 942 base = ((u64)high << 32) | low; 943 if (HYPERVISOR_set_segment_base(which, base) != 0) 944 ret = -EIO; 945 break; 946 947 case MSR_STAR: 948 case MSR_CSTAR: 949 case MSR_LSTAR: 950 case MSR_SYSCALL_MASK: 951 case MSR_IA32_SYSENTER_CS: 952 case MSR_IA32_SYSENTER_ESP: 953 case MSR_IA32_SYSENTER_EIP: 954 /* Fast syscall setup is all done in hypercalls, so 955 these are all ignored. Stub them out here to stop 956 Xen console noise. */ 957 break; 958 959 default: 960 if (!pmu_msr_write(msr, low, high, &ret)) 961 ret = native_write_msr_safe(msr, low, high); 962 } 963 964 return ret; 965 } 966 967 static u64 xen_read_msr(unsigned int msr) 968 { 969 /* 970 * This will silently swallow a #GP from RDMSR. It may be worth 971 * changing that. 972 */ 973 int err; 974 975 return xen_read_msr_safe(msr, &err); 976 } 977 978 static void xen_write_msr(unsigned int msr, unsigned low, unsigned high) 979 { 980 /* 981 * This will silently swallow a #GP from WRMSR. It may be worth 982 * changing that. 983 */ 984 xen_write_msr_safe(msr, low, high); 985 } 986 987 /* This is called once we have the cpu_possible_mask */ 988 void __init xen_setup_vcpu_info_placement(void) 989 { 990 int cpu; 991 992 for_each_possible_cpu(cpu) { 993 /* Set up direct vCPU id mapping for PV guests. */ 994 per_cpu(xen_vcpu_id, cpu) = cpu; 995 xen_vcpu_setup(cpu); 996 } 997 998 pv_ops.irq.save_fl = __PV_IS_CALLEE_SAVE(xen_save_fl_direct); 999 pv_ops.irq.irq_disable = __PV_IS_CALLEE_SAVE(xen_irq_disable_direct); 1000 pv_ops.irq.irq_enable = __PV_IS_CALLEE_SAVE(xen_irq_enable_direct); 1001 pv_ops.mmu.read_cr2 = __PV_IS_CALLEE_SAVE(xen_read_cr2_direct); 1002 } 1003 1004 static const struct pv_info xen_info __initconst = { 1005 .extra_user_64bit_cs = FLAT_USER_CS64, 1006 .name = "Xen", 1007 }; 1008 1009 static const typeof(pv_ops) xen_cpu_ops __initconst = { 1010 .cpu = { 1011 .cpuid = xen_cpuid, 1012 1013 .set_debugreg = xen_set_debugreg, 1014 .get_debugreg = xen_get_debugreg, 1015 1016 .read_cr0 = xen_read_cr0, 1017 .write_cr0 = xen_write_cr0, 1018 1019 .write_cr4 = xen_write_cr4, 1020 1021 .wbinvd = native_wbinvd, 1022 1023 .read_msr = xen_read_msr, 1024 .write_msr = xen_write_msr, 1025 1026 .read_msr_safe = xen_read_msr_safe, 1027 .write_msr_safe = xen_write_msr_safe, 1028 1029 .read_pmc = xen_read_pmc, 1030 1031 .load_tr_desc = paravirt_nop, 1032 .set_ldt = xen_set_ldt, 1033 .load_gdt = xen_load_gdt, 1034 .load_idt = xen_load_idt, 1035 .load_tls = xen_load_tls, 1036 .load_gs_index = xen_load_gs_index, 1037 1038 .alloc_ldt = xen_alloc_ldt, 1039 .free_ldt = xen_free_ldt, 1040 1041 .store_tr = xen_store_tr, 1042 1043 .write_ldt_entry = xen_write_ldt_entry, 1044 .write_gdt_entry = xen_write_gdt_entry, 1045 .write_idt_entry = xen_write_idt_entry, 1046 .load_sp0 = xen_load_sp0, 1047 1048 #ifdef CONFIG_X86_IOPL_IOPERM 1049 .invalidate_io_bitmap = xen_invalidate_io_bitmap, 1050 .update_io_bitmap = xen_update_io_bitmap, 1051 #endif 1052 .io_delay = xen_io_delay, 1053 1054 .start_context_switch = paravirt_start_context_switch, 1055 .end_context_switch = xen_end_context_switch, 1056 }, 1057 }; 1058 1059 static void xen_restart(char *msg) 1060 { 1061 xen_reboot(SHUTDOWN_reboot); 1062 } 1063 1064 static void xen_machine_halt(void) 1065 { 1066 xen_reboot(SHUTDOWN_poweroff); 1067 } 1068 1069 static void xen_machine_power_off(void) 1070 { 1071 if (pm_power_off) 1072 pm_power_off(); 1073 xen_reboot(SHUTDOWN_poweroff); 1074 } 1075 1076 static void xen_crash_shutdown(struct pt_regs *regs) 1077 { 1078 xen_reboot(SHUTDOWN_crash); 1079 } 1080 1081 static const struct machine_ops xen_machine_ops __initconst = { 1082 .restart = xen_restart, 1083 .halt = xen_machine_halt, 1084 .power_off = xen_machine_power_off, 1085 .shutdown = xen_machine_halt, 1086 .crash_shutdown = xen_crash_shutdown, 1087 .emergency_restart = xen_emergency_restart, 1088 }; 1089 1090 static unsigned char xen_get_nmi_reason(void) 1091 { 1092 unsigned char reason = 0; 1093 1094 /* Construct a value which looks like it came from port 0x61. */ 1095 if (test_bit(_XEN_NMIREASON_io_error, 1096 &HYPERVISOR_shared_info->arch.nmi_reason)) 1097 reason |= NMI_REASON_IOCHK; 1098 if (test_bit(_XEN_NMIREASON_pci_serr, 1099 &HYPERVISOR_shared_info->arch.nmi_reason)) 1100 reason |= NMI_REASON_SERR; 1101 1102 return reason; 1103 } 1104 1105 static void __init xen_boot_params_init_edd(void) 1106 { 1107 #if IS_ENABLED(CONFIG_EDD) 1108 struct xen_platform_op op; 1109 struct edd_info *edd_info; 1110 u32 *mbr_signature; 1111 unsigned nr; 1112 int ret; 1113 1114 edd_info = boot_params.eddbuf; 1115 mbr_signature = boot_params.edd_mbr_sig_buffer; 1116 1117 op.cmd = XENPF_firmware_info; 1118 1119 op.u.firmware_info.type = XEN_FW_DISK_INFO; 1120 for (nr = 0; nr < EDDMAXNR; nr++) { 1121 struct edd_info *info = edd_info + nr; 1122 1123 op.u.firmware_info.index = nr; 1124 info->params.length = sizeof(info->params); 1125 set_xen_guest_handle(op.u.firmware_info.u.disk_info.edd_params, 1126 &info->params); 1127 ret = HYPERVISOR_platform_op(&op); 1128 if (ret) 1129 break; 1130 1131 #define C(x) info->x = op.u.firmware_info.u.disk_info.x 1132 C(device); 1133 C(version); 1134 C(interface_support); 1135 C(legacy_max_cylinder); 1136 C(legacy_max_head); 1137 C(legacy_sectors_per_track); 1138 #undef C 1139 } 1140 boot_params.eddbuf_entries = nr; 1141 1142 op.u.firmware_info.type = XEN_FW_DISK_MBR_SIGNATURE; 1143 for (nr = 0; nr < EDD_MBR_SIG_MAX; nr++) { 1144 op.u.firmware_info.index = nr; 1145 ret = HYPERVISOR_platform_op(&op); 1146 if (ret) 1147 break; 1148 mbr_signature[nr] = op.u.firmware_info.u.disk_mbr_signature.mbr_signature; 1149 } 1150 boot_params.edd_mbr_sig_buf_entries = nr; 1151 #endif 1152 } 1153 1154 /* 1155 * Set up the GDT and segment registers for -fstack-protector. Until 1156 * we do this, we have to be careful not to call any stack-protected 1157 * function, which is most of the kernel. 1158 */ 1159 static void __init xen_setup_gdt(int cpu) 1160 { 1161 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry_boot; 1162 pv_ops.cpu.load_gdt = xen_load_gdt_boot; 1163 1164 switch_to_new_gdt(cpu); 1165 1166 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry; 1167 pv_ops.cpu.load_gdt = xen_load_gdt; 1168 } 1169 1170 static void __init xen_dom0_set_legacy_features(void) 1171 { 1172 x86_platform.legacy.rtc = 1; 1173 } 1174 1175 static void __init xen_domu_set_legacy_features(void) 1176 { 1177 x86_platform.legacy.rtc = 0; 1178 } 1179 1180 /* First C function to be called on Xen boot */ 1181 asmlinkage __visible void __init xen_start_kernel(void) 1182 { 1183 struct physdev_set_iopl set_iopl; 1184 unsigned long initrd_start = 0; 1185 int rc; 1186 1187 if (!xen_start_info) 1188 return; 1189 1190 xen_domain_type = XEN_PV_DOMAIN; 1191 xen_start_flags = xen_start_info->flags; 1192 1193 xen_setup_features(); 1194 1195 /* Install Xen paravirt ops */ 1196 pv_info = xen_info; 1197 pv_ops.cpu = xen_cpu_ops.cpu; 1198 paravirt_iret = xen_iret; 1199 xen_init_irq_ops(); 1200 1201 /* 1202 * Setup xen_vcpu early because it is needed for 1203 * local_irq_disable(), irqs_disabled(), e.g. in printk(). 1204 * 1205 * Don't do the full vcpu_info placement stuff until we have 1206 * the cpu_possible_mask and a non-dummy shared_info. 1207 */ 1208 xen_vcpu_info_reset(0); 1209 1210 x86_platform.get_nmi_reason = xen_get_nmi_reason; 1211 1212 x86_init.resources.memory_setup = xen_memory_setup; 1213 x86_init.irqs.intr_mode_select = x86_init_noop; 1214 x86_init.irqs.intr_mode_init = x86_init_noop; 1215 x86_init.oem.arch_setup = xen_arch_setup; 1216 x86_init.oem.banner = xen_banner; 1217 x86_init.hyper.init_platform = xen_pv_init_platform; 1218 x86_init.hyper.guest_late_init = xen_pv_guest_late_init; 1219 1220 /* 1221 * Set up some pagetable state before starting to set any ptes. 1222 */ 1223 1224 xen_setup_machphys_mapping(); 1225 xen_init_mmu_ops(); 1226 1227 /* Prevent unwanted bits from being set in PTEs. */ 1228 __supported_pte_mask &= ~_PAGE_GLOBAL; 1229 __default_kernel_pte_mask &= ~_PAGE_GLOBAL; 1230 1231 /* Get mfn list */ 1232 xen_build_dynamic_phys_to_machine(); 1233 1234 /* Work out if we support NX */ 1235 get_cpu_cap(&boot_cpu_data); 1236 x86_configure_nx(); 1237 1238 /* 1239 * Set up kernel GDT and segment registers, mainly so that 1240 * -fstack-protector code can be executed. 1241 */ 1242 xen_setup_gdt(0); 1243 1244 /* Determine virtual and physical address sizes */ 1245 get_cpu_address_sizes(&boot_cpu_data); 1246 1247 /* Let's presume PV guests always boot on vCPU with id 0. */ 1248 per_cpu(xen_vcpu_id, 0) = 0; 1249 1250 idt_setup_early_handler(); 1251 1252 xen_init_capabilities(); 1253 1254 #ifdef CONFIG_X86_LOCAL_APIC 1255 /* 1256 * set up the basic apic ops. 1257 */ 1258 xen_init_apic(); 1259 #endif 1260 1261 machine_ops = xen_machine_ops; 1262 1263 /* 1264 * The only reliable way to retain the initial address of the 1265 * percpu gdt_page is to remember it here, so we can go and 1266 * mark it RW later, when the initial percpu area is freed. 1267 */ 1268 xen_initial_gdt = &per_cpu(gdt_page, 0); 1269 1270 xen_smp_init(); 1271 1272 #ifdef CONFIG_ACPI_NUMA 1273 /* 1274 * The pages we from Xen are not related to machine pages, so 1275 * any NUMA information the kernel tries to get from ACPI will 1276 * be meaningless. Prevent it from trying. 1277 */ 1278 disable_srat(); 1279 #endif 1280 WARN_ON(xen_cpuhp_setup(xen_cpu_up_prepare_pv, xen_cpu_dead_pv)); 1281 1282 local_irq_disable(); 1283 early_boot_irqs_disabled = true; 1284 1285 xen_raw_console_write("mapping kernel into physical memory\n"); 1286 xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base, 1287 xen_start_info->nr_pages); 1288 xen_reserve_special_pages(); 1289 1290 /* 1291 * We used to do this in xen_arch_setup, but that is too late 1292 * on AMD were early_cpu_init (run before ->arch_setup()) calls 1293 * early_amd_init which pokes 0xcf8 port. 1294 */ 1295 set_iopl.iopl = 1; 1296 rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl); 1297 if (rc != 0) 1298 xen_raw_printk("physdev_op failed %d\n", rc); 1299 1300 1301 if (xen_start_info->mod_start) { 1302 if (xen_start_info->flags & SIF_MOD_START_PFN) 1303 initrd_start = PFN_PHYS(xen_start_info->mod_start); 1304 else 1305 initrd_start = __pa(xen_start_info->mod_start); 1306 } 1307 1308 /* Poke various useful things into boot_params */ 1309 boot_params.hdr.type_of_loader = (9 << 4) | 0; 1310 boot_params.hdr.ramdisk_image = initrd_start; 1311 boot_params.hdr.ramdisk_size = xen_start_info->mod_len; 1312 boot_params.hdr.cmd_line_ptr = __pa(xen_start_info->cmd_line); 1313 boot_params.hdr.hardware_subarch = X86_SUBARCH_XEN; 1314 1315 if (!xen_initial_domain()) { 1316 if (pci_xen) 1317 x86_init.pci.arch_init = pci_xen_init; 1318 x86_platform.set_legacy_features = 1319 xen_domu_set_legacy_features; 1320 } else { 1321 const struct dom0_vga_console_info *info = 1322 (void *)((char *)xen_start_info + 1323 xen_start_info->console.dom0.info_off); 1324 struct xen_platform_op op = { 1325 .cmd = XENPF_firmware_info, 1326 .interface_version = XENPF_INTERFACE_VERSION, 1327 .u.firmware_info.type = XEN_FW_KBD_SHIFT_FLAGS, 1328 }; 1329 1330 x86_platform.set_legacy_features = 1331 xen_dom0_set_legacy_features; 1332 xen_init_vga(info, xen_start_info->console.dom0.info_size); 1333 xen_start_info->console.domU.mfn = 0; 1334 xen_start_info->console.domU.evtchn = 0; 1335 1336 if (HYPERVISOR_platform_op(&op) == 0) 1337 boot_params.kbd_status = op.u.firmware_info.u.kbd_shift_flags; 1338 1339 /* Make sure ACS will be enabled */ 1340 pci_request_acs(); 1341 1342 xen_acpi_sleep_register(); 1343 1344 /* Avoid searching for BIOS MP tables */ 1345 x86_init.mpparse.find_smp_config = x86_init_noop; 1346 x86_init.mpparse.get_smp_config = x86_init_uint_noop; 1347 1348 xen_boot_params_init_edd(); 1349 1350 #ifdef CONFIG_ACPI 1351 /* 1352 * Disable selecting "Firmware First mode" for correctable 1353 * memory errors, as this is the duty of the hypervisor to 1354 * decide. 1355 */ 1356 acpi_disable_cmcff = 1; 1357 #endif 1358 } 1359 1360 xen_add_preferred_consoles(); 1361 1362 #ifdef CONFIG_PCI 1363 /* PCI BIOS service won't work from a PV guest. */ 1364 pci_probe &= ~PCI_PROBE_BIOS; 1365 #endif 1366 xen_raw_console_write("about to get started...\n"); 1367 1368 /* We need this for printk timestamps */ 1369 xen_setup_runstate_info(0); 1370 1371 xen_efi_init(&boot_params); 1372 1373 /* Start the world */ 1374 cr4_init_shadow(); /* 32b kernel does this in i386_start_kernel() */ 1375 x86_64_start_reservations((char *)__pa_symbol(&boot_params)); 1376 } 1377 1378 static int xen_cpu_up_prepare_pv(unsigned int cpu) 1379 { 1380 int rc; 1381 1382 if (per_cpu(xen_vcpu, cpu) == NULL) 1383 return -ENODEV; 1384 1385 xen_setup_timer(cpu); 1386 1387 rc = xen_smp_intr_init(cpu); 1388 if (rc) { 1389 WARN(1, "xen_smp_intr_init() for CPU %d failed: %d\n", 1390 cpu, rc); 1391 return rc; 1392 } 1393 1394 rc = xen_smp_intr_init_pv(cpu); 1395 if (rc) { 1396 WARN(1, "xen_smp_intr_init_pv() for CPU %d failed: %d\n", 1397 cpu, rc); 1398 return rc; 1399 } 1400 1401 return 0; 1402 } 1403 1404 static int xen_cpu_dead_pv(unsigned int cpu) 1405 { 1406 xen_smp_intr_free(cpu); 1407 xen_smp_intr_free_pv(cpu); 1408 1409 xen_teardown_timer(cpu); 1410 1411 return 0; 1412 } 1413 1414 static uint32_t __init xen_platform_pv(void) 1415 { 1416 if (xen_pv_domain()) 1417 return xen_cpuid_base(); 1418 1419 return 0; 1420 } 1421 1422 const __initconst struct hypervisor_x86 x86_hyper_xen_pv = { 1423 .name = "Xen PV", 1424 .detect = xen_platform_pv, 1425 .type = X86_HYPER_XEN_PV, 1426 .runtime.pin_vcpu = xen_pin_vcpu, 1427 .ignore_nopv = true, 1428 }; 1429