1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/uaccess.h> 39 #include <linux/pci.h> 40 #include <linux/pm_runtime.h> 41 #include "amdgpu_amdkfd.h" 42 #include "amdgpu_gem.h" 43 #include "amdgpu_display.h" 44 #include "amdgpu_ras.h" 45 46 static void amdgpu_runtime_pm_quirk(struct amdgpu_device *adev) 47 { 48 /* 49 * Add below quirk on several sienna_cichlid cards to disable 50 * runtime pm to fix EMI failures. 51 */ 52 if (((adev->pdev->device == 0x73A1) && (adev->pdev->revision == 0x00)) || 53 ((adev->pdev->device == 0x73BF) && (adev->pdev->revision == 0xCF))) 54 adev->runpm = false; 55 } 56 57 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 58 { 59 struct amdgpu_gpu_instance *gpu_instance; 60 int i; 61 62 mutex_lock(&mgpu_info.mutex); 63 64 for (i = 0; i < mgpu_info.num_gpu; i++) { 65 gpu_instance = &(mgpu_info.gpu_ins[i]); 66 if (gpu_instance->adev == adev) { 67 mgpu_info.gpu_ins[i] = 68 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 69 mgpu_info.num_gpu--; 70 if (adev->flags & AMD_IS_APU) 71 mgpu_info.num_apu--; 72 else 73 mgpu_info.num_dgpu--; 74 break; 75 } 76 } 77 78 mutex_unlock(&mgpu_info.mutex); 79 } 80 81 /** 82 * amdgpu_driver_unload_kms - Main unload function for KMS. 83 * 84 * @dev: drm dev pointer 85 * 86 * This is the main unload function for KMS (all asics). 87 * Returns 0 on success. 88 */ 89 void amdgpu_driver_unload_kms(struct drm_device *dev) 90 { 91 struct amdgpu_device *adev = drm_to_adev(dev); 92 93 if (adev == NULL) 94 return; 95 96 amdgpu_unregister_gpu_instance(adev); 97 98 if (adev->rmmio == NULL) 99 return; 100 101 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 102 DRM_WARN("smart shift update failed\n"); 103 104 amdgpu_acpi_fini(adev); 105 amdgpu_device_fini_hw(adev); 106 } 107 108 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 109 { 110 struct amdgpu_gpu_instance *gpu_instance; 111 112 mutex_lock(&mgpu_info.mutex); 113 114 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 115 DRM_ERROR("Cannot register more gpu instance\n"); 116 mutex_unlock(&mgpu_info.mutex); 117 return; 118 } 119 120 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 121 gpu_instance->adev = adev; 122 gpu_instance->mgpu_fan_enabled = 0; 123 124 mgpu_info.num_gpu++; 125 if (adev->flags & AMD_IS_APU) 126 mgpu_info.num_apu++; 127 else 128 mgpu_info.num_dgpu++; 129 130 mutex_unlock(&mgpu_info.mutex); 131 } 132 133 /** 134 * amdgpu_driver_load_kms - Main load function for KMS. 135 * 136 * @adev: pointer to struct amdgpu_device 137 * @flags: device flags 138 * 139 * This is the main load function for KMS (all asics). 140 * Returns 0 on success, error on failure. 141 */ 142 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 143 { 144 struct drm_device *dev; 145 int r, acpi_status; 146 147 dev = adev_to_drm(adev); 148 149 /* amdgpu_device_init should report only fatal error 150 * like memory allocation failure or iomapping failure, 151 * or memory manager initialization failure, it must 152 * properly initialize the GPU MC controller and permit 153 * VRAM allocation 154 */ 155 r = amdgpu_device_init(adev, flags); 156 if (r) { 157 dev_err(dev->dev, "Fatal error during GPU init\n"); 158 goto out; 159 } 160 161 if (amdgpu_device_supports_px(dev) && 162 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */ 163 adev->runpm = true; 164 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 165 } else if (amdgpu_device_supports_boco(dev) && 166 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */ 167 adev->runpm = true; 168 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 169 } else if (amdgpu_device_supports_baco(dev) && 170 (amdgpu_runtime_pm != 0)) { 171 switch (adev->asic_type) { 172 case CHIP_VEGA20: 173 case CHIP_ARCTURUS: 174 /* enable runpm if runpm=1 */ 175 if (amdgpu_runtime_pm > 0) 176 adev->runpm = true; 177 break; 178 case CHIP_VEGA10: 179 /* turn runpm on if noretry=0 */ 180 if (!adev->gmc.noretry) 181 adev->runpm = true; 182 break; 183 default: 184 /* enable runpm on CI+ */ 185 adev->runpm = true; 186 break; 187 } 188 189 amdgpu_runtime_pm_quirk(adev); 190 191 if (adev->runpm) 192 dev_info(adev->dev, "Using BACO for runtime pm\n"); 193 } 194 195 /* Call ACPI methods: require modeset init 196 * but failure is not fatal 197 */ 198 199 acpi_status = amdgpu_acpi_init(adev); 200 if (acpi_status) 201 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 202 203 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 204 DRM_WARN("smart shift update failed\n"); 205 206 out: 207 if (r) 208 amdgpu_driver_unload_kms(dev); 209 210 return r; 211 } 212 213 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 214 struct drm_amdgpu_query_fw *query_fw, 215 struct amdgpu_device *adev) 216 { 217 switch (query_fw->fw_type) { 218 case AMDGPU_INFO_FW_VCE: 219 fw_info->ver = adev->vce.fw_version; 220 fw_info->feature = adev->vce.fb_version; 221 break; 222 case AMDGPU_INFO_FW_UVD: 223 fw_info->ver = adev->uvd.fw_version; 224 fw_info->feature = 0; 225 break; 226 case AMDGPU_INFO_FW_VCN: 227 fw_info->ver = adev->vcn.fw_version; 228 fw_info->feature = 0; 229 break; 230 case AMDGPU_INFO_FW_GMC: 231 fw_info->ver = adev->gmc.fw_version; 232 fw_info->feature = 0; 233 break; 234 case AMDGPU_INFO_FW_GFX_ME: 235 fw_info->ver = adev->gfx.me_fw_version; 236 fw_info->feature = adev->gfx.me_feature_version; 237 break; 238 case AMDGPU_INFO_FW_GFX_PFP: 239 fw_info->ver = adev->gfx.pfp_fw_version; 240 fw_info->feature = adev->gfx.pfp_feature_version; 241 break; 242 case AMDGPU_INFO_FW_GFX_CE: 243 fw_info->ver = adev->gfx.ce_fw_version; 244 fw_info->feature = adev->gfx.ce_feature_version; 245 break; 246 case AMDGPU_INFO_FW_GFX_RLC: 247 fw_info->ver = adev->gfx.rlc_fw_version; 248 fw_info->feature = adev->gfx.rlc_feature_version; 249 break; 250 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 251 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 252 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 253 break; 254 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 255 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 256 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 257 break; 258 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 259 fw_info->ver = adev->gfx.rlc_srls_fw_version; 260 fw_info->feature = adev->gfx.rlc_srls_feature_version; 261 break; 262 case AMDGPU_INFO_FW_GFX_MEC: 263 if (query_fw->index == 0) { 264 fw_info->ver = adev->gfx.mec_fw_version; 265 fw_info->feature = adev->gfx.mec_feature_version; 266 } else if (query_fw->index == 1) { 267 fw_info->ver = adev->gfx.mec2_fw_version; 268 fw_info->feature = adev->gfx.mec2_feature_version; 269 } else 270 return -EINVAL; 271 break; 272 case AMDGPU_INFO_FW_SMC: 273 fw_info->ver = adev->pm.fw_version; 274 fw_info->feature = 0; 275 break; 276 case AMDGPU_INFO_FW_TA: 277 switch (query_fw->index) { 278 case TA_FW_TYPE_PSP_XGMI: 279 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 280 fw_info->feature = adev->psp.xgmi_context.context 281 .bin_desc.feature_version; 282 break; 283 case TA_FW_TYPE_PSP_RAS: 284 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 285 fw_info->feature = adev->psp.ras_context.context 286 .bin_desc.feature_version; 287 break; 288 case TA_FW_TYPE_PSP_HDCP: 289 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 290 fw_info->feature = adev->psp.hdcp_context.context 291 .bin_desc.feature_version; 292 break; 293 case TA_FW_TYPE_PSP_DTM: 294 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 295 fw_info->feature = adev->psp.dtm_context.context 296 .bin_desc.feature_version; 297 break; 298 case TA_FW_TYPE_PSP_RAP: 299 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 300 fw_info->feature = adev->psp.rap_context.context 301 .bin_desc.feature_version; 302 break; 303 case TA_FW_TYPE_PSP_SECUREDISPLAY: 304 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 305 fw_info->feature = 306 adev->psp.securedisplay_context.context.bin_desc 307 .feature_version; 308 break; 309 default: 310 return -EINVAL; 311 } 312 break; 313 case AMDGPU_INFO_FW_SDMA: 314 if (query_fw->index >= adev->sdma.num_instances) 315 return -EINVAL; 316 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 317 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 318 break; 319 case AMDGPU_INFO_FW_SOS: 320 fw_info->ver = adev->psp.sos.fw_version; 321 fw_info->feature = adev->psp.sos.feature_version; 322 break; 323 case AMDGPU_INFO_FW_ASD: 324 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 325 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 326 break; 327 case AMDGPU_INFO_FW_DMCU: 328 fw_info->ver = adev->dm.dmcu_fw_version; 329 fw_info->feature = 0; 330 break; 331 case AMDGPU_INFO_FW_DMCUB: 332 fw_info->ver = adev->dm.dmcub_fw_version; 333 fw_info->feature = 0; 334 break; 335 case AMDGPU_INFO_FW_TOC: 336 fw_info->ver = adev->psp.toc.fw_version; 337 fw_info->feature = adev->psp.toc.feature_version; 338 break; 339 case AMDGPU_INFO_FW_CAP: 340 fw_info->ver = adev->psp.cap_fw_version; 341 fw_info->feature = adev->psp.cap_feature_version; 342 break; 343 default: 344 return -EINVAL; 345 } 346 return 0; 347 } 348 349 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 350 struct drm_amdgpu_info *info, 351 struct drm_amdgpu_info_hw_ip *result) 352 { 353 uint32_t ib_start_alignment = 0; 354 uint32_t ib_size_alignment = 0; 355 enum amd_ip_block_type type; 356 unsigned int num_rings = 0; 357 unsigned int i, j; 358 359 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 360 return -EINVAL; 361 362 switch (info->query_hw_ip.type) { 363 case AMDGPU_HW_IP_GFX: 364 type = AMD_IP_BLOCK_TYPE_GFX; 365 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 366 if (adev->gfx.gfx_ring[i].sched.ready) 367 ++num_rings; 368 ib_start_alignment = 32; 369 ib_size_alignment = 32; 370 break; 371 case AMDGPU_HW_IP_COMPUTE: 372 type = AMD_IP_BLOCK_TYPE_GFX; 373 for (i = 0; i < adev->gfx.num_compute_rings; i++) 374 if (adev->gfx.compute_ring[i].sched.ready) 375 ++num_rings; 376 ib_start_alignment = 32; 377 ib_size_alignment = 32; 378 break; 379 case AMDGPU_HW_IP_DMA: 380 type = AMD_IP_BLOCK_TYPE_SDMA; 381 for (i = 0; i < adev->sdma.num_instances; i++) 382 if (adev->sdma.instance[i].ring.sched.ready) 383 ++num_rings; 384 ib_start_alignment = 256; 385 ib_size_alignment = 4; 386 break; 387 case AMDGPU_HW_IP_UVD: 388 type = AMD_IP_BLOCK_TYPE_UVD; 389 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 390 if (adev->uvd.harvest_config & (1 << i)) 391 continue; 392 393 if (adev->uvd.inst[i].ring.sched.ready) 394 ++num_rings; 395 } 396 ib_start_alignment = 64; 397 ib_size_alignment = 64; 398 break; 399 case AMDGPU_HW_IP_VCE: 400 type = AMD_IP_BLOCK_TYPE_VCE; 401 for (i = 0; i < adev->vce.num_rings; i++) 402 if (adev->vce.ring[i].sched.ready) 403 ++num_rings; 404 ib_start_alignment = 4; 405 ib_size_alignment = 1; 406 break; 407 case AMDGPU_HW_IP_UVD_ENC: 408 type = AMD_IP_BLOCK_TYPE_UVD; 409 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 410 if (adev->uvd.harvest_config & (1 << i)) 411 continue; 412 413 for (j = 0; j < adev->uvd.num_enc_rings; j++) 414 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 415 ++num_rings; 416 } 417 ib_start_alignment = 64; 418 ib_size_alignment = 64; 419 break; 420 case AMDGPU_HW_IP_VCN_DEC: 421 type = AMD_IP_BLOCK_TYPE_VCN; 422 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 423 if (adev->uvd.harvest_config & (1 << i)) 424 continue; 425 426 if (adev->vcn.inst[i].ring_dec.sched.ready) 427 ++num_rings; 428 } 429 ib_start_alignment = 16; 430 ib_size_alignment = 16; 431 break; 432 case AMDGPU_HW_IP_VCN_ENC: 433 type = AMD_IP_BLOCK_TYPE_VCN; 434 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 435 if (adev->uvd.harvest_config & (1 << i)) 436 continue; 437 438 for (j = 0; j < adev->vcn.num_enc_rings; j++) 439 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 440 ++num_rings; 441 } 442 ib_start_alignment = 64; 443 ib_size_alignment = 1; 444 break; 445 case AMDGPU_HW_IP_VCN_JPEG: 446 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 447 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 448 449 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 450 if (adev->jpeg.harvest_config & (1 << i)) 451 continue; 452 453 if (adev->jpeg.inst[i].ring_dec.sched.ready) 454 ++num_rings; 455 } 456 ib_start_alignment = 16; 457 ib_size_alignment = 16; 458 break; 459 default: 460 return -EINVAL; 461 } 462 463 for (i = 0; i < adev->num_ip_blocks; i++) 464 if (adev->ip_blocks[i].version->type == type && 465 adev->ip_blocks[i].status.valid) 466 break; 467 468 if (i == adev->num_ip_blocks) 469 return 0; 470 471 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 472 num_rings); 473 474 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 475 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 476 result->capabilities_flags = 0; 477 result->available_rings = (1 << num_rings) - 1; 478 result->ib_start_alignment = ib_start_alignment; 479 result->ib_size_alignment = ib_size_alignment; 480 return 0; 481 } 482 483 /* 484 * Userspace get information ioctl 485 */ 486 /** 487 * amdgpu_info_ioctl - answer a device specific request. 488 * 489 * @dev: drm device pointer 490 * @data: request object 491 * @filp: drm filp 492 * 493 * This function is used to pass device specific parameters to the userspace 494 * drivers. Examples include: pci device id, pipeline parms, tiling params, 495 * etc. (all asics). 496 * Returns 0 on success, -EINVAL on failure. 497 */ 498 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 499 { 500 struct amdgpu_device *adev = drm_to_adev(dev); 501 struct drm_amdgpu_info *info = data; 502 struct amdgpu_mode_info *minfo = &adev->mode_info; 503 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 504 uint32_t size = info->return_size; 505 struct drm_crtc *crtc; 506 uint32_t ui32 = 0; 507 uint64_t ui64 = 0; 508 int i, found; 509 int ui32_size = sizeof(ui32); 510 511 if (!info->return_size || !info->return_pointer) 512 return -EINVAL; 513 514 switch (info->query) { 515 case AMDGPU_INFO_ACCEL_WORKING: 516 ui32 = adev->accel_working; 517 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 518 case AMDGPU_INFO_CRTC_FROM_ID: 519 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 520 crtc = (struct drm_crtc *)minfo->crtcs[i]; 521 if (crtc && crtc->base.id == info->mode_crtc.id) { 522 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 523 ui32 = amdgpu_crtc->crtc_id; 524 found = 1; 525 break; 526 } 527 } 528 if (!found) { 529 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 530 return -EINVAL; 531 } 532 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 533 case AMDGPU_INFO_HW_IP_INFO: { 534 struct drm_amdgpu_info_hw_ip ip = {}; 535 int ret; 536 537 ret = amdgpu_hw_ip_info(adev, info, &ip); 538 if (ret) 539 return ret; 540 541 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 542 return ret ? -EFAULT : 0; 543 } 544 case AMDGPU_INFO_HW_IP_COUNT: { 545 enum amd_ip_block_type type; 546 uint32_t count = 0; 547 548 switch (info->query_hw_ip.type) { 549 case AMDGPU_HW_IP_GFX: 550 type = AMD_IP_BLOCK_TYPE_GFX; 551 break; 552 case AMDGPU_HW_IP_COMPUTE: 553 type = AMD_IP_BLOCK_TYPE_GFX; 554 break; 555 case AMDGPU_HW_IP_DMA: 556 type = AMD_IP_BLOCK_TYPE_SDMA; 557 break; 558 case AMDGPU_HW_IP_UVD: 559 type = AMD_IP_BLOCK_TYPE_UVD; 560 break; 561 case AMDGPU_HW_IP_VCE: 562 type = AMD_IP_BLOCK_TYPE_VCE; 563 break; 564 case AMDGPU_HW_IP_UVD_ENC: 565 type = AMD_IP_BLOCK_TYPE_UVD; 566 break; 567 case AMDGPU_HW_IP_VCN_DEC: 568 case AMDGPU_HW_IP_VCN_ENC: 569 type = AMD_IP_BLOCK_TYPE_VCN; 570 break; 571 case AMDGPU_HW_IP_VCN_JPEG: 572 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 573 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 574 break; 575 default: 576 return -EINVAL; 577 } 578 579 for (i = 0; i < adev->num_ip_blocks; i++) 580 if (adev->ip_blocks[i].version->type == type && 581 adev->ip_blocks[i].status.valid && 582 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 583 count++; 584 585 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 586 } 587 case AMDGPU_INFO_TIMESTAMP: 588 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 589 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 590 case AMDGPU_INFO_FW_VERSION: { 591 struct drm_amdgpu_info_firmware fw_info; 592 int ret; 593 594 /* We only support one instance of each IP block right now. */ 595 if (info->query_fw.ip_instance != 0) 596 return -EINVAL; 597 598 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 599 if (ret) 600 return ret; 601 602 return copy_to_user(out, &fw_info, 603 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 604 } 605 case AMDGPU_INFO_NUM_BYTES_MOVED: 606 ui64 = atomic64_read(&adev->num_bytes_moved); 607 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 608 case AMDGPU_INFO_NUM_EVICTIONS: 609 ui64 = atomic64_read(&adev->num_evictions); 610 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 611 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 612 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 613 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 614 case AMDGPU_INFO_VRAM_USAGE: 615 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); 616 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 617 case AMDGPU_INFO_VIS_VRAM_USAGE: 618 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 619 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 620 case AMDGPU_INFO_GTT_USAGE: 621 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 622 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 623 case AMDGPU_INFO_GDS_CONFIG: { 624 struct drm_amdgpu_info_gds gds_info; 625 626 memset(&gds_info, 0, sizeof(gds_info)); 627 gds_info.compute_partition_size = adev->gds.gds_size; 628 gds_info.gds_total_size = adev->gds.gds_size; 629 gds_info.gws_per_compute_partition = adev->gds.gws_size; 630 gds_info.oa_per_compute_partition = adev->gds.oa_size; 631 return copy_to_user(out, &gds_info, 632 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 633 } 634 case AMDGPU_INFO_VRAM_GTT: { 635 struct drm_amdgpu_info_vram_gtt vram_gtt; 636 637 vram_gtt.vram_size = adev->gmc.real_vram_size - 638 atomic64_read(&adev->vram_pin_size) - 639 AMDGPU_VM_RESERVED_VRAM; 640 vram_gtt.vram_cpu_accessible_size = 641 min(adev->gmc.visible_vram_size - 642 atomic64_read(&adev->visible_pin_size), 643 vram_gtt.vram_size); 644 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 645 vram_gtt.gtt_size *= PAGE_SIZE; 646 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 647 return copy_to_user(out, &vram_gtt, 648 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 649 } 650 case AMDGPU_INFO_MEMORY: { 651 struct drm_amdgpu_memory_info mem; 652 struct ttm_resource_manager *gtt_man = 653 &adev->mman.gtt_mgr.manager; 654 struct ttm_resource_manager *vram_man = 655 &adev->mman.vram_mgr.manager; 656 657 memset(&mem, 0, sizeof(mem)); 658 mem.vram.total_heap_size = adev->gmc.real_vram_size; 659 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 660 atomic64_read(&adev->vram_pin_size) - 661 AMDGPU_VM_RESERVED_VRAM; 662 mem.vram.heap_usage = 663 ttm_resource_manager_usage(vram_man); 664 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 665 666 mem.cpu_accessible_vram.total_heap_size = 667 adev->gmc.visible_vram_size; 668 mem.cpu_accessible_vram.usable_heap_size = 669 min(adev->gmc.visible_vram_size - 670 atomic64_read(&adev->visible_pin_size), 671 mem.vram.usable_heap_size); 672 mem.cpu_accessible_vram.heap_usage = 673 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 674 mem.cpu_accessible_vram.max_allocation = 675 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 676 677 mem.gtt.total_heap_size = gtt_man->size; 678 mem.gtt.total_heap_size *= PAGE_SIZE; 679 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 680 atomic64_read(&adev->gart_pin_size); 681 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 682 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 683 684 return copy_to_user(out, &mem, 685 min((size_t)size, sizeof(mem))) 686 ? -EFAULT : 0; 687 } 688 case AMDGPU_INFO_READ_MMR_REG: { 689 unsigned n, alloc_size; 690 uint32_t *regs; 691 unsigned se_num = (info->read_mmr_reg.instance >> 692 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 693 AMDGPU_INFO_MMR_SE_INDEX_MASK; 694 unsigned sh_num = (info->read_mmr_reg.instance >> 695 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 696 AMDGPU_INFO_MMR_SH_INDEX_MASK; 697 698 /* set full masks if the userspace set all bits 699 * in the bitfields */ 700 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 701 se_num = 0xffffffff; 702 else if (se_num >= AMDGPU_GFX_MAX_SE) 703 return -EINVAL; 704 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 705 sh_num = 0xffffffff; 706 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 707 return -EINVAL; 708 709 if (info->read_mmr_reg.count > 128) 710 return -EINVAL; 711 712 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 713 if (!regs) 714 return -ENOMEM; 715 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 716 717 amdgpu_gfx_off_ctrl(adev, false); 718 for (i = 0; i < info->read_mmr_reg.count; i++) { 719 if (amdgpu_asic_read_register(adev, se_num, sh_num, 720 info->read_mmr_reg.dword_offset + i, 721 ®s[i])) { 722 DRM_DEBUG_KMS("unallowed offset %#x\n", 723 info->read_mmr_reg.dword_offset + i); 724 kfree(regs); 725 amdgpu_gfx_off_ctrl(adev, true); 726 return -EFAULT; 727 } 728 } 729 amdgpu_gfx_off_ctrl(adev, true); 730 n = copy_to_user(out, regs, min(size, alloc_size)); 731 kfree(regs); 732 return n ? -EFAULT : 0; 733 } 734 case AMDGPU_INFO_DEV_INFO: { 735 struct drm_amdgpu_info_device *dev_info; 736 uint64_t vm_size; 737 int ret; 738 739 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 740 if (!dev_info) 741 return -ENOMEM; 742 743 dev_info->device_id = adev->pdev->device; 744 dev_info->chip_rev = adev->rev_id; 745 dev_info->external_rev = adev->external_rev_id; 746 dev_info->pci_rev = adev->pdev->revision; 747 dev_info->family = adev->family; 748 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 749 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 750 /* return all clocks in KHz */ 751 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 752 if (adev->pm.dpm_enabled) { 753 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 754 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 755 } else { 756 dev_info->max_engine_clock = adev->clock.default_sclk * 10; 757 dev_info->max_memory_clock = adev->clock.default_mclk * 10; 758 } 759 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 760 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 761 adev->gfx.config.max_shader_engines; 762 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 763 dev_info->_pad = 0; 764 dev_info->ids_flags = 0; 765 if (adev->flags & AMD_IS_APU) 766 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 767 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 768 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 769 if (amdgpu_is_tmz(adev)) 770 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 771 772 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 773 vm_size -= AMDGPU_VA_RESERVED_SIZE; 774 775 /* Older VCE FW versions are buggy and can handle only 40bits */ 776 if (adev->vce.fw_version && 777 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 778 vm_size = min(vm_size, 1ULL << 40); 779 780 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 781 dev_info->virtual_address_max = 782 min(vm_size, AMDGPU_GMC_HOLE_START); 783 784 if (vm_size > AMDGPU_GMC_HOLE_START) { 785 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 786 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 787 } 788 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 789 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 790 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 791 dev_info->cu_active_number = adev->gfx.cu_info.number; 792 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 793 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 794 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 795 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 796 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 797 sizeof(adev->gfx.cu_info.bitmap)); 798 dev_info->vram_type = adev->gmc.vram_type; 799 dev_info->vram_bit_width = adev->gmc.vram_width; 800 dev_info->vce_harvest_config = adev->vce.harvest_config; 801 dev_info->gc_double_offchip_lds_buf = 802 adev->gfx.config.double_offchip_lds_buf; 803 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 804 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 805 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 806 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 807 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 808 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 809 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 810 811 if (adev->family >= AMDGPU_FAMILY_NV) 812 dev_info->pa_sc_tile_steering_override = 813 adev->gfx.config.pa_sc_tile_steering_override; 814 815 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 816 817 ret = copy_to_user(out, dev_info, 818 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 819 kfree(dev_info); 820 return ret; 821 } 822 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 823 unsigned i; 824 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 825 struct amd_vce_state *vce_state; 826 827 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 828 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 829 if (vce_state) { 830 vce_clk_table.entries[i].sclk = vce_state->sclk; 831 vce_clk_table.entries[i].mclk = vce_state->mclk; 832 vce_clk_table.entries[i].eclk = vce_state->evclk; 833 vce_clk_table.num_valid_entries++; 834 } 835 } 836 837 return copy_to_user(out, &vce_clk_table, 838 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 839 } 840 case AMDGPU_INFO_VBIOS: { 841 uint32_t bios_size = adev->bios_size; 842 843 switch (info->vbios_info.type) { 844 case AMDGPU_INFO_VBIOS_SIZE: 845 return copy_to_user(out, &bios_size, 846 min((size_t)size, sizeof(bios_size))) 847 ? -EFAULT : 0; 848 case AMDGPU_INFO_VBIOS_IMAGE: { 849 uint8_t *bios; 850 uint32_t bios_offset = info->vbios_info.offset; 851 852 if (bios_offset >= bios_size) 853 return -EINVAL; 854 855 bios = adev->bios + bios_offset; 856 return copy_to_user(out, bios, 857 min((size_t)size, (size_t)(bios_size - bios_offset))) 858 ? -EFAULT : 0; 859 } 860 case AMDGPU_INFO_VBIOS_INFO: { 861 struct drm_amdgpu_info_vbios vbios_info = {}; 862 struct atom_context *atom_context; 863 864 atom_context = adev->mode_info.atom_context; 865 memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name)); 866 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn)); 867 vbios_info.version = atom_context->version; 868 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 869 sizeof(atom_context->vbios_ver_str)); 870 memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date)); 871 872 return copy_to_user(out, &vbios_info, 873 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 874 } 875 default: 876 DRM_DEBUG_KMS("Invalid request %d\n", 877 info->vbios_info.type); 878 return -EINVAL; 879 } 880 } 881 case AMDGPU_INFO_NUM_HANDLES: { 882 struct drm_amdgpu_info_num_handles handle; 883 884 switch (info->query_hw_ip.type) { 885 case AMDGPU_HW_IP_UVD: 886 /* Starting Polaris, we support unlimited UVD handles */ 887 if (adev->asic_type < CHIP_POLARIS10) { 888 handle.uvd_max_handles = adev->uvd.max_handles; 889 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 890 891 return copy_to_user(out, &handle, 892 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 893 } else { 894 return -ENODATA; 895 } 896 897 break; 898 default: 899 return -EINVAL; 900 } 901 } 902 case AMDGPU_INFO_SENSOR: { 903 if (!adev->pm.dpm_enabled) 904 return -ENOENT; 905 906 switch (info->sensor_info.type) { 907 case AMDGPU_INFO_SENSOR_GFX_SCLK: 908 /* get sclk in Mhz */ 909 if (amdgpu_dpm_read_sensor(adev, 910 AMDGPU_PP_SENSOR_GFX_SCLK, 911 (void *)&ui32, &ui32_size)) { 912 return -EINVAL; 913 } 914 ui32 /= 100; 915 break; 916 case AMDGPU_INFO_SENSOR_GFX_MCLK: 917 /* get mclk in Mhz */ 918 if (amdgpu_dpm_read_sensor(adev, 919 AMDGPU_PP_SENSOR_GFX_MCLK, 920 (void *)&ui32, &ui32_size)) { 921 return -EINVAL; 922 } 923 ui32 /= 100; 924 break; 925 case AMDGPU_INFO_SENSOR_GPU_TEMP: 926 /* get temperature in millidegrees C */ 927 if (amdgpu_dpm_read_sensor(adev, 928 AMDGPU_PP_SENSOR_GPU_TEMP, 929 (void *)&ui32, &ui32_size)) { 930 return -EINVAL; 931 } 932 break; 933 case AMDGPU_INFO_SENSOR_GPU_LOAD: 934 /* get GPU load */ 935 if (amdgpu_dpm_read_sensor(adev, 936 AMDGPU_PP_SENSOR_GPU_LOAD, 937 (void *)&ui32, &ui32_size)) { 938 return -EINVAL; 939 } 940 break; 941 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 942 /* get average GPU power */ 943 if (amdgpu_dpm_read_sensor(adev, 944 AMDGPU_PP_SENSOR_GPU_POWER, 945 (void *)&ui32, &ui32_size)) { 946 return -EINVAL; 947 } 948 ui32 >>= 8; 949 break; 950 case AMDGPU_INFO_SENSOR_VDDNB: 951 /* get VDDNB in millivolts */ 952 if (amdgpu_dpm_read_sensor(adev, 953 AMDGPU_PP_SENSOR_VDDNB, 954 (void *)&ui32, &ui32_size)) { 955 return -EINVAL; 956 } 957 break; 958 case AMDGPU_INFO_SENSOR_VDDGFX: 959 /* get VDDGFX in millivolts */ 960 if (amdgpu_dpm_read_sensor(adev, 961 AMDGPU_PP_SENSOR_VDDGFX, 962 (void *)&ui32, &ui32_size)) { 963 return -EINVAL; 964 } 965 break; 966 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 967 /* get stable pstate sclk in Mhz */ 968 if (amdgpu_dpm_read_sensor(adev, 969 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 970 (void *)&ui32, &ui32_size)) { 971 return -EINVAL; 972 } 973 ui32 /= 100; 974 break; 975 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 976 /* get stable pstate mclk in Mhz */ 977 if (amdgpu_dpm_read_sensor(adev, 978 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 979 (void *)&ui32, &ui32_size)) { 980 return -EINVAL; 981 } 982 ui32 /= 100; 983 break; 984 default: 985 DRM_DEBUG_KMS("Invalid request %d\n", 986 info->sensor_info.type); 987 return -EINVAL; 988 } 989 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 990 } 991 case AMDGPU_INFO_VRAM_LOST_COUNTER: 992 ui32 = atomic_read(&adev->vram_lost_counter); 993 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 994 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 995 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 996 uint64_t ras_mask; 997 998 if (!ras) 999 return -EINVAL; 1000 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1001 1002 return copy_to_user(out, &ras_mask, 1003 min_t(u64, size, sizeof(ras_mask))) ? 1004 -EFAULT : 0; 1005 } 1006 case AMDGPU_INFO_VIDEO_CAPS: { 1007 const struct amdgpu_video_codecs *codecs; 1008 struct drm_amdgpu_info_video_caps *caps; 1009 int r; 1010 1011 switch (info->video_cap.type) { 1012 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1013 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1014 if (r) 1015 return -EINVAL; 1016 break; 1017 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1018 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1019 if (r) 1020 return -EINVAL; 1021 break; 1022 default: 1023 DRM_DEBUG_KMS("Invalid request %d\n", 1024 info->video_cap.type); 1025 return -EINVAL; 1026 } 1027 1028 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1029 if (!caps) 1030 return -ENOMEM; 1031 1032 for (i = 0; i < codecs->codec_count; i++) { 1033 int idx = codecs->codec_array[i].codec_type; 1034 1035 switch (idx) { 1036 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1037 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1038 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1039 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1040 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1041 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1042 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1043 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1044 caps->codec_info[idx].valid = 1; 1045 caps->codec_info[idx].max_width = 1046 codecs->codec_array[i].max_width; 1047 caps->codec_info[idx].max_height = 1048 codecs->codec_array[i].max_height; 1049 caps->codec_info[idx].max_pixels_per_frame = 1050 codecs->codec_array[i].max_pixels_per_frame; 1051 caps->codec_info[idx].max_level = 1052 codecs->codec_array[i].max_level; 1053 break; 1054 default: 1055 break; 1056 } 1057 } 1058 r = copy_to_user(out, caps, 1059 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1060 kfree(caps); 1061 return r; 1062 } 1063 default: 1064 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1065 return -EINVAL; 1066 } 1067 return 0; 1068 } 1069 1070 1071 /* 1072 * Outdated mess for old drm with Xorg being in charge (void function now). 1073 */ 1074 /** 1075 * amdgpu_driver_lastclose_kms - drm callback for last close 1076 * 1077 * @dev: drm dev pointer 1078 * 1079 * Switch vga_switcheroo state after last close (all asics). 1080 */ 1081 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1082 { 1083 drm_fb_helper_lastclose(dev); 1084 vga_switcheroo_process_delayed_switch(); 1085 } 1086 1087 /** 1088 * amdgpu_driver_open_kms - drm callback for open 1089 * 1090 * @dev: drm dev pointer 1091 * @file_priv: drm file 1092 * 1093 * On device open, init vm on cayman+ (all asics). 1094 * Returns 0 on success, error on failure. 1095 */ 1096 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1097 { 1098 struct amdgpu_device *adev = drm_to_adev(dev); 1099 struct amdgpu_fpriv *fpriv; 1100 int r, pasid; 1101 1102 /* Ensure IB tests are run on ring */ 1103 flush_delayed_work(&adev->delayed_init_work); 1104 1105 1106 if (amdgpu_ras_intr_triggered()) { 1107 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1108 return -EHWPOISON; 1109 } 1110 1111 file_priv->driver_priv = NULL; 1112 1113 r = pm_runtime_get_sync(dev->dev); 1114 if (r < 0) 1115 goto pm_put; 1116 1117 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1118 if (unlikely(!fpriv)) { 1119 r = -ENOMEM; 1120 goto out_suspend; 1121 } 1122 1123 pasid = amdgpu_pasid_alloc(16); 1124 if (pasid < 0) { 1125 dev_warn(adev->dev, "No more PASIDs available!"); 1126 pasid = 0; 1127 } 1128 1129 r = amdgpu_vm_init(adev, &fpriv->vm); 1130 if (r) 1131 goto error_pasid; 1132 1133 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1134 if (r) 1135 goto error_vm; 1136 1137 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1138 if (!fpriv->prt_va) { 1139 r = -ENOMEM; 1140 goto error_vm; 1141 } 1142 1143 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1144 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1145 1146 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1147 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1148 if (r) 1149 goto error_vm; 1150 } 1151 1152 mutex_init(&fpriv->bo_list_lock); 1153 idr_init(&fpriv->bo_list_handles); 1154 1155 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1156 1157 file_priv->driver_priv = fpriv; 1158 goto out_suspend; 1159 1160 error_vm: 1161 amdgpu_vm_fini(adev, &fpriv->vm); 1162 1163 error_pasid: 1164 if (pasid) { 1165 amdgpu_pasid_free(pasid); 1166 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); 1167 } 1168 1169 kfree(fpriv); 1170 1171 out_suspend: 1172 pm_runtime_mark_last_busy(dev->dev); 1173 pm_put: 1174 pm_runtime_put_autosuspend(dev->dev); 1175 1176 return r; 1177 } 1178 1179 /** 1180 * amdgpu_driver_postclose_kms - drm callback for post close 1181 * 1182 * @dev: drm dev pointer 1183 * @file_priv: drm file 1184 * 1185 * On device post close, tear down vm on cayman+ (all asics). 1186 */ 1187 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1188 struct drm_file *file_priv) 1189 { 1190 struct amdgpu_device *adev = drm_to_adev(dev); 1191 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1192 struct amdgpu_bo_list *list; 1193 struct amdgpu_bo *pd; 1194 u32 pasid; 1195 int handle; 1196 1197 if (!fpriv) 1198 return; 1199 1200 pm_runtime_get_sync(dev->dev); 1201 1202 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1203 amdgpu_uvd_free_handles(adev, file_priv); 1204 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1205 amdgpu_vce_free_handles(adev, file_priv); 1206 1207 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1208 /* TODO: how to handle reserve failure */ 1209 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1210 amdgpu_vm_bo_del(adev, fpriv->csa_va); 1211 fpriv->csa_va = NULL; 1212 amdgpu_bo_unreserve(adev->virt.csa_obj); 1213 } 1214 1215 pasid = fpriv->vm.pasid; 1216 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1217 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1218 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1219 amdgpu_bo_unreserve(pd); 1220 } 1221 1222 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1223 amdgpu_vm_fini(adev, &fpriv->vm); 1224 1225 if (pasid) 1226 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1227 amdgpu_bo_unref(&pd); 1228 1229 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1230 amdgpu_bo_list_put(list); 1231 1232 idr_destroy(&fpriv->bo_list_handles); 1233 mutex_destroy(&fpriv->bo_list_lock); 1234 1235 kfree(fpriv); 1236 file_priv->driver_priv = NULL; 1237 1238 pm_runtime_mark_last_busy(dev->dev); 1239 pm_runtime_put_autosuspend(dev->dev); 1240 } 1241 1242 1243 void amdgpu_driver_release_kms(struct drm_device *dev) 1244 { 1245 struct amdgpu_device *adev = drm_to_adev(dev); 1246 1247 amdgpu_device_fini_sw(adev); 1248 pci_set_drvdata(adev->pdev, NULL); 1249 } 1250 1251 /* 1252 * VBlank related functions. 1253 */ 1254 /** 1255 * amdgpu_get_vblank_counter_kms - get frame count 1256 * 1257 * @crtc: crtc to get the frame count from 1258 * 1259 * Gets the frame count on the requested crtc (all asics). 1260 * Returns frame count on success, -EINVAL on failure. 1261 */ 1262 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1263 { 1264 struct drm_device *dev = crtc->dev; 1265 unsigned int pipe = crtc->index; 1266 struct amdgpu_device *adev = drm_to_adev(dev); 1267 int vpos, hpos, stat; 1268 u32 count; 1269 1270 if (pipe >= adev->mode_info.num_crtc) { 1271 DRM_ERROR("Invalid crtc %u\n", pipe); 1272 return -EINVAL; 1273 } 1274 1275 /* The hw increments its frame counter at start of vsync, not at start 1276 * of vblank, as is required by DRM core vblank counter handling. 1277 * Cook the hw count here to make it appear to the caller as if it 1278 * incremented at start of vblank. We measure distance to start of 1279 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1280 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1281 * result by 1 to give the proper appearance to caller. 1282 */ 1283 if (adev->mode_info.crtcs[pipe]) { 1284 /* Repeat readout if needed to provide stable result if 1285 * we cross start of vsync during the queries. 1286 */ 1287 do { 1288 count = amdgpu_display_vblank_get_counter(adev, pipe); 1289 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1290 * vpos as distance to start of vblank, instead of 1291 * regular vertical scanout pos. 1292 */ 1293 stat = amdgpu_display_get_crtc_scanoutpos( 1294 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1295 &vpos, &hpos, NULL, NULL, 1296 &adev->mode_info.crtcs[pipe]->base.hwmode); 1297 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1298 1299 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1300 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1301 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1302 } else { 1303 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1304 pipe, vpos); 1305 1306 /* Bump counter if we are at >= leading edge of vblank, 1307 * but before vsync where vpos would turn negative and 1308 * the hw counter really increments. 1309 */ 1310 if (vpos >= 0) 1311 count++; 1312 } 1313 } else { 1314 /* Fallback to use value as is. */ 1315 count = amdgpu_display_vblank_get_counter(adev, pipe); 1316 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1317 } 1318 1319 return count; 1320 } 1321 1322 /** 1323 * amdgpu_enable_vblank_kms - enable vblank interrupt 1324 * 1325 * @crtc: crtc to enable vblank interrupt for 1326 * 1327 * Enable the interrupt on the requested crtc (all asics). 1328 * Returns 0 on success, -EINVAL on failure. 1329 */ 1330 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1331 { 1332 struct drm_device *dev = crtc->dev; 1333 unsigned int pipe = crtc->index; 1334 struct amdgpu_device *adev = drm_to_adev(dev); 1335 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1336 1337 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1338 } 1339 1340 /** 1341 * amdgpu_disable_vblank_kms - disable vblank interrupt 1342 * 1343 * @crtc: crtc to disable vblank interrupt for 1344 * 1345 * Disable the interrupt on the requested crtc (all asics). 1346 */ 1347 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1348 { 1349 struct drm_device *dev = crtc->dev; 1350 unsigned int pipe = crtc->index; 1351 struct amdgpu_device *adev = drm_to_adev(dev); 1352 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1353 1354 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1355 } 1356 1357 /* 1358 * Debugfs info 1359 */ 1360 #if defined(CONFIG_DEBUG_FS) 1361 1362 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1363 { 1364 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 1365 struct drm_amdgpu_info_firmware fw_info; 1366 struct drm_amdgpu_query_fw query_fw; 1367 struct atom_context *ctx = adev->mode_info.atom_context; 1368 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1369 int ret, i; 1370 1371 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1372 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type 1373 TA_FW_NAME(XGMI), 1374 TA_FW_NAME(RAS), 1375 TA_FW_NAME(HDCP), 1376 TA_FW_NAME(DTM), 1377 TA_FW_NAME(RAP), 1378 TA_FW_NAME(SECUREDISPLAY), 1379 #undef TA_FW_NAME 1380 }; 1381 1382 /* VCE */ 1383 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1384 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1385 if (ret) 1386 return ret; 1387 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1388 fw_info.feature, fw_info.ver); 1389 1390 /* UVD */ 1391 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1392 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1393 if (ret) 1394 return ret; 1395 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1396 fw_info.feature, fw_info.ver); 1397 1398 /* GMC */ 1399 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1400 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1401 if (ret) 1402 return ret; 1403 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1404 fw_info.feature, fw_info.ver); 1405 1406 /* ME */ 1407 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1408 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1409 if (ret) 1410 return ret; 1411 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1412 fw_info.feature, fw_info.ver); 1413 1414 /* PFP */ 1415 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1416 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1417 if (ret) 1418 return ret; 1419 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1420 fw_info.feature, fw_info.ver); 1421 1422 /* CE */ 1423 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1424 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1425 if (ret) 1426 return ret; 1427 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1428 fw_info.feature, fw_info.ver); 1429 1430 /* RLC */ 1431 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1432 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1433 if (ret) 1434 return ret; 1435 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1436 fw_info.feature, fw_info.ver); 1437 1438 /* RLC SAVE RESTORE LIST CNTL */ 1439 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1440 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1441 if (ret) 1442 return ret; 1443 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1444 fw_info.feature, fw_info.ver); 1445 1446 /* RLC SAVE RESTORE LIST GPM MEM */ 1447 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1448 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1449 if (ret) 1450 return ret; 1451 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1452 fw_info.feature, fw_info.ver); 1453 1454 /* RLC SAVE RESTORE LIST SRM MEM */ 1455 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1456 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1457 if (ret) 1458 return ret; 1459 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1460 fw_info.feature, fw_info.ver); 1461 1462 /* MEC */ 1463 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1464 query_fw.index = 0; 1465 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1466 if (ret) 1467 return ret; 1468 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1469 fw_info.feature, fw_info.ver); 1470 1471 /* MEC2 */ 1472 if (adev->gfx.mec2_fw) { 1473 query_fw.index = 1; 1474 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1475 if (ret) 1476 return ret; 1477 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1478 fw_info.feature, fw_info.ver); 1479 } 1480 1481 /* PSP SOS */ 1482 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1483 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1484 if (ret) 1485 return ret; 1486 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1487 fw_info.feature, fw_info.ver); 1488 1489 1490 /* PSP ASD */ 1491 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1492 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1493 if (ret) 1494 return ret; 1495 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1496 fw_info.feature, fw_info.ver); 1497 1498 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1499 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1500 query_fw.index = i; 1501 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1502 if (ret) 1503 continue; 1504 1505 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1506 ta_fw_name[i], fw_info.feature, fw_info.ver); 1507 } 1508 1509 /* SMC */ 1510 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1511 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1512 if (ret) 1513 return ret; 1514 smu_program = (fw_info.ver >> 24) & 0xff; 1515 smu_major = (fw_info.ver >> 16) & 0xff; 1516 smu_minor = (fw_info.ver >> 8) & 0xff; 1517 smu_debug = (fw_info.ver >> 0) & 0xff; 1518 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1519 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1520 1521 /* SDMA */ 1522 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1523 for (i = 0; i < adev->sdma.num_instances; i++) { 1524 query_fw.index = i; 1525 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1526 if (ret) 1527 return ret; 1528 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1529 i, fw_info.feature, fw_info.ver); 1530 } 1531 1532 /* VCN */ 1533 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1534 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1535 if (ret) 1536 return ret; 1537 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1538 fw_info.feature, fw_info.ver); 1539 1540 /* DMCU */ 1541 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1542 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1543 if (ret) 1544 return ret; 1545 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1546 fw_info.feature, fw_info.ver); 1547 1548 /* DMCUB */ 1549 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1550 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1551 if (ret) 1552 return ret; 1553 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1554 fw_info.feature, fw_info.ver); 1555 1556 /* TOC */ 1557 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1558 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1559 if (ret) 1560 return ret; 1561 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1562 fw_info.feature, fw_info.ver); 1563 1564 /* CAP */ 1565 if (adev->psp.cap_fw) { 1566 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1567 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1568 if (ret) 1569 return ret; 1570 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1571 fw_info.feature, fw_info.ver); 1572 } 1573 1574 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1575 1576 return 0; 1577 } 1578 1579 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1580 1581 #endif 1582 1583 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1584 { 1585 #if defined(CONFIG_DEBUG_FS) 1586 struct drm_minor *minor = adev_to_drm(adev)->primary; 1587 struct dentry *root = minor->debugfs_root; 1588 1589 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1590 adev, &amdgpu_debugfs_firmware_info_fops); 1591 1592 #endif 1593 } 1594