xref: /openbmc/linux/drivers/mtd/spi-nor/core.c (revision 724ba675)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4  * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
5  *
6  * Copyright (C) 2005, Intec Automation Inc.
7  * Copyright (C) 2014, Freescale Semiconductor, Inc.
8  */
9 
10 #include <linux/err.h>
11 #include <linux/errno.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/math64.h>
15 #include <linux/module.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/spi-nor.h>
18 #include <linux/mutex.h>
19 #include <linux/of_platform.h>
20 #include <linux/sched/task_stack.h>
21 #include <linux/sizes.h>
22 #include <linux/slab.h>
23 #include <linux/spi/flash.h>
24 
25 #include "core.h"
26 
27 /* Define max times to check status register before we give up. */
28 
29 /*
30  * For everything but full-chip erase; probably could be much smaller, but kept
31  * around for safety for now
32  */
33 #define DEFAULT_READY_WAIT_JIFFIES		(40UL * HZ)
34 
35 /*
36  * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
37  * for larger flash
38  */
39 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES	(40UL * HZ)
40 
41 #define SPI_NOR_MAX_ADDR_NBYTES	4
42 
43 #define SPI_NOR_SRST_SLEEP_MIN 200
44 #define SPI_NOR_SRST_SLEEP_MAX 400
45 
46 /**
47  * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
48  *			   extension type.
49  * @nor:		pointer to a 'struct spi_nor'
50  * @op:			pointer to the 'struct spi_mem_op' whose properties
51  *			need to be initialized.
52  *
53  * Right now, only "repeat" and "invert" are supported.
54  *
55  * Return: The opcode extension.
56  */
57 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,
58 			      const struct spi_mem_op *op)
59 {
60 	switch (nor->cmd_ext_type) {
61 	case SPI_NOR_EXT_INVERT:
62 		return ~op->cmd.opcode;
63 
64 	case SPI_NOR_EXT_REPEAT:
65 		return op->cmd.opcode;
66 
67 	default:
68 		dev_err(nor->dev, "Unknown command extension type\n");
69 		return 0;
70 	}
71 }
72 
73 /**
74  * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op.
75  * @nor:		pointer to a 'struct spi_nor'
76  * @op:			pointer to the 'struct spi_mem_op' whose properties
77  *			need to be initialized.
78  * @proto:		the protocol from which the properties need to be set.
79  */
80 void spi_nor_spimem_setup_op(const struct spi_nor *nor,
81 			     struct spi_mem_op *op,
82 			     const enum spi_nor_protocol proto)
83 {
84 	u8 ext;
85 
86 	op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto);
87 
88 	if (op->addr.nbytes)
89 		op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto);
90 
91 	if (op->dummy.nbytes)
92 		op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto);
93 
94 	if (op->data.nbytes)
95 		op->data.buswidth = spi_nor_get_protocol_data_nbits(proto);
96 
97 	if (spi_nor_protocol_is_dtr(proto)) {
98 		/*
99 		 * SPIMEM supports mixed DTR modes, but right now we can only
100 		 * have all phases either DTR or STR. IOW, SPIMEM can have
101 		 * something like 4S-4D-4D, but SPI NOR can't. So, set all 4
102 		 * phases to either DTR or STR.
103 		 */
104 		op->cmd.dtr = true;
105 		op->addr.dtr = true;
106 		op->dummy.dtr = true;
107 		op->data.dtr = true;
108 
109 		/* 2 bytes per clock cycle in DTR mode. */
110 		op->dummy.nbytes *= 2;
111 
112 		ext = spi_nor_get_cmd_ext(nor, op);
113 		op->cmd.opcode = (op->cmd.opcode << 8) | ext;
114 		op->cmd.nbytes = 2;
115 	}
116 }
117 
118 /**
119  * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data
120  *                           transfer
121  * @nor:        pointer to 'struct spi_nor'
122  * @op:         pointer to 'struct spi_mem_op' template for transfer
123  *
124  * If we have to use the bounce buffer, the data field in @op will be updated.
125  *
126  * Return: true if the bounce buffer is needed, false if not
127  */
128 static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op)
129 {
130 	/* op->data.buf.in occupies the same memory as op->data.buf.out */
131 	if (object_is_on_stack(op->data.buf.in) ||
132 	    !virt_addr_valid(op->data.buf.in)) {
133 		if (op->data.nbytes > nor->bouncebuf_size)
134 			op->data.nbytes = nor->bouncebuf_size;
135 		op->data.buf.in = nor->bouncebuf;
136 		return true;
137 	}
138 
139 	return false;
140 }
141 
142 /**
143  * spi_nor_spimem_exec_op() - execute a memory operation
144  * @nor:        pointer to 'struct spi_nor'
145  * @op:         pointer to 'struct spi_mem_op' template for transfer
146  *
147  * Return: 0 on success, -error otherwise.
148  */
149 static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op)
150 {
151 	int error;
152 
153 	error = spi_mem_adjust_op_size(nor->spimem, op);
154 	if (error)
155 		return error;
156 
157 	return spi_mem_exec_op(nor->spimem, op);
158 }
159 
160 int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,
161 				    u8 *buf, size_t len)
162 {
163 	if (spi_nor_protocol_is_dtr(nor->reg_proto))
164 		return -EOPNOTSUPP;
165 
166 	return nor->controller_ops->read_reg(nor, opcode, buf, len);
167 }
168 
169 int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
170 				     const u8 *buf, size_t len)
171 {
172 	if (spi_nor_protocol_is_dtr(nor->reg_proto))
173 		return -EOPNOTSUPP;
174 
175 	return nor->controller_ops->write_reg(nor, opcode, buf, len);
176 }
177 
178 static int spi_nor_controller_ops_erase(struct spi_nor *nor, loff_t offs)
179 {
180 	if (spi_nor_protocol_is_dtr(nor->reg_proto))
181 		return -EOPNOTSUPP;
182 
183 	return nor->controller_ops->erase(nor, offs);
184 }
185 
186 /**
187  * spi_nor_spimem_read_data() - read data from flash's memory region via
188  *                              spi-mem
189  * @nor:        pointer to 'struct spi_nor'
190  * @from:       offset to read from
191  * @len:        number of bytes to read
192  * @buf:        pointer to dst buffer
193  *
194  * Return: number of bytes read successfully, -errno otherwise
195  */
196 static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from,
197 					size_t len, u8 *buf)
198 {
199 	struct spi_mem_op op =
200 		SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
201 			   SPI_MEM_OP_ADDR(nor->addr_nbytes, from, 0),
202 			   SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
203 			   SPI_MEM_OP_DATA_IN(len, buf, 0));
204 	bool usebouncebuf;
205 	ssize_t nbytes;
206 	int error;
207 
208 	spi_nor_spimem_setup_op(nor, &op, nor->read_proto);
209 
210 	/* convert the dummy cycles to the number of bytes */
211 	op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
212 	if (spi_nor_protocol_is_dtr(nor->read_proto))
213 		op.dummy.nbytes *= 2;
214 
215 	usebouncebuf = spi_nor_spimem_bounce(nor, &op);
216 
217 	if (nor->dirmap.rdesc) {
218 		nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val,
219 					     op.data.nbytes, op.data.buf.in);
220 	} else {
221 		error = spi_nor_spimem_exec_op(nor, &op);
222 		if (error)
223 			return error;
224 		nbytes = op.data.nbytes;
225 	}
226 
227 	if (usebouncebuf && nbytes > 0)
228 		memcpy(buf, op.data.buf.in, nbytes);
229 
230 	return nbytes;
231 }
232 
233 /**
234  * spi_nor_read_data() - read data from flash memory
235  * @nor:        pointer to 'struct spi_nor'
236  * @from:       offset to read from
237  * @len:        number of bytes to read
238  * @buf:        pointer to dst buffer
239  *
240  * Return: number of bytes read successfully, -errno otherwise
241  */
242 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf)
243 {
244 	if (nor->spimem)
245 		return spi_nor_spimem_read_data(nor, from, len, buf);
246 
247 	return nor->controller_ops->read(nor, from, len, buf);
248 }
249 
250 /**
251  * spi_nor_spimem_write_data() - write data to flash memory via
252  *                               spi-mem
253  * @nor:        pointer to 'struct spi_nor'
254  * @to:         offset to write to
255  * @len:        number of bytes to write
256  * @buf:        pointer to src buffer
257  *
258  * Return: number of bytes written successfully, -errno otherwise
259  */
260 static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,
261 					 size_t len, const u8 *buf)
262 {
263 	struct spi_mem_op op =
264 		SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
265 			   SPI_MEM_OP_ADDR(nor->addr_nbytes, to, 0),
266 			   SPI_MEM_OP_NO_DUMMY,
267 			   SPI_MEM_OP_DATA_OUT(len, buf, 0));
268 	ssize_t nbytes;
269 	int error;
270 
271 	if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
272 		op.addr.nbytes = 0;
273 
274 	spi_nor_spimem_setup_op(nor, &op, nor->write_proto);
275 
276 	if (spi_nor_spimem_bounce(nor, &op))
277 		memcpy(nor->bouncebuf, buf, op.data.nbytes);
278 
279 	if (nor->dirmap.wdesc) {
280 		nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val,
281 					      op.data.nbytes, op.data.buf.out);
282 	} else {
283 		error = spi_nor_spimem_exec_op(nor, &op);
284 		if (error)
285 			return error;
286 		nbytes = op.data.nbytes;
287 	}
288 
289 	return nbytes;
290 }
291 
292 /**
293  * spi_nor_write_data() - write data to flash memory
294  * @nor:        pointer to 'struct spi_nor'
295  * @to:         offset to write to
296  * @len:        number of bytes to write
297  * @buf:        pointer to src buffer
298  *
299  * Return: number of bytes written successfully, -errno otherwise
300  */
301 ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
302 			   const u8 *buf)
303 {
304 	if (nor->spimem)
305 		return spi_nor_spimem_write_data(nor, to, len, buf);
306 
307 	return nor->controller_ops->write(nor, to, len, buf);
308 }
309 
310 /**
311  * spi_nor_read_any_reg() - read any register from flash memory, nonvolatile or
312  * volatile.
313  * @nor:        pointer to 'struct spi_nor'.
314  * @op:		SPI memory operation. op->data.buf must be DMA-able.
315  * @proto:	SPI protocol to use for the register operation.
316  *
317  * Return: zero on success, -errno otherwise
318  */
319 int spi_nor_read_any_reg(struct spi_nor *nor, struct spi_mem_op *op,
320 			 enum spi_nor_protocol proto)
321 {
322 	if (!nor->spimem)
323 		return -EOPNOTSUPP;
324 
325 	spi_nor_spimem_setup_op(nor, op, proto);
326 	return spi_nor_spimem_exec_op(nor, op);
327 }
328 
329 /**
330  * spi_nor_write_any_volatile_reg() - write any volatile register to flash
331  * memory.
332  * @nor:        pointer to 'struct spi_nor'
333  * @op:		SPI memory operation. op->data.buf must be DMA-able.
334  * @proto:	SPI protocol to use for the register operation.
335  *
336  * Writing volatile registers are instant according to some manufacturers
337  * (Cypress, Micron) and do not need any status polling.
338  *
339  * Return: zero on success, -errno otherwise
340  */
341 int spi_nor_write_any_volatile_reg(struct spi_nor *nor, struct spi_mem_op *op,
342 				   enum spi_nor_protocol proto)
343 {
344 	int ret;
345 
346 	if (!nor->spimem)
347 		return -EOPNOTSUPP;
348 
349 	ret = spi_nor_write_enable(nor);
350 	if (ret)
351 		return ret;
352 	spi_nor_spimem_setup_op(nor, op, proto);
353 	return spi_nor_spimem_exec_op(nor, op);
354 }
355 
356 /**
357  * spi_nor_write_enable() - Set write enable latch with Write Enable command.
358  * @nor:	pointer to 'struct spi_nor'.
359  *
360  * Return: 0 on success, -errno otherwise.
361  */
362 int spi_nor_write_enable(struct spi_nor *nor)
363 {
364 	int ret;
365 
366 	if (nor->spimem) {
367 		struct spi_mem_op op = SPI_NOR_WREN_OP;
368 
369 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
370 
371 		ret = spi_mem_exec_op(nor->spimem, &op);
372 	} else {
373 		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN,
374 						       NULL, 0);
375 	}
376 
377 	if (ret)
378 		dev_dbg(nor->dev, "error %d on Write Enable\n", ret);
379 
380 	return ret;
381 }
382 
383 /**
384  * spi_nor_write_disable() - Send Write Disable instruction to the chip.
385  * @nor:	pointer to 'struct spi_nor'.
386  *
387  * Return: 0 on success, -errno otherwise.
388  */
389 int spi_nor_write_disable(struct spi_nor *nor)
390 {
391 	int ret;
392 
393 	if (nor->spimem) {
394 		struct spi_mem_op op = SPI_NOR_WRDI_OP;
395 
396 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
397 
398 		ret = spi_mem_exec_op(nor->spimem, &op);
399 	} else {
400 		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI,
401 						       NULL, 0);
402 	}
403 
404 	if (ret)
405 		dev_dbg(nor->dev, "error %d on Write Disable\n", ret);
406 
407 	return ret;
408 }
409 
410 /**
411  * spi_nor_read_id() - Read the JEDEC ID.
412  * @nor:	pointer to 'struct spi_nor'.
413  * @naddr:	number of address bytes to send. Can be zero if the operation
414  *		does not need to send an address.
415  * @ndummy:	number of dummy bytes to send after an opcode or address. Can
416  *		be zero if the operation does not require dummy bytes.
417  * @id:		pointer to a DMA-able buffer where the value of the JEDEC ID
418  *		will be written.
419  * @proto:	the SPI protocol for register operation.
420  *
421  * Return: 0 on success, -errno otherwise.
422  */
423 int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
424 		    enum spi_nor_protocol proto)
425 {
426 	int ret;
427 
428 	if (nor->spimem) {
429 		struct spi_mem_op op =
430 			SPI_NOR_READID_OP(naddr, ndummy, id, SPI_NOR_MAX_ID_LEN);
431 
432 		spi_nor_spimem_setup_op(nor, &op, proto);
433 		ret = spi_mem_exec_op(nor->spimem, &op);
434 	} else {
435 		ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
436 						    SPI_NOR_MAX_ID_LEN);
437 	}
438 	return ret;
439 }
440 
441 /**
442  * spi_nor_read_sr() - Read the Status Register.
443  * @nor:	pointer to 'struct spi_nor'.
444  * @sr:		pointer to a DMA-able buffer where the value of the
445  *              Status Register will be written. Should be at least 2 bytes.
446  *
447  * Return: 0 on success, -errno otherwise.
448  */
449 int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
450 {
451 	int ret;
452 
453 	if (nor->spimem) {
454 		struct spi_mem_op op = SPI_NOR_RDSR_OP(sr);
455 
456 		if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
457 			op.addr.nbytes = nor->params->rdsr_addr_nbytes;
458 			op.dummy.nbytes = nor->params->rdsr_dummy;
459 			/*
460 			 * We don't want to read only one byte in DTR mode. So,
461 			 * read 2 and then discard the second byte.
462 			 */
463 			op.data.nbytes = 2;
464 		}
465 
466 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
467 
468 		ret = spi_mem_exec_op(nor->spimem, &op);
469 	} else {
470 		ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr,
471 						      1);
472 	}
473 
474 	if (ret)
475 		dev_dbg(nor->dev, "error %d reading SR\n", ret);
476 
477 	return ret;
478 }
479 
480 /**
481  * spi_nor_read_cr() - Read the Configuration Register using the
482  * SPINOR_OP_RDCR (35h) command.
483  * @nor:	pointer to 'struct spi_nor'
484  * @cr:		pointer to a DMA-able buffer where the value of the
485  *              Configuration Register will be written.
486  *
487  * Return: 0 on success, -errno otherwise.
488  */
489 int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
490 {
491 	int ret;
492 
493 	if (nor->spimem) {
494 		struct spi_mem_op op = SPI_NOR_RDCR_OP(cr);
495 
496 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
497 
498 		ret = spi_mem_exec_op(nor->spimem, &op);
499 	} else {
500 		ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr,
501 						      1);
502 	}
503 
504 	if (ret)
505 		dev_dbg(nor->dev, "error %d reading CR\n", ret);
506 
507 	return ret;
508 }
509 
510 /**
511  * spi_nor_set_4byte_addr_mode_en4b_ex4b() - Enter/Exit 4-byte address mode
512  *			using SPINOR_OP_EN4B/SPINOR_OP_EX4B. Typically used by
513  *			Winbond and Macronix.
514  * @nor:	pointer to 'struct spi_nor'.
515  * @enable:	true to enter the 4-byte address mode, false to exit the 4-byte
516  *		address mode.
517  *
518  * Return: 0 on success, -errno otherwise.
519  */
520 int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable)
521 {
522 	int ret;
523 
524 	if (nor->spimem) {
525 		struct spi_mem_op op = SPI_NOR_EN4B_EX4B_OP(enable);
526 
527 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
528 
529 		ret = spi_mem_exec_op(nor->spimem, &op);
530 	} else {
531 		ret = spi_nor_controller_ops_write_reg(nor,
532 						       enable ? SPINOR_OP_EN4B :
533 								SPINOR_OP_EX4B,
534 						       NULL, 0);
535 	}
536 
537 	if (ret)
538 		dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
539 
540 	return ret;
541 }
542 
543 /**
544  * spi_nor_set_4byte_addr_mode_wren_en4b_ex4b() - Set 4-byte address mode using
545  * SPINOR_OP_WREN followed by SPINOR_OP_EN4B or SPINOR_OP_EX4B. Typically used
546  * by ST and Micron flashes.
547  * @nor:	pointer to 'struct spi_nor'.
548  * @enable:	true to enter the 4-byte address mode, false to exit the 4-byte
549  *		address mode.
550  *
551  * Return: 0 on success, -errno otherwise.
552  */
553 int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool enable)
554 {
555 	int ret;
556 
557 	ret = spi_nor_write_enable(nor);
558 	if (ret)
559 		return ret;
560 
561 	ret = spi_nor_set_4byte_addr_mode_en4b_ex4b(nor, enable);
562 	if (ret)
563 		return ret;
564 
565 	return spi_nor_write_disable(nor);
566 }
567 
568 /**
569  * spi_nor_set_4byte_addr_mode_brwr() - Set 4-byte address mode using
570  *			SPINOR_OP_BRWR. Typically used by Spansion flashes.
571  * @nor:	pointer to 'struct spi_nor'.
572  * @enable:	true to enter the 4-byte address mode, false to exit the 4-byte
573  *		address mode.
574  *
575  * 8-bit volatile bank register used to define A[30:A24] bits. MSB (bit[7]) is
576  * used to enable/disable 4-byte address mode. When MSB is set to ‘1’, 4-byte
577  * address mode is active and A[30:24] bits are don’t care. Write instruction is
578  * SPINOR_OP_BRWR(17h) with 1 byte of data.
579  *
580  * Return: 0 on success, -errno otherwise.
581  */
582 int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable)
583 {
584 	int ret;
585 
586 	nor->bouncebuf[0] = enable << 7;
587 
588 	if (nor->spimem) {
589 		struct spi_mem_op op = SPI_NOR_BRWR_OP(nor->bouncebuf);
590 
591 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
592 
593 		ret = spi_mem_exec_op(nor->spimem, &op);
594 	} else {
595 		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_BRWR,
596 						       nor->bouncebuf, 1);
597 	}
598 
599 	if (ret)
600 		dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
601 
602 	return ret;
603 }
604 
605 /**
606  * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready
607  * for new commands.
608  * @nor:	pointer to 'struct spi_nor'.
609  *
610  * Return: 1 if ready, 0 if not ready, -errno on errors.
611  */
612 int spi_nor_sr_ready(struct spi_nor *nor)
613 {
614 	int ret;
615 
616 	ret = spi_nor_read_sr(nor, nor->bouncebuf);
617 	if (ret)
618 		return ret;
619 
620 	return !(nor->bouncebuf[0] & SR_WIP);
621 }
622 
623 /**
624  * spi_nor_use_parallel_locking() - Checks if RWW locking scheme shall be used
625  * @nor:	pointer to 'struct spi_nor'.
626  *
627  * Return: true if parallel locking is enabled, false otherwise.
628  */
629 static bool spi_nor_use_parallel_locking(struct spi_nor *nor)
630 {
631 	return nor->flags & SNOR_F_RWW;
632 }
633 
634 /* Locking helpers for status read operations */
635 static int spi_nor_rww_start_rdst(struct spi_nor *nor)
636 {
637 	struct spi_nor_rww *rww = &nor->rww;
638 	int ret = -EAGAIN;
639 
640 	mutex_lock(&nor->lock);
641 
642 	if (rww->ongoing_io || rww->ongoing_rd)
643 		goto busy;
644 
645 	rww->ongoing_io = true;
646 	rww->ongoing_rd = true;
647 	ret = 0;
648 
649 busy:
650 	mutex_unlock(&nor->lock);
651 	return ret;
652 }
653 
654 static void spi_nor_rww_end_rdst(struct spi_nor *nor)
655 {
656 	struct spi_nor_rww *rww = &nor->rww;
657 
658 	mutex_lock(&nor->lock);
659 
660 	rww->ongoing_io = false;
661 	rww->ongoing_rd = false;
662 
663 	mutex_unlock(&nor->lock);
664 }
665 
666 static int spi_nor_lock_rdst(struct spi_nor *nor)
667 {
668 	if (spi_nor_use_parallel_locking(nor))
669 		return spi_nor_rww_start_rdst(nor);
670 
671 	return 0;
672 }
673 
674 static void spi_nor_unlock_rdst(struct spi_nor *nor)
675 {
676 	if (spi_nor_use_parallel_locking(nor)) {
677 		spi_nor_rww_end_rdst(nor);
678 		wake_up(&nor->rww.wait);
679 	}
680 }
681 
682 /**
683  * spi_nor_ready() - Query the flash to see if it is ready for new commands.
684  * @nor:	pointer to 'struct spi_nor'.
685  *
686  * Return: 1 if ready, 0 if not ready, -errno on errors.
687  */
688 static int spi_nor_ready(struct spi_nor *nor)
689 {
690 	int ret;
691 
692 	ret = spi_nor_lock_rdst(nor);
693 	if (ret)
694 		return 0;
695 
696 	/* Flashes might override the standard routine. */
697 	if (nor->params->ready)
698 		ret = nor->params->ready(nor);
699 	else
700 		ret = spi_nor_sr_ready(nor);
701 
702 	spi_nor_unlock_rdst(nor);
703 
704 	return ret;
705 }
706 
707 /**
708  * spi_nor_wait_till_ready_with_timeout() - Service routine to read the
709  * Status Register until ready, or timeout occurs.
710  * @nor:		pointer to "struct spi_nor".
711  * @timeout_jiffies:	jiffies to wait until timeout.
712  *
713  * Return: 0 on success, -errno otherwise.
714  */
715 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
716 						unsigned long timeout_jiffies)
717 {
718 	unsigned long deadline;
719 	int timeout = 0, ret;
720 
721 	deadline = jiffies + timeout_jiffies;
722 
723 	while (!timeout) {
724 		if (time_after_eq(jiffies, deadline))
725 			timeout = 1;
726 
727 		ret = spi_nor_ready(nor);
728 		if (ret < 0)
729 			return ret;
730 		if (ret)
731 			return 0;
732 
733 		cond_resched();
734 	}
735 
736 	dev_dbg(nor->dev, "flash operation timed out\n");
737 
738 	return -ETIMEDOUT;
739 }
740 
741 /**
742  * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the
743  * flash to be ready, or timeout occurs.
744  * @nor:	pointer to "struct spi_nor".
745  *
746  * Return: 0 on success, -errno otherwise.
747  */
748 int spi_nor_wait_till_ready(struct spi_nor *nor)
749 {
750 	return spi_nor_wait_till_ready_with_timeout(nor,
751 						    DEFAULT_READY_WAIT_JIFFIES);
752 }
753 
754 /**
755  * spi_nor_global_block_unlock() - Unlock Global Block Protection.
756  * @nor:	pointer to 'struct spi_nor'.
757  *
758  * Return: 0 on success, -errno otherwise.
759  */
760 int spi_nor_global_block_unlock(struct spi_nor *nor)
761 {
762 	int ret;
763 
764 	ret = spi_nor_write_enable(nor);
765 	if (ret)
766 		return ret;
767 
768 	if (nor->spimem) {
769 		struct spi_mem_op op = SPI_NOR_GBULK_OP;
770 
771 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
772 
773 		ret = spi_mem_exec_op(nor->spimem, &op);
774 	} else {
775 		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_GBULK,
776 						       NULL, 0);
777 	}
778 
779 	if (ret) {
780 		dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret);
781 		return ret;
782 	}
783 
784 	return spi_nor_wait_till_ready(nor);
785 }
786 
787 /**
788  * spi_nor_write_sr() - Write the Status Register.
789  * @nor:	pointer to 'struct spi_nor'.
790  * @sr:		pointer to DMA-able buffer to write to the Status Register.
791  * @len:	number of bytes to write to the Status Register.
792  *
793  * Return: 0 on success, -errno otherwise.
794  */
795 int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
796 {
797 	int ret;
798 
799 	ret = spi_nor_write_enable(nor);
800 	if (ret)
801 		return ret;
802 
803 	if (nor->spimem) {
804 		struct spi_mem_op op = SPI_NOR_WRSR_OP(sr, len);
805 
806 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
807 
808 		ret = spi_mem_exec_op(nor->spimem, &op);
809 	} else {
810 		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr,
811 						       len);
812 	}
813 
814 	if (ret) {
815 		dev_dbg(nor->dev, "error %d writing SR\n", ret);
816 		return ret;
817 	}
818 
819 	return spi_nor_wait_till_ready(nor);
820 }
821 
822 /**
823  * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and
824  * ensure that the byte written match the received value.
825  * @nor:	pointer to a 'struct spi_nor'.
826  * @sr1:	byte value to be written to the Status Register.
827  *
828  * Return: 0 on success, -errno otherwise.
829  */
830 static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1)
831 {
832 	int ret;
833 
834 	nor->bouncebuf[0] = sr1;
835 
836 	ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
837 	if (ret)
838 		return ret;
839 
840 	ret = spi_nor_read_sr(nor, nor->bouncebuf);
841 	if (ret)
842 		return ret;
843 
844 	if (nor->bouncebuf[0] != sr1) {
845 		dev_dbg(nor->dev, "SR1: read back test failed\n");
846 		return -EIO;
847 	}
848 
849 	return 0;
850 }
851 
852 /**
853  * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the
854  * Status Register 2 in one shot. Ensure that the byte written in the Status
855  * Register 1 match the received value, and that the 16-bit Write did not
856  * affect what was already in the Status Register 2.
857  * @nor:	pointer to a 'struct spi_nor'.
858  * @sr1:	byte value to be written to the Status Register 1.
859  *
860  * Return: 0 on success, -errno otherwise.
861  */
862 static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
863 {
864 	int ret;
865 	u8 *sr_cr = nor->bouncebuf;
866 	u8 cr_written;
867 
868 	/* Make sure we don't overwrite the contents of Status Register 2. */
869 	if (!(nor->flags & SNOR_F_NO_READ_CR)) {
870 		ret = spi_nor_read_cr(nor, &sr_cr[1]);
871 		if (ret)
872 			return ret;
873 	} else if (nor->params->quad_enable) {
874 		/*
875 		 * If the Status Register 2 Read command (35h) is not
876 		 * supported, we should at least be sure we don't
877 		 * change the value of the SR2 Quad Enable bit.
878 		 *
879 		 * We can safely assume that when the Quad Enable method is
880 		 * set, the value of the QE bit is one, as a consequence of the
881 		 * nor->params->quad_enable() call.
882 		 *
883 		 * We can safely assume that the Quad Enable bit is present in
884 		 * the Status Register 2 at BIT(1). According to the JESD216
885 		 * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit
886 		 * Write Status (01h) command is available just for the cases
887 		 * in which the QE bit is described in SR2 at BIT(1).
888 		 */
889 		sr_cr[1] = SR2_QUAD_EN_BIT1;
890 	} else {
891 		sr_cr[1] = 0;
892 	}
893 
894 	sr_cr[0] = sr1;
895 
896 	ret = spi_nor_write_sr(nor, sr_cr, 2);
897 	if (ret)
898 		return ret;
899 
900 	ret = spi_nor_read_sr(nor, sr_cr);
901 	if (ret)
902 		return ret;
903 
904 	if (sr1 != sr_cr[0]) {
905 		dev_dbg(nor->dev, "SR: Read back test failed\n");
906 		return -EIO;
907 	}
908 
909 	if (nor->flags & SNOR_F_NO_READ_CR)
910 		return 0;
911 
912 	cr_written = sr_cr[1];
913 
914 	ret = spi_nor_read_cr(nor, &sr_cr[1]);
915 	if (ret)
916 		return ret;
917 
918 	if (cr_written != sr_cr[1]) {
919 		dev_dbg(nor->dev, "CR: read back test failed\n");
920 		return -EIO;
921 	}
922 
923 	return 0;
924 }
925 
926 /**
927  * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the
928  * Configuration Register in one shot. Ensure that the byte written in the
929  * Configuration Register match the received value, and that the 16-bit Write
930  * did not affect what was already in the Status Register 1.
931  * @nor:	pointer to a 'struct spi_nor'.
932  * @cr:		byte value to be written to the Configuration Register.
933  *
934  * Return: 0 on success, -errno otherwise.
935  */
936 int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr)
937 {
938 	int ret;
939 	u8 *sr_cr = nor->bouncebuf;
940 	u8 sr_written;
941 
942 	/* Keep the current value of the Status Register 1. */
943 	ret = spi_nor_read_sr(nor, sr_cr);
944 	if (ret)
945 		return ret;
946 
947 	sr_cr[1] = cr;
948 
949 	ret = spi_nor_write_sr(nor, sr_cr, 2);
950 	if (ret)
951 		return ret;
952 
953 	sr_written = sr_cr[0];
954 
955 	ret = spi_nor_read_sr(nor, sr_cr);
956 	if (ret)
957 		return ret;
958 
959 	if (sr_written != sr_cr[0]) {
960 		dev_dbg(nor->dev, "SR: Read back test failed\n");
961 		return -EIO;
962 	}
963 
964 	if (nor->flags & SNOR_F_NO_READ_CR)
965 		return 0;
966 
967 	ret = spi_nor_read_cr(nor, &sr_cr[1]);
968 	if (ret)
969 		return ret;
970 
971 	if (cr != sr_cr[1]) {
972 		dev_dbg(nor->dev, "CR: read back test failed\n");
973 		return -EIO;
974 	}
975 
976 	return 0;
977 }
978 
979 /**
980  * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that
981  * the byte written match the received value without affecting other bits in the
982  * Status Register 1 and 2.
983  * @nor:	pointer to a 'struct spi_nor'.
984  * @sr1:	byte value to be written to the Status Register.
985  *
986  * Return: 0 on success, -errno otherwise.
987  */
988 int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1)
989 {
990 	if (nor->flags & SNOR_F_HAS_16BIT_SR)
991 		return spi_nor_write_16bit_sr_and_check(nor, sr1);
992 
993 	return spi_nor_write_sr1_and_check(nor, sr1);
994 }
995 
996 /**
997  * spi_nor_write_sr2() - Write the Status Register 2 using the
998  * SPINOR_OP_WRSR2 (3eh) command.
999  * @nor:	pointer to 'struct spi_nor'.
1000  * @sr2:	pointer to DMA-able buffer to write to the Status Register 2.
1001  *
1002  * Return: 0 on success, -errno otherwise.
1003  */
1004 static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
1005 {
1006 	int ret;
1007 
1008 	ret = spi_nor_write_enable(nor);
1009 	if (ret)
1010 		return ret;
1011 
1012 	if (nor->spimem) {
1013 		struct spi_mem_op op = SPI_NOR_WRSR2_OP(sr2);
1014 
1015 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
1016 
1017 		ret = spi_mem_exec_op(nor->spimem, &op);
1018 	} else {
1019 		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2,
1020 						       sr2, 1);
1021 	}
1022 
1023 	if (ret) {
1024 		dev_dbg(nor->dev, "error %d writing SR2\n", ret);
1025 		return ret;
1026 	}
1027 
1028 	return spi_nor_wait_till_ready(nor);
1029 }
1030 
1031 /**
1032  * spi_nor_read_sr2() - Read the Status Register 2 using the
1033  * SPINOR_OP_RDSR2 (3fh) command.
1034  * @nor:	pointer to 'struct spi_nor'.
1035  * @sr2:	pointer to DMA-able buffer where the value of the
1036  *		Status Register 2 will be written.
1037  *
1038  * Return: 0 on success, -errno otherwise.
1039  */
1040 static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
1041 {
1042 	int ret;
1043 
1044 	if (nor->spimem) {
1045 		struct spi_mem_op op = SPI_NOR_RDSR2_OP(sr2);
1046 
1047 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
1048 
1049 		ret = spi_mem_exec_op(nor->spimem, &op);
1050 	} else {
1051 		ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2,
1052 						      1);
1053 	}
1054 
1055 	if (ret)
1056 		dev_dbg(nor->dev, "error %d reading SR2\n", ret);
1057 
1058 	return ret;
1059 }
1060 
1061 /**
1062  * spi_nor_erase_chip() - Erase the entire flash memory.
1063  * @nor:	pointer to 'struct spi_nor'.
1064  *
1065  * Return: 0 on success, -errno otherwise.
1066  */
1067 static int spi_nor_erase_chip(struct spi_nor *nor)
1068 {
1069 	int ret;
1070 
1071 	dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
1072 
1073 	if (nor->spimem) {
1074 		struct spi_mem_op op = SPI_NOR_CHIP_ERASE_OP;
1075 
1076 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
1077 
1078 		ret = spi_mem_exec_op(nor->spimem, &op);
1079 	} else {
1080 		ret = spi_nor_controller_ops_write_reg(nor,
1081 						       SPINOR_OP_CHIP_ERASE,
1082 						       NULL, 0);
1083 	}
1084 
1085 	if (ret)
1086 		dev_dbg(nor->dev, "error %d erasing chip\n", ret);
1087 
1088 	return ret;
1089 }
1090 
1091 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
1092 {
1093 	size_t i;
1094 
1095 	for (i = 0; i < size; i++)
1096 		if (table[i][0] == opcode)
1097 			return table[i][1];
1098 
1099 	/* No conversion found, keep input op code. */
1100 	return opcode;
1101 }
1102 
1103 u8 spi_nor_convert_3to4_read(u8 opcode)
1104 {
1105 	static const u8 spi_nor_3to4_read[][2] = {
1106 		{ SPINOR_OP_READ,	SPINOR_OP_READ_4B },
1107 		{ SPINOR_OP_READ_FAST,	SPINOR_OP_READ_FAST_4B },
1108 		{ SPINOR_OP_READ_1_1_2,	SPINOR_OP_READ_1_1_2_4B },
1109 		{ SPINOR_OP_READ_1_2_2,	SPINOR_OP_READ_1_2_2_4B },
1110 		{ SPINOR_OP_READ_1_1_4,	SPINOR_OP_READ_1_1_4_4B },
1111 		{ SPINOR_OP_READ_1_4_4,	SPINOR_OP_READ_1_4_4_4B },
1112 		{ SPINOR_OP_READ_1_1_8,	SPINOR_OP_READ_1_1_8_4B },
1113 		{ SPINOR_OP_READ_1_8_8,	SPINOR_OP_READ_1_8_8_4B },
1114 
1115 		{ SPINOR_OP_READ_1_1_1_DTR,	SPINOR_OP_READ_1_1_1_DTR_4B },
1116 		{ SPINOR_OP_READ_1_2_2_DTR,	SPINOR_OP_READ_1_2_2_DTR_4B },
1117 		{ SPINOR_OP_READ_1_4_4_DTR,	SPINOR_OP_READ_1_4_4_DTR_4B },
1118 	};
1119 
1120 	return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
1121 				      ARRAY_SIZE(spi_nor_3to4_read));
1122 }
1123 
1124 static u8 spi_nor_convert_3to4_program(u8 opcode)
1125 {
1126 	static const u8 spi_nor_3to4_program[][2] = {
1127 		{ SPINOR_OP_PP,		SPINOR_OP_PP_4B },
1128 		{ SPINOR_OP_PP_1_1_4,	SPINOR_OP_PP_1_1_4_4B },
1129 		{ SPINOR_OP_PP_1_4_4,	SPINOR_OP_PP_1_4_4_4B },
1130 		{ SPINOR_OP_PP_1_1_8,	SPINOR_OP_PP_1_1_8_4B },
1131 		{ SPINOR_OP_PP_1_8_8,	SPINOR_OP_PP_1_8_8_4B },
1132 	};
1133 
1134 	return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
1135 				      ARRAY_SIZE(spi_nor_3to4_program));
1136 }
1137 
1138 static u8 spi_nor_convert_3to4_erase(u8 opcode)
1139 {
1140 	static const u8 spi_nor_3to4_erase[][2] = {
1141 		{ SPINOR_OP_BE_4K,	SPINOR_OP_BE_4K_4B },
1142 		{ SPINOR_OP_BE_32K,	SPINOR_OP_BE_32K_4B },
1143 		{ SPINOR_OP_SE,		SPINOR_OP_SE_4B },
1144 	};
1145 
1146 	return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
1147 				      ARRAY_SIZE(spi_nor_3to4_erase));
1148 }
1149 
1150 static bool spi_nor_has_uniform_erase(const struct spi_nor *nor)
1151 {
1152 	return !!nor->params->erase_map.uniform_erase_type;
1153 }
1154 
1155 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
1156 {
1157 	nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
1158 	nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
1159 	nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
1160 
1161 	if (!spi_nor_has_uniform_erase(nor)) {
1162 		struct spi_nor_erase_map *map = &nor->params->erase_map;
1163 		struct spi_nor_erase_type *erase;
1164 		int i;
1165 
1166 		for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
1167 			erase = &map->erase_type[i];
1168 			erase->opcode =
1169 				spi_nor_convert_3to4_erase(erase->opcode);
1170 		}
1171 	}
1172 }
1173 
1174 static int spi_nor_prep(struct spi_nor *nor)
1175 {
1176 	int ret = 0;
1177 
1178 	if (nor->controller_ops && nor->controller_ops->prepare)
1179 		ret = nor->controller_ops->prepare(nor);
1180 
1181 	return ret;
1182 }
1183 
1184 static void spi_nor_unprep(struct spi_nor *nor)
1185 {
1186 	if (nor->controller_ops && nor->controller_ops->unprepare)
1187 		nor->controller_ops->unprepare(nor);
1188 }
1189 
1190 static void spi_nor_offset_to_banks(u64 bank_size, loff_t start, size_t len,
1191 				    u8 *first, u8 *last)
1192 {
1193 	/* This is currently safe, the number of banks being very small */
1194 	*first = DIV_ROUND_DOWN_ULL(start, bank_size);
1195 	*last = DIV_ROUND_DOWN_ULL(start + len - 1, bank_size);
1196 }
1197 
1198 /* Generic helpers for internal locking and serialization */
1199 static bool spi_nor_rww_start_io(struct spi_nor *nor)
1200 {
1201 	struct spi_nor_rww *rww = &nor->rww;
1202 	bool start = false;
1203 
1204 	mutex_lock(&nor->lock);
1205 
1206 	if (rww->ongoing_io)
1207 		goto busy;
1208 
1209 	rww->ongoing_io = true;
1210 	start = true;
1211 
1212 busy:
1213 	mutex_unlock(&nor->lock);
1214 	return start;
1215 }
1216 
1217 static void spi_nor_rww_end_io(struct spi_nor *nor)
1218 {
1219 	mutex_lock(&nor->lock);
1220 	nor->rww.ongoing_io = false;
1221 	mutex_unlock(&nor->lock);
1222 }
1223 
1224 static int spi_nor_lock_device(struct spi_nor *nor)
1225 {
1226 	if (!spi_nor_use_parallel_locking(nor))
1227 		return 0;
1228 
1229 	return wait_event_killable(nor->rww.wait, spi_nor_rww_start_io(nor));
1230 }
1231 
1232 static void spi_nor_unlock_device(struct spi_nor *nor)
1233 {
1234 	if (spi_nor_use_parallel_locking(nor)) {
1235 		spi_nor_rww_end_io(nor);
1236 		wake_up(&nor->rww.wait);
1237 	}
1238 }
1239 
1240 /* Generic helpers for internal locking and serialization */
1241 static bool spi_nor_rww_start_exclusive(struct spi_nor *nor)
1242 {
1243 	struct spi_nor_rww *rww = &nor->rww;
1244 	bool start = false;
1245 
1246 	mutex_lock(&nor->lock);
1247 
1248 	if (rww->ongoing_io || rww->ongoing_rd || rww->ongoing_pe)
1249 		goto busy;
1250 
1251 	rww->ongoing_io = true;
1252 	rww->ongoing_rd = true;
1253 	rww->ongoing_pe = true;
1254 	start = true;
1255 
1256 busy:
1257 	mutex_unlock(&nor->lock);
1258 	return start;
1259 }
1260 
1261 static void spi_nor_rww_end_exclusive(struct spi_nor *nor)
1262 {
1263 	struct spi_nor_rww *rww = &nor->rww;
1264 
1265 	mutex_lock(&nor->lock);
1266 	rww->ongoing_io = false;
1267 	rww->ongoing_rd = false;
1268 	rww->ongoing_pe = false;
1269 	mutex_unlock(&nor->lock);
1270 }
1271 
1272 int spi_nor_prep_and_lock(struct spi_nor *nor)
1273 {
1274 	int ret;
1275 
1276 	ret = spi_nor_prep(nor);
1277 	if (ret)
1278 		return ret;
1279 
1280 	if (!spi_nor_use_parallel_locking(nor))
1281 		mutex_lock(&nor->lock);
1282 	else
1283 		ret = wait_event_killable(nor->rww.wait,
1284 					  spi_nor_rww_start_exclusive(nor));
1285 
1286 	return ret;
1287 }
1288 
1289 void spi_nor_unlock_and_unprep(struct spi_nor *nor)
1290 {
1291 	if (!spi_nor_use_parallel_locking(nor)) {
1292 		mutex_unlock(&nor->lock);
1293 	} else {
1294 		spi_nor_rww_end_exclusive(nor);
1295 		wake_up(&nor->rww.wait);
1296 	}
1297 
1298 	spi_nor_unprep(nor);
1299 }
1300 
1301 /* Internal locking helpers for program and erase operations */
1302 static bool spi_nor_rww_start_pe(struct spi_nor *nor, loff_t start, size_t len)
1303 {
1304 	struct spi_nor_rww *rww = &nor->rww;
1305 	unsigned int used_banks = 0;
1306 	bool started = false;
1307 	u8 first, last;
1308 	int bank;
1309 
1310 	mutex_lock(&nor->lock);
1311 
1312 	if (rww->ongoing_io || rww->ongoing_rd || rww->ongoing_pe)
1313 		goto busy;
1314 
1315 	spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
1316 	for (bank = first; bank <= last; bank++) {
1317 		if (rww->used_banks & BIT(bank))
1318 			goto busy;
1319 
1320 		used_banks |= BIT(bank);
1321 	}
1322 
1323 	rww->used_banks |= used_banks;
1324 	rww->ongoing_pe = true;
1325 	started = true;
1326 
1327 busy:
1328 	mutex_unlock(&nor->lock);
1329 	return started;
1330 }
1331 
1332 static void spi_nor_rww_end_pe(struct spi_nor *nor, loff_t start, size_t len)
1333 {
1334 	struct spi_nor_rww *rww = &nor->rww;
1335 	u8 first, last;
1336 	int bank;
1337 
1338 	mutex_lock(&nor->lock);
1339 
1340 	spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
1341 	for (bank = first; bank <= last; bank++)
1342 		rww->used_banks &= ~BIT(bank);
1343 
1344 	rww->ongoing_pe = false;
1345 
1346 	mutex_unlock(&nor->lock);
1347 }
1348 
1349 static int spi_nor_prep_and_lock_pe(struct spi_nor *nor, loff_t start, size_t len)
1350 {
1351 	int ret;
1352 
1353 	ret = spi_nor_prep(nor);
1354 	if (ret)
1355 		return ret;
1356 
1357 	if (!spi_nor_use_parallel_locking(nor))
1358 		mutex_lock(&nor->lock);
1359 	else
1360 		ret = wait_event_killable(nor->rww.wait,
1361 					  spi_nor_rww_start_pe(nor, start, len));
1362 
1363 	return ret;
1364 }
1365 
1366 static void spi_nor_unlock_and_unprep_pe(struct spi_nor *nor, loff_t start, size_t len)
1367 {
1368 	if (!spi_nor_use_parallel_locking(nor)) {
1369 		mutex_unlock(&nor->lock);
1370 	} else {
1371 		spi_nor_rww_end_pe(nor, start, len);
1372 		wake_up(&nor->rww.wait);
1373 	}
1374 
1375 	spi_nor_unprep(nor);
1376 }
1377 
1378 /* Internal locking helpers for read operations */
1379 static bool spi_nor_rww_start_rd(struct spi_nor *nor, loff_t start, size_t len)
1380 {
1381 	struct spi_nor_rww *rww = &nor->rww;
1382 	unsigned int used_banks = 0;
1383 	bool started = false;
1384 	u8 first, last;
1385 	int bank;
1386 
1387 	mutex_lock(&nor->lock);
1388 
1389 	if (rww->ongoing_io || rww->ongoing_rd)
1390 		goto busy;
1391 
1392 	spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
1393 	for (bank = first; bank <= last; bank++) {
1394 		if (rww->used_banks & BIT(bank))
1395 			goto busy;
1396 
1397 		used_banks |= BIT(bank);
1398 	}
1399 
1400 	rww->used_banks |= used_banks;
1401 	rww->ongoing_io = true;
1402 	rww->ongoing_rd = true;
1403 	started = true;
1404 
1405 busy:
1406 	mutex_unlock(&nor->lock);
1407 	return started;
1408 }
1409 
1410 static void spi_nor_rww_end_rd(struct spi_nor *nor, loff_t start, size_t len)
1411 {
1412 	struct spi_nor_rww *rww = &nor->rww;
1413 	u8 first, last;
1414 	int bank;
1415 
1416 	mutex_lock(&nor->lock);
1417 
1418 	spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
1419 	for (bank = first; bank <= last; bank++)
1420 		nor->rww.used_banks &= ~BIT(bank);
1421 
1422 	rww->ongoing_io = false;
1423 	rww->ongoing_rd = false;
1424 
1425 	mutex_unlock(&nor->lock);
1426 }
1427 
1428 static int spi_nor_prep_and_lock_rd(struct spi_nor *nor, loff_t start, size_t len)
1429 {
1430 	int ret;
1431 
1432 	ret = spi_nor_prep(nor);
1433 	if (ret)
1434 		return ret;
1435 
1436 	if (!spi_nor_use_parallel_locking(nor))
1437 		mutex_lock(&nor->lock);
1438 	else
1439 		ret = wait_event_killable(nor->rww.wait,
1440 					  spi_nor_rww_start_rd(nor, start, len));
1441 
1442 	return ret;
1443 }
1444 
1445 static void spi_nor_unlock_and_unprep_rd(struct spi_nor *nor, loff_t start, size_t len)
1446 {
1447 	if (!spi_nor_use_parallel_locking(nor)) {
1448 		mutex_unlock(&nor->lock);
1449 	} else {
1450 		spi_nor_rww_end_rd(nor, start, len);
1451 		wake_up(&nor->rww.wait);
1452 	}
1453 
1454 	spi_nor_unprep(nor);
1455 }
1456 
1457 static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr)
1458 {
1459 	if (!nor->params->convert_addr)
1460 		return addr;
1461 
1462 	return nor->params->convert_addr(nor, addr);
1463 }
1464 
1465 /*
1466  * Initiate the erasure of a single sector
1467  */
1468 int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
1469 {
1470 	int i;
1471 
1472 	addr = spi_nor_convert_addr(nor, addr);
1473 
1474 	if (nor->spimem) {
1475 		struct spi_mem_op op =
1476 			SPI_NOR_SECTOR_ERASE_OP(nor->erase_opcode,
1477 						nor->addr_nbytes, addr);
1478 
1479 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
1480 
1481 		return spi_mem_exec_op(nor->spimem, &op);
1482 	} else if (nor->controller_ops->erase) {
1483 		return spi_nor_controller_ops_erase(nor, addr);
1484 	}
1485 
1486 	/*
1487 	 * Default implementation, if driver doesn't have a specialized HW
1488 	 * control
1489 	 */
1490 	for (i = nor->addr_nbytes - 1; i >= 0; i--) {
1491 		nor->bouncebuf[i] = addr & 0xff;
1492 		addr >>= 8;
1493 	}
1494 
1495 	return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode,
1496 						nor->bouncebuf, nor->addr_nbytes);
1497 }
1498 
1499 /**
1500  * spi_nor_div_by_erase_size() - calculate remainder and update new dividend
1501  * @erase:	pointer to a structure that describes a SPI NOR erase type
1502  * @dividend:	dividend value
1503  * @remainder:	pointer to u32 remainder (will be updated)
1504  *
1505  * Return: the result of the division
1506  */
1507 static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase,
1508 				     u64 dividend, u32 *remainder)
1509 {
1510 	/* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
1511 	*remainder = (u32)dividend & erase->size_mask;
1512 	return dividend >> erase->size_shift;
1513 }
1514 
1515 /**
1516  * spi_nor_find_best_erase_type() - find the best erase type for the given
1517  *				    offset in the serial flash memory and the
1518  *				    number of bytes to erase. The region in
1519  *				    which the address fits is expected to be
1520  *				    provided.
1521  * @map:	the erase map of the SPI NOR
1522  * @region:	pointer to a structure that describes a SPI NOR erase region
1523  * @addr:	offset in the serial flash memory
1524  * @len:	number of bytes to erase
1525  *
1526  * Return: a pointer to the best fitted erase type, NULL otherwise.
1527  */
1528 static const struct spi_nor_erase_type *
1529 spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map,
1530 			     const struct spi_nor_erase_region *region,
1531 			     u64 addr, u32 len)
1532 {
1533 	const struct spi_nor_erase_type *erase;
1534 	u32 rem;
1535 	int i;
1536 	u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
1537 
1538 	/*
1539 	 * Erase types are ordered by size, with the smallest erase type at
1540 	 * index 0.
1541 	 */
1542 	for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
1543 		/* Does the erase region support the tested erase type? */
1544 		if (!(erase_mask & BIT(i)))
1545 			continue;
1546 
1547 		erase = &map->erase_type[i];
1548 		if (!erase->size)
1549 			continue;
1550 
1551 		/* Alignment is not mandatory for overlaid regions */
1552 		if (region->offset & SNOR_OVERLAID_REGION &&
1553 		    region->size <= len)
1554 			return erase;
1555 
1556 		/* Don't erase more than what the user has asked for. */
1557 		if (erase->size > len)
1558 			continue;
1559 
1560 		spi_nor_div_by_erase_size(erase, addr, &rem);
1561 		if (!rem)
1562 			return erase;
1563 	}
1564 
1565 	return NULL;
1566 }
1567 
1568 static u64 spi_nor_region_is_last(const struct spi_nor_erase_region *region)
1569 {
1570 	return region->offset & SNOR_LAST_REGION;
1571 }
1572 
1573 static u64 spi_nor_region_end(const struct spi_nor_erase_region *region)
1574 {
1575 	return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size;
1576 }
1577 
1578 /**
1579  * spi_nor_region_next() - get the next spi nor region
1580  * @region:	pointer to a structure that describes a SPI NOR erase region
1581  *
1582  * Return: the next spi nor region or NULL if last region.
1583  */
1584 struct spi_nor_erase_region *
1585 spi_nor_region_next(struct spi_nor_erase_region *region)
1586 {
1587 	if (spi_nor_region_is_last(region))
1588 		return NULL;
1589 	region++;
1590 	return region;
1591 }
1592 
1593 /**
1594  * spi_nor_find_erase_region() - find the region of the serial flash memory in
1595  *				 which the offset fits
1596  * @map:	the erase map of the SPI NOR
1597  * @addr:	offset in the serial flash memory
1598  *
1599  * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno)
1600  *	   otherwise.
1601  */
1602 static struct spi_nor_erase_region *
1603 spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr)
1604 {
1605 	struct spi_nor_erase_region *region = map->regions;
1606 	u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1607 	u64 region_end = region_start + region->size;
1608 
1609 	while (addr < region_start || addr >= region_end) {
1610 		region = spi_nor_region_next(region);
1611 		if (!region)
1612 			return ERR_PTR(-EINVAL);
1613 
1614 		region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1615 		region_end = region_start + region->size;
1616 	}
1617 
1618 	return region;
1619 }
1620 
1621 /**
1622  * spi_nor_init_erase_cmd() - initialize an erase command
1623  * @region:	pointer to a structure that describes a SPI NOR erase region
1624  * @erase:	pointer to a structure that describes a SPI NOR erase type
1625  *
1626  * Return: the pointer to the allocated erase command, ERR_PTR(-errno)
1627  *	   otherwise.
1628  */
1629 static struct spi_nor_erase_command *
1630 spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region,
1631 		       const struct spi_nor_erase_type *erase)
1632 {
1633 	struct spi_nor_erase_command *cmd;
1634 
1635 	cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
1636 	if (!cmd)
1637 		return ERR_PTR(-ENOMEM);
1638 
1639 	INIT_LIST_HEAD(&cmd->list);
1640 	cmd->opcode = erase->opcode;
1641 	cmd->count = 1;
1642 
1643 	if (region->offset & SNOR_OVERLAID_REGION)
1644 		cmd->size = region->size;
1645 	else
1646 		cmd->size = erase->size;
1647 
1648 	return cmd;
1649 }
1650 
1651 /**
1652  * spi_nor_destroy_erase_cmd_list() - destroy erase command list
1653  * @erase_list:	list of erase commands
1654  */
1655 static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list)
1656 {
1657 	struct spi_nor_erase_command *cmd, *next;
1658 
1659 	list_for_each_entry_safe(cmd, next, erase_list, list) {
1660 		list_del(&cmd->list);
1661 		kfree(cmd);
1662 	}
1663 }
1664 
1665 /**
1666  * spi_nor_init_erase_cmd_list() - initialize erase command list
1667  * @nor:	pointer to a 'struct spi_nor'
1668  * @erase_list:	list of erase commands to be executed once we validate that the
1669  *		erase can be performed
1670  * @addr:	offset in the serial flash memory
1671  * @len:	number of bytes to erase
1672  *
1673  * Builds the list of best fitted erase commands and verifies if the erase can
1674  * be performed.
1675  *
1676  * Return: 0 on success, -errno otherwise.
1677  */
1678 static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
1679 				       struct list_head *erase_list,
1680 				       u64 addr, u32 len)
1681 {
1682 	const struct spi_nor_erase_map *map = &nor->params->erase_map;
1683 	const struct spi_nor_erase_type *erase, *prev_erase = NULL;
1684 	struct spi_nor_erase_region *region;
1685 	struct spi_nor_erase_command *cmd = NULL;
1686 	u64 region_end;
1687 	int ret = -EINVAL;
1688 
1689 	region = spi_nor_find_erase_region(map, addr);
1690 	if (IS_ERR(region))
1691 		return PTR_ERR(region);
1692 
1693 	region_end = spi_nor_region_end(region);
1694 
1695 	while (len) {
1696 		erase = spi_nor_find_best_erase_type(map, region, addr, len);
1697 		if (!erase)
1698 			goto destroy_erase_cmd_list;
1699 
1700 		if (prev_erase != erase ||
1701 		    erase->size != cmd->size ||
1702 		    region->offset & SNOR_OVERLAID_REGION) {
1703 			cmd = spi_nor_init_erase_cmd(region, erase);
1704 			if (IS_ERR(cmd)) {
1705 				ret = PTR_ERR(cmd);
1706 				goto destroy_erase_cmd_list;
1707 			}
1708 
1709 			list_add_tail(&cmd->list, erase_list);
1710 		} else {
1711 			cmd->count++;
1712 		}
1713 
1714 		addr += cmd->size;
1715 		len -= cmd->size;
1716 
1717 		if (len && addr >= region_end) {
1718 			region = spi_nor_region_next(region);
1719 			if (!region)
1720 				goto destroy_erase_cmd_list;
1721 			region_end = spi_nor_region_end(region);
1722 		}
1723 
1724 		prev_erase = erase;
1725 	}
1726 
1727 	return 0;
1728 
1729 destroy_erase_cmd_list:
1730 	spi_nor_destroy_erase_cmd_list(erase_list);
1731 	return ret;
1732 }
1733 
1734 /**
1735  * spi_nor_erase_multi_sectors() - perform a non-uniform erase
1736  * @nor:	pointer to a 'struct spi_nor'
1737  * @addr:	offset in the serial flash memory
1738  * @len:	number of bytes to erase
1739  *
1740  * Build a list of best fitted erase commands and execute it once we validate
1741  * that the erase can be performed.
1742  *
1743  * Return: 0 on success, -errno otherwise.
1744  */
1745 static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
1746 {
1747 	LIST_HEAD(erase_list);
1748 	struct spi_nor_erase_command *cmd, *next;
1749 	int ret;
1750 
1751 	ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len);
1752 	if (ret)
1753 		return ret;
1754 
1755 	list_for_each_entry_safe(cmd, next, &erase_list, list) {
1756 		nor->erase_opcode = cmd->opcode;
1757 		while (cmd->count) {
1758 			dev_vdbg(nor->dev, "erase_cmd->size = 0x%08x, erase_cmd->opcode = 0x%02x, erase_cmd->count = %u\n",
1759 				 cmd->size, cmd->opcode, cmd->count);
1760 
1761 			ret = spi_nor_lock_device(nor);
1762 			if (ret)
1763 				goto destroy_erase_cmd_list;
1764 
1765 			ret = spi_nor_write_enable(nor);
1766 			if (ret) {
1767 				spi_nor_unlock_device(nor);
1768 				goto destroy_erase_cmd_list;
1769 			}
1770 
1771 			ret = spi_nor_erase_sector(nor, addr);
1772 			spi_nor_unlock_device(nor);
1773 			if (ret)
1774 				goto destroy_erase_cmd_list;
1775 
1776 			ret = spi_nor_wait_till_ready(nor);
1777 			if (ret)
1778 				goto destroy_erase_cmd_list;
1779 
1780 			addr += cmd->size;
1781 			cmd->count--;
1782 		}
1783 		list_del(&cmd->list);
1784 		kfree(cmd);
1785 	}
1786 
1787 	return 0;
1788 
1789 destroy_erase_cmd_list:
1790 	spi_nor_destroy_erase_cmd_list(&erase_list);
1791 	return ret;
1792 }
1793 
1794 /*
1795  * Erase an address range on the nor chip.  The address range may extend
1796  * one or more erase sectors. Return an error if there is a problem erasing.
1797  */
1798 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
1799 {
1800 	struct spi_nor *nor = mtd_to_spi_nor(mtd);
1801 	u32 addr, len;
1802 	uint32_t rem;
1803 	int ret;
1804 
1805 	dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
1806 			(long long)instr->len);
1807 
1808 	if (spi_nor_has_uniform_erase(nor)) {
1809 		div_u64_rem(instr->len, mtd->erasesize, &rem);
1810 		if (rem)
1811 			return -EINVAL;
1812 	}
1813 
1814 	addr = instr->addr;
1815 	len = instr->len;
1816 
1817 	ret = spi_nor_prep_and_lock_pe(nor, instr->addr, instr->len);
1818 	if (ret)
1819 		return ret;
1820 
1821 	/* whole-chip erase? */
1822 	if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
1823 		unsigned long timeout;
1824 
1825 		ret = spi_nor_lock_device(nor);
1826 		if (ret)
1827 			goto erase_err;
1828 
1829 		ret = spi_nor_write_enable(nor);
1830 		if (ret) {
1831 			spi_nor_unlock_device(nor);
1832 			goto erase_err;
1833 		}
1834 
1835 		ret = spi_nor_erase_chip(nor);
1836 		spi_nor_unlock_device(nor);
1837 		if (ret)
1838 			goto erase_err;
1839 
1840 		/*
1841 		 * Scale the timeout linearly with the size of the flash, with
1842 		 * a minimum calibrated to an old 2MB flash. We could try to
1843 		 * pull these from CFI/SFDP, but these values should be good
1844 		 * enough for now.
1845 		 */
1846 		timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
1847 			      CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
1848 			      (unsigned long)(mtd->size / SZ_2M));
1849 		ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
1850 		if (ret)
1851 			goto erase_err;
1852 
1853 	/* REVISIT in some cases we could speed up erasing large regions
1854 	 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K.  We may have set up
1855 	 * to use "small sector erase", but that's not always optimal.
1856 	 */
1857 
1858 	/* "sector"-at-a-time erase */
1859 	} else if (spi_nor_has_uniform_erase(nor)) {
1860 		while (len) {
1861 			ret = spi_nor_lock_device(nor);
1862 			if (ret)
1863 				goto erase_err;
1864 
1865 			ret = spi_nor_write_enable(nor);
1866 			if (ret) {
1867 				spi_nor_unlock_device(nor);
1868 				goto erase_err;
1869 			}
1870 
1871 			ret = spi_nor_erase_sector(nor, addr);
1872 			spi_nor_unlock_device(nor);
1873 			if (ret)
1874 				goto erase_err;
1875 
1876 			ret = spi_nor_wait_till_ready(nor);
1877 			if (ret)
1878 				goto erase_err;
1879 
1880 			addr += mtd->erasesize;
1881 			len -= mtd->erasesize;
1882 		}
1883 
1884 	/* erase multiple sectors */
1885 	} else {
1886 		ret = spi_nor_erase_multi_sectors(nor, addr, len);
1887 		if (ret)
1888 			goto erase_err;
1889 	}
1890 
1891 	ret = spi_nor_write_disable(nor);
1892 
1893 erase_err:
1894 	spi_nor_unlock_and_unprep_pe(nor, instr->addr, instr->len);
1895 
1896 	return ret;
1897 }
1898 
1899 /**
1900  * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
1901  * Register 1.
1902  * @nor:	pointer to a 'struct spi_nor'
1903  *
1904  * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
1905  *
1906  * Return: 0 on success, -errno otherwise.
1907  */
1908 int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
1909 {
1910 	int ret;
1911 
1912 	ret = spi_nor_read_sr(nor, nor->bouncebuf);
1913 	if (ret)
1914 		return ret;
1915 
1916 	if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
1917 		return 0;
1918 
1919 	nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
1920 
1921 	return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);
1922 }
1923 
1924 /**
1925  * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
1926  * Register 2.
1927  * @nor:       pointer to a 'struct spi_nor'.
1928  *
1929  * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
1930  *
1931  * Return: 0 on success, -errno otherwise.
1932  */
1933 int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
1934 {
1935 	int ret;
1936 
1937 	if (nor->flags & SNOR_F_NO_READ_CR)
1938 		return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1);
1939 
1940 	ret = spi_nor_read_cr(nor, nor->bouncebuf);
1941 	if (ret)
1942 		return ret;
1943 
1944 	if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
1945 		return 0;
1946 
1947 	nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
1948 
1949 	return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
1950 }
1951 
1952 /**
1953  * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
1954  * @nor:	pointer to a 'struct spi_nor'
1955  *
1956  * Set the Quad Enable (QE) bit in the Status Register 2.
1957  *
1958  * This is one of the procedures to set the QE bit described in the SFDP
1959  * (JESD216 rev B) specification but no manufacturer using this procedure has
1960  * been identified yet, hence the name of the function.
1961  *
1962  * Return: 0 on success, -errno otherwise.
1963  */
1964 int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
1965 {
1966 	u8 *sr2 = nor->bouncebuf;
1967 	int ret;
1968 	u8 sr2_written;
1969 
1970 	/* Check current Quad Enable bit value. */
1971 	ret = spi_nor_read_sr2(nor, sr2);
1972 	if (ret)
1973 		return ret;
1974 	if (*sr2 & SR2_QUAD_EN_BIT7)
1975 		return 0;
1976 
1977 	/* Update the Quad Enable bit. */
1978 	*sr2 |= SR2_QUAD_EN_BIT7;
1979 
1980 	ret = spi_nor_write_sr2(nor, sr2);
1981 	if (ret)
1982 		return ret;
1983 
1984 	sr2_written = *sr2;
1985 
1986 	/* Read back and check it. */
1987 	ret = spi_nor_read_sr2(nor, sr2);
1988 	if (ret)
1989 		return ret;
1990 
1991 	if (*sr2 != sr2_written) {
1992 		dev_dbg(nor->dev, "SR2: Read back test failed\n");
1993 		return -EIO;
1994 	}
1995 
1996 	return 0;
1997 }
1998 
1999 static const struct spi_nor_manufacturer *manufacturers[] = {
2000 	&spi_nor_atmel,
2001 	&spi_nor_catalyst,
2002 	&spi_nor_eon,
2003 	&spi_nor_esmt,
2004 	&spi_nor_everspin,
2005 	&spi_nor_fujitsu,
2006 	&spi_nor_gigadevice,
2007 	&spi_nor_intel,
2008 	&spi_nor_issi,
2009 	&spi_nor_macronix,
2010 	&spi_nor_micron,
2011 	&spi_nor_st,
2012 	&spi_nor_spansion,
2013 	&spi_nor_sst,
2014 	&spi_nor_winbond,
2015 	&spi_nor_xilinx,
2016 	&spi_nor_xmc,
2017 };
2018 
2019 static const struct flash_info spi_nor_generic_flash = {
2020 	.name = "spi-nor-generic",
2021 	/*
2022 	 * JESD216 rev A doesn't specify the page size, therefore we need a
2023 	 * sane default.
2024 	 */
2025 	.page_size = 256,
2026 	.parse_sfdp = true,
2027 };
2028 
2029 static const struct flash_info *spi_nor_match_id(struct spi_nor *nor,
2030 						 const u8 *id)
2031 {
2032 	const struct flash_info *part;
2033 	unsigned int i, j;
2034 
2035 	for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
2036 		for (j = 0; j < manufacturers[i]->nparts; j++) {
2037 			part = &manufacturers[i]->parts[j];
2038 			if (part->id_len &&
2039 			    !memcmp(part->id, id, part->id_len)) {
2040 				nor->manufacturer = manufacturers[i];
2041 				return part;
2042 			}
2043 		}
2044 	}
2045 
2046 	return NULL;
2047 }
2048 
2049 static const struct flash_info *spi_nor_detect(struct spi_nor *nor)
2050 {
2051 	const struct flash_info *info;
2052 	u8 *id = nor->bouncebuf;
2053 	int ret;
2054 
2055 	ret = spi_nor_read_id(nor, 0, 0, id, nor->reg_proto);
2056 	if (ret) {
2057 		dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret);
2058 		return ERR_PTR(ret);
2059 	}
2060 
2061 	/* Cache the complete flash ID. */
2062 	nor->id = devm_kmemdup(nor->dev, id, SPI_NOR_MAX_ID_LEN, GFP_KERNEL);
2063 	if (!nor->id)
2064 		return ERR_PTR(-ENOMEM);
2065 
2066 	info = spi_nor_match_id(nor, id);
2067 
2068 	/* Fallback to a generic flash described only by its SFDP data. */
2069 	if (!info) {
2070 		ret = spi_nor_check_sfdp_signature(nor);
2071 		if (!ret)
2072 			info = &spi_nor_generic_flash;
2073 	}
2074 
2075 	if (!info) {
2076 		dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",
2077 			SPI_NOR_MAX_ID_LEN, id);
2078 		return ERR_PTR(-ENODEV);
2079 	}
2080 	return info;
2081 }
2082 
2083 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
2084 			size_t *retlen, u_char *buf)
2085 {
2086 	struct spi_nor *nor = mtd_to_spi_nor(mtd);
2087 	loff_t from_lock = from;
2088 	size_t len_lock = len;
2089 	ssize_t ret;
2090 
2091 	dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
2092 
2093 	ret = spi_nor_prep_and_lock_rd(nor, from_lock, len_lock);
2094 	if (ret)
2095 		return ret;
2096 
2097 	while (len) {
2098 		loff_t addr = from;
2099 
2100 		addr = spi_nor_convert_addr(nor, addr);
2101 
2102 		ret = spi_nor_read_data(nor, addr, len, buf);
2103 		if (ret == 0) {
2104 			/* We shouldn't see 0-length reads */
2105 			ret = -EIO;
2106 			goto read_err;
2107 		}
2108 		if (ret < 0)
2109 			goto read_err;
2110 
2111 		WARN_ON(ret > len);
2112 		*retlen += ret;
2113 		buf += ret;
2114 		from += ret;
2115 		len -= ret;
2116 	}
2117 	ret = 0;
2118 
2119 read_err:
2120 	spi_nor_unlock_and_unprep_rd(nor, from_lock, len_lock);
2121 
2122 	return ret;
2123 }
2124 
2125 /*
2126  * Write an address range to the nor chip.  Data must be written in
2127  * FLASH_PAGESIZE chunks.  The address range may be any size provided
2128  * it is within the physical boundaries.
2129  */
2130 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
2131 	size_t *retlen, const u_char *buf)
2132 {
2133 	struct spi_nor *nor = mtd_to_spi_nor(mtd);
2134 	size_t page_offset, page_remain, i;
2135 	ssize_t ret;
2136 	u32 page_size = nor->params->page_size;
2137 
2138 	dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
2139 
2140 	ret = spi_nor_prep_and_lock_pe(nor, to, len);
2141 	if (ret)
2142 		return ret;
2143 
2144 	for (i = 0; i < len; ) {
2145 		ssize_t written;
2146 		loff_t addr = to + i;
2147 
2148 		/*
2149 		 * If page_size is a power of two, the offset can be quickly
2150 		 * calculated with an AND operation. On the other cases we
2151 		 * need to do a modulus operation (more expensive).
2152 		 */
2153 		if (is_power_of_2(page_size)) {
2154 			page_offset = addr & (page_size - 1);
2155 		} else {
2156 			uint64_t aux = addr;
2157 
2158 			page_offset = do_div(aux, page_size);
2159 		}
2160 		/* the size of data remaining on the first page */
2161 		page_remain = min_t(size_t, page_size - page_offset, len - i);
2162 
2163 		addr = spi_nor_convert_addr(nor, addr);
2164 
2165 		ret = spi_nor_lock_device(nor);
2166 		if (ret)
2167 			goto write_err;
2168 
2169 		ret = spi_nor_write_enable(nor);
2170 		if (ret) {
2171 			spi_nor_unlock_device(nor);
2172 			goto write_err;
2173 		}
2174 
2175 		ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
2176 		spi_nor_unlock_device(nor);
2177 		if (ret < 0)
2178 			goto write_err;
2179 		written = ret;
2180 
2181 		ret = spi_nor_wait_till_ready(nor);
2182 		if (ret)
2183 			goto write_err;
2184 		*retlen += written;
2185 		i += written;
2186 	}
2187 
2188 write_err:
2189 	spi_nor_unlock_and_unprep_pe(nor, to, len);
2190 
2191 	return ret;
2192 }
2193 
2194 static int spi_nor_check(struct spi_nor *nor)
2195 {
2196 	if (!nor->dev ||
2197 	    (!nor->spimem && !nor->controller_ops) ||
2198 	    (!nor->spimem && nor->controller_ops &&
2199 	    (!nor->controller_ops->read ||
2200 	     !nor->controller_ops->write ||
2201 	     !nor->controller_ops->read_reg ||
2202 	     !nor->controller_ops->write_reg))) {
2203 		pr_err("spi-nor: please fill all the necessary fields!\n");
2204 		return -EINVAL;
2205 	}
2206 
2207 	if (nor->spimem && nor->controller_ops) {
2208 		dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n");
2209 		return -EINVAL;
2210 	}
2211 
2212 	return 0;
2213 }
2214 
2215 void
2216 spi_nor_set_read_settings(struct spi_nor_read_command *read,
2217 			  u8 num_mode_clocks,
2218 			  u8 num_wait_states,
2219 			  u8 opcode,
2220 			  enum spi_nor_protocol proto)
2221 {
2222 	read->num_mode_clocks = num_mode_clocks;
2223 	read->num_wait_states = num_wait_states;
2224 	read->opcode = opcode;
2225 	read->proto = proto;
2226 }
2227 
2228 void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,
2229 			     enum spi_nor_protocol proto)
2230 {
2231 	pp->opcode = opcode;
2232 	pp->proto = proto;
2233 }
2234 
2235 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2236 {
2237 	size_t i;
2238 
2239 	for (i = 0; i < size; i++)
2240 		if (table[i][0] == (int)hwcaps)
2241 			return table[i][1];
2242 
2243 	return -EINVAL;
2244 }
2245 
2246 int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2247 {
2248 	static const int hwcaps_read2cmd[][2] = {
2249 		{ SNOR_HWCAPS_READ,		SNOR_CMD_READ },
2250 		{ SNOR_HWCAPS_READ_FAST,	SNOR_CMD_READ_FAST },
2251 		{ SNOR_HWCAPS_READ_1_1_1_DTR,	SNOR_CMD_READ_1_1_1_DTR },
2252 		{ SNOR_HWCAPS_READ_1_1_2,	SNOR_CMD_READ_1_1_2 },
2253 		{ SNOR_HWCAPS_READ_1_2_2,	SNOR_CMD_READ_1_2_2 },
2254 		{ SNOR_HWCAPS_READ_2_2_2,	SNOR_CMD_READ_2_2_2 },
2255 		{ SNOR_HWCAPS_READ_1_2_2_DTR,	SNOR_CMD_READ_1_2_2_DTR },
2256 		{ SNOR_HWCAPS_READ_1_1_4,	SNOR_CMD_READ_1_1_4 },
2257 		{ SNOR_HWCAPS_READ_1_4_4,	SNOR_CMD_READ_1_4_4 },
2258 		{ SNOR_HWCAPS_READ_4_4_4,	SNOR_CMD_READ_4_4_4 },
2259 		{ SNOR_HWCAPS_READ_1_4_4_DTR,	SNOR_CMD_READ_1_4_4_DTR },
2260 		{ SNOR_HWCAPS_READ_1_1_8,	SNOR_CMD_READ_1_1_8 },
2261 		{ SNOR_HWCAPS_READ_1_8_8,	SNOR_CMD_READ_1_8_8 },
2262 		{ SNOR_HWCAPS_READ_8_8_8,	SNOR_CMD_READ_8_8_8 },
2263 		{ SNOR_HWCAPS_READ_1_8_8_DTR,	SNOR_CMD_READ_1_8_8_DTR },
2264 		{ SNOR_HWCAPS_READ_8_8_8_DTR,	SNOR_CMD_READ_8_8_8_DTR },
2265 	};
2266 
2267 	return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2268 				  ARRAY_SIZE(hwcaps_read2cmd));
2269 }
2270 
2271 int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2272 {
2273 	static const int hwcaps_pp2cmd[][2] = {
2274 		{ SNOR_HWCAPS_PP,		SNOR_CMD_PP },
2275 		{ SNOR_HWCAPS_PP_1_1_4,		SNOR_CMD_PP_1_1_4 },
2276 		{ SNOR_HWCAPS_PP_1_4_4,		SNOR_CMD_PP_1_4_4 },
2277 		{ SNOR_HWCAPS_PP_4_4_4,		SNOR_CMD_PP_4_4_4 },
2278 		{ SNOR_HWCAPS_PP_1_1_8,		SNOR_CMD_PP_1_1_8 },
2279 		{ SNOR_HWCAPS_PP_1_8_8,		SNOR_CMD_PP_1_8_8 },
2280 		{ SNOR_HWCAPS_PP_8_8_8,		SNOR_CMD_PP_8_8_8 },
2281 		{ SNOR_HWCAPS_PP_8_8_8_DTR,	SNOR_CMD_PP_8_8_8_DTR },
2282 	};
2283 
2284 	return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2285 				  ARRAY_SIZE(hwcaps_pp2cmd));
2286 }
2287 
2288 /**
2289  * spi_nor_spimem_check_op - check if the operation is supported
2290  *                           by controller
2291  *@nor:        pointer to a 'struct spi_nor'
2292  *@op:         pointer to op template to be checked
2293  *
2294  * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
2295  */
2296 static int spi_nor_spimem_check_op(struct spi_nor *nor,
2297 				   struct spi_mem_op *op)
2298 {
2299 	/*
2300 	 * First test with 4 address bytes. The opcode itself might
2301 	 * be a 3B addressing opcode but we don't care, because
2302 	 * SPI controller implementation should not check the opcode,
2303 	 * but just the sequence.
2304 	 */
2305 	op->addr.nbytes = 4;
2306 	if (!spi_mem_supports_op(nor->spimem, op)) {
2307 		if (nor->params->size > SZ_16M)
2308 			return -EOPNOTSUPP;
2309 
2310 		/* If flash size <= 16MB, 3 address bytes are sufficient */
2311 		op->addr.nbytes = 3;
2312 		if (!spi_mem_supports_op(nor->spimem, op))
2313 			return -EOPNOTSUPP;
2314 	}
2315 
2316 	return 0;
2317 }
2318 
2319 /**
2320  * spi_nor_spimem_check_readop - check if the read op is supported
2321  *                               by controller
2322  *@nor:         pointer to a 'struct spi_nor'
2323  *@read:        pointer to op template to be checked
2324  *
2325  * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
2326  */
2327 static int spi_nor_spimem_check_readop(struct spi_nor *nor,
2328 				       const struct spi_nor_read_command *read)
2329 {
2330 	struct spi_mem_op op = SPI_NOR_READ_OP(read->opcode);
2331 
2332 	spi_nor_spimem_setup_op(nor, &op, read->proto);
2333 
2334 	/* convert the dummy cycles to the number of bytes */
2335 	op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *
2336 			  op.dummy.buswidth / 8;
2337 	if (spi_nor_protocol_is_dtr(nor->read_proto))
2338 		op.dummy.nbytes *= 2;
2339 
2340 	return spi_nor_spimem_check_op(nor, &op);
2341 }
2342 
2343 /**
2344  * spi_nor_spimem_check_pp - check if the page program op is supported
2345  *                           by controller
2346  *@nor:         pointer to a 'struct spi_nor'
2347  *@pp:          pointer to op template to be checked
2348  *
2349  * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
2350  */
2351 static int spi_nor_spimem_check_pp(struct spi_nor *nor,
2352 				   const struct spi_nor_pp_command *pp)
2353 {
2354 	struct spi_mem_op op = SPI_NOR_PP_OP(pp->opcode);
2355 
2356 	spi_nor_spimem_setup_op(nor, &op, pp->proto);
2357 
2358 	return spi_nor_spimem_check_op(nor, &op);
2359 }
2360 
2361 /**
2362  * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol
2363  *                                based on SPI controller capabilities
2364  * @nor:        pointer to a 'struct spi_nor'
2365  * @hwcaps:     pointer to resulting capabilities after adjusting
2366  *              according to controller and flash's capability
2367  */
2368 static void
2369 spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
2370 {
2371 	struct spi_nor_flash_parameter *params = nor->params;
2372 	unsigned int cap;
2373 
2374 	/* X-X-X modes are not supported yet, mask them all. */
2375 	*hwcaps &= ~SNOR_HWCAPS_X_X_X;
2376 
2377 	/*
2378 	 * If the reset line is broken, we do not want to enter a stateful
2379 	 * mode.
2380 	 */
2381 	if (nor->flags & SNOR_F_BROKEN_RESET)
2382 		*hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR);
2383 
2384 	for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
2385 		int rdidx, ppidx;
2386 
2387 		if (!(*hwcaps & BIT(cap)))
2388 			continue;
2389 
2390 		rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
2391 		if (rdidx >= 0 &&
2392 		    spi_nor_spimem_check_readop(nor, &params->reads[rdidx]))
2393 			*hwcaps &= ~BIT(cap);
2394 
2395 		ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
2396 		if (ppidx < 0)
2397 			continue;
2398 
2399 		if (spi_nor_spimem_check_pp(nor,
2400 					    &params->page_programs[ppidx]))
2401 			*hwcaps &= ~BIT(cap);
2402 	}
2403 }
2404 
2405 /**
2406  * spi_nor_set_erase_type() - set a SPI NOR erase type
2407  * @erase:	pointer to a structure that describes a SPI NOR erase type
2408  * @size:	the size of the sector/block erased by the erase type
2409  * @opcode:	the SPI command op code to erase the sector/block
2410  */
2411 void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,
2412 			    u8 opcode)
2413 {
2414 	erase->size = size;
2415 	erase->opcode = opcode;
2416 	/* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
2417 	erase->size_shift = ffs(erase->size) - 1;
2418 	erase->size_mask = (1 << erase->size_shift) - 1;
2419 }
2420 
2421 /**
2422  * spi_nor_mask_erase_type() - mask out a SPI NOR erase type
2423  * @erase:	pointer to a structure that describes a SPI NOR erase type
2424  */
2425 void spi_nor_mask_erase_type(struct spi_nor_erase_type *erase)
2426 {
2427 	erase->size = 0;
2428 }
2429 
2430 /**
2431  * spi_nor_init_uniform_erase_map() - Initialize uniform erase map
2432  * @map:		the erase map of the SPI NOR
2433  * @erase_mask:		bitmask encoding erase types that can erase the entire
2434  *			flash memory
2435  * @flash_size:		the spi nor flash memory size
2436  */
2437 void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
2438 				    u8 erase_mask, u64 flash_size)
2439 {
2440 	/* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */
2441 	map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) |
2442 				     SNOR_LAST_REGION;
2443 	map->uniform_region.size = flash_size;
2444 	map->regions = &map->uniform_region;
2445 	map->uniform_erase_type = erase_mask;
2446 }
2447 
2448 int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
2449 			     const struct sfdp_parameter_header *bfpt_header,
2450 			     const struct sfdp_bfpt *bfpt)
2451 {
2452 	int ret;
2453 
2454 	if (nor->manufacturer && nor->manufacturer->fixups &&
2455 	    nor->manufacturer->fixups->post_bfpt) {
2456 		ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header,
2457 							   bfpt);
2458 		if (ret)
2459 			return ret;
2460 	}
2461 
2462 	if (nor->info->fixups && nor->info->fixups->post_bfpt)
2463 		return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt);
2464 
2465 	return 0;
2466 }
2467 
2468 static int spi_nor_select_read(struct spi_nor *nor,
2469 			       u32 shared_hwcaps)
2470 {
2471 	int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2472 	const struct spi_nor_read_command *read;
2473 
2474 	if (best_match < 0)
2475 		return -EINVAL;
2476 
2477 	cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2478 	if (cmd < 0)
2479 		return -EINVAL;
2480 
2481 	read = &nor->params->reads[cmd];
2482 	nor->read_opcode = read->opcode;
2483 	nor->read_proto = read->proto;
2484 
2485 	/*
2486 	 * In the SPI NOR framework, we don't need to make the difference
2487 	 * between mode clock cycles and wait state clock cycles.
2488 	 * Indeed, the value of the mode clock cycles is used by a QSPI
2489 	 * flash memory to know whether it should enter or leave its 0-4-4
2490 	 * (Continuous Read / XIP) mode.
2491 	 * eXecution In Place is out of the scope of the mtd sub-system.
2492 	 * Hence we choose to merge both mode and wait state clock cycles
2493 	 * into the so called dummy clock cycles.
2494 	 */
2495 	nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2496 	return 0;
2497 }
2498 
2499 static int spi_nor_select_pp(struct spi_nor *nor,
2500 			     u32 shared_hwcaps)
2501 {
2502 	int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2503 	const struct spi_nor_pp_command *pp;
2504 
2505 	if (best_match < 0)
2506 		return -EINVAL;
2507 
2508 	cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2509 	if (cmd < 0)
2510 		return -EINVAL;
2511 
2512 	pp = &nor->params->page_programs[cmd];
2513 	nor->program_opcode = pp->opcode;
2514 	nor->write_proto = pp->proto;
2515 	return 0;
2516 }
2517 
2518 /**
2519  * spi_nor_select_uniform_erase() - select optimum uniform erase type
2520  * @map:		the erase map of the SPI NOR
2521  * @wanted_size:	the erase type size to search for. Contains the value of
2522  *			info->sector_size, the "small sector" size in case
2523  *			CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined or 0 if
2524  *			there is no information about the sector size. The
2525  *			latter is the case if the flash parameters are parsed
2526  *			solely by SFDP, then the largest supported erase type
2527  *			is selected.
2528  *
2529  * Once the optimum uniform sector erase command is found, disable all the
2530  * other.
2531  *
2532  * Return: pointer to erase type on success, NULL otherwise.
2533  */
2534 static const struct spi_nor_erase_type *
2535 spi_nor_select_uniform_erase(struct spi_nor_erase_map *map,
2536 			     const u32 wanted_size)
2537 {
2538 	const struct spi_nor_erase_type *tested_erase, *erase = NULL;
2539 	int i;
2540 	u8 uniform_erase_type = map->uniform_erase_type;
2541 
2542 	for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2543 		if (!(uniform_erase_type & BIT(i)))
2544 			continue;
2545 
2546 		tested_erase = &map->erase_type[i];
2547 
2548 		/* Skip masked erase types. */
2549 		if (!tested_erase->size)
2550 			continue;
2551 
2552 		/*
2553 		 * If the current erase size is the one, stop here:
2554 		 * we have found the right uniform Sector Erase command.
2555 		 */
2556 		if (tested_erase->size == wanted_size) {
2557 			erase = tested_erase;
2558 			break;
2559 		}
2560 
2561 		/*
2562 		 * Otherwise, the current erase size is still a valid candidate.
2563 		 * Select the biggest valid candidate.
2564 		 */
2565 		if (!erase && tested_erase->size)
2566 			erase = tested_erase;
2567 			/* keep iterating to find the wanted_size */
2568 	}
2569 
2570 	if (!erase)
2571 		return NULL;
2572 
2573 	/* Disable all other Sector Erase commands. */
2574 	map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK;
2575 	map->uniform_erase_type |= BIT(erase - map->erase_type);
2576 	return erase;
2577 }
2578 
2579 static int spi_nor_select_erase(struct spi_nor *nor)
2580 {
2581 	struct spi_nor_erase_map *map = &nor->params->erase_map;
2582 	const struct spi_nor_erase_type *erase = NULL;
2583 	struct mtd_info *mtd = &nor->mtd;
2584 	u32 wanted_size = nor->info->sector_size;
2585 	int i;
2586 
2587 	/*
2588 	 * The previous implementation handling Sector Erase commands assumed
2589 	 * that the SPI flash memory has an uniform layout then used only one
2590 	 * of the supported erase sizes for all Sector Erase commands.
2591 	 * So to be backward compatible, the new implementation also tries to
2592 	 * manage the SPI flash memory as uniform with a single erase sector
2593 	 * size, when possible.
2594 	 */
2595 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
2596 	/* prefer "small sector" erase if possible */
2597 	wanted_size = 4096u;
2598 #endif
2599 
2600 	if (spi_nor_has_uniform_erase(nor)) {
2601 		erase = spi_nor_select_uniform_erase(map, wanted_size);
2602 		if (!erase)
2603 			return -EINVAL;
2604 		nor->erase_opcode = erase->opcode;
2605 		mtd->erasesize = erase->size;
2606 		return 0;
2607 	}
2608 
2609 	/*
2610 	 * For non-uniform SPI flash memory, set mtd->erasesize to the
2611 	 * maximum erase sector size. No need to set nor->erase_opcode.
2612 	 */
2613 	for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2614 		if (map->erase_type[i].size) {
2615 			erase = &map->erase_type[i];
2616 			break;
2617 		}
2618 	}
2619 
2620 	if (!erase)
2621 		return -EINVAL;
2622 
2623 	mtd->erasesize = erase->size;
2624 	return 0;
2625 }
2626 
2627 static int spi_nor_default_setup(struct spi_nor *nor,
2628 				 const struct spi_nor_hwcaps *hwcaps)
2629 {
2630 	struct spi_nor_flash_parameter *params = nor->params;
2631 	u32 ignored_mask, shared_mask;
2632 	int err;
2633 
2634 	/*
2635 	 * Keep only the hardware capabilities supported by both the SPI
2636 	 * controller and the SPI flash memory.
2637 	 */
2638 	shared_mask = hwcaps->mask & params->hwcaps.mask;
2639 
2640 	if (nor->spimem) {
2641 		/*
2642 		 * When called from spi_nor_probe(), all caps are set and we
2643 		 * need to discard some of them based on what the SPI
2644 		 * controller actually supports (using spi_mem_supports_op()).
2645 		 */
2646 		spi_nor_spimem_adjust_hwcaps(nor, &shared_mask);
2647 	} else {
2648 		/*
2649 		 * SPI n-n-n protocols are not supported when the SPI
2650 		 * controller directly implements the spi_nor interface.
2651 		 * Yet another reason to switch to spi-mem.
2652 		 */
2653 		ignored_mask = SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR;
2654 		if (shared_mask & ignored_mask) {
2655 			dev_dbg(nor->dev,
2656 				"SPI n-n-n protocols are not supported.\n");
2657 			shared_mask &= ~ignored_mask;
2658 		}
2659 	}
2660 
2661 	/* Select the (Fast) Read command. */
2662 	err = spi_nor_select_read(nor, shared_mask);
2663 	if (err) {
2664 		dev_dbg(nor->dev,
2665 			"can't select read settings supported by both the SPI controller and memory.\n");
2666 		return err;
2667 	}
2668 
2669 	/* Select the Page Program command. */
2670 	err = spi_nor_select_pp(nor, shared_mask);
2671 	if (err) {
2672 		dev_dbg(nor->dev,
2673 			"can't select write settings supported by both the SPI controller and memory.\n");
2674 		return err;
2675 	}
2676 
2677 	/* Select the Sector Erase command. */
2678 	err = spi_nor_select_erase(nor);
2679 	if (err) {
2680 		dev_dbg(nor->dev,
2681 			"can't select erase settings supported by both the SPI controller and memory.\n");
2682 		return err;
2683 	}
2684 
2685 	return 0;
2686 }
2687 
2688 static int spi_nor_set_addr_nbytes(struct spi_nor *nor)
2689 {
2690 	if (nor->params->addr_nbytes) {
2691 		nor->addr_nbytes = nor->params->addr_nbytes;
2692 	} else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) {
2693 		/*
2694 		 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So
2695 		 * in this protocol an odd addr_nbytes cannot be used because
2696 		 * then the address phase would only span a cycle and a half.
2697 		 * Half a cycle would be left over. We would then have to start
2698 		 * the dummy phase in the middle of a cycle and so too the data
2699 		 * phase, and we will end the transaction with half a cycle left
2700 		 * over.
2701 		 *
2702 		 * Force all 8D-8D-8D flashes to use an addr_nbytes of 4 to
2703 		 * avoid this situation.
2704 		 */
2705 		nor->addr_nbytes = 4;
2706 	} else if (nor->info->addr_nbytes) {
2707 		nor->addr_nbytes = nor->info->addr_nbytes;
2708 	} else {
2709 		nor->addr_nbytes = 3;
2710 	}
2711 
2712 	if (nor->addr_nbytes == 3 && nor->params->size > 0x1000000) {
2713 		/* enable 4-byte addressing if the device exceeds 16MiB */
2714 		nor->addr_nbytes = 4;
2715 	}
2716 
2717 	if (nor->addr_nbytes > SPI_NOR_MAX_ADDR_NBYTES) {
2718 		dev_dbg(nor->dev, "The number of address bytes is too large: %u\n",
2719 			nor->addr_nbytes);
2720 		return -EINVAL;
2721 	}
2722 
2723 	/* Set 4byte opcodes when possible. */
2724 	if (nor->addr_nbytes == 4 && nor->flags & SNOR_F_4B_OPCODES &&
2725 	    !(nor->flags & SNOR_F_HAS_4BAIT))
2726 		spi_nor_set_4byte_opcodes(nor);
2727 
2728 	return 0;
2729 }
2730 
2731 static int spi_nor_setup(struct spi_nor *nor,
2732 			 const struct spi_nor_hwcaps *hwcaps)
2733 {
2734 	int ret;
2735 
2736 	if (nor->params->setup)
2737 		ret = nor->params->setup(nor, hwcaps);
2738 	else
2739 		ret = spi_nor_default_setup(nor, hwcaps);
2740 	if (ret)
2741 		return ret;
2742 
2743 	return spi_nor_set_addr_nbytes(nor);
2744 }
2745 
2746 /**
2747  * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
2748  * settings based on MFR register and ->default_init() hook.
2749  * @nor:	pointer to a 'struct spi_nor'.
2750  */
2751 static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
2752 {
2753 	if (nor->manufacturer && nor->manufacturer->fixups &&
2754 	    nor->manufacturer->fixups->default_init)
2755 		nor->manufacturer->fixups->default_init(nor);
2756 
2757 	if (nor->info->fixups && nor->info->fixups->default_init)
2758 		nor->info->fixups->default_init(nor);
2759 }
2760 
2761 /**
2762  * spi_nor_no_sfdp_init_params() - Initialize the flash's parameters and
2763  * settings based on nor->info->sfdp_flags. This method should be called only by
2764  * flashes that do not define SFDP tables. If the flash supports SFDP but the
2765  * information is wrong and the settings from this function can not be retrieved
2766  * by parsing SFDP, one should instead use the fixup hooks and update the wrong
2767  * bits.
2768  * @nor:	pointer to a 'struct spi_nor'.
2769  */
2770 static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
2771 {
2772 	struct spi_nor_flash_parameter *params = nor->params;
2773 	struct spi_nor_erase_map *map = &params->erase_map;
2774 	const u8 no_sfdp_flags = nor->info->no_sfdp_flags;
2775 	u8 i, erase_mask;
2776 
2777 	if (no_sfdp_flags & SPI_NOR_DUAL_READ) {
2778 		params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2779 		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
2780 					  0, 8, SPINOR_OP_READ_1_1_2,
2781 					  SNOR_PROTO_1_1_2);
2782 	}
2783 
2784 	if (no_sfdp_flags & SPI_NOR_QUAD_READ) {
2785 		params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2786 		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
2787 					  0, 8, SPINOR_OP_READ_1_1_4,
2788 					  SNOR_PROTO_1_1_4);
2789 	}
2790 
2791 	if (no_sfdp_flags & SPI_NOR_OCTAL_READ) {
2792 		params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
2793 		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
2794 					  0, 8, SPINOR_OP_READ_1_1_8,
2795 					  SNOR_PROTO_1_1_8);
2796 	}
2797 
2798 	if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_READ) {
2799 		params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
2800 		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_8_8_8_DTR],
2801 					  0, 20, SPINOR_OP_READ_FAST,
2802 					  SNOR_PROTO_8_8_8_DTR);
2803 	}
2804 
2805 	if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_PP) {
2806 		params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
2807 		/*
2808 		 * Since xSPI Page Program opcode is backward compatible with
2809 		 * Legacy SPI, use Legacy SPI opcode there as well.
2810 		 */
2811 		spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
2812 					SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
2813 	}
2814 
2815 	/*
2816 	 * Sector Erase settings. Sort Erase Types in ascending order, with the
2817 	 * smallest erase size starting at BIT(0).
2818 	 */
2819 	erase_mask = 0;
2820 	i = 0;
2821 	if (no_sfdp_flags & SECT_4K) {
2822 		erase_mask |= BIT(i);
2823 		spi_nor_set_erase_type(&map->erase_type[i], 4096u,
2824 				       SPINOR_OP_BE_4K);
2825 		i++;
2826 	}
2827 	erase_mask |= BIT(i);
2828 	spi_nor_set_erase_type(&map->erase_type[i], nor->info->sector_size,
2829 			       SPINOR_OP_SE);
2830 	spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
2831 }
2832 
2833 /**
2834  * spi_nor_init_flags() - Initialize NOR flags for settings that are not defined
2835  * in the JESD216 SFDP standard, thus can not be retrieved when parsing SFDP.
2836  * @nor:	pointer to a 'struct spi_nor'
2837  */
2838 static void spi_nor_init_flags(struct spi_nor *nor)
2839 {
2840 	struct device_node *np = spi_nor_get_flash_node(nor);
2841 	const u16 flags = nor->info->flags;
2842 
2843 	if (of_property_read_bool(np, "broken-flash-reset"))
2844 		nor->flags |= SNOR_F_BROKEN_RESET;
2845 
2846 	if (flags & SPI_NOR_SWP_IS_VOLATILE)
2847 		nor->flags |= SNOR_F_SWP_IS_VOLATILE;
2848 
2849 	if (flags & SPI_NOR_HAS_LOCK)
2850 		nor->flags |= SNOR_F_HAS_LOCK;
2851 
2852 	if (flags & SPI_NOR_HAS_TB) {
2853 		nor->flags |= SNOR_F_HAS_SR_TB;
2854 		if (flags & SPI_NOR_TB_SR_BIT6)
2855 			nor->flags |= SNOR_F_HAS_SR_TB_BIT6;
2856 	}
2857 
2858 	if (flags & SPI_NOR_4BIT_BP) {
2859 		nor->flags |= SNOR_F_HAS_4BIT_BP;
2860 		if (flags & SPI_NOR_BP3_SR_BIT6)
2861 			nor->flags |= SNOR_F_HAS_SR_BP3_BIT6;
2862 	}
2863 
2864 	if (flags & NO_CHIP_ERASE)
2865 		nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2866 
2867 	if (flags & SPI_NOR_RWW && nor->info->n_banks > 1 &&
2868 	    !nor->controller_ops)
2869 		nor->flags |= SNOR_F_RWW;
2870 }
2871 
2872 /**
2873  * spi_nor_init_fixup_flags() - Initialize NOR flags for settings that can not
2874  * be discovered by SFDP for this particular flash because the SFDP table that
2875  * indicates this support is not defined in the flash. In case the table for
2876  * this support is defined but has wrong values, one should instead use a
2877  * post_sfdp() hook to set the SNOR_F equivalent flag.
2878  * @nor:       pointer to a 'struct spi_nor'
2879  */
2880 static void spi_nor_init_fixup_flags(struct spi_nor *nor)
2881 {
2882 	const u8 fixup_flags = nor->info->fixup_flags;
2883 
2884 	if (fixup_flags & SPI_NOR_4B_OPCODES)
2885 		nor->flags |= SNOR_F_4B_OPCODES;
2886 
2887 	if (fixup_flags & SPI_NOR_IO_MODE_EN_VOLATILE)
2888 		nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE;
2889 }
2890 
2891 /**
2892  * spi_nor_late_init_params() - Late initialization of default flash parameters.
2893  * @nor:	pointer to a 'struct spi_nor'
2894  *
2895  * Used to initialize flash parameters that are not declared in the JESD216
2896  * SFDP standard, or where SFDP tables are not defined at all.
2897  * Will replace the spi_nor_manufacturer_init_params() method.
2898  */
2899 static void spi_nor_late_init_params(struct spi_nor *nor)
2900 {
2901 	struct spi_nor_flash_parameter *params = nor->params;
2902 
2903 	if (nor->manufacturer && nor->manufacturer->fixups &&
2904 	    nor->manufacturer->fixups->late_init)
2905 		nor->manufacturer->fixups->late_init(nor);
2906 
2907 	if (nor->info->fixups && nor->info->fixups->late_init)
2908 		nor->info->fixups->late_init(nor);
2909 
2910 	/* Default method kept for backward compatibility. */
2911 	if (!params->set_4byte_addr_mode)
2912 		params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr;
2913 
2914 	spi_nor_init_flags(nor);
2915 	spi_nor_init_fixup_flags(nor);
2916 
2917 	/*
2918 	 * NOR protection support. When locking_ops are not provided, we pick
2919 	 * the default ones.
2920 	 */
2921 	if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops)
2922 		spi_nor_init_default_locking_ops(nor);
2923 
2924 	nor->params->bank_size = div64_u64(nor->params->size, nor->info->n_banks);
2925 }
2926 
2927 /**
2928  * spi_nor_sfdp_init_params_deprecated() - Deprecated way of initializing flash
2929  * parameters and settings based on JESD216 SFDP standard.
2930  * @nor:	pointer to a 'struct spi_nor'.
2931  *
2932  * The method has a roll-back mechanism: in case the SFDP parsing fails, the
2933  * legacy flash parameters and settings will be restored.
2934  */
2935 static void spi_nor_sfdp_init_params_deprecated(struct spi_nor *nor)
2936 {
2937 	struct spi_nor_flash_parameter sfdp_params;
2938 
2939 	memcpy(&sfdp_params, nor->params, sizeof(sfdp_params));
2940 
2941 	if (spi_nor_parse_sfdp(nor)) {
2942 		memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
2943 		nor->flags &= ~SNOR_F_4B_OPCODES;
2944 	}
2945 }
2946 
2947 /**
2948  * spi_nor_init_params_deprecated() - Deprecated way of initializing flash
2949  * parameters and settings.
2950  * @nor:	pointer to a 'struct spi_nor'.
2951  *
2952  * The method assumes that flash doesn't support SFDP so it initializes flash
2953  * parameters in spi_nor_no_sfdp_init_params() which later on can be overwritten
2954  * when parsing SFDP, if supported.
2955  */
2956 static void spi_nor_init_params_deprecated(struct spi_nor *nor)
2957 {
2958 	spi_nor_no_sfdp_init_params(nor);
2959 
2960 	spi_nor_manufacturer_init_params(nor);
2961 
2962 	if (nor->info->no_sfdp_flags & (SPI_NOR_DUAL_READ |
2963 					SPI_NOR_QUAD_READ |
2964 					SPI_NOR_OCTAL_READ |
2965 					SPI_NOR_OCTAL_DTR_READ))
2966 		spi_nor_sfdp_init_params_deprecated(nor);
2967 }
2968 
2969 /**
2970  * spi_nor_init_default_params() - Default initialization of flash parameters
2971  * and settings. Done for all flashes, regardless is they define SFDP tables
2972  * or not.
2973  * @nor:	pointer to a 'struct spi_nor'.
2974  */
2975 static void spi_nor_init_default_params(struct spi_nor *nor)
2976 {
2977 	struct spi_nor_flash_parameter *params = nor->params;
2978 	const struct flash_info *info = nor->info;
2979 	struct device_node *np = spi_nor_get_flash_node(nor);
2980 
2981 	params->quad_enable = spi_nor_sr2_bit1_quad_enable;
2982 	params->otp.org = &info->otp_org;
2983 
2984 	/* Default to 16-bit Write Status (01h) Command */
2985 	nor->flags |= SNOR_F_HAS_16BIT_SR;
2986 
2987 	/* Set SPI NOR sizes. */
2988 	params->writesize = 1;
2989 	params->size = (u64)info->sector_size * info->n_sectors;
2990 	params->page_size = info->page_size;
2991 
2992 	if (!(info->flags & SPI_NOR_NO_FR)) {
2993 		/* Default to Fast Read for DT and non-DT platform devices. */
2994 		params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2995 
2996 		/* Mask out Fast Read if not requested at DT instantiation. */
2997 		if (np && !of_property_read_bool(np, "m25p,fast-read"))
2998 			params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2999 	}
3000 
3001 	/* (Fast) Read settings. */
3002 	params->hwcaps.mask |= SNOR_HWCAPS_READ;
3003 	spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
3004 				  0, 0, SPINOR_OP_READ,
3005 				  SNOR_PROTO_1_1_1);
3006 
3007 	if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
3008 		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
3009 					  0, 8, SPINOR_OP_READ_FAST,
3010 					  SNOR_PROTO_1_1_1);
3011 	/* Page Program settings. */
3012 	params->hwcaps.mask |= SNOR_HWCAPS_PP;
3013 	spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
3014 				SPINOR_OP_PP, SNOR_PROTO_1_1_1);
3015 
3016 	if (info->flags & SPI_NOR_QUAD_PP) {
3017 		params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
3018 		spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_1_1_4],
3019 					SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
3020 	}
3021 }
3022 
3023 /**
3024  * spi_nor_init_params() - Initialize the flash's parameters and settings.
3025  * @nor:	pointer to a 'struct spi_nor'.
3026  *
3027  * The flash parameters and settings are initialized based on a sequence of
3028  * calls that are ordered by priority:
3029  *
3030  * 1/ Default flash parameters initialization. The initializations are done
3031  *    based on nor->info data:
3032  *		spi_nor_info_init_params()
3033  *
3034  * which can be overwritten by:
3035  * 2/ Manufacturer flash parameters initialization. The initializations are
3036  *    done based on MFR register, or when the decisions can not be done solely
3037  *    based on MFR, by using specific flash_info tweeks, ->default_init():
3038  *		spi_nor_manufacturer_init_params()
3039  *
3040  * which can be overwritten by:
3041  * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and
3042  *    should be more accurate that the above.
3043  *		spi_nor_parse_sfdp() or spi_nor_no_sfdp_init_params()
3044  *
3045  *    Please note that there is a ->post_bfpt() fixup hook that can overwrite
3046  *    the flash parameters and settings immediately after parsing the Basic
3047  *    Flash Parameter Table.
3048  *    spi_nor_post_sfdp_fixups() is called after the SFDP tables are parsed.
3049  *    It is used to tweak various flash parameters when information provided
3050  *    by the SFDP tables are wrong.
3051  *
3052  * which can be overwritten by:
3053  * 4/ Late flash parameters initialization, used to initialize flash
3054  * parameters that are not declared in the JESD216 SFDP standard, or where SFDP
3055  * tables are not defined at all.
3056  *		spi_nor_late_init_params()
3057  *
3058  * Return: 0 on success, -errno otherwise.
3059  */
3060 static int spi_nor_init_params(struct spi_nor *nor)
3061 {
3062 	int ret;
3063 
3064 	nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL);
3065 	if (!nor->params)
3066 		return -ENOMEM;
3067 
3068 	spi_nor_init_default_params(nor);
3069 
3070 	if (nor->info->parse_sfdp) {
3071 		ret = spi_nor_parse_sfdp(nor);
3072 		if (ret) {
3073 			dev_err(nor->dev, "BFPT parsing failed. Please consider using SPI_NOR_SKIP_SFDP when declaring the flash\n");
3074 			return ret;
3075 		}
3076 	} else if (nor->info->no_sfdp_flags & SPI_NOR_SKIP_SFDP) {
3077 		spi_nor_no_sfdp_init_params(nor);
3078 	} else {
3079 		spi_nor_init_params_deprecated(nor);
3080 	}
3081 
3082 	spi_nor_late_init_params(nor);
3083 
3084 	return 0;
3085 }
3086 
3087 /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
3088  * @nor:                 pointer to a 'struct spi_nor'
3089  * @enable:              whether to enable or disable Octal DTR
3090  *
3091  * Return: 0 on success, -errno otherwise.
3092  */
3093 static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
3094 {
3095 	int ret;
3096 
3097 	if (!nor->params->octal_dtr_enable)
3098 		return 0;
3099 
3100 	if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR &&
3101 	      nor->write_proto == SNOR_PROTO_8_8_8_DTR))
3102 		return 0;
3103 
3104 	if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE))
3105 		return 0;
3106 
3107 	ret = nor->params->octal_dtr_enable(nor, enable);
3108 	if (ret)
3109 		return ret;
3110 
3111 	if (enable)
3112 		nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
3113 	else
3114 		nor->reg_proto = SNOR_PROTO_1_1_1;
3115 
3116 	return 0;
3117 }
3118 
3119 /**
3120  * spi_nor_quad_enable() - enable Quad I/O if needed.
3121  * @nor:                pointer to a 'struct spi_nor'
3122  *
3123  * Return: 0 on success, -errno otherwise.
3124  */
3125 static int spi_nor_quad_enable(struct spi_nor *nor)
3126 {
3127 	if (!nor->params->quad_enable)
3128 		return 0;
3129 
3130 	if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
3131 	      spi_nor_get_protocol_width(nor->write_proto) == 4))
3132 		return 0;
3133 
3134 	return nor->params->quad_enable(nor);
3135 }
3136 
3137 /**
3138  * spi_nor_set_4byte_addr_mode() - Set address mode.
3139  * @nor:                pointer to a 'struct spi_nor'.
3140  * @enable:             enable/disable 4 byte address mode.
3141  *
3142  * Return: 0 on success, -errno otherwise.
3143  */
3144 int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
3145 {
3146 	struct spi_nor_flash_parameter *params = nor->params;
3147 	int ret;
3148 
3149 	ret = params->set_4byte_addr_mode(nor, enable);
3150 	if (ret && ret != -ENOTSUPP)
3151 		return ret;
3152 
3153 	if (enable) {
3154 		params->addr_nbytes = 4;
3155 		params->addr_mode_nbytes = 4;
3156 	} else {
3157 		params->addr_nbytes = 3;
3158 		params->addr_mode_nbytes = 3;
3159 	}
3160 
3161 	return 0;
3162 }
3163 
3164 static int spi_nor_init(struct spi_nor *nor)
3165 {
3166 	int err;
3167 
3168 	err = spi_nor_octal_dtr_enable(nor, true);
3169 	if (err) {
3170 		dev_dbg(nor->dev, "octal mode not supported\n");
3171 		return err;
3172 	}
3173 
3174 	err = spi_nor_quad_enable(nor);
3175 	if (err) {
3176 		dev_dbg(nor->dev, "quad mode not supported\n");
3177 		return err;
3178 	}
3179 
3180 	/*
3181 	 * Some SPI NOR flashes are write protected by default after a power-on
3182 	 * reset cycle, in order to avoid inadvertent writes during power-up.
3183 	 * Backward compatibility imposes to unlock the entire flash memory
3184 	 * array at power-up by default. Depending on the kernel configuration
3185 	 * (1) do nothing, (2) always unlock the entire flash array or (3)
3186 	 * unlock the entire flash array only when the software write
3187 	 * protection bits are volatile. The latter is indicated by
3188 	 * SNOR_F_SWP_IS_VOLATILE.
3189 	 */
3190 	if (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE) ||
3191 	    (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE) &&
3192 	     nor->flags & SNOR_F_SWP_IS_VOLATILE))
3193 		spi_nor_try_unlock_all(nor);
3194 
3195 	if (nor->addr_nbytes == 4 &&
3196 	    nor->read_proto != SNOR_PROTO_8_8_8_DTR &&
3197 	    !(nor->flags & SNOR_F_4B_OPCODES)) {
3198 		/*
3199 		 * If the RESET# pin isn't hooked up properly, or the system
3200 		 * otherwise doesn't perform a reset command in the boot
3201 		 * sequence, it's impossible to 100% protect against unexpected
3202 		 * reboots (e.g., crashes). Warn the user (or hopefully, system
3203 		 * designer) that this is bad.
3204 		 */
3205 		WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
3206 			  "enabling reset hack; may not recover from unexpected reboots\n");
3207 		err = spi_nor_set_4byte_addr_mode(nor, true);
3208 		if (err)
3209 			return err;
3210 	}
3211 
3212 	return 0;
3213 }
3214 
3215 /**
3216  * spi_nor_soft_reset() - Perform a software reset
3217  * @nor:	pointer to 'struct spi_nor'
3218  *
3219  * Performs a "Soft Reset and Enter Default Protocol Mode" sequence which resets
3220  * the device to its power-on-reset state. This is useful when the software has
3221  * made some changes to device (volatile) registers and needs to reset it before
3222  * shutting down, for example.
3223  *
3224  * Not every flash supports this sequence. The same set of opcodes might be used
3225  * for some other operation on a flash that does not support this. Support for
3226  * this sequence can be discovered via SFDP in the BFPT table.
3227  *
3228  * Return: 0 on success, -errno otherwise.
3229  */
3230 static void spi_nor_soft_reset(struct spi_nor *nor)
3231 {
3232 	struct spi_mem_op op;
3233 	int ret;
3234 
3235 	op = (struct spi_mem_op)SPINOR_SRSTEN_OP;
3236 
3237 	spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
3238 
3239 	ret = spi_mem_exec_op(nor->spimem, &op);
3240 	if (ret) {
3241 		dev_warn(nor->dev, "Software reset failed: %d\n", ret);
3242 		return;
3243 	}
3244 
3245 	op = (struct spi_mem_op)SPINOR_SRST_OP;
3246 
3247 	spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
3248 
3249 	ret = spi_mem_exec_op(nor->spimem, &op);
3250 	if (ret) {
3251 		dev_warn(nor->dev, "Software reset failed: %d\n", ret);
3252 		return;
3253 	}
3254 
3255 	/*
3256 	 * Software Reset is not instant, and the delay varies from flash to
3257 	 * flash. Looking at a few flashes, most range somewhere below 100
3258 	 * microseconds. So, sleep for a range of 200-400 us.
3259 	 */
3260 	usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX);
3261 }
3262 
3263 /* mtd suspend handler */
3264 static int spi_nor_suspend(struct mtd_info *mtd)
3265 {
3266 	struct spi_nor *nor = mtd_to_spi_nor(mtd);
3267 	int ret;
3268 
3269 	/* Disable octal DTR mode if we enabled it. */
3270 	ret = spi_nor_octal_dtr_enable(nor, false);
3271 	if (ret)
3272 		dev_err(nor->dev, "suspend() failed\n");
3273 
3274 	return ret;
3275 }
3276 
3277 /* mtd resume handler */
3278 static void spi_nor_resume(struct mtd_info *mtd)
3279 {
3280 	struct spi_nor *nor = mtd_to_spi_nor(mtd);
3281 	struct device *dev = nor->dev;
3282 	int ret;
3283 
3284 	/* re-initialize the nor chip */
3285 	ret = spi_nor_init(nor);
3286 	if (ret)
3287 		dev_err(dev, "resume() failed\n");
3288 }
3289 
3290 static int spi_nor_get_device(struct mtd_info *mtd)
3291 {
3292 	struct mtd_info *master = mtd_get_master(mtd);
3293 	struct spi_nor *nor = mtd_to_spi_nor(master);
3294 	struct device *dev;
3295 
3296 	if (nor->spimem)
3297 		dev = nor->spimem->spi->controller->dev.parent;
3298 	else
3299 		dev = nor->dev;
3300 
3301 	if (!try_module_get(dev->driver->owner))
3302 		return -ENODEV;
3303 
3304 	return 0;
3305 }
3306 
3307 static void spi_nor_put_device(struct mtd_info *mtd)
3308 {
3309 	struct mtd_info *master = mtd_get_master(mtd);
3310 	struct spi_nor *nor = mtd_to_spi_nor(master);
3311 	struct device *dev;
3312 
3313 	if (nor->spimem)
3314 		dev = nor->spimem->spi->controller->dev.parent;
3315 	else
3316 		dev = nor->dev;
3317 
3318 	module_put(dev->driver->owner);
3319 }
3320 
3321 static void spi_nor_restore(struct spi_nor *nor)
3322 {
3323 	int ret;
3324 
3325 	/* restore the addressing mode */
3326 	if (nor->addr_nbytes == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
3327 	    nor->flags & SNOR_F_BROKEN_RESET) {
3328 		ret = spi_nor_set_4byte_addr_mode(nor, false);
3329 		if (ret)
3330 			/*
3331 			 * Do not stop the execution in the hope that the flash
3332 			 * will default to the 3-byte address mode after the
3333 			 * software reset.
3334 			 */
3335 			dev_err(nor->dev, "Failed to exit 4-byte address mode, err = %d\n", ret);
3336 	}
3337 
3338 	if (nor->flags & SNOR_F_SOFT_RESET)
3339 		spi_nor_soft_reset(nor);
3340 }
3341 
3342 static const struct flash_info *spi_nor_match_name(struct spi_nor *nor,
3343 						   const char *name)
3344 {
3345 	unsigned int i, j;
3346 
3347 	for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
3348 		for (j = 0; j < manufacturers[i]->nparts; j++) {
3349 			if (!strcmp(name, manufacturers[i]->parts[j].name)) {
3350 				nor->manufacturer = manufacturers[i];
3351 				return &manufacturers[i]->parts[j];
3352 			}
3353 		}
3354 	}
3355 
3356 	return NULL;
3357 }
3358 
3359 static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
3360 						       const char *name)
3361 {
3362 	const struct flash_info *info = NULL;
3363 
3364 	if (name)
3365 		info = spi_nor_match_name(nor, name);
3366 	/* Try to auto-detect if chip name wasn't specified or not found */
3367 	if (!info)
3368 		return spi_nor_detect(nor);
3369 
3370 	/*
3371 	 * If caller has specified name of flash model that can normally be
3372 	 * detected using JEDEC, let's verify it.
3373 	 */
3374 	if (name && info->id_len) {
3375 		const struct flash_info *jinfo;
3376 
3377 		jinfo = spi_nor_detect(nor);
3378 		if (IS_ERR(jinfo)) {
3379 			return jinfo;
3380 		} else if (jinfo != info) {
3381 			/*
3382 			 * JEDEC knows better, so overwrite platform ID. We
3383 			 * can't trust partitions any longer, but we'll let
3384 			 * mtd apply them anyway, since some partitions may be
3385 			 * marked read-only, and we don't want to loose that
3386 			 * information, even if it's not 100% accurate.
3387 			 */
3388 			dev_warn(nor->dev, "found %s, expected %s\n",
3389 				 jinfo->name, info->name);
3390 			info = jinfo;
3391 		}
3392 	}
3393 
3394 	return info;
3395 }
3396 
3397 static void spi_nor_set_mtd_info(struct spi_nor *nor)
3398 {
3399 	struct mtd_info *mtd = &nor->mtd;
3400 	struct device *dev = nor->dev;
3401 
3402 	spi_nor_set_mtd_locking_ops(nor);
3403 	spi_nor_set_mtd_otp_ops(nor);
3404 
3405 	mtd->dev.parent = dev;
3406 	if (!mtd->name)
3407 		mtd->name = dev_name(dev);
3408 	mtd->type = MTD_NORFLASH;
3409 	mtd->flags = MTD_CAP_NORFLASH;
3410 	/* Unset BIT_WRITEABLE to enable JFFS2 write buffer for ECC'd NOR */
3411 	if (nor->flags & SNOR_F_ECC)
3412 		mtd->flags &= ~MTD_BIT_WRITEABLE;
3413 	if (nor->info->flags & SPI_NOR_NO_ERASE)
3414 		mtd->flags |= MTD_NO_ERASE;
3415 	else
3416 		mtd->_erase = spi_nor_erase;
3417 	mtd->writesize = nor->params->writesize;
3418 	mtd->writebufsize = nor->params->page_size;
3419 	mtd->size = nor->params->size;
3420 	mtd->_read = spi_nor_read;
3421 	/* Might be already set by some SST flashes. */
3422 	if (!mtd->_write)
3423 		mtd->_write = spi_nor_write;
3424 	mtd->_suspend = spi_nor_suspend;
3425 	mtd->_resume = spi_nor_resume;
3426 	mtd->_get_device = spi_nor_get_device;
3427 	mtd->_put_device = spi_nor_put_device;
3428 }
3429 
3430 static int spi_nor_hw_reset(struct spi_nor *nor)
3431 {
3432 	struct gpio_desc *reset;
3433 
3434 	reset = devm_gpiod_get_optional(nor->dev, "reset", GPIOD_OUT_LOW);
3435 	if (IS_ERR_OR_NULL(reset))
3436 		return PTR_ERR_OR_ZERO(reset);
3437 
3438 	/*
3439 	 * Experimental delay values by looking at different flash device
3440 	 * vendors datasheets.
3441 	 */
3442 	usleep_range(1, 5);
3443 	gpiod_set_value_cansleep(reset, 1);
3444 	usleep_range(100, 150);
3445 	gpiod_set_value_cansleep(reset, 0);
3446 	usleep_range(1000, 1200);
3447 
3448 	return 0;
3449 }
3450 
3451 int spi_nor_scan(struct spi_nor *nor, const char *name,
3452 		 const struct spi_nor_hwcaps *hwcaps)
3453 {
3454 	const struct flash_info *info;
3455 	struct device *dev = nor->dev;
3456 	struct mtd_info *mtd = &nor->mtd;
3457 	int ret;
3458 	int i;
3459 
3460 	ret = spi_nor_check(nor);
3461 	if (ret)
3462 		return ret;
3463 
3464 	/* Reset SPI protocol for all commands. */
3465 	nor->reg_proto = SNOR_PROTO_1_1_1;
3466 	nor->read_proto = SNOR_PROTO_1_1_1;
3467 	nor->write_proto = SNOR_PROTO_1_1_1;
3468 
3469 	/*
3470 	 * We need the bounce buffer early to read/write registers when going
3471 	 * through the spi-mem layer (buffers have to be DMA-able).
3472 	 * For spi-mem drivers, we'll reallocate a new buffer if
3473 	 * nor->params->page_size turns out to be greater than PAGE_SIZE (which
3474 	 * shouldn't happen before long since NOR pages are usually less
3475 	 * than 1KB) after spi_nor_scan() returns.
3476 	 */
3477 	nor->bouncebuf_size = PAGE_SIZE;
3478 	nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size,
3479 				      GFP_KERNEL);
3480 	if (!nor->bouncebuf)
3481 		return -ENOMEM;
3482 
3483 	ret = spi_nor_hw_reset(nor);
3484 	if (ret)
3485 		return ret;
3486 
3487 	info = spi_nor_get_flash_info(nor, name);
3488 	if (IS_ERR(info))
3489 		return PTR_ERR(info);
3490 
3491 	nor->info = info;
3492 
3493 	mutex_init(&nor->lock);
3494 
3495 	/* Init flash parameters based on flash_info struct and SFDP */
3496 	ret = spi_nor_init_params(nor);
3497 	if (ret)
3498 		return ret;
3499 
3500 	if (spi_nor_use_parallel_locking(nor))
3501 		init_waitqueue_head(&nor->rww.wait);
3502 
3503 	/*
3504 	 * Configure the SPI memory:
3505 	 * - select op codes for (Fast) Read, Page Program and Sector Erase.
3506 	 * - set the number of dummy cycles (mode cycles + wait states).
3507 	 * - set the SPI protocols for register and memory accesses.
3508 	 * - set the number of address bytes.
3509 	 */
3510 	ret = spi_nor_setup(nor, hwcaps);
3511 	if (ret)
3512 		return ret;
3513 
3514 	/* Send all the required SPI flash commands to initialize device */
3515 	ret = spi_nor_init(nor);
3516 	if (ret)
3517 		return ret;
3518 
3519 	/* No mtd_info fields should be used up to this point. */
3520 	spi_nor_set_mtd_info(nor);
3521 
3522 	dev_info(dev, "%s (%lld Kbytes)\n", info->name,
3523 			(long long)mtd->size >> 10);
3524 
3525 	dev_dbg(dev,
3526 		"mtd .name = %s, .size = 0x%llx (%lldMiB), "
3527 		".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
3528 		mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
3529 		mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
3530 
3531 	if (mtd->numeraseregions)
3532 		for (i = 0; i < mtd->numeraseregions; i++)
3533 			dev_dbg(dev,
3534 				"mtd.eraseregions[%d] = { .offset = 0x%llx, "
3535 				".erasesize = 0x%.8x (%uKiB), "
3536 				".numblocks = %d }\n",
3537 				i, (long long)mtd->eraseregions[i].offset,
3538 				mtd->eraseregions[i].erasesize,
3539 				mtd->eraseregions[i].erasesize / 1024,
3540 				mtd->eraseregions[i].numblocks);
3541 	return 0;
3542 }
3543 EXPORT_SYMBOL_GPL(spi_nor_scan);
3544 
3545 static int spi_nor_create_read_dirmap(struct spi_nor *nor)
3546 {
3547 	struct spi_mem_dirmap_info info = {
3548 		.op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
3549 				      SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
3550 				      SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
3551 				      SPI_MEM_OP_DATA_IN(0, NULL, 0)),
3552 		.offset = 0,
3553 		.length = nor->params->size,
3554 	};
3555 	struct spi_mem_op *op = &info.op_tmpl;
3556 
3557 	spi_nor_spimem_setup_op(nor, op, nor->read_proto);
3558 
3559 	/* convert the dummy cycles to the number of bytes */
3560 	op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8;
3561 	if (spi_nor_protocol_is_dtr(nor->read_proto))
3562 		op->dummy.nbytes *= 2;
3563 
3564 	/*
3565 	 * Since spi_nor_spimem_setup_op() only sets buswidth when the number
3566 	 * of data bytes is non-zero, the data buswidth won't be set here. So,
3567 	 * do it explicitly.
3568 	 */
3569 	op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
3570 
3571 	nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3572 						       &info);
3573 	return PTR_ERR_OR_ZERO(nor->dirmap.rdesc);
3574 }
3575 
3576 static int spi_nor_create_write_dirmap(struct spi_nor *nor)
3577 {
3578 	struct spi_mem_dirmap_info info = {
3579 		.op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
3580 				      SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
3581 				      SPI_MEM_OP_NO_DUMMY,
3582 				      SPI_MEM_OP_DATA_OUT(0, NULL, 0)),
3583 		.offset = 0,
3584 		.length = nor->params->size,
3585 	};
3586 	struct spi_mem_op *op = &info.op_tmpl;
3587 
3588 	if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
3589 		op->addr.nbytes = 0;
3590 
3591 	spi_nor_spimem_setup_op(nor, op, nor->write_proto);
3592 
3593 	/*
3594 	 * Since spi_nor_spimem_setup_op() only sets buswidth when the number
3595 	 * of data bytes is non-zero, the data buswidth won't be set here. So,
3596 	 * do it explicitly.
3597 	 */
3598 	op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
3599 
3600 	nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3601 						       &info);
3602 	return PTR_ERR_OR_ZERO(nor->dirmap.wdesc);
3603 }
3604 
3605 static int spi_nor_probe(struct spi_mem *spimem)
3606 {
3607 	struct spi_device *spi = spimem->spi;
3608 	struct flash_platform_data *data = dev_get_platdata(&spi->dev);
3609 	struct spi_nor *nor;
3610 	/*
3611 	 * Enable all caps by default. The core will mask them after
3612 	 * checking what's really supported using spi_mem_supports_op().
3613 	 */
3614 	const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL };
3615 	char *flash_name;
3616 	int ret;
3617 
3618 	nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL);
3619 	if (!nor)
3620 		return -ENOMEM;
3621 
3622 	nor->spimem = spimem;
3623 	nor->dev = &spi->dev;
3624 	spi_nor_set_flash_node(nor, spi->dev.of_node);
3625 
3626 	spi_mem_set_drvdata(spimem, nor);
3627 
3628 	if (data && data->name)
3629 		nor->mtd.name = data->name;
3630 
3631 	if (!nor->mtd.name)
3632 		nor->mtd.name = spi_mem_get_name(spimem);
3633 
3634 	/*
3635 	 * For some (historical?) reason many platforms provide two different
3636 	 * names in flash_platform_data: "name" and "type". Quite often name is
3637 	 * set to "m25p80" and then "type" provides a real chip name.
3638 	 * If that's the case, respect "type" and ignore a "name".
3639 	 */
3640 	if (data && data->type)
3641 		flash_name = data->type;
3642 	else if (!strcmp(spi->modalias, "spi-nor"))
3643 		flash_name = NULL; /* auto-detect */
3644 	else
3645 		flash_name = spi->modalias;
3646 
3647 	ret = spi_nor_scan(nor, flash_name, &hwcaps);
3648 	if (ret)
3649 		return ret;
3650 
3651 	spi_nor_debugfs_register(nor);
3652 
3653 	/*
3654 	 * None of the existing parts have > 512B pages, but let's play safe
3655 	 * and add this logic so that if anyone ever adds support for such
3656 	 * a NOR we don't end up with buffer overflows.
3657 	 */
3658 	if (nor->params->page_size > PAGE_SIZE) {
3659 		nor->bouncebuf_size = nor->params->page_size;
3660 		devm_kfree(nor->dev, nor->bouncebuf);
3661 		nor->bouncebuf = devm_kmalloc(nor->dev,
3662 					      nor->bouncebuf_size,
3663 					      GFP_KERNEL);
3664 		if (!nor->bouncebuf)
3665 			return -ENOMEM;
3666 	}
3667 
3668 	ret = spi_nor_create_read_dirmap(nor);
3669 	if (ret)
3670 		return ret;
3671 
3672 	ret = spi_nor_create_write_dirmap(nor);
3673 	if (ret)
3674 		return ret;
3675 
3676 	return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
3677 				   data ? data->nr_parts : 0);
3678 }
3679 
3680 static int spi_nor_remove(struct spi_mem *spimem)
3681 {
3682 	struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3683 
3684 	spi_nor_restore(nor);
3685 
3686 	/* Clean up MTD stuff. */
3687 	return mtd_device_unregister(&nor->mtd);
3688 }
3689 
3690 static void spi_nor_shutdown(struct spi_mem *spimem)
3691 {
3692 	struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3693 
3694 	spi_nor_restore(nor);
3695 }
3696 
3697 /*
3698  * Do NOT add to this array without reading the following:
3699  *
3700  * Historically, many flash devices are bound to this driver by their name. But
3701  * since most of these flash are compatible to some extent, and their
3702  * differences can often be differentiated by the JEDEC read-ID command, we
3703  * encourage new users to add support to the spi-nor library, and simply bind
3704  * against a generic string here (e.g., "jedec,spi-nor").
3705  *
3706  * Many flash names are kept here in this list to keep them available
3707  * as module aliases for existing platforms.
3708  */
3709 static const struct spi_device_id spi_nor_dev_ids[] = {
3710 	/*
3711 	 * Allow non-DT platform devices to bind to the "spi-nor" modalias, and
3712 	 * hack around the fact that the SPI core does not provide uevent
3713 	 * matching for .of_match_table
3714 	 */
3715 	{"spi-nor"},
3716 
3717 	/*
3718 	 * Entries not used in DTs that should be safe to drop after replacing
3719 	 * them with "spi-nor" in platform data.
3720 	 */
3721 	{"s25sl064a"},	{"w25x16"},	{"m25p10"},	{"m25px64"},
3722 
3723 	/*
3724 	 * Entries that were used in DTs without "jedec,spi-nor" fallback and
3725 	 * should be kept for backward compatibility.
3726 	 */
3727 	{"at25df321a"},	{"at25df641"},	{"at26df081a"},
3728 	{"mx25l4005a"},	{"mx25l1606e"},	{"mx25l6405d"},	{"mx25l12805d"},
3729 	{"mx25l25635e"},{"mx66l51235l"},
3730 	{"n25q064"},	{"n25q128a11"},	{"n25q128a13"},	{"n25q512a"},
3731 	{"s25fl256s1"},	{"s25fl512s"},	{"s25sl12801"},	{"s25fl008k"},
3732 	{"s25fl064k"},
3733 	{"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},
3734 	{"m25p40"},	{"m25p80"},	{"m25p16"},	{"m25p32"},
3735 	{"m25p64"},	{"m25p128"},
3736 	{"w25x80"},	{"w25x32"},	{"w25q32"},	{"w25q32dw"},
3737 	{"w25q80bl"},	{"w25q128"},	{"w25q256"},
3738 
3739 	/* Flashes that can't be detected using JEDEC */
3740 	{"m25p05-nonjedec"},	{"m25p10-nonjedec"},	{"m25p20-nonjedec"},
3741 	{"m25p40-nonjedec"},	{"m25p80-nonjedec"},	{"m25p16-nonjedec"},
3742 	{"m25p32-nonjedec"},	{"m25p64-nonjedec"},	{"m25p128-nonjedec"},
3743 
3744 	/* Everspin MRAMs (non-JEDEC) */
3745 	{ "mr25h128" }, /* 128 Kib, 40 MHz */
3746 	{ "mr25h256" }, /* 256 Kib, 40 MHz */
3747 	{ "mr25h10" },  /*   1 Mib, 40 MHz */
3748 	{ "mr25h40" },  /*   4 Mib, 40 MHz */
3749 
3750 	{ },
3751 };
3752 MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids);
3753 
3754 static const struct of_device_id spi_nor_of_table[] = {
3755 	/*
3756 	 * Generic compatibility for SPI NOR that can be identified by the
3757 	 * JEDEC READ ID opcode (0x9F). Use this, if possible.
3758 	 */
3759 	{ .compatible = "jedec,spi-nor" },
3760 	{ /* sentinel */ },
3761 };
3762 MODULE_DEVICE_TABLE(of, spi_nor_of_table);
3763 
3764 /*
3765  * REVISIT: many of these chips have deep power-down modes, which
3766  * should clearly be entered on suspend() to minimize power use.
3767  * And also when they're otherwise idle...
3768  */
3769 static struct spi_mem_driver spi_nor_driver = {
3770 	.spidrv = {
3771 		.driver = {
3772 			.name = "spi-nor",
3773 			.of_match_table = spi_nor_of_table,
3774 			.dev_groups = spi_nor_sysfs_groups,
3775 		},
3776 		.id_table = spi_nor_dev_ids,
3777 	},
3778 	.probe = spi_nor_probe,
3779 	.remove = spi_nor_remove,
3780 	.shutdown = spi_nor_shutdown,
3781 };
3782 
3783 static int __init spi_nor_module_init(void)
3784 {
3785 	return spi_mem_driver_register(&spi_nor_driver);
3786 }
3787 module_init(spi_nor_module_init);
3788 
3789 static void __exit spi_nor_module_exit(void)
3790 {
3791 	spi_mem_driver_unregister(&spi_nor_driver);
3792 	spi_nor_debugfs_shutdown();
3793 }
3794 module_exit(spi_nor_module_exit);
3795 
3796 MODULE_LICENSE("GPL v2");
3797 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
3798 MODULE_AUTHOR("Mike Lavender");
3799 MODULE_DESCRIPTION("framework for SPI NOR");
3800