1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,gcc-sm8350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,sm8350.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19#include <dt-bindings/thermal/thermal.h> 20#include <dt-bindings/interconnect/qcom,sm8350.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <38400000>; 35 clock-output-names = "xo_board"; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 clock-frequency = <32000>; 41 #clock-cells = <0>; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 CPU0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "qcom,kryo685"; 52 reg = <0x0 0x0>; 53 clocks = <&cpufreq_hw 0>; 54 enable-method = "psci"; 55 next-level-cache = <&L2_0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 power-domains = <&CPU_PD0>; 58 power-domain-names = "psci"; 59 #cooling-cells = <2>; 60 L2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 next-level-cache = <&L3_0>; 64 L3_0: l3-cache { 65 compatible = "cache"; 66 cache-level = <3>; 67 }; 68 }; 69 }; 70 71 CPU1: cpu@100 { 72 device_type = "cpu"; 73 compatible = "qcom,kryo685"; 74 reg = <0x0 0x100>; 75 clocks = <&cpufreq_hw 0>; 76 enable-method = "psci"; 77 next-level-cache = <&L2_100>; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 power-domains = <&CPU_PD1>; 80 power-domain-names = "psci"; 81 #cooling-cells = <2>; 82 L2_100: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 next-level-cache = <&L3_0>; 86 }; 87 }; 88 89 CPU2: cpu@200 { 90 device_type = "cpu"; 91 compatible = "qcom,kryo685"; 92 reg = <0x0 0x200>; 93 clocks = <&cpufreq_hw 0>; 94 enable-method = "psci"; 95 next-level-cache = <&L2_200>; 96 qcom,freq-domain = <&cpufreq_hw 0>; 97 power-domains = <&CPU_PD2>; 98 power-domain-names = "psci"; 99 #cooling-cells = <2>; 100 L2_200: l2-cache { 101 compatible = "cache"; 102 cache-level = <2>; 103 next-level-cache = <&L3_0>; 104 }; 105 }; 106 107 CPU3: cpu@300 { 108 device_type = "cpu"; 109 compatible = "qcom,kryo685"; 110 reg = <0x0 0x300>; 111 clocks = <&cpufreq_hw 0>; 112 enable-method = "psci"; 113 next-level-cache = <&L2_300>; 114 qcom,freq-domain = <&cpufreq_hw 0>; 115 power-domains = <&CPU_PD3>; 116 power-domain-names = "psci"; 117 #cooling-cells = <2>; 118 L2_300: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 next-level-cache = <&L3_0>; 122 }; 123 }; 124 125 CPU4: cpu@400 { 126 device_type = "cpu"; 127 compatible = "qcom,kryo685"; 128 reg = <0x0 0x400>; 129 clocks = <&cpufreq_hw 1>; 130 enable-method = "psci"; 131 next-level-cache = <&L2_400>; 132 qcom,freq-domain = <&cpufreq_hw 1>; 133 power-domains = <&CPU_PD4>; 134 power-domain-names = "psci"; 135 #cooling-cells = <2>; 136 L2_400: l2-cache { 137 compatible = "cache"; 138 cache-level = <2>; 139 next-level-cache = <&L3_0>; 140 }; 141 }; 142 143 CPU5: cpu@500 { 144 device_type = "cpu"; 145 compatible = "qcom,kryo685"; 146 reg = <0x0 0x500>; 147 clocks = <&cpufreq_hw 1>; 148 enable-method = "psci"; 149 next-level-cache = <&L2_500>; 150 qcom,freq-domain = <&cpufreq_hw 1>; 151 power-domains = <&CPU_PD5>; 152 power-domain-names = "psci"; 153 #cooling-cells = <2>; 154 L2_500: l2-cache { 155 compatible = "cache"; 156 cache-level = <2>; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 161 CPU6: cpu@600 { 162 device_type = "cpu"; 163 compatible = "qcom,kryo685"; 164 reg = <0x0 0x600>; 165 clocks = <&cpufreq_hw 1>; 166 enable-method = "psci"; 167 next-level-cache = <&L2_600>; 168 qcom,freq-domain = <&cpufreq_hw 1>; 169 power-domains = <&CPU_PD6>; 170 power-domain-names = "psci"; 171 #cooling-cells = <2>; 172 L2_600: l2-cache { 173 compatible = "cache"; 174 cache-level = <2>; 175 next-level-cache = <&L3_0>; 176 }; 177 }; 178 179 CPU7: cpu@700 { 180 device_type = "cpu"; 181 compatible = "qcom,kryo685"; 182 reg = <0x0 0x700>; 183 clocks = <&cpufreq_hw 2>; 184 enable-method = "psci"; 185 next-level-cache = <&L2_700>; 186 qcom,freq-domain = <&cpufreq_hw 2>; 187 power-domains = <&CPU_PD7>; 188 power-domain-names = "psci"; 189 #cooling-cells = <2>; 190 L2_700: l2-cache { 191 compatible = "cache"; 192 cache-level = <2>; 193 next-level-cache = <&L3_0>; 194 }; 195 }; 196 197 cpu-map { 198 cluster0 { 199 core0 { 200 cpu = <&CPU0>; 201 }; 202 203 core1 { 204 cpu = <&CPU1>; 205 }; 206 207 core2 { 208 cpu = <&CPU2>; 209 }; 210 211 core3 { 212 cpu = <&CPU3>; 213 }; 214 215 core4 { 216 cpu = <&CPU4>; 217 }; 218 219 core5 { 220 cpu = <&CPU5>; 221 }; 222 223 core6 { 224 cpu = <&CPU6>; 225 }; 226 227 core7 { 228 cpu = <&CPU7>; 229 }; 230 }; 231 }; 232 233 idle-states { 234 entry-method = "psci"; 235 236 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 237 compatible = "arm,idle-state"; 238 idle-state-name = "silver-rail-power-collapse"; 239 arm,psci-suspend-param = <0x40000004>; 240 entry-latency-us = <355>; 241 exit-latency-us = <909>; 242 min-residency-us = <3934>; 243 local-timer-stop; 244 }; 245 246 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 247 compatible = "arm,idle-state"; 248 idle-state-name = "gold-rail-power-collapse"; 249 arm,psci-suspend-param = <0x40000004>; 250 entry-latency-us = <241>; 251 exit-latency-us = <1461>; 252 min-residency-us = <4488>; 253 local-timer-stop; 254 }; 255 }; 256 257 domain-idle-states { 258 CLUSTER_SLEEP_0: cluster-sleep-0 { 259 compatible = "domain-idle-state"; 260 arm,psci-suspend-param = <0x4100c344>; 261 entry-latency-us = <3263>; 262 exit-latency-us = <6562>; 263 min-residency-us = <9987>; 264 }; 265 }; 266 }; 267 268 firmware { 269 scm: scm { 270 compatible = "qcom,scm-sm8350", "qcom,scm"; 271 #reset-cells = <1>; 272 }; 273 }; 274 275 memory@80000000 { 276 device_type = "memory"; 277 /* We expect the bootloader to fill in the size */ 278 reg = <0x0 0x80000000 0x0 0x0>; 279 }; 280 281 pmu { 282 compatible = "arm,armv8-pmuv3"; 283 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 284 }; 285 286 psci { 287 compatible = "arm,psci-1.0"; 288 method = "smc"; 289 290 CPU_PD0: power-domain-cpu0 { 291 #power-domain-cells = <0>; 292 power-domains = <&CLUSTER_PD>; 293 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 294 }; 295 296 CPU_PD1: power-domain-cpu1 { 297 #power-domain-cells = <0>; 298 power-domains = <&CLUSTER_PD>; 299 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 300 }; 301 302 CPU_PD2: power-domain-cpu2 { 303 #power-domain-cells = <0>; 304 power-domains = <&CLUSTER_PD>; 305 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 306 }; 307 308 CPU_PD3: power-domain-cpu3 { 309 #power-domain-cells = <0>; 310 power-domains = <&CLUSTER_PD>; 311 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 312 }; 313 314 CPU_PD4: power-domain-cpu4 { 315 #power-domain-cells = <0>; 316 power-domains = <&CLUSTER_PD>; 317 domain-idle-states = <&BIG_CPU_SLEEP_0>; 318 }; 319 320 CPU_PD5: power-domain-cpu5 { 321 #power-domain-cells = <0>; 322 power-domains = <&CLUSTER_PD>; 323 domain-idle-states = <&BIG_CPU_SLEEP_0>; 324 }; 325 326 CPU_PD6: power-domain-cpu6 { 327 #power-domain-cells = <0>; 328 power-domains = <&CLUSTER_PD>; 329 domain-idle-states = <&BIG_CPU_SLEEP_0>; 330 }; 331 332 CPU_PD7: power-domain-cpu7 { 333 #power-domain-cells = <0>; 334 power-domains = <&CLUSTER_PD>; 335 domain-idle-states = <&BIG_CPU_SLEEP_0>; 336 }; 337 338 CLUSTER_PD: power-domain-cpu-cluster0 { 339 #power-domain-cells = <0>; 340 domain-idle-states = <&CLUSTER_SLEEP_0>; 341 }; 342 }; 343 344 qup_opp_table_100mhz: opp-table-qup100mhz { 345 compatible = "operating-points-v2"; 346 347 opp-50000000 { 348 opp-hz = /bits/ 64 <50000000>; 349 required-opps = <&rpmhpd_opp_min_svs>; 350 }; 351 352 opp-75000000 { 353 opp-hz = /bits/ 64 <75000000>; 354 required-opps = <&rpmhpd_opp_low_svs>; 355 }; 356 357 opp-100000000 { 358 opp-hz = /bits/ 64 <100000000>; 359 required-opps = <&rpmhpd_opp_svs>; 360 }; 361 }; 362 363 qup_opp_table_120mhz: opp-table-qup120mhz { 364 compatible = "operating-points-v2"; 365 366 opp-50000000 { 367 opp-hz = /bits/ 64 <50000000>; 368 required-opps = <&rpmhpd_opp_min_svs>; 369 }; 370 371 opp-75000000 { 372 opp-hz = /bits/ 64 <75000000>; 373 required-opps = <&rpmhpd_opp_low_svs>; 374 }; 375 376 opp-120000000 { 377 opp-hz = /bits/ 64 <120000000>; 378 required-opps = <&rpmhpd_opp_svs>; 379 }; 380 }; 381 382 reserved_memory: reserved-memory { 383 #address-cells = <2>; 384 #size-cells = <2>; 385 ranges; 386 387 hyp_mem: memory@80000000 { 388 reg = <0x0 0x80000000 0x0 0x600000>; 389 no-map; 390 }; 391 392 xbl_aop_mem: memory@80700000 { 393 no-map; 394 reg = <0x0 0x80700000 0x0 0x160000>; 395 }; 396 397 cmd_db: memory@80860000 { 398 compatible = "qcom,cmd-db"; 399 reg = <0x0 0x80860000 0x0 0x20000>; 400 no-map; 401 }; 402 403 reserved_xbl_uefi_log: memory@80880000 { 404 reg = <0x0 0x80880000 0x0 0x14000>; 405 no-map; 406 }; 407 408 smem@80900000 { 409 compatible = "qcom,smem"; 410 reg = <0x0 0x80900000 0x0 0x200000>; 411 hwlocks = <&tcsr_mutex 3>; 412 no-map; 413 }; 414 415 cpucp_fw_mem: memory@80b00000 { 416 reg = <0x0 0x80b00000 0x0 0x100000>; 417 no-map; 418 }; 419 420 cdsp_secure_heap: memory@80c00000 { 421 reg = <0x0 0x80c00000 0x0 0x4600000>; 422 no-map; 423 }; 424 425 pil_camera_mem: mmeory@85200000 { 426 reg = <0x0 0x85200000 0x0 0x500000>; 427 no-map; 428 }; 429 430 pil_video_mem: memory@85700000 { 431 reg = <0x0 0x85700000 0x0 0x500000>; 432 no-map; 433 }; 434 435 pil_cvp_mem: memory@85c00000 { 436 reg = <0x0 0x85c00000 0x0 0x500000>; 437 no-map; 438 }; 439 440 pil_adsp_mem: memory@86100000 { 441 reg = <0x0 0x86100000 0x0 0x2100000>; 442 no-map; 443 }; 444 445 pil_slpi_mem: memory@88200000 { 446 reg = <0x0 0x88200000 0x0 0x1500000>; 447 no-map; 448 }; 449 450 pil_cdsp_mem: memory@89700000 { 451 reg = <0x0 0x89700000 0x0 0x1e00000>; 452 no-map; 453 }; 454 455 pil_ipa_fw_mem: memory@8b500000 { 456 reg = <0x0 0x8b500000 0x0 0x10000>; 457 no-map; 458 }; 459 460 pil_ipa_gsi_mem: memory@8b510000 { 461 reg = <0x0 0x8b510000 0x0 0xa000>; 462 no-map; 463 }; 464 465 pil_gpu_mem: memory@8b51a000 { 466 reg = <0x0 0x8b51a000 0x0 0x2000>; 467 no-map; 468 }; 469 470 pil_spss_mem: memory@8b600000 { 471 reg = <0x0 0x8b600000 0x0 0x100000>; 472 no-map; 473 }; 474 475 pil_modem_mem: memory@8b800000 { 476 reg = <0x0 0x8b800000 0x0 0x10000000>; 477 no-map; 478 }; 479 480 rmtfs_mem: memory@9b800000 { 481 compatible = "qcom,rmtfs-mem"; 482 reg = <0x0 0x9b800000 0x0 0x280000>; 483 no-map; 484 485 qcom,client-id = <1>; 486 qcom,vmid = <15>; 487 }; 488 489 hyp_reserved_mem: memory@d0000000 { 490 reg = <0x0 0xd0000000 0x0 0x800000>; 491 no-map; 492 }; 493 494 pil_trustedvm_mem: memory@d0800000 { 495 reg = <0x0 0xd0800000 0x0 0x76f7000>; 496 no-map; 497 }; 498 499 qrtr_shbuf: memory@d7ef7000 { 500 reg = <0x0 0xd7ef7000 0x0 0x9000>; 501 no-map; 502 }; 503 504 chan0_shbuf: memory@d7f00000 { 505 reg = <0x0 0xd7f00000 0x0 0x80000>; 506 no-map; 507 }; 508 509 chan1_shbuf: memory@d7f80000 { 510 reg = <0x0 0xd7f80000 0x0 0x80000>; 511 no-map; 512 }; 513 514 removed_mem: memory@d8800000 { 515 reg = <0x0 0xd8800000 0x0 0x6800000>; 516 no-map; 517 }; 518 }; 519 520 smp2p-adsp { 521 compatible = "qcom,smp2p"; 522 qcom,smem = <443>, <429>; 523 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 524 IPCC_MPROC_SIGNAL_SMP2P 525 IRQ_TYPE_EDGE_RISING>; 526 mboxes = <&ipcc IPCC_CLIENT_LPASS 527 IPCC_MPROC_SIGNAL_SMP2P>; 528 529 qcom,local-pid = <0>; 530 qcom,remote-pid = <2>; 531 532 smp2p_adsp_out: master-kernel { 533 qcom,entry-name = "master-kernel"; 534 #qcom,smem-state-cells = <1>; 535 }; 536 537 smp2p_adsp_in: slave-kernel { 538 qcom,entry-name = "slave-kernel"; 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 }; 542 }; 543 544 smp2p-cdsp { 545 compatible = "qcom,smp2p"; 546 qcom,smem = <94>, <432>; 547 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 548 IPCC_MPROC_SIGNAL_SMP2P 549 IRQ_TYPE_EDGE_RISING>; 550 mboxes = <&ipcc IPCC_CLIENT_CDSP 551 IPCC_MPROC_SIGNAL_SMP2P>; 552 553 qcom,local-pid = <0>; 554 qcom,remote-pid = <5>; 555 556 smp2p_cdsp_out: master-kernel { 557 qcom,entry-name = "master-kernel"; 558 #qcom,smem-state-cells = <1>; 559 }; 560 561 smp2p_cdsp_in: slave-kernel { 562 qcom,entry-name = "slave-kernel"; 563 interrupt-controller; 564 #interrupt-cells = <2>; 565 }; 566 }; 567 568 smp2p-modem { 569 compatible = "qcom,smp2p"; 570 qcom,smem = <435>, <428>; 571 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 572 IPCC_MPROC_SIGNAL_SMP2P 573 IRQ_TYPE_EDGE_RISING>; 574 mboxes = <&ipcc IPCC_CLIENT_MPSS 575 IPCC_MPROC_SIGNAL_SMP2P>; 576 577 qcom,local-pid = <0>; 578 qcom,remote-pid = <1>; 579 580 smp2p_modem_out: master-kernel { 581 qcom,entry-name = "master-kernel"; 582 #qcom,smem-state-cells = <1>; 583 }; 584 585 smp2p_modem_in: slave-kernel { 586 qcom,entry-name = "slave-kernel"; 587 interrupt-controller; 588 #interrupt-cells = <2>; 589 }; 590 591 ipa_smp2p_out: ipa-ap-to-modem { 592 qcom,entry-name = "ipa"; 593 #qcom,smem-state-cells = <1>; 594 }; 595 596 ipa_smp2p_in: ipa-modem-to-ap { 597 qcom,entry-name = "ipa"; 598 interrupt-controller; 599 #interrupt-cells = <2>; 600 }; 601 }; 602 603 smp2p-slpi { 604 compatible = "qcom,smp2p"; 605 qcom,smem = <481>, <430>; 606 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 607 IPCC_MPROC_SIGNAL_SMP2P 608 IRQ_TYPE_EDGE_RISING>; 609 mboxes = <&ipcc IPCC_CLIENT_SLPI 610 IPCC_MPROC_SIGNAL_SMP2P>; 611 612 qcom,local-pid = <0>; 613 qcom,remote-pid = <3>; 614 615 smp2p_slpi_out: master-kernel { 616 qcom,entry-name = "master-kernel"; 617 #qcom,smem-state-cells = <1>; 618 }; 619 620 smp2p_slpi_in: slave-kernel { 621 qcom,entry-name = "slave-kernel"; 622 interrupt-controller; 623 #interrupt-cells = <2>; 624 }; 625 }; 626 627 soc: soc@0 { 628 #address-cells = <2>; 629 #size-cells = <2>; 630 ranges = <0 0 0 0 0x10 0>; 631 dma-ranges = <0 0 0 0 0x10 0>; 632 compatible = "simple-bus"; 633 634 gcc: clock-controller@100000 { 635 compatible = "qcom,gcc-sm8350"; 636 reg = <0x0 0x00100000 0x0 0x1f0000>; 637 #clock-cells = <1>; 638 #reset-cells = <1>; 639 #power-domain-cells = <1>; 640 clock-names = "bi_tcxo", 641 "sleep_clk", 642 "pcie_0_pipe_clk", 643 "pcie_1_pipe_clk", 644 "ufs_card_rx_symbol_0_clk", 645 "ufs_card_rx_symbol_1_clk", 646 "ufs_card_tx_symbol_0_clk", 647 "ufs_phy_rx_symbol_0_clk", 648 "ufs_phy_rx_symbol_1_clk", 649 "ufs_phy_tx_symbol_0_clk", 650 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 651 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 652 clocks = <&rpmhcc RPMH_CXO_CLK>, 653 <&sleep_clk>, 654 <&pcie0_phy>, 655 <&pcie1_phy>, 656 <0>, 657 <0>, 658 <0>, 659 <&ufs_mem_phy_lanes 0>, 660 <&ufs_mem_phy_lanes 1>, 661 <&ufs_mem_phy_lanes 2>, 662 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 663 <0>; 664 }; 665 666 ipcc: mailbox@408000 { 667 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 668 reg = <0 0x00408000 0 0x1000>; 669 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 670 interrupt-controller; 671 #interrupt-cells = <3>; 672 #mbox-cells = <2>; 673 }; 674 675 gpi_dma2: dma-controller@800000 { 676 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 677 reg = <0 0x00800000 0 0x60000>; 678 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 690 dma-channels = <12>; 691 dma-channel-mask = <0xff>; 692 iommus = <&apps_smmu 0x5f6 0x0>; 693 #dma-cells = <3>; 694 status = "disabled"; 695 }; 696 697 qupv3_id_2: geniqup@8c0000 { 698 compatible = "qcom,geni-se-qup"; 699 reg = <0x0 0x008c0000 0x0 0x6000>; 700 clock-names = "m-ahb", "s-ahb"; 701 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 702 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 703 iommus = <&apps_smmu 0x5e3 0x0>; 704 #address-cells = <2>; 705 #size-cells = <2>; 706 ranges; 707 status = "disabled"; 708 709 i2c14: i2c@880000 { 710 compatible = "qcom,geni-i2c"; 711 reg = <0 0x00880000 0 0x4000>; 712 clock-names = "se"; 713 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 714 pinctrl-names = "default"; 715 pinctrl-0 = <&qup_i2c14_default>; 716 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 717 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 718 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 719 dma-names = "tx", "rx"; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 status = "disabled"; 723 }; 724 725 spi14: spi@880000 { 726 compatible = "qcom,geni-spi"; 727 reg = <0 0x00880000 0 0x4000>; 728 clock-names = "se"; 729 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 730 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 731 power-domains = <&rpmhpd SM8350_CX>; 732 operating-points-v2 = <&qup_opp_table_120mhz>; 733 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 734 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 735 dma-names = "tx", "rx"; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 status = "disabled"; 739 }; 740 741 i2c15: i2c@884000 { 742 compatible = "qcom,geni-i2c"; 743 reg = <0 0x00884000 0 0x4000>; 744 clock-names = "se"; 745 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 746 pinctrl-names = "default"; 747 pinctrl-0 = <&qup_i2c15_default>; 748 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 749 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 750 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 751 dma-names = "tx", "rx"; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 status = "disabled"; 755 }; 756 757 spi15: spi@884000 { 758 compatible = "qcom,geni-spi"; 759 reg = <0 0x00884000 0 0x4000>; 760 clock-names = "se"; 761 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 762 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 763 power-domains = <&rpmhpd SM8350_CX>; 764 operating-points-v2 = <&qup_opp_table_120mhz>; 765 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 766 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 767 dma-names = "tx", "rx"; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 status = "disabled"; 771 }; 772 773 i2c16: i2c@888000 { 774 compatible = "qcom,geni-i2c"; 775 reg = <0 0x00888000 0 0x4000>; 776 clock-names = "se"; 777 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 778 pinctrl-names = "default"; 779 pinctrl-0 = <&qup_i2c16_default>; 780 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 781 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 782 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 783 dma-names = "tx", "rx"; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 status = "disabled"; 787 }; 788 789 spi16: spi@888000 { 790 compatible = "qcom,geni-spi"; 791 reg = <0 0x00888000 0 0x4000>; 792 clock-names = "se"; 793 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 794 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 795 power-domains = <&rpmhpd SM8350_CX>; 796 operating-points-v2 = <&qup_opp_table_100mhz>; 797 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 798 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 799 dma-names = "tx", "rx"; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 status = "disabled"; 803 }; 804 805 i2c17: i2c@88c000 { 806 compatible = "qcom,geni-i2c"; 807 reg = <0 0x0088c000 0 0x4000>; 808 clock-names = "se"; 809 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 810 pinctrl-names = "default"; 811 pinctrl-0 = <&qup_i2c17_default>; 812 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 813 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 814 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 815 dma-names = "tx", "rx"; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 status = "disabled"; 819 }; 820 821 spi17: spi@88c000 { 822 compatible = "qcom,geni-spi"; 823 reg = <0 0x0088c000 0 0x4000>; 824 clock-names = "se"; 825 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 826 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 827 power-domains = <&rpmhpd SM8350_CX>; 828 operating-points-v2 = <&qup_opp_table_100mhz>; 829 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 830 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 831 dma-names = "tx", "rx"; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 status = "disabled"; 835 }; 836 837 /* QUP no. 18 seems to be strictly SPI/UART-only */ 838 839 spi18: spi@890000 { 840 compatible = "qcom,geni-spi"; 841 reg = <0 0x00890000 0 0x4000>; 842 clock-names = "se"; 843 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 844 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 845 power-domains = <&rpmhpd SM8350_CX>; 846 operating-points-v2 = <&qup_opp_table_100mhz>; 847 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 848 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 849 dma-names = "tx", "rx"; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 status = "disabled"; 853 }; 854 855 uart18: serial@890000 { 856 compatible = "qcom,geni-uart"; 857 reg = <0 0x00890000 0 0x4000>; 858 clock-names = "se"; 859 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&qup_uart18_default>; 862 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 863 power-domains = <&rpmhpd SM8350_CX>; 864 operating-points-v2 = <&qup_opp_table_100mhz>; 865 status = "disabled"; 866 }; 867 868 i2c19: i2c@894000 { 869 compatible = "qcom,geni-i2c"; 870 reg = <0 0x00894000 0 0x4000>; 871 clock-names = "se"; 872 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&qup_i2c19_default>; 875 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 876 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 877 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 878 dma-names = "tx", "rx"; 879 #address-cells = <1>; 880 #size-cells = <0>; 881 status = "disabled"; 882 }; 883 884 spi19: spi@894000 { 885 compatible = "qcom,geni-spi"; 886 reg = <0 0x00894000 0 0x4000>; 887 clock-names = "se"; 888 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 889 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 890 power-domains = <&rpmhpd SM8350_CX>; 891 operating-points-v2 = <&qup_opp_table_100mhz>; 892 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 893 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 894 dma-names = "tx", "rx"; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 status = "disabled"; 898 }; 899 }; 900 901 gpi_dma0: dma-controller@9800000 { 902 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 903 reg = <0 0x09800000 0 0x60000>; 904 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 916 dma-channels = <12>; 917 dma-channel-mask = <0x7e>; 918 iommus = <&apps_smmu 0x5b6 0x0>; 919 #dma-cells = <3>; 920 status = "disabled"; 921 }; 922 923 qupv3_id_0: geniqup@9c0000 { 924 compatible = "qcom,geni-se-qup"; 925 reg = <0x0 0x009c0000 0x0 0x6000>; 926 clock-names = "m-ahb", "s-ahb"; 927 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 928 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 929 iommus = <&apps_smmu 0x5a3 0>; 930 #address-cells = <2>; 931 #size-cells = <2>; 932 ranges; 933 status = "disabled"; 934 935 i2c0: i2c@980000 { 936 compatible = "qcom,geni-i2c"; 937 reg = <0 0x00980000 0 0x4000>; 938 clock-names = "se"; 939 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 940 pinctrl-names = "default"; 941 pinctrl-0 = <&qup_i2c0_default>; 942 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 943 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 944 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 945 dma-names = "tx", "rx"; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 status = "disabled"; 949 }; 950 951 spi0: spi@980000 { 952 compatible = "qcom,geni-spi"; 953 reg = <0 0x00980000 0 0x4000>; 954 clock-names = "se"; 955 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 956 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 957 power-domains = <&rpmhpd SM8350_CX>; 958 operating-points-v2 = <&qup_opp_table_100mhz>; 959 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 960 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 961 dma-names = "tx", "rx"; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 status = "disabled"; 965 }; 966 967 i2c1: i2c@984000 { 968 compatible = "qcom,geni-i2c"; 969 reg = <0 0x00984000 0 0x4000>; 970 clock-names = "se"; 971 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&qup_i2c1_default>; 974 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 975 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 976 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 977 dma-names = "tx", "rx"; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 status = "disabled"; 981 }; 982 983 spi1: spi@984000 { 984 compatible = "qcom,geni-spi"; 985 reg = <0 0x00984000 0 0x4000>; 986 clock-names = "se"; 987 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 988 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 989 power-domains = <&rpmhpd SM8350_CX>; 990 operating-points-v2 = <&qup_opp_table_100mhz>; 991 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 992 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 993 dma-names = "tx", "rx"; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 status = "disabled"; 997 }; 998 999 i2c2: i2c@988000 { 1000 compatible = "qcom,geni-i2c"; 1001 reg = <0 0x00988000 0 0x4000>; 1002 clock-names = "se"; 1003 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1004 pinctrl-names = "default"; 1005 pinctrl-0 = <&qup_i2c2_default>; 1006 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1007 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1008 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1009 dma-names = "tx", "rx"; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 status = "disabled"; 1013 }; 1014 1015 spi2: spi@988000 { 1016 compatible = "qcom,geni-spi"; 1017 reg = <0 0x00988000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1020 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1021 power-domains = <&rpmhpd SM8350_CX>; 1022 operating-points-v2 = <&qup_opp_table_100mhz>; 1023 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1024 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1025 dma-names = "tx", "rx"; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 status = "disabled"; 1029 }; 1030 1031 uart2: serial@98c000 { 1032 compatible = "qcom,geni-debug-uart"; 1033 reg = <0 0x0098c000 0 0x4000>; 1034 clock-names = "se"; 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1036 pinctrl-names = "default"; 1037 pinctrl-0 = <&qup_uart3_default_state>; 1038 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1039 power-domains = <&rpmhpd SM8350_CX>; 1040 operating-points-v2 = <&qup_opp_table_100mhz>; 1041 status = "disabled"; 1042 }; 1043 1044 /* QUP no. 3 seems to be strictly SPI-only */ 1045 1046 spi3: spi@98c000 { 1047 compatible = "qcom,geni-spi"; 1048 reg = <0 0x0098c000 0 0x4000>; 1049 clock-names = "se"; 1050 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1051 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1052 power-domains = <&rpmhpd SM8350_CX>; 1053 operating-points-v2 = <&qup_opp_table_100mhz>; 1054 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1055 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1056 dma-names = "tx", "rx"; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 status = "disabled"; 1060 }; 1061 1062 i2c4: i2c@990000 { 1063 compatible = "qcom,geni-i2c"; 1064 reg = <0 0x00990000 0 0x4000>; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1067 pinctrl-names = "default"; 1068 pinctrl-0 = <&qup_i2c4_default>; 1069 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1070 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1071 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1072 dma-names = "tx", "rx"; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 status = "disabled"; 1076 }; 1077 1078 spi4: spi@990000 { 1079 compatible = "qcom,geni-spi"; 1080 reg = <0 0x00990000 0 0x4000>; 1081 clock-names = "se"; 1082 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1083 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1084 power-domains = <&rpmhpd SM8350_CX>; 1085 operating-points-v2 = <&qup_opp_table_100mhz>; 1086 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1087 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1088 dma-names = "tx", "rx"; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 status = "disabled"; 1092 }; 1093 1094 i2c5: i2c@994000 { 1095 compatible = "qcom,geni-i2c"; 1096 reg = <0 0x00994000 0 0x4000>; 1097 clock-names = "se"; 1098 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1099 pinctrl-names = "default"; 1100 pinctrl-0 = <&qup_i2c5_default>; 1101 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1102 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1103 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1104 dma-names = "tx", "rx"; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 status = "disabled"; 1108 }; 1109 1110 spi5: spi@994000 { 1111 compatible = "qcom,geni-spi"; 1112 reg = <0 0x00994000 0 0x4000>; 1113 clock-names = "se"; 1114 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1115 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1116 power-domains = <&rpmhpd SM8350_CX>; 1117 operating-points-v2 = <&qup_opp_table_100mhz>; 1118 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1119 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1120 dma-names = "tx", "rx"; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 1126 i2c6: i2c@998000 { 1127 compatible = "qcom,geni-i2c"; 1128 reg = <0 0x00998000 0 0x4000>; 1129 clock-names = "se"; 1130 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&qup_i2c6_default>; 1133 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1134 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1135 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1136 dma-names = "tx", "rx"; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 status = "disabled"; 1140 }; 1141 1142 spi6: spi@998000 { 1143 compatible = "qcom,geni-spi"; 1144 reg = <0 0x00998000 0 0x4000>; 1145 clock-names = "se"; 1146 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1147 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1148 power-domains = <&rpmhpd SM8350_CX>; 1149 operating-points-v2 = <&qup_opp_table_100mhz>; 1150 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1151 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1152 dma-names = "tx", "rx"; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 status = "disabled"; 1156 }; 1157 1158 uart6: serial@998000 { 1159 compatible = "qcom,geni-uart"; 1160 reg = <0 0x00998000 0 0x4000>; 1161 clock-names = "se"; 1162 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&qup_uart6_default>; 1165 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1166 power-domains = <&rpmhpd SM8350_CX>; 1167 operating-points-v2 = <&qup_opp_table_100mhz>; 1168 status = "disabled"; 1169 }; 1170 1171 i2c7: i2c@99c000 { 1172 compatible = "qcom,geni-i2c"; 1173 reg = <0 0x0099c000 0 0x4000>; 1174 clock-names = "se"; 1175 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1176 pinctrl-names = "default"; 1177 pinctrl-0 = <&qup_i2c7_default>; 1178 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1179 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1180 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1181 dma-names = "tx", "rx"; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 status = "disabled"; 1185 }; 1186 1187 spi7: spi@99c000 { 1188 compatible = "qcom,geni-spi"; 1189 reg = <0 0x0099c000 0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1192 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1193 power-domains = <&rpmhpd SM8350_CX>; 1194 operating-points-v2 = <&qup_opp_table_100mhz>; 1195 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1196 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1197 dma-names = "tx", "rx"; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 status = "disabled"; 1201 }; 1202 }; 1203 1204 gpi_dma1: dma-controller@a00000 { 1205 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1206 reg = <0 0x00a00000 0 0x60000>; 1207 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1219 dma-channels = <12>; 1220 dma-channel-mask = <0xff>; 1221 iommus = <&apps_smmu 0x56 0x0>; 1222 #dma-cells = <3>; 1223 status = "disabled"; 1224 }; 1225 1226 qupv3_id_1: geniqup@ac0000 { 1227 compatible = "qcom,geni-se-qup"; 1228 reg = <0x0 0x00ac0000 0x0 0x6000>; 1229 clock-names = "m-ahb", "s-ahb"; 1230 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1231 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1232 iommus = <&apps_smmu 0x43 0>; 1233 #address-cells = <2>; 1234 #size-cells = <2>; 1235 ranges; 1236 status = "disabled"; 1237 1238 i2c8: i2c@a80000 { 1239 compatible = "qcom,geni-i2c"; 1240 reg = <0 0x00a80000 0 0x4000>; 1241 clock-names = "se"; 1242 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&qup_i2c8_default>; 1245 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1246 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1247 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1248 dma-names = "tx", "rx"; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 status = "disabled"; 1252 }; 1253 1254 spi8: spi@a80000 { 1255 compatible = "qcom,geni-spi"; 1256 reg = <0 0x00a80000 0 0x4000>; 1257 clock-names = "se"; 1258 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1259 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1260 power-domains = <&rpmhpd SM8350_CX>; 1261 operating-points-v2 = <&qup_opp_table_120mhz>; 1262 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1263 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1264 dma-names = "tx", "rx"; 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 status = "disabled"; 1268 }; 1269 1270 i2c9: i2c@a84000 { 1271 compatible = "qcom,geni-i2c"; 1272 reg = <0 0x00a84000 0 0x4000>; 1273 clock-names = "se"; 1274 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1275 pinctrl-names = "default"; 1276 pinctrl-0 = <&qup_i2c9_default>; 1277 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1278 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1279 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1280 dma-names = "tx", "rx"; 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 status = "disabled"; 1284 }; 1285 1286 spi9: spi@a84000 { 1287 compatible = "qcom,geni-spi"; 1288 reg = <0 0x00a84000 0 0x4000>; 1289 clock-names = "se"; 1290 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1291 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1292 power-domains = <&rpmhpd SM8350_CX>; 1293 operating-points-v2 = <&qup_opp_table_100mhz>; 1294 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1295 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1296 dma-names = "tx", "rx"; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 status = "disabled"; 1300 }; 1301 1302 i2c10: i2c@a88000 { 1303 compatible = "qcom,geni-i2c"; 1304 reg = <0 0x00a88000 0 0x4000>; 1305 clock-names = "se"; 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&qup_i2c10_default>; 1309 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1310 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1311 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1312 dma-names = "tx", "rx"; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 status = "disabled"; 1316 }; 1317 1318 spi10: spi@a88000 { 1319 compatible = "qcom,geni-spi"; 1320 reg = <0 0x00a88000 0 0x4000>; 1321 clock-names = "se"; 1322 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1323 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1324 power-domains = <&rpmhpd SM8350_CX>; 1325 operating-points-v2 = <&qup_opp_table_100mhz>; 1326 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1327 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1328 dma-names = "tx", "rx"; 1329 #address-cells = <1>; 1330 #size-cells = <0>; 1331 status = "disabled"; 1332 }; 1333 1334 i2c11: i2c@a8c000 { 1335 compatible = "qcom,geni-i2c"; 1336 reg = <0 0x00a8c000 0 0x4000>; 1337 clock-names = "se"; 1338 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1339 pinctrl-names = "default"; 1340 pinctrl-0 = <&qup_i2c11_default>; 1341 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1342 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1343 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1344 dma-names = "tx", "rx"; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 status = "disabled"; 1348 }; 1349 1350 spi11: spi@a8c000 { 1351 compatible = "qcom,geni-spi"; 1352 reg = <0 0x00a8c000 0 0x4000>; 1353 clock-names = "se"; 1354 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1355 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1356 power-domains = <&rpmhpd SM8350_CX>; 1357 operating-points-v2 = <&qup_opp_table_100mhz>; 1358 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1359 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1360 dma-names = "tx", "rx"; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 status = "disabled"; 1364 }; 1365 1366 i2c12: i2c@a90000 { 1367 compatible = "qcom,geni-i2c"; 1368 reg = <0 0x00a90000 0 0x4000>; 1369 clock-names = "se"; 1370 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1371 pinctrl-names = "default"; 1372 pinctrl-0 = <&qup_i2c12_default>; 1373 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1374 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1375 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1376 dma-names = "tx", "rx"; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 status = "disabled"; 1380 }; 1381 1382 spi12: spi@a90000 { 1383 compatible = "qcom,geni-spi"; 1384 reg = <0 0x00a90000 0 0x4000>; 1385 clock-names = "se"; 1386 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1387 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1388 power-domains = <&rpmhpd SM8350_CX>; 1389 operating-points-v2 = <&qup_opp_table_100mhz>; 1390 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1391 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1392 dma-names = "tx", "rx"; 1393 #address-cells = <1>; 1394 #size-cells = <0>; 1395 status = "disabled"; 1396 }; 1397 1398 i2c13: i2c@a94000 { 1399 compatible = "qcom,geni-i2c"; 1400 reg = <0 0x00a94000 0 0x4000>; 1401 clock-names = "se"; 1402 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1403 pinctrl-names = "default"; 1404 pinctrl-0 = <&qup_i2c13_default>; 1405 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1406 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1407 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1408 dma-names = "tx", "rx"; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 status = "disabled"; 1412 }; 1413 1414 spi13: spi@a94000 { 1415 compatible = "qcom,geni-spi"; 1416 reg = <0 0x00a94000 0 0x4000>; 1417 clock-names = "se"; 1418 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1419 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1420 power-domains = <&rpmhpd SM8350_CX>; 1421 operating-points-v2 = <&qup_opp_table_100mhz>; 1422 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1423 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1424 dma-names = "tx", "rx"; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 status = "disabled"; 1428 }; 1429 }; 1430 1431 rng: rng@10d3000 { 1432 compatible = "qcom,prng-ee"; 1433 reg = <0 0x010d3000 0 0x1000>; 1434 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1435 clock-names = "core"; 1436 }; 1437 1438 config_noc: interconnect@1500000 { 1439 compatible = "qcom,sm8350-config-noc"; 1440 reg = <0 0x01500000 0 0xa580>; 1441 #interconnect-cells = <2>; 1442 qcom,bcm-voters = <&apps_bcm_voter>; 1443 }; 1444 1445 mc_virt: interconnect@1580000 { 1446 compatible = "qcom,sm8350-mc-virt"; 1447 reg = <0 0x01580000 0 0x1000>; 1448 #interconnect-cells = <2>; 1449 qcom,bcm-voters = <&apps_bcm_voter>; 1450 }; 1451 1452 system_noc: interconnect@1680000 { 1453 compatible = "qcom,sm8350-system-noc"; 1454 reg = <0 0x01680000 0 0x1c200>; 1455 #interconnect-cells = <2>; 1456 qcom,bcm-voters = <&apps_bcm_voter>; 1457 }; 1458 1459 aggre1_noc: interconnect@16e0000 { 1460 compatible = "qcom,sm8350-aggre1-noc"; 1461 reg = <0 0x016e0000 0 0x1f180>; 1462 #interconnect-cells = <2>; 1463 qcom,bcm-voters = <&apps_bcm_voter>; 1464 }; 1465 1466 aggre2_noc: interconnect@1700000 { 1467 compatible = "qcom,sm8350-aggre2-noc"; 1468 reg = <0 0x01700000 0 0x33000>; 1469 #interconnect-cells = <2>; 1470 qcom,bcm-voters = <&apps_bcm_voter>; 1471 }; 1472 1473 mmss_noc: interconnect@1740000 { 1474 compatible = "qcom,sm8350-mmss-noc"; 1475 reg = <0 0x01740000 0 0x1f080>; 1476 #interconnect-cells = <2>; 1477 qcom,bcm-voters = <&apps_bcm_voter>; 1478 }; 1479 1480 pcie0: pci@1c00000 { 1481 compatible = "qcom,pcie-sm8350"; 1482 reg = <0 0x01c00000 0 0x3000>, 1483 <0 0x60000000 0 0xf1d>, 1484 <0 0x60000f20 0 0xa8>, 1485 <0 0x60001000 0 0x1000>, 1486 <0 0x60100000 0 0x100000>; 1487 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1488 device_type = "pci"; 1489 linux,pci-domain = <0>; 1490 bus-range = <0x00 0xff>; 1491 num-lanes = <1>; 1492 1493 #address-cells = <3>; 1494 #size-cells = <2>; 1495 1496 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1497 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1498 1499 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1507 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1508 "msi4", "msi5", "msi6", "msi7"; 1509 #interrupt-cells = <1>; 1510 interrupt-map-mask = <0 0 0 0x7>; 1511 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1512 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1513 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1514 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1515 1516 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1517 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1518 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1519 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1520 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1521 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1522 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1523 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1524 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1525 clock-names = "aux", 1526 "cfg", 1527 "bus_master", 1528 "bus_slave", 1529 "slave_q2a", 1530 "tbu", 1531 "ddrss_sf_tbu", 1532 "aggre1", 1533 "aggre0"; 1534 1535 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1536 <0x100 &apps_smmu 0x1c01 0x1>; 1537 1538 resets = <&gcc GCC_PCIE_0_BCR>; 1539 reset-names = "pci"; 1540 1541 power-domains = <&gcc PCIE_0_GDSC>; 1542 1543 phys = <&pcie0_phy>; 1544 phy-names = "pciephy"; 1545 1546 status = "disabled"; 1547 }; 1548 1549 pcie0_phy: phy@1c06000 { 1550 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1551 reg = <0 0x01c06000 0 0x2000>; 1552 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1553 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1554 <&gcc GCC_PCIE_0_CLKREF_EN>, 1555 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1556 <&gcc GCC_PCIE_0_PIPE_CLK>; 1557 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1558 1559 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1560 reset-names = "phy"; 1561 1562 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1563 assigned-clock-rates = <100000000>; 1564 1565 #clock-cells = <0>; 1566 clock-output-names = "pcie_0_pipe_clk"; 1567 1568 #phy-cells = <0>; 1569 1570 status = "disabled"; 1571 }; 1572 1573 pcie1: pci@1c08000 { 1574 compatible = "qcom,pcie-sm8350"; 1575 reg = <0 0x01c08000 0 0x3000>, 1576 <0 0x40000000 0 0xf1d>, 1577 <0 0x40000f20 0 0xa8>, 1578 <0 0x40001000 0 0x1000>, 1579 <0 0x40100000 0 0x100000>; 1580 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1581 device_type = "pci"; 1582 linux,pci-domain = <1>; 1583 bus-range = <0x00 0xff>; 1584 num-lanes = <2>; 1585 1586 #address-cells = <3>; 1587 #size-cells = <2>; 1588 1589 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1590 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1591 1592 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1593 interrupt-names = "msi"; 1594 #interrupt-cells = <1>; 1595 interrupt-map-mask = <0 0 0 0x7>; 1596 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1597 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1598 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1599 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1600 1601 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1602 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1603 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1604 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1605 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1606 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1607 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1608 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1609 clock-names = "aux", 1610 "cfg", 1611 "bus_master", 1612 "bus_slave", 1613 "slave_q2a", 1614 "tbu", 1615 "ddrss_sf_tbu", 1616 "aggre1"; 1617 1618 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1619 <0x100 &apps_smmu 0x1c81 0x1>; 1620 1621 resets = <&gcc GCC_PCIE_1_BCR>; 1622 reset-names = "pci"; 1623 1624 power-domains = <&gcc PCIE_1_GDSC>; 1625 1626 phys = <&pcie1_phy>; 1627 phy-names = "pciephy"; 1628 1629 status = "disabled"; 1630 }; 1631 1632 pcie1_phy: phy@1c0e000 { 1633 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1634 reg = <0 0x01c0e000 0 0x2000>; 1635 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1636 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1637 <&gcc GCC_PCIE_1_CLKREF_EN>, 1638 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1639 <&gcc GCC_PCIE_1_PIPE_CLK>; 1640 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1641 1642 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1643 reset-names = "phy"; 1644 1645 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1646 assigned-clock-rates = <100000000>; 1647 1648 #clock-cells = <0>; 1649 clock-output-names = "pcie_1_pipe_clk"; 1650 1651 #phy-cells = <0>; 1652 1653 status = "disabled"; 1654 }; 1655 1656 ufs_mem_hc: ufshc@1d84000 { 1657 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1658 "jedec,ufs-2.0"; 1659 reg = <0 0x01d84000 0 0x3000>; 1660 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1661 phys = <&ufs_mem_phy_lanes>; 1662 phy-names = "ufsphy"; 1663 lanes-per-direction = <2>; 1664 #reset-cells = <1>; 1665 resets = <&gcc GCC_UFS_PHY_BCR>; 1666 reset-names = "rst"; 1667 1668 power-domains = <&gcc UFS_PHY_GDSC>; 1669 1670 iommus = <&apps_smmu 0xe0 0x0>; 1671 dma-coherent; 1672 1673 clock-names = 1674 "core_clk", 1675 "bus_aggr_clk", 1676 "iface_clk", 1677 "core_clk_unipro", 1678 "ref_clk", 1679 "tx_lane0_sync_clk", 1680 "rx_lane0_sync_clk", 1681 "rx_lane1_sync_clk"; 1682 clocks = 1683 <&gcc GCC_UFS_PHY_AXI_CLK>, 1684 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1685 <&gcc GCC_UFS_PHY_AHB_CLK>, 1686 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1687 <&rpmhcc RPMH_CXO_CLK>, 1688 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1689 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1690 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1691 freq-table-hz = 1692 <75000000 300000000>, 1693 <0 0>, 1694 <0 0>, 1695 <75000000 300000000>, 1696 <0 0>, 1697 <0 0>, 1698 <0 0>, 1699 <0 0>; 1700 status = "disabled"; 1701 }; 1702 1703 ufs_mem_phy: phy@1d87000 { 1704 compatible = "qcom,sm8350-qmp-ufs-phy"; 1705 reg = <0 0x01d87000 0 0x1c4>; 1706 #address-cells = <2>; 1707 #size-cells = <2>; 1708 ranges; 1709 clock-names = "ref", 1710 "ref_aux"; 1711 clocks = <&rpmhcc RPMH_CXO_CLK>, 1712 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1713 1714 resets = <&ufs_mem_hc 0>; 1715 reset-names = "ufsphy"; 1716 status = "disabled"; 1717 1718 ufs_mem_phy_lanes: phy@1d87400 { 1719 reg = <0 0x01d87400 0 0x188>, 1720 <0 0x01d87600 0 0x200>, 1721 <0 0x01d87c00 0 0x200>, 1722 <0 0x01d87800 0 0x188>, 1723 <0 0x01d87a00 0 0x200>; 1724 #clock-cells = <1>; 1725 #phy-cells = <0>; 1726 }; 1727 }; 1728 1729 cryptobam: dma-controller@1dc4000 { 1730 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1731 reg = <0 0x01dc4000 0 0x24000>; 1732 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1733 #dma-cells = <1>; 1734 qcom,ee = <0>; 1735 qcom,controlled-remotely; 1736 iommus = <&apps_smmu 0x594 0x0011>, 1737 <&apps_smmu 0x596 0x0011>; 1738 }; 1739 1740 crypto: crypto@1dfa000 { 1741 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1742 reg = <0 0x01dfa000 0 0x6000>; 1743 dmas = <&cryptobam 4>, <&cryptobam 5>; 1744 dma-names = "rx", "tx"; 1745 iommus = <&apps_smmu 0x594 0x0011>, 1746 <&apps_smmu 0x596 0x0011>; 1747 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1748 interconnect-names = "memory"; 1749 }; 1750 1751 ipa: ipa@1e40000 { 1752 compatible = "qcom,sm8350-ipa"; 1753 1754 iommus = <&apps_smmu 0x5c0 0x0>, 1755 <&apps_smmu 0x5c2 0x0>; 1756 reg = <0 0x01e40000 0 0x8000>, 1757 <0 0x01e50000 0 0x4b20>, 1758 <0 0x01e04000 0 0x23000>; 1759 reg-names = "ipa-reg", 1760 "ipa-shared", 1761 "gsi"; 1762 1763 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1764 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1765 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1766 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1767 interrupt-names = "ipa", 1768 "gsi", 1769 "ipa-clock-query", 1770 "ipa-setup-ready"; 1771 1772 clocks = <&rpmhcc RPMH_IPA_CLK>; 1773 clock-names = "core"; 1774 1775 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1776 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1777 interconnect-names = "memory", 1778 "config"; 1779 1780 qcom,qmp = <&aoss_qmp>; 1781 1782 qcom,smem-states = <&ipa_smp2p_out 0>, 1783 <&ipa_smp2p_out 1>; 1784 qcom,smem-state-names = "ipa-clock-enabled-valid", 1785 "ipa-clock-enabled"; 1786 1787 status = "disabled"; 1788 }; 1789 1790 tcsr_mutex: hwlock@1f40000 { 1791 compatible = "qcom,tcsr-mutex"; 1792 reg = <0x0 0x01f40000 0x0 0x40000>; 1793 #hwlock-cells = <1>; 1794 }; 1795 1796 gpu: gpu@3d00000 { 1797 compatible = "qcom,adreno-660.1", "qcom,adreno"; 1798 1799 reg = <0 0x03d00000 0 0x40000>, 1800 <0 0x03d9e000 0 0x1000>, 1801 <0 0x03d61000 0 0x800>; 1802 reg-names = "kgsl_3d0_reg_memory", 1803 "cx_mem", 1804 "cx_dbgc"; 1805 1806 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1807 1808 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 1809 1810 operating-points-v2 = <&gpu_opp_table>; 1811 1812 qcom,gmu = <&gmu>; 1813 1814 status = "disabled"; 1815 1816 zap-shader { 1817 memory-region = <&pil_gpu_mem>; 1818 }; 1819 1820 /* note: downstream checks gpu binning for 670 Mhz */ 1821 gpu_opp_table: opp-table { 1822 compatible = "operating-points-v2"; 1823 1824 opp-840000000 { 1825 opp-hz = /bits/ 64 <840000000>; 1826 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1827 }; 1828 1829 opp-778000000 { 1830 opp-hz = /bits/ 64 <778000000>; 1831 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1832 }; 1833 1834 opp-738000000 { 1835 opp-hz = /bits/ 64 <738000000>; 1836 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1837 }; 1838 1839 opp-676000000 { 1840 opp-hz = /bits/ 64 <676000000>; 1841 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1842 }; 1843 1844 opp-608000000 { 1845 opp-hz = /bits/ 64 <608000000>; 1846 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1847 }; 1848 1849 opp-540000000 { 1850 opp-hz = /bits/ 64 <540000000>; 1851 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1852 }; 1853 1854 opp-491000000 { 1855 opp-hz = /bits/ 64 <491000000>; 1856 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1857 }; 1858 1859 opp-443000000 { 1860 opp-hz = /bits/ 64 <443000000>; 1861 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1862 }; 1863 1864 opp-379000000 { 1865 opp-hz = /bits/ 64 <379000000>; 1866 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 1867 }; 1868 1869 opp-315000000 { 1870 opp-hz = /bits/ 64 <315000000>; 1871 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1872 }; 1873 }; 1874 }; 1875 1876 gmu: gmu@3d6a000 { 1877 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 1878 1879 reg = <0 0x03d6a000 0 0x34000>, 1880 <0 0x03de0000 0 0x10000>, 1881 <0 0x0b290000 0 0x10000>; 1882 reg-names = "gmu", "rscc", "gmu_pdc"; 1883 1884 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1886 interrupt-names = "hfi", "gmu"; 1887 1888 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1889 <&gpucc GPU_CC_CXO_CLK>, 1890 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1891 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1892 <&gpucc GPU_CC_AHB_CLK>, 1893 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1894 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 1895 clock-names = "gmu", 1896 "cxo", 1897 "axi", 1898 "memnoc", 1899 "ahb", 1900 "hub", 1901 "smmu_vote"; 1902 1903 power-domains = <&gpucc GPU_CX_GDSC>, 1904 <&gpucc GPU_GX_GDSC>; 1905 power-domain-names = "cx", 1906 "gx"; 1907 1908 iommus = <&adreno_smmu 5 0x400>; 1909 1910 operating-points-v2 = <&gmu_opp_table>; 1911 1912 gmu_opp_table: opp-table { 1913 compatible = "operating-points-v2"; 1914 1915 opp-200000000 { 1916 opp-hz = /bits/ 64 <200000000>; 1917 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1918 }; 1919 }; 1920 }; 1921 1922 gpucc: clock-controller@3d90000 { 1923 compatible = "qcom,sm8350-gpucc"; 1924 reg = <0 0x03d90000 0 0x9000>; 1925 clocks = <&rpmhcc RPMH_CXO_CLK>, 1926 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1927 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1928 clock-names = "bi_tcxo", 1929 "gcc_gpu_gpll0_clk_src", 1930 "gcc_gpu_gpll0_div_clk_src"; 1931 #clock-cells = <1>; 1932 #reset-cells = <1>; 1933 #power-domain-cells = <1>; 1934 }; 1935 1936 adreno_smmu: iommu@3da0000 { 1937 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 1938 "qcom,smmu-500", "arm,mmu-500"; 1939 reg = <0 0x03da0000 0 0x20000>; 1940 #iommu-cells = <2>; 1941 #global-interrupts = <2>; 1942 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1954 1955 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1956 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1957 <&gpucc GPU_CC_AHB_CLK>, 1958 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1959 <&gpucc GPU_CC_CX_GMU_CLK>, 1960 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1961 <&gpucc GPU_CC_HUB_AON_CLK>; 1962 clock-names = "bus", 1963 "iface", 1964 "ahb", 1965 "hlos1_vote_gpu_smmu", 1966 "cx_gmu", 1967 "hub_cx_int", 1968 "hub_aon"; 1969 1970 power-domains = <&gpucc GPU_CX_GDSC>; 1971 dma-coherent; 1972 }; 1973 1974 lpass_ag_noc: interconnect@3c40000 { 1975 compatible = "qcom,sm8350-lpass-ag-noc"; 1976 reg = <0 0x03c40000 0 0xf080>; 1977 #interconnect-cells = <2>; 1978 qcom,bcm-voters = <&apps_bcm_voter>; 1979 }; 1980 1981 mpss: remoteproc@4080000 { 1982 compatible = "qcom,sm8350-mpss-pas"; 1983 reg = <0x0 0x04080000 0x0 0x4040>; 1984 1985 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1986 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1987 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1988 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1989 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1990 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1991 interrupt-names = "wdog", "fatal", "ready", "handover", 1992 "stop-ack", "shutdown-ack"; 1993 1994 clocks = <&rpmhcc RPMH_CXO_CLK>; 1995 clock-names = "xo"; 1996 1997 power-domains = <&rpmhpd SM8350_CX>, 1998 <&rpmhpd SM8350_MSS>; 1999 power-domain-names = "cx", "mss"; 2000 2001 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2002 2003 memory-region = <&pil_modem_mem>; 2004 2005 qcom,qmp = <&aoss_qmp>; 2006 2007 qcom,smem-states = <&smp2p_modem_out 0>; 2008 qcom,smem-state-names = "stop"; 2009 2010 status = "disabled"; 2011 2012 glink-edge { 2013 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2014 IPCC_MPROC_SIGNAL_GLINK_QMP 2015 IRQ_TYPE_EDGE_RISING>; 2016 mboxes = <&ipcc IPCC_CLIENT_MPSS 2017 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2018 label = "modem"; 2019 qcom,remote-pid = <1>; 2020 }; 2021 }; 2022 2023 slpi: remoteproc@5c00000 { 2024 compatible = "qcom,sm8350-slpi-pas"; 2025 reg = <0 0x05c00000 0 0x4000>; 2026 2027 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2028 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2029 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2030 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2031 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2032 interrupt-names = "wdog", "fatal", "ready", 2033 "handover", "stop-ack"; 2034 2035 clocks = <&rpmhcc RPMH_CXO_CLK>; 2036 clock-names = "xo"; 2037 2038 power-domains = <&rpmhpd SM8350_LCX>, 2039 <&rpmhpd SM8350_LMX>; 2040 power-domain-names = "lcx", "lmx"; 2041 2042 memory-region = <&pil_slpi_mem>; 2043 2044 qcom,qmp = <&aoss_qmp>; 2045 2046 qcom,smem-states = <&smp2p_slpi_out 0>; 2047 qcom,smem-state-names = "stop"; 2048 2049 status = "disabled"; 2050 2051 glink-edge { 2052 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2053 IPCC_MPROC_SIGNAL_GLINK_QMP 2054 IRQ_TYPE_EDGE_RISING>; 2055 mboxes = <&ipcc IPCC_CLIENT_SLPI 2056 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2057 2058 label = "slpi"; 2059 qcom,remote-pid = <3>; 2060 2061 fastrpc { 2062 compatible = "qcom,fastrpc"; 2063 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2064 label = "sdsp"; 2065 qcom,non-secure-domain; 2066 #address-cells = <1>; 2067 #size-cells = <0>; 2068 2069 compute-cb@1 { 2070 compatible = "qcom,fastrpc-compute-cb"; 2071 reg = <1>; 2072 iommus = <&apps_smmu 0x0541 0x0>; 2073 }; 2074 2075 compute-cb@2 { 2076 compatible = "qcom,fastrpc-compute-cb"; 2077 reg = <2>; 2078 iommus = <&apps_smmu 0x0542 0x0>; 2079 }; 2080 2081 compute-cb@3 { 2082 compatible = "qcom,fastrpc-compute-cb"; 2083 reg = <3>; 2084 iommus = <&apps_smmu 0x0543 0x0>; 2085 /* note: shared-cb = <4> in downstream */ 2086 }; 2087 }; 2088 }; 2089 }; 2090 2091 sdhc_2: mmc@8804000 { 2092 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2093 reg = <0 0x08804000 0 0x1000>; 2094 2095 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2097 interrupt-names = "hc_irq", "pwr_irq"; 2098 2099 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2100 <&gcc GCC_SDCC2_APPS_CLK>, 2101 <&rpmhcc RPMH_CXO_CLK>; 2102 clock-names = "iface", "core", "xo"; 2103 resets = <&gcc GCC_SDCC2_BCR>; 2104 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2105 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2106 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2107 iommus = <&apps_smmu 0x4a0 0x0>; 2108 power-domains = <&rpmhpd SM8350_CX>; 2109 operating-points-v2 = <&sdhc2_opp_table>; 2110 bus-width = <4>; 2111 dma-coherent; 2112 2113 status = "disabled"; 2114 2115 sdhc2_opp_table: opp-table { 2116 compatible = "operating-points-v2"; 2117 2118 opp-100000000 { 2119 opp-hz = /bits/ 64 <100000000>; 2120 required-opps = <&rpmhpd_opp_low_svs>; 2121 }; 2122 2123 opp-202000000 { 2124 opp-hz = /bits/ 64 <202000000>; 2125 required-opps = <&rpmhpd_opp_svs_l1>; 2126 }; 2127 }; 2128 }; 2129 2130 usb_1_hsphy: phy@88e3000 { 2131 compatible = "qcom,sm8350-usb-hs-phy", 2132 "qcom,usb-snps-hs-7nm-phy"; 2133 reg = <0 0x088e3000 0 0x400>; 2134 status = "disabled"; 2135 #phy-cells = <0>; 2136 2137 clocks = <&rpmhcc RPMH_CXO_CLK>; 2138 clock-names = "ref"; 2139 2140 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2141 }; 2142 2143 usb_2_hsphy: phy@88e4000 { 2144 compatible = "qcom,sm8250-usb-hs-phy", 2145 "qcom,usb-snps-hs-7nm-phy"; 2146 reg = <0 0x088e4000 0 0x400>; 2147 status = "disabled"; 2148 #phy-cells = <0>; 2149 2150 clocks = <&rpmhcc RPMH_CXO_CLK>; 2151 clock-names = "ref"; 2152 2153 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2154 }; 2155 2156 usb_1_qmpphy: phy@88e8000 { 2157 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2158 reg = <0 0x088e8000 0 0x3000>; 2159 2160 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2161 <&rpmhcc RPMH_CXO_CLK>, 2162 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2163 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2164 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2165 2166 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2167 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2168 reset-names = "phy", "common"; 2169 2170 #clock-cells = <1>; 2171 #phy-cells = <1>; 2172 2173 status = "disabled"; 2174 2175 ports { 2176 #address-cells = <1>; 2177 #size-cells = <0>; 2178 2179 port@0 { 2180 reg = <0>; 2181 2182 usb_1_qmpphy_out: endpoint { 2183 }; 2184 }; 2185 2186 port@1 { 2187 reg = <1>; 2188 2189 usb_1_qmpphy_usb_ss_in: endpoint { 2190 }; 2191 }; 2192 2193 port@2 { 2194 reg = <2>; 2195 2196 usb_1_qmpphy_dp_in: endpoint { 2197 }; 2198 }; 2199 }; 2200 }; 2201 2202 usb_2_qmpphy: phy-wrapper@88eb000 { 2203 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2204 reg = <0 0x088eb000 0 0x200>; 2205 status = "disabled"; 2206 #address-cells = <2>; 2207 #size-cells = <2>; 2208 ranges; 2209 2210 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2211 <&rpmhcc RPMH_CXO_CLK>, 2212 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2213 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2214 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2215 2216 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2217 <&gcc GCC_USB3_PHY_SEC_BCR>; 2218 reset-names = "phy", "common"; 2219 2220 usb_2_ssphy: phy@88ebe00 { 2221 reg = <0 0x088ebe00 0 0x200>, 2222 <0 0x088ec000 0 0x200>, 2223 <0 0x088eb200 0 0x1100>; 2224 #phy-cells = <0>; 2225 #clock-cells = <0>; 2226 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2227 clock-names = "pipe0"; 2228 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2229 }; 2230 }; 2231 2232 dc_noc: interconnect@90c0000 { 2233 compatible = "qcom,sm8350-dc-noc"; 2234 reg = <0 0x090c0000 0 0x4200>; 2235 #interconnect-cells = <2>; 2236 qcom,bcm-voters = <&apps_bcm_voter>; 2237 }; 2238 2239 gem_noc: interconnect@9100000 { 2240 compatible = "qcom,sm8350-gem-noc"; 2241 reg = <0 0x09100000 0 0xb4000>; 2242 #interconnect-cells = <2>; 2243 qcom,bcm-voters = <&apps_bcm_voter>; 2244 }; 2245 2246 system-cache-controller@9200000 { 2247 compatible = "qcom,sm8350-llcc"; 2248 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2249 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2250 <0 0x09600000 0 0x58000>; 2251 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2252 "llcc3_base", "llcc_broadcast_base"; 2253 }; 2254 2255 compute_noc: interconnect@a0c0000 { 2256 compatible = "qcom,sm8350-compute-noc"; 2257 reg = <0 0x0a0c0000 0 0xa180>; 2258 #interconnect-cells = <2>; 2259 qcom,bcm-voters = <&apps_bcm_voter>; 2260 }; 2261 2262 usb_1: usb@a6f8800 { 2263 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2264 reg = <0 0x0a6f8800 0 0x400>; 2265 status = "disabled"; 2266 #address-cells = <2>; 2267 #size-cells = <2>; 2268 ranges; 2269 2270 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2271 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2272 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2273 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2274 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2275 clock-names = "cfg_noc", 2276 "core", 2277 "iface", 2278 "sleep", 2279 "mock_utmi"; 2280 2281 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2282 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2283 assigned-clock-rates = <19200000>, <200000000>; 2284 2285 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2286 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2287 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2288 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 2289 interrupt-names = "hs_phy_irq", 2290 "ss_phy_irq", 2291 "dm_hs_phy_irq", 2292 "dp_hs_phy_irq"; 2293 2294 power-domains = <&gcc USB30_PRIM_GDSC>; 2295 2296 resets = <&gcc GCC_USB30_PRIM_BCR>; 2297 2298 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2299 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2300 interconnect-names = "usb-ddr", "apps-usb"; 2301 2302 usb_1_dwc3: usb@a600000 { 2303 compatible = "snps,dwc3"; 2304 reg = <0 0x0a600000 0 0xcd00>; 2305 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2306 iommus = <&apps_smmu 0x0 0x0>; 2307 snps,dis_u2_susphy_quirk; 2308 snps,dis_enblslpm_quirk; 2309 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2310 phy-names = "usb2-phy", "usb3-phy"; 2311 2312 ports { 2313 #address-cells = <1>; 2314 #size-cells = <0>; 2315 2316 port@0 { 2317 reg = <0>; 2318 2319 usb_1_dwc3_hs: endpoint { 2320 }; 2321 }; 2322 2323 port@1 { 2324 reg = <1>; 2325 2326 usb_1_dwc3_ss: endpoint { 2327 }; 2328 }; 2329 }; 2330 }; 2331 }; 2332 2333 usb_2: usb@a8f8800 { 2334 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2335 reg = <0 0x0a8f8800 0 0x400>; 2336 status = "disabled"; 2337 #address-cells = <2>; 2338 #size-cells = <2>; 2339 ranges; 2340 2341 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2342 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2343 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2344 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2345 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2346 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2347 clock-names = "cfg_noc", 2348 "core", 2349 "iface", 2350 "sleep", 2351 "mock_utmi", 2352 "xo"; 2353 2354 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2355 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2356 assigned-clock-rates = <19200000>, <200000000>; 2357 2358 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2359 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 2360 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2361 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 2362 interrupt-names = "hs_phy_irq", 2363 "ss_phy_irq", 2364 "dm_hs_phy_irq", 2365 "dp_hs_phy_irq"; 2366 2367 power-domains = <&gcc USB30_SEC_GDSC>; 2368 2369 resets = <&gcc GCC_USB30_SEC_BCR>; 2370 2371 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2372 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2373 interconnect-names = "usb-ddr", "apps-usb"; 2374 2375 usb_2_dwc3: usb@a800000 { 2376 compatible = "snps,dwc3"; 2377 reg = <0 0x0a800000 0 0xcd00>; 2378 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2379 iommus = <&apps_smmu 0x20 0x0>; 2380 snps,dis_u2_susphy_quirk; 2381 snps,dis_enblslpm_quirk; 2382 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2383 phy-names = "usb2-phy", "usb3-phy"; 2384 }; 2385 }; 2386 2387 mdss: display-subsystem@ae00000 { 2388 compatible = "qcom,sm8350-mdss"; 2389 reg = <0 0x0ae00000 0 0x1000>; 2390 reg-names = "mdss"; 2391 2392 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2393 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 2394 interconnect-names = "mdp0-mem", "mdp1-mem"; 2395 2396 power-domains = <&dispcc MDSS_GDSC>; 2397 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2398 2399 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2400 <&gcc GCC_DISP_HF_AXI_CLK>, 2401 <&gcc GCC_DISP_SF_AXI_CLK>, 2402 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2403 clock-names = "iface", "bus", "nrt_bus", "core"; 2404 2405 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2406 interrupt-controller; 2407 #interrupt-cells = <1>; 2408 2409 iommus = <&apps_smmu 0x820 0x402>; 2410 2411 status = "disabled"; 2412 2413 #address-cells = <2>; 2414 #size-cells = <2>; 2415 ranges; 2416 2417 dpu_opp_table: opp-table { 2418 compatible = "operating-points-v2"; 2419 2420 /* TODO: opp-200000000 should work with 2421 * &rpmhpd_opp_low_svs, but one some of 2422 * sm8350_hdk boards reboot using this 2423 * opp. 2424 */ 2425 opp-200000000 { 2426 opp-hz = /bits/ 64 <200000000>; 2427 required-opps = <&rpmhpd_opp_svs>; 2428 }; 2429 2430 opp-300000000 { 2431 opp-hz = /bits/ 64 <300000000>; 2432 required-opps = <&rpmhpd_opp_svs>; 2433 }; 2434 2435 opp-345000000 { 2436 opp-hz = /bits/ 64 <345000000>; 2437 required-opps = <&rpmhpd_opp_svs_l1>; 2438 }; 2439 2440 opp-460000000 { 2441 opp-hz = /bits/ 64 <460000000>; 2442 required-opps = <&rpmhpd_opp_nom>; 2443 }; 2444 }; 2445 2446 mdss_mdp: display-controller@ae01000 { 2447 compatible = "qcom,sm8350-dpu"; 2448 reg = <0 0x0ae01000 0 0x8f000>, 2449 <0 0x0aeb0000 0 0x2008>; 2450 reg-names = "mdp", "vbif"; 2451 2452 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2453 <&gcc GCC_DISP_SF_AXI_CLK>, 2454 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2455 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2456 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2457 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2458 clock-names = "bus", 2459 "nrt_bus", 2460 "iface", 2461 "lut", 2462 "core", 2463 "vsync"; 2464 2465 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2466 assigned-clock-rates = <19200000>; 2467 2468 operating-points-v2 = <&dpu_opp_table>; 2469 power-domains = <&rpmhpd SM8350_MMCX>; 2470 2471 interrupt-parent = <&mdss>; 2472 interrupts = <0>; 2473 2474 ports { 2475 #address-cells = <1>; 2476 #size-cells = <0>; 2477 2478 port@0 { 2479 reg = <0>; 2480 dpu_intf1_out: endpoint { 2481 remote-endpoint = <&mdss_dsi0_in>; 2482 }; 2483 }; 2484 2485 port@1 { 2486 reg = <1>; 2487 dpu_intf2_out: endpoint { 2488 remote-endpoint = <&mdss_dsi1_in>; 2489 }; 2490 }; 2491 2492 port@2 { 2493 reg = <2>; 2494 dpu_intf0_out: endpoint { 2495 remote-endpoint = <&mdss_dp_in>; 2496 }; 2497 }; 2498 }; 2499 }; 2500 2501 mdss_dp: displayport-controller@ae90000 { 2502 compatible = "qcom,sm8350-dp"; 2503 reg = <0 0xae90000 0 0x200>, 2504 <0 0xae90200 0 0x200>, 2505 <0 0xae90400 0 0x600>, 2506 <0 0xae91000 0 0x400>, 2507 <0 0xae91400 0 0x400>; 2508 interrupt-parent = <&mdss>; 2509 interrupts = <12>; 2510 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2511 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2512 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2513 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2514 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2515 clock-names = "core_iface", 2516 "core_aux", 2517 "ctrl_link", 2518 "ctrl_link_iface", 2519 "stream_pixel"; 2520 2521 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2522 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2523 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2524 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2525 2526 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2527 phy-names = "dp"; 2528 2529 #sound-dai-cells = <0>; 2530 2531 operating-points-v2 = <&dp_opp_table>; 2532 power-domains = <&rpmhpd SM8350_MMCX>; 2533 2534 status = "disabled"; 2535 2536 ports { 2537 #address-cells = <1>; 2538 #size-cells = <0>; 2539 2540 port@0 { 2541 reg = <0>; 2542 mdss_dp_in: endpoint { 2543 remote-endpoint = <&dpu_intf0_out>; 2544 }; 2545 }; 2546 }; 2547 2548 dp_opp_table: opp-table { 2549 compatible = "operating-points-v2"; 2550 2551 opp-160000000 { 2552 opp-hz = /bits/ 64 <160000000>; 2553 required-opps = <&rpmhpd_opp_low_svs>; 2554 }; 2555 2556 opp-270000000 { 2557 opp-hz = /bits/ 64 <270000000>; 2558 required-opps = <&rpmhpd_opp_svs>; 2559 }; 2560 2561 opp-540000000 { 2562 opp-hz = /bits/ 64 <540000000>; 2563 required-opps = <&rpmhpd_opp_svs_l1>; 2564 }; 2565 2566 opp-810000000 { 2567 opp-hz = /bits/ 64 <810000000>; 2568 required-opps = <&rpmhpd_opp_nom>; 2569 }; 2570 }; 2571 }; 2572 2573 mdss_dsi0: dsi@ae94000 { 2574 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2575 reg = <0 0x0ae94000 0 0x400>; 2576 reg-names = "dsi_ctrl"; 2577 2578 interrupt-parent = <&mdss>; 2579 interrupts = <4>; 2580 2581 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2582 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2583 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2584 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2585 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2586 <&gcc GCC_DISP_HF_AXI_CLK>; 2587 clock-names = "byte", 2588 "byte_intf", 2589 "pixel", 2590 "core", 2591 "iface", 2592 "bus"; 2593 2594 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2595 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2596 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2597 <&mdss_dsi0_phy 1>; 2598 2599 operating-points-v2 = <&dsi0_opp_table>; 2600 power-domains = <&rpmhpd SM8350_MMCX>; 2601 2602 phys = <&mdss_dsi0_phy>; 2603 2604 #address-cells = <1>; 2605 #size-cells = <0>; 2606 2607 status = "disabled"; 2608 2609 dsi0_opp_table: opp-table { 2610 compatible = "operating-points-v2"; 2611 2612 /* TODO: opp-187500000 should work with 2613 * &rpmhpd_opp_low_svs, but one some of 2614 * sm8350_hdk boards reboot using this 2615 * opp. 2616 */ 2617 opp-187500000 { 2618 opp-hz = /bits/ 64 <187500000>; 2619 required-opps = <&rpmhpd_opp_svs>; 2620 }; 2621 2622 opp-300000000 { 2623 opp-hz = /bits/ 64 <300000000>; 2624 required-opps = <&rpmhpd_opp_svs>; 2625 }; 2626 2627 opp-358000000 { 2628 opp-hz = /bits/ 64 <358000000>; 2629 required-opps = <&rpmhpd_opp_svs_l1>; 2630 }; 2631 }; 2632 2633 ports { 2634 #address-cells = <1>; 2635 #size-cells = <0>; 2636 2637 port@0 { 2638 reg = <0>; 2639 mdss_dsi0_in: endpoint { 2640 remote-endpoint = <&dpu_intf1_out>; 2641 }; 2642 }; 2643 2644 port@1 { 2645 reg = <1>; 2646 mdss_dsi0_out: endpoint { 2647 }; 2648 }; 2649 }; 2650 }; 2651 2652 mdss_dsi0_phy: phy@ae94400 { 2653 compatible = "qcom,sm8350-dsi-phy-5nm"; 2654 reg = <0 0x0ae94400 0 0x200>, 2655 <0 0x0ae94600 0 0x280>, 2656 <0 0x0ae94900 0 0x27c>; 2657 reg-names = "dsi_phy", 2658 "dsi_phy_lane", 2659 "dsi_pll"; 2660 2661 #clock-cells = <1>; 2662 #phy-cells = <0>; 2663 2664 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2665 <&rpmhcc RPMH_CXO_CLK>; 2666 clock-names = "iface", "ref"; 2667 2668 status = "disabled"; 2669 }; 2670 2671 mdss_dsi1: dsi@ae96000 { 2672 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2673 reg = <0 0x0ae96000 0 0x400>; 2674 reg-names = "dsi_ctrl"; 2675 2676 interrupt-parent = <&mdss>; 2677 interrupts = <5>; 2678 2679 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2680 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2681 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2682 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2683 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2684 <&gcc GCC_DISP_HF_AXI_CLK>; 2685 clock-names = "byte", 2686 "byte_intf", 2687 "pixel", 2688 "core", 2689 "iface", 2690 "bus"; 2691 2692 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2693 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2694 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2695 <&mdss_dsi1_phy 1>; 2696 2697 operating-points-v2 = <&dsi1_opp_table>; 2698 power-domains = <&rpmhpd SM8350_MMCX>; 2699 2700 phys = <&mdss_dsi1_phy>; 2701 2702 #address-cells = <1>; 2703 #size-cells = <0>; 2704 2705 status = "disabled"; 2706 2707 dsi1_opp_table: opp-table { 2708 compatible = "operating-points-v2"; 2709 2710 /* TODO: opp-187500000 should work with 2711 * &rpmhpd_opp_low_svs, but one some of 2712 * sm8350_hdk boards reboot using this 2713 * opp. 2714 */ 2715 opp-187500000 { 2716 opp-hz = /bits/ 64 <187500000>; 2717 required-opps = <&rpmhpd_opp_svs>; 2718 }; 2719 2720 opp-300000000 { 2721 opp-hz = /bits/ 64 <300000000>; 2722 required-opps = <&rpmhpd_opp_svs>; 2723 }; 2724 2725 opp-358000000 { 2726 opp-hz = /bits/ 64 <358000000>; 2727 required-opps = <&rpmhpd_opp_svs_l1>; 2728 }; 2729 }; 2730 2731 ports { 2732 #address-cells = <1>; 2733 #size-cells = <0>; 2734 2735 port@0 { 2736 reg = <0>; 2737 mdss_dsi1_in: endpoint { 2738 remote-endpoint = <&dpu_intf2_out>; 2739 }; 2740 }; 2741 2742 port@1 { 2743 reg = <1>; 2744 mdss_dsi1_out: endpoint { 2745 }; 2746 }; 2747 }; 2748 }; 2749 2750 mdss_dsi1_phy: phy@ae96400 { 2751 compatible = "qcom,sm8350-dsi-phy-5nm"; 2752 reg = <0 0x0ae96400 0 0x200>, 2753 <0 0x0ae96600 0 0x280>, 2754 <0 0x0ae96900 0 0x27c>; 2755 reg-names = "dsi_phy", 2756 "dsi_phy_lane", 2757 "dsi_pll"; 2758 2759 #clock-cells = <1>; 2760 #phy-cells = <0>; 2761 2762 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2763 <&rpmhcc RPMH_CXO_CLK>; 2764 clock-names = "iface", "ref"; 2765 2766 status = "disabled"; 2767 }; 2768 }; 2769 2770 dispcc: clock-controller@af00000 { 2771 compatible = "qcom,sm8350-dispcc"; 2772 reg = <0 0x0af00000 0 0x10000>; 2773 clocks = <&rpmhcc RPMH_CXO_CLK>, 2774 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 2775 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 2776 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2777 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2778 clock-names = "bi_tcxo", 2779 "dsi0_phy_pll_out_byteclk", 2780 "dsi0_phy_pll_out_dsiclk", 2781 "dsi1_phy_pll_out_byteclk", 2782 "dsi1_phy_pll_out_dsiclk", 2783 "dp_phy_pll_link_clk", 2784 "dp_phy_pll_vco_div_clk"; 2785 #clock-cells = <1>; 2786 #reset-cells = <1>; 2787 #power-domain-cells = <1>; 2788 2789 power-domains = <&rpmhpd SM8350_MMCX>; 2790 }; 2791 2792 pdc: interrupt-controller@b220000 { 2793 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 2794 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2795 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 2796 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 2797 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 2798 <156 716 12>; 2799 #interrupt-cells = <2>; 2800 interrupt-parent = <&intc>; 2801 interrupt-controller; 2802 }; 2803 2804 tsens0: thermal-sensor@c263000 { 2805 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2806 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2807 <0 0x0c222000 0 0x8>; /* SROT */ 2808 #qcom,sensors = <15>; 2809 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2810 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2811 interrupt-names = "uplow", "critical"; 2812 #thermal-sensor-cells = <1>; 2813 }; 2814 2815 tsens1: thermal-sensor@c265000 { 2816 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2817 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2818 <0 0x0c223000 0 0x8>; /* SROT */ 2819 #qcom,sensors = <14>; 2820 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2821 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2822 interrupt-names = "uplow", "critical"; 2823 #thermal-sensor-cells = <1>; 2824 }; 2825 2826 aoss_qmp: power-management@c300000 { 2827 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 2828 reg = <0 0x0c300000 0 0x400>; 2829 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2830 IRQ_TYPE_EDGE_RISING>; 2831 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2832 2833 #clock-cells = <0>; 2834 }; 2835 2836 sram@c3f0000 { 2837 compatible = "qcom,rpmh-stats"; 2838 reg = <0 0x0c3f0000 0 0x400>; 2839 }; 2840 2841 spmi_bus: spmi@c440000 { 2842 compatible = "qcom,spmi-pmic-arb"; 2843 reg = <0x0 0x0c440000 0x0 0x1100>, 2844 <0x0 0x0c600000 0x0 0x2000000>, 2845 <0x0 0x0e600000 0x0 0x100000>, 2846 <0x0 0x0e700000 0x0 0xa0000>, 2847 <0x0 0x0c40a000 0x0 0x26000>; 2848 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2849 interrupt-names = "periph_irq"; 2850 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2851 qcom,ee = <0>; 2852 qcom,channel = <0>; 2853 #address-cells = <2>; 2854 #size-cells = <0>; 2855 interrupt-controller; 2856 #interrupt-cells = <4>; 2857 }; 2858 2859 tlmm: pinctrl@f100000 { 2860 compatible = "qcom,sm8350-tlmm"; 2861 reg = <0 0x0f100000 0 0x300000>; 2862 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2863 gpio-controller; 2864 #gpio-cells = <2>; 2865 interrupt-controller; 2866 #interrupt-cells = <2>; 2867 gpio-ranges = <&tlmm 0 0 204>; 2868 wakeup-parent = <&pdc>; 2869 2870 sdc2_default_state: sdc2-default-state { 2871 clk-pins { 2872 pins = "sdc2_clk"; 2873 drive-strength = <16>; 2874 bias-disable; 2875 }; 2876 2877 cmd-pins { 2878 pins = "sdc2_cmd"; 2879 drive-strength = <16>; 2880 bias-pull-up; 2881 }; 2882 2883 data-pins { 2884 pins = "sdc2_data"; 2885 drive-strength = <16>; 2886 bias-pull-up; 2887 }; 2888 }; 2889 2890 sdc2_sleep_state: sdc2-sleep-state { 2891 clk-pins { 2892 pins = "sdc2_clk"; 2893 drive-strength = <2>; 2894 bias-disable; 2895 }; 2896 2897 cmd-pins { 2898 pins = "sdc2_cmd"; 2899 drive-strength = <2>; 2900 bias-pull-up; 2901 }; 2902 2903 data-pins { 2904 pins = "sdc2_data"; 2905 drive-strength = <2>; 2906 bias-pull-up; 2907 }; 2908 }; 2909 2910 qup_uart3_default_state: qup-uart3-default-state { 2911 rx-pins { 2912 pins = "gpio18"; 2913 function = "qup3"; 2914 }; 2915 tx-pins { 2916 pins = "gpio19"; 2917 function = "qup3"; 2918 }; 2919 }; 2920 2921 qup_uart6_default: qup-uart6-default-state { 2922 pins = "gpio30", "gpio31"; 2923 function = "qup6"; 2924 drive-strength = <2>; 2925 bias-disable; 2926 }; 2927 2928 qup_uart18_default: qup-uart18-default-state { 2929 pins = "gpio58", "gpio59"; 2930 function = "qup18"; 2931 drive-strength = <2>; 2932 bias-disable; 2933 }; 2934 2935 qup_i2c0_default: qup-i2c0-default-state { 2936 pins = "gpio4", "gpio5"; 2937 function = "qup0"; 2938 drive-strength = <2>; 2939 bias-pull-up; 2940 }; 2941 2942 qup_i2c1_default: qup-i2c1-default-state { 2943 pins = "gpio8", "gpio9"; 2944 function = "qup1"; 2945 drive-strength = <2>; 2946 bias-pull-up; 2947 }; 2948 2949 qup_i2c2_default: qup-i2c2-default-state { 2950 pins = "gpio12", "gpio13"; 2951 function = "qup2"; 2952 drive-strength = <2>; 2953 bias-pull-up; 2954 }; 2955 2956 qup_i2c4_default: qup-i2c4-default-state { 2957 pins = "gpio20", "gpio21"; 2958 function = "qup4"; 2959 drive-strength = <2>; 2960 bias-pull-up; 2961 }; 2962 2963 qup_i2c5_default: qup-i2c5-default-state { 2964 pins = "gpio24", "gpio25"; 2965 function = "qup5"; 2966 drive-strength = <2>; 2967 bias-pull-up; 2968 }; 2969 2970 qup_i2c6_default: qup-i2c6-default-state { 2971 pins = "gpio28", "gpio29"; 2972 function = "qup6"; 2973 drive-strength = <2>; 2974 bias-pull-up; 2975 }; 2976 2977 qup_i2c7_default: qup-i2c7-default-state { 2978 pins = "gpio32", "gpio33"; 2979 function = "qup7"; 2980 drive-strength = <2>; 2981 bias-disable; 2982 }; 2983 2984 qup_i2c8_default: qup-i2c8-default-state { 2985 pins = "gpio36", "gpio37"; 2986 function = "qup8"; 2987 drive-strength = <2>; 2988 bias-pull-up; 2989 }; 2990 2991 qup_i2c9_default: qup-i2c9-default-state { 2992 pins = "gpio40", "gpio41"; 2993 function = "qup9"; 2994 drive-strength = <2>; 2995 bias-pull-up; 2996 }; 2997 2998 qup_i2c10_default: qup-i2c10-default-state { 2999 pins = "gpio44", "gpio45"; 3000 function = "qup10"; 3001 drive-strength = <2>; 3002 bias-pull-up; 3003 }; 3004 3005 qup_i2c11_default: qup-i2c11-default-state { 3006 pins = "gpio48", "gpio49"; 3007 function = "qup11"; 3008 drive-strength = <2>; 3009 bias-pull-up; 3010 }; 3011 3012 qup_i2c12_default: qup-i2c12-default-state { 3013 pins = "gpio52", "gpio53"; 3014 function = "qup12"; 3015 drive-strength = <2>; 3016 bias-pull-up; 3017 }; 3018 3019 qup_i2c13_default: qup-i2c13-default-state { 3020 pins = "gpio0", "gpio1"; 3021 function = "qup13"; 3022 drive-strength = <2>; 3023 bias-pull-up; 3024 }; 3025 3026 qup_i2c14_default: qup-i2c14-default-state { 3027 pins = "gpio56", "gpio57"; 3028 function = "qup14"; 3029 drive-strength = <2>; 3030 bias-disable; 3031 }; 3032 3033 qup_i2c15_default: qup-i2c15-default-state { 3034 pins = "gpio60", "gpio61"; 3035 function = "qup15"; 3036 drive-strength = <2>; 3037 bias-disable; 3038 }; 3039 3040 qup_i2c16_default: qup-i2c16-default-state { 3041 pins = "gpio64", "gpio65"; 3042 function = "qup16"; 3043 drive-strength = <2>; 3044 bias-disable; 3045 }; 3046 3047 qup_i2c17_default: qup-i2c17-default-state { 3048 pins = "gpio72", "gpio73"; 3049 function = "qup17"; 3050 drive-strength = <2>; 3051 bias-disable; 3052 }; 3053 3054 qup_i2c19_default: qup-i2c19-default-state { 3055 pins = "gpio76", "gpio77"; 3056 function = "qup19"; 3057 drive-strength = <2>; 3058 bias-disable; 3059 }; 3060 }; 3061 3062 apps_smmu: iommu@15000000 { 3063 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3064 reg = <0 0x15000000 0 0x100000>; 3065 #iommu-cells = <2>; 3066 #global-interrupts = <2>; 3067 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3068 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3069 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3070 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3071 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3072 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3073 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3074 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3076 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3077 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3078 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3079 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3080 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3088 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3089 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3090 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3091 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3092 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3095 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3099 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3100 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3101 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3104 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3119 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3124 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3145 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3149 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3150 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3161 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3162 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3163 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3164 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3165 }; 3166 3167 adsp: remoteproc@17300000 { 3168 compatible = "qcom,sm8350-adsp-pas"; 3169 reg = <0 0x17300000 0 0x100>; 3170 3171 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3172 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3173 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3174 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3175 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3176 interrupt-names = "wdog", "fatal", "ready", 3177 "handover", "stop-ack"; 3178 3179 clocks = <&rpmhcc RPMH_CXO_CLK>; 3180 clock-names = "xo"; 3181 3182 power-domains = <&rpmhpd SM8350_LCX>, 3183 <&rpmhpd SM8350_LMX>; 3184 power-domain-names = "lcx", "lmx"; 3185 3186 memory-region = <&pil_adsp_mem>; 3187 3188 qcom,qmp = <&aoss_qmp>; 3189 3190 qcom,smem-states = <&smp2p_adsp_out 0>; 3191 qcom,smem-state-names = "stop"; 3192 3193 status = "disabled"; 3194 3195 glink-edge { 3196 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3197 IPCC_MPROC_SIGNAL_GLINK_QMP 3198 IRQ_TYPE_EDGE_RISING>; 3199 mboxes = <&ipcc IPCC_CLIENT_LPASS 3200 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3201 3202 label = "lpass"; 3203 qcom,remote-pid = <2>; 3204 3205 fastrpc { 3206 compatible = "qcom,fastrpc"; 3207 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3208 label = "adsp"; 3209 qcom,non-secure-domain; 3210 #address-cells = <1>; 3211 #size-cells = <0>; 3212 3213 compute-cb@3 { 3214 compatible = "qcom,fastrpc-compute-cb"; 3215 reg = <3>; 3216 iommus = <&apps_smmu 0x1803 0x0>; 3217 }; 3218 3219 compute-cb@4 { 3220 compatible = "qcom,fastrpc-compute-cb"; 3221 reg = <4>; 3222 iommus = <&apps_smmu 0x1804 0x0>; 3223 }; 3224 3225 compute-cb@5 { 3226 compatible = "qcom,fastrpc-compute-cb"; 3227 reg = <5>; 3228 iommus = <&apps_smmu 0x1805 0x0>; 3229 }; 3230 }; 3231 }; 3232 }; 3233 3234 intc: interrupt-controller@17a00000 { 3235 compatible = "arm,gic-v3"; 3236 #interrupt-cells = <3>; 3237 interrupt-controller; 3238 #redistributor-regions = <1>; 3239 redistributor-stride = <0 0x20000>; 3240 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3241 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3242 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3243 }; 3244 3245 timer@17c20000 { 3246 compatible = "arm,armv7-timer-mem"; 3247 #address-cells = <1>; 3248 #size-cells = <1>; 3249 ranges = <0 0 0 0x20000000>; 3250 reg = <0x0 0x17c20000 0x0 0x1000>; 3251 clock-frequency = <19200000>; 3252 3253 frame@17c21000 { 3254 frame-number = <0>; 3255 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3257 reg = <0x17c21000 0x1000>, 3258 <0x17c22000 0x1000>; 3259 }; 3260 3261 frame@17c23000 { 3262 frame-number = <1>; 3263 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3264 reg = <0x17c23000 0x1000>; 3265 status = "disabled"; 3266 }; 3267 3268 frame@17c25000 { 3269 frame-number = <2>; 3270 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3271 reg = <0x17c25000 0x1000>; 3272 status = "disabled"; 3273 }; 3274 3275 frame@17c27000 { 3276 frame-number = <3>; 3277 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3278 reg = <0x17c27000 0x1000>; 3279 status = "disabled"; 3280 }; 3281 3282 frame@17c29000 { 3283 frame-number = <4>; 3284 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3285 reg = <0x17c29000 0x1000>; 3286 status = "disabled"; 3287 }; 3288 3289 frame@17c2b000 { 3290 frame-number = <5>; 3291 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3292 reg = <0x17c2b000 0x1000>; 3293 status = "disabled"; 3294 }; 3295 3296 frame@17c2d000 { 3297 frame-number = <6>; 3298 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3299 reg = <0x17c2d000 0x1000>; 3300 status = "disabled"; 3301 }; 3302 }; 3303 3304 apps_rsc: rsc@18200000 { 3305 label = "apps_rsc"; 3306 compatible = "qcom,rpmh-rsc"; 3307 reg = <0x0 0x18200000 0x0 0x10000>, 3308 <0x0 0x18210000 0x0 0x10000>, 3309 <0x0 0x18220000 0x0 0x10000>; 3310 reg-names = "drv-0", "drv-1", "drv-2"; 3311 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3314 qcom,tcs-offset = <0xd00>; 3315 qcom,drv-id = <2>; 3316 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3317 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3318 power-domains = <&CLUSTER_PD>; 3319 3320 rpmhcc: clock-controller { 3321 compatible = "qcom,sm8350-rpmh-clk"; 3322 #clock-cells = <1>; 3323 clock-names = "xo"; 3324 clocks = <&xo_board>; 3325 }; 3326 3327 rpmhpd: power-controller { 3328 compatible = "qcom,sm8350-rpmhpd"; 3329 #power-domain-cells = <1>; 3330 operating-points-v2 = <&rpmhpd_opp_table>; 3331 3332 rpmhpd_opp_table: opp-table { 3333 compatible = "operating-points-v2"; 3334 3335 rpmhpd_opp_ret: opp1 { 3336 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3337 }; 3338 3339 rpmhpd_opp_min_svs: opp2 { 3340 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3341 }; 3342 3343 rpmhpd_opp_low_svs: opp3 { 3344 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3345 }; 3346 3347 rpmhpd_opp_svs: opp4 { 3348 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3349 }; 3350 3351 rpmhpd_opp_svs_l1: opp5 { 3352 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3353 }; 3354 3355 rpmhpd_opp_nom: opp6 { 3356 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3357 }; 3358 3359 rpmhpd_opp_nom_l1: opp7 { 3360 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3361 }; 3362 3363 rpmhpd_opp_nom_l2: opp8 { 3364 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3365 }; 3366 3367 rpmhpd_opp_turbo: opp9 { 3368 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3369 }; 3370 3371 rpmhpd_opp_turbo_l1: opp10 { 3372 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3373 }; 3374 }; 3375 }; 3376 3377 apps_bcm_voter: bcm-voter { 3378 compatible = "qcom,bcm-voter"; 3379 }; 3380 }; 3381 3382 cpufreq_hw: cpufreq@18591000 { 3383 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3384 reg = <0 0x18591000 0 0x1000>, 3385 <0 0x18592000 0 0x1000>, 3386 <0 0x18593000 0 0x1000>; 3387 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3388 3389 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3390 clock-names = "xo", "alternate"; 3391 3392 #freq-domain-cells = <1>; 3393 #clock-cells = <1>; 3394 }; 3395 3396 cdsp: remoteproc@98900000 { 3397 compatible = "qcom,sm8350-cdsp-pas"; 3398 reg = <0 0x98900000 0 0x1400000>; 3399 3400 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3401 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3402 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3403 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3404 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3405 interrupt-names = "wdog", "fatal", "ready", 3406 "handover", "stop-ack"; 3407 3408 clocks = <&rpmhcc RPMH_CXO_CLK>; 3409 clock-names = "xo"; 3410 3411 power-domains = <&rpmhpd SM8350_CX>, 3412 <&rpmhpd SM8350_MXC>; 3413 power-domain-names = "cx", "mxc"; 3414 3415 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3416 3417 memory-region = <&pil_cdsp_mem>; 3418 3419 qcom,qmp = <&aoss_qmp>; 3420 3421 qcom,smem-states = <&smp2p_cdsp_out 0>; 3422 qcom,smem-state-names = "stop"; 3423 3424 status = "disabled"; 3425 3426 glink-edge { 3427 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3428 IPCC_MPROC_SIGNAL_GLINK_QMP 3429 IRQ_TYPE_EDGE_RISING>; 3430 mboxes = <&ipcc IPCC_CLIENT_CDSP 3431 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3432 3433 label = "cdsp"; 3434 qcom,remote-pid = <5>; 3435 3436 fastrpc { 3437 compatible = "qcom,fastrpc"; 3438 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3439 label = "cdsp"; 3440 qcom,non-secure-domain; 3441 #address-cells = <1>; 3442 #size-cells = <0>; 3443 3444 compute-cb@1 { 3445 compatible = "qcom,fastrpc-compute-cb"; 3446 reg = <1>; 3447 iommus = <&apps_smmu 0x2161 0x0400>, 3448 <&apps_smmu 0x1181 0x0420>; 3449 }; 3450 3451 compute-cb@2 { 3452 compatible = "qcom,fastrpc-compute-cb"; 3453 reg = <2>; 3454 iommus = <&apps_smmu 0x2162 0x0400>, 3455 <&apps_smmu 0x1182 0x0420>; 3456 }; 3457 3458 compute-cb@3 { 3459 compatible = "qcom,fastrpc-compute-cb"; 3460 reg = <3>; 3461 iommus = <&apps_smmu 0x2163 0x0400>, 3462 <&apps_smmu 0x1183 0x0420>; 3463 }; 3464 3465 compute-cb@4 { 3466 compatible = "qcom,fastrpc-compute-cb"; 3467 reg = <4>; 3468 iommus = <&apps_smmu 0x2164 0x0400>, 3469 <&apps_smmu 0x1184 0x0420>; 3470 }; 3471 3472 compute-cb@5 { 3473 compatible = "qcom,fastrpc-compute-cb"; 3474 reg = <5>; 3475 iommus = <&apps_smmu 0x2165 0x0400>, 3476 <&apps_smmu 0x1185 0x0420>; 3477 }; 3478 3479 compute-cb@6 { 3480 compatible = "qcom,fastrpc-compute-cb"; 3481 reg = <6>; 3482 iommus = <&apps_smmu 0x2166 0x0400>, 3483 <&apps_smmu 0x1186 0x0420>; 3484 }; 3485 3486 compute-cb@7 { 3487 compatible = "qcom,fastrpc-compute-cb"; 3488 reg = <7>; 3489 iommus = <&apps_smmu 0x2167 0x0400>, 3490 <&apps_smmu 0x1187 0x0420>; 3491 }; 3492 3493 compute-cb@8 { 3494 compatible = "qcom,fastrpc-compute-cb"; 3495 reg = <8>; 3496 iommus = <&apps_smmu 0x2168 0x0400>, 3497 <&apps_smmu 0x1188 0x0420>; 3498 }; 3499 3500 /* note: secure cb9 in downstream */ 3501 }; 3502 }; 3503 }; 3504 }; 3505 3506 thermal_zones: thermal-zones { 3507 cpu0-thermal { 3508 polling-delay-passive = <250>; 3509 polling-delay = <1000>; 3510 3511 thermal-sensors = <&tsens0 1>; 3512 3513 trips { 3514 cpu0_alert0: trip-point0 { 3515 temperature = <90000>; 3516 hysteresis = <2000>; 3517 type = "passive"; 3518 }; 3519 3520 cpu0_alert1: trip-point1 { 3521 temperature = <95000>; 3522 hysteresis = <2000>; 3523 type = "passive"; 3524 }; 3525 3526 cpu0_crit: cpu-crit { 3527 temperature = <110000>; 3528 hysteresis = <1000>; 3529 type = "critical"; 3530 }; 3531 }; 3532 3533 cooling-maps { 3534 map0 { 3535 trip = <&cpu0_alert0>; 3536 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3537 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3538 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3539 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3540 }; 3541 map1 { 3542 trip = <&cpu0_alert1>; 3543 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3544 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3545 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3546 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3547 }; 3548 }; 3549 }; 3550 3551 cpu1-thermal { 3552 polling-delay-passive = <250>; 3553 polling-delay = <1000>; 3554 3555 thermal-sensors = <&tsens0 2>; 3556 3557 trips { 3558 cpu1_alert0: trip-point0 { 3559 temperature = <90000>; 3560 hysteresis = <2000>; 3561 type = "passive"; 3562 }; 3563 3564 cpu1_alert1: trip-point1 { 3565 temperature = <95000>; 3566 hysteresis = <2000>; 3567 type = "passive"; 3568 }; 3569 3570 cpu1_crit: cpu-crit { 3571 temperature = <110000>; 3572 hysteresis = <1000>; 3573 type = "critical"; 3574 }; 3575 }; 3576 3577 cooling-maps { 3578 map0 { 3579 trip = <&cpu1_alert0>; 3580 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3581 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3582 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3583 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3584 }; 3585 map1 { 3586 trip = <&cpu1_alert1>; 3587 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3588 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3589 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3590 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3591 }; 3592 }; 3593 }; 3594 3595 cpu2-thermal { 3596 polling-delay-passive = <250>; 3597 polling-delay = <1000>; 3598 3599 thermal-sensors = <&tsens0 3>; 3600 3601 trips { 3602 cpu2_alert0: trip-point0 { 3603 temperature = <90000>; 3604 hysteresis = <2000>; 3605 type = "passive"; 3606 }; 3607 3608 cpu2_alert1: trip-point1 { 3609 temperature = <95000>; 3610 hysteresis = <2000>; 3611 type = "passive"; 3612 }; 3613 3614 cpu2_crit: cpu-crit { 3615 temperature = <110000>; 3616 hysteresis = <1000>; 3617 type = "critical"; 3618 }; 3619 }; 3620 3621 cooling-maps { 3622 map0 { 3623 trip = <&cpu2_alert0>; 3624 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3625 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3626 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3627 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3628 }; 3629 map1 { 3630 trip = <&cpu2_alert1>; 3631 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3632 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3633 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3634 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3635 }; 3636 }; 3637 }; 3638 3639 cpu3-thermal { 3640 polling-delay-passive = <250>; 3641 polling-delay = <1000>; 3642 3643 thermal-sensors = <&tsens0 4>; 3644 3645 trips { 3646 cpu3_alert0: trip-point0 { 3647 temperature = <90000>; 3648 hysteresis = <2000>; 3649 type = "passive"; 3650 }; 3651 3652 cpu3_alert1: trip-point1 { 3653 temperature = <95000>; 3654 hysteresis = <2000>; 3655 type = "passive"; 3656 }; 3657 3658 cpu3_crit: cpu-crit { 3659 temperature = <110000>; 3660 hysteresis = <1000>; 3661 type = "critical"; 3662 }; 3663 }; 3664 3665 cooling-maps { 3666 map0 { 3667 trip = <&cpu3_alert0>; 3668 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3669 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3670 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3671 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3672 }; 3673 map1 { 3674 trip = <&cpu3_alert1>; 3675 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3676 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3677 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3678 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3679 }; 3680 }; 3681 }; 3682 3683 cpu4-top-thermal { 3684 polling-delay-passive = <250>; 3685 polling-delay = <1000>; 3686 3687 thermal-sensors = <&tsens0 7>; 3688 3689 trips { 3690 cpu4_top_alert0: trip-point0 { 3691 temperature = <90000>; 3692 hysteresis = <2000>; 3693 type = "passive"; 3694 }; 3695 3696 cpu4_top_alert1: trip-point1 { 3697 temperature = <95000>; 3698 hysteresis = <2000>; 3699 type = "passive"; 3700 }; 3701 3702 cpu4_top_crit: cpu-crit { 3703 temperature = <110000>; 3704 hysteresis = <1000>; 3705 type = "critical"; 3706 }; 3707 }; 3708 3709 cooling-maps { 3710 map0 { 3711 trip = <&cpu4_top_alert0>; 3712 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3713 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3714 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3715 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3716 }; 3717 map1 { 3718 trip = <&cpu4_top_alert1>; 3719 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3720 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3721 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3722 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3723 }; 3724 }; 3725 }; 3726 3727 cpu5-top-thermal { 3728 polling-delay-passive = <250>; 3729 polling-delay = <1000>; 3730 3731 thermal-sensors = <&tsens0 8>; 3732 3733 trips { 3734 cpu5_top_alert0: trip-point0 { 3735 temperature = <90000>; 3736 hysteresis = <2000>; 3737 type = "passive"; 3738 }; 3739 3740 cpu5_top_alert1: trip-point1 { 3741 temperature = <95000>; 3742 hysteresis = <2000>; 3743 type = "passive"; 3744 }; 3745 3746 cpu5_top_crit: cpu-crit { 3747 temperature = <110000>; 3748 hysteresis = <1000>; 3749 type = "critical"; 3750 }; 3751 }; 3752 3753 cooling-maps { 3754 map0 { 3755 trip = <&cpu5_top_alert0>; 3756 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3757 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3758 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3759 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3760 }; 3761 map1 { 3762 trip = <&cpu5_top_alert1>; 3763 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3764 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3765 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3766 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3767 }; 3768 }; 3769 }; 3770 3771 cpu6-top-thermal { 3772 polling-delay-passive = <250>; 3773 polling-delay = <1000>; 3774 3775 thermal-sensors = <&tsens0 9>; 3776 3777 trips { 3778 cpu6_top_alert0: trip-point0 { 3779 temperature = <90000>; 3780 hysteresis = <2000>; 3781 type = "passive"; 3782 }; 3783 3784 cpu6_top_alert1: trip-point1 { 3785 temperature = <95000>; 3786 hysteresis = <2000>; 3787 type = "passive"; 3788 }; 3789 3790 cpu6_top_crit: cpu-crit { 3791 temperature = <110000>; 3792 hysteresis = <1000>; 3793 type = "critical"; 3794 }; 3795 }; 3796 3797 cooling-maps { 3798 map0 { 3799 trip = <&cpu6_top_alert0>; 3800 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3801 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3802 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3803 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3804 }; 3805 map1 { 3806 trip = <&cpu6_top_alert1>; 3807 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3808 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3809 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3810 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3811 }; 3812 }; 3813 }; 3814 3815 cpu7-top-thermal { 3816 polling-delay-passive = <250>; 3817 polling-delay = <1000>; 3818 3819 thermal-sensors = <&tsens0 10>; 3820 3821 trips { 3822 cpu7_top_alert0: trip-point0 { 3823 temperature = <90000>; 3824 hysteresis = <2000>; 3825 type = "passive"; 3826 }; 3827 3828 cpu7_top_alert1: trip-point1 { 3829 temperature = <95000>; 3830 hysteresis = <2000>; 3831 type = "passive"; 3832 }; 3833 3834 cpu7_top_crit: cpu-crit { 3835 temperature = <110000>; 3836 hysteresis = <1000>; 3837 type = "critical"; 3838 }; 3839 }; 3840 3841 cooling-maps { 3842 map0 { 3843 trip = <&cpu7_top_alert0>; 3844 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3845 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3846 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3847 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3848 }; 3849 map1 { 3850 trip = <&cpu7_top_alert1>; 3851 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3852 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3853 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3854 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3855 }; 3856 }; 3857 }; 3858 3859 cpu4-bottom-thermal { 3860 polling-delay-passive = <250>; 3861 polling-delay = <1000>; 3862 3863 thermal-sensors = <&tsens0 11>; 3864 3865 trips { 3866 cpu4_bottom_alert0: trip-point0 { 3867 temperature = <90000>; 3868 hysteresis = <2000>; 3869 type = "passive"; 3870 }; 3871 3872 cpu4_bottom_alert1: trip-point1 { 3873 temperature = <95000>; 3874 hysteresis = <2000>; 3875 type = "passive"; 3876 }; 3877 3878 cpu4_bottom_crit: cpu-crit { 3879 temperature = <110000>; 3880 hysteresis = <1000>; 3881 type = "critical"; 3882 }; 3883 }; 3884 3885 cooling-maps { 3886 map0 { 3887 trip = <&cpu4_bottom_alert0>; 3888 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3889 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3890 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3891 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3892 }; 3893 map1 { 3894 trip = <&cpu4_bottom_alert1>; 3895 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3896 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3897 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3898 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3899 }; 3900 }; 3901 }; 3902 3903 cpu5-bottom-thermal { 3904 polling-delay-passive = <250>; 3905 polling-delay = <1000>; 3906 3907 thermal-sensors = <&tsens0 12>; 3908 3909 trips { 3910 cpu5_bottom_alert0: trip-point0 { 3911 temperature = <90000>; 3912 hysteresis = <2000>; 3913 type = "passive"; 3914 }; 3915 3916 cpu5_bottom_alert1: trip-point1 { 3917 temperature = <95000>; 3918 hysteresis = <2000>; 3919 type = "passive"; 3920 }; 3921 3922 cpu5_bottom_crit: cpu-crit { 3923 temperature = <110000>; 3924 hysteresis = <1000>; 3925 type = "critical"; 3926 }; 3927 }; 3928 3929 cooling-maps { 3930 map0 { 3931 trip = <&cpu5_bottom_alert0>; 3932 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3933 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3934 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3935 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3936 }; 3937 map1 { 3938 trip = <&cpu5_bottom_alert1>; 3939 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3940 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3941 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3942 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3943 }; 3944 }; 3945 }; 3946 3947 cpu6-bottom-thermal { 3948 polling-delay-passive = <250>; 3949 polling-delay = <1000>; 3950 3951 thermal-sensors = <&tsens0 13>; 3952 3953 trips { 3954 cpu6_bottom_alert0: trip-point0 { 3955 temperature = <90000>; 3956 hysteresis = <2000>; 3957 type = "passive"; 3958 }; 3959 3960 cpu6_bottom_alert1: trip-point1 { 3961 temperature = <95000>; 3962 hysteresis = <2000>; 3963 type = "passive"; 3964 }; 3965 3966 cpu6_bottom_crit: cpu-crit { 3967 temperature = <110000>; 3968 hysteresis = <1000>; 3969 type = "critical"; 3970 }; 3971 }; 3972 3973 cooling-maps { 3974 map0 { 3975 trip = <&cpu6_bottom_alert0>; 3976 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3977 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3978 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3979 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3980 }; 3981 map1 { 3982 trip = <&cpu6_bottom_alert1>; 3983 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3984 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3985 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3986 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3987 }; 3988 }; 3989 }; 3990 3991 cpu7-bottom-thermal { 3992 polling-delay-passive = <250>; 3993 polling-delay = <1000>; 3994 3995 thermal-sensors = <&tsens0 14>; 3996 3997 trips { 3998 cpu7_bottom_alert0: trip-point0 { 3999 temperature = <90000>; 4000 hysteresis = <2000>; 4001 type = "passive"; 4002 }; 4003 4004 cpu7_bottom_alert1: trip-point1 { 4005 temperature = <95000>; 4006 hysteresis = <2000>; 4007 type = "passive"; 4008 }; 4009 4010 cpu7_bottom_crit: cpu-crit { 4011 temperature = <110000>; 4012 hysteresis = <1000>; 4013 type = "critical"; 4014 }; 4015 }; 4016 4017 cooling-maps { 4018 map0 { 4019 trip = <&cpu7_bottom_alert0>; 4020 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4021 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4022 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4023 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4024 }; 4025 map1 { 4026 trip = <&cpu7_bottom_alert1>; 4027 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4028 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4029 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4030 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4031 }; 4032 }; 4033 }; 4034 4035 aoss0-thermal { 4036 polling-delay-passive = <250>; 4037 polling-delay = <1000>; 4038 4039 thermal-sensors = <&tsens0 0>; 4040 4041 trips { 4042 aoss0_alert0: trip-point0 { 4043 temperature = <90000>; 4044 hysteresis = <2000>; 4045 type = "hot"; 4046 }; 4047 }; 4048 }; 4049 4050 cluster0-thermal { 4051 polling-delay-passive = <250>; 4052 polling-delay = <1000>; 4053 4054 thermal-sensors = <&tsens0 5>; 4055 4056 trips { 4057 cluster0_alert0: trip-point0 { 4058 temperature = <90000>; 4059 hysteresis = <2000>; 4060 type = "hot"; 4061 }; 4062 cluster0_crit: cluster0_crit { 4063 temperature = <110000>; 4064 hysteresis = <2000>; 4065 type = "critical"; 4066 }; 4067 }; 4068 }; 4069 4070 cluster1-thermal { 4071 polling-delay-passive = <250>; 4072 polling-delay = <1000>; 4073 4074 thermal-sensors = <&tsens0 6>; 4075 4076 trips { 4077 cluster1_alert0: trip-point0 { 4078 temperature = <90000>; 4079 hysteresis = <2000>; 4080 type = "hot"; 4081 }; 4082 cluster1_crit: cluster1_crit { 4083 temperature = <110000>; 4084 hysteresis = <2000>; 4085 type = "critical"; 4086 }; 4087 }; 4088 }; 4089 4090 aoss1-thermal { 4091 polling-delay-passive = <250>; 4092 polling-delay = <1000>; 4093 4094 thermal-sensors = <&tsens1 0>; 4095 4096 trips { 4097 aoss1_alert0: trip-point0 { 4098 temperature = <90000>; 4099 hysteresis = <2000>; 4100 type = "hot"; 4101 }; 4102 }; 4103 }; 4104 4105 gpu-top-thermal { 4106 polling-delay-passive = <250>; 4107 polling-delay = <1000>; 4108 4109 thermal-sensors = <&tsens1 1>; 4110 4111 trips { 4112 gpu1_alert0: trip-point0 { 4113 temperature = <90000>; 4114 hysteresis = <1000>; 4115 type = "hot"; 4116 }; 4117 }; 4118 }; 4119 4120 gpu-bottom-thermal { 4121 polling-delay-passive = <250>; 4122 polling-delay = <1000>; 4123 4124 thermal-sensors = <&tsens1 2>; 4125 4126 trips { 4127 gpu2_alert0: trip-point0 { 4128 temperature = <90000>; 4129 hysteresis = <1000>; 4130 type = "hot"; 4131 }; 4132 }; 4133 }; 4134 4135 nspss1-thermal { 4136 polling-delay-passive = <250>; 4137 polling-delay = <1000>; 4138 4139 thermal-sensors = <&tsens1 3>; 4140 4141 trips { 4142 nspss1_alert0: trip-point0 { 4143 temperature = <90000>; 4144 hysteresis = <1000>; 4145 type = "hot"; 4146 }; 4147 }; 4148 }; 4149 4150 nspss2-thermal { 4151 polling-delay-passive = <250>; 4152 polling-delay = <1000>; 4153 4154 thermal-sensors = <&tsens1 4>; 4155 4156 trips { 4157 nspss2_alert0: trip-point0 { 4158 temperature = <90000>; 4159 hysteresis = <1000>; 4160 type = "hot"; 4161 }; 4162 }; 4163 }; 4164 4165 nspss3-thermal { 4166 polling-delay-passive = <250>; 4167 polling-delay = <1000>; 4168 4169 thermal-sensors = <&tsens1 5>; 4170 4171 trips { 4172 nspss3_alert0: trip-point0 { 4173 temperature = <90000>; 4174 hysteresis = <1000>; 4175 type = "hot"; 4176 }; 4177 }; 4178 }; 4179 4180 video-thermal { 4181 polling-delay-passive = <250>; 4182 polling-delay = <1000>; 4183 4184 thermal-sensors = <&tsens1 6>; 4185 4186 trips { 4187 video_alert0: trip-point0 { 4188 temperature = <90000>; 4189 hysteresis = <2000>; 4190 type = "hot"; 4191 }; 4192 }; 4193 }; 4194 4195 mem-thermal { 4196 polling-delay-passive = <250>; 4197 polling-delay = <1000>; 4198 4199 thermal-sensors = <&tsens1 7>; 4200 4201 trips { 4202 mem_alert0: trip-point0 { 4203 temperature = <90000>; 4204 hysteresis = <2000>; 4205 type = "hot"; 4206 }; 4207 }; 4208 }; 4209 4210 modem1-top-thermal { 4211 polling-delay-passive = <250>; 4212 polling-delay = <1000>; 4213 4214 thermal-sensors = <&tsens1 8>; 4215 4216 trips { 4217 modem1_alert0: trip-point0 { 4218 temperature = <90000>; 4219 hysteresis = <2000>; 4220 type = "hot"; 4221 }; 4222 }; 4223 }; 4224 4225 modem2-top-thermal { 4226 polling-delay-passive = <250>; 4227 polling-delay = <1000>; 4228 4229 thermal-sensors = <&tsens1 9>; 4230 4231 trips { 4232 modem2_alert0: trip-point0 { 4233 temperature = <90000>; 4234 hysteresis = <2000>; 4235 type = "hot"; 4236 }; 4237 }; 4238 }; 4239 4240 modem3-top-thermal { 4241 polling-delay-passive = <250>; 4242 polling-delay = <1000>; 4243 4244 thermal-sensors = <&tsens1 10>; 4245 4246 trips { 4247 modem3_alert0: trip-point0 { 4248 temperature = <90000>; 4249 hysteresis = <2000>; 4250 type = "hot"; 4251 }; 4252 }; 4253 }; 4254 4255 modem4-top-thermal { 4256 polling-delay-passive = <250>; 4257 polling-delay = <1000>; 4258 4259 thermal-sensors = <&tsens1 11>; 4260 4261 trips { 4262 modem4_alert0: trip-point0 { 4263 temperature = <90000>; 4264 hysteresis = <2000>; 4265 type = "hot"; 4266 }; 4267 }; 4268 }; 4269 4270 camera-top-thermal { 4271 polling-delay-passive = <250>; 4272 polling-delay = <1000>; 4273 4274 thermal-sensors = <&tsens1 12>; 4275 4276 trips { 4277 camera1_alert0: trip-point0 { 4278 temperature = <90000>; 4279 hysteresis = <2000>; 4280 type = "hot"; 4281 }; 4282 }; 4283 }; 4284 4285 cam-bottom-thermal { 4286 polling-delay-passive = <250>; 4287 polling-delay = <1000>; 4288 4289 thermal-sensors = <&tsens1 13>; 4290 4291 trips { 4292 camera2_alert0: trip-point0 { 4293 temperature = <90000>; 4294 hysteresis = <2000>; 4295 type = "hot"; 4296 }; 4297 }; 4298 }; 4299 }; 4300 4301 timer { 4302 compatible = "arm,armv8-timer"; 4303 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4304 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4305 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4306 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4307 }; 4308}; 4309