1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 13 #include <drm/drm_atomic.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_blend.h> 16 #include <drm/drm_damage_helper.h> 17 #include <drm/drm_framebuffer.h> 18 #include <drm/drm_gem_atomic_helper.h> 19 20 #include "msm_drv.h" 21 #include "dpu_kms.h" 22 #include "dpu_formats.h" 23 #include "dpu_hw_sspp.h" 24 #include "dpu_trace.h" 25 #include "dpu_crtc.h" 26 #include "dpu_vbif.h" 27 #include "dpu_plane.h" 28 29 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\ 30 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 31 32 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ 33 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 34 35 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 36 #define PHASE_STEP_SHIFT 21 37 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) 38 #define PHASE_RESIDUAL 15 39 40 #define SHARP_STRENGTH_DEFAULT 32 41 #define SHARP_EDGE_THR_DEFAULT 112 42 #define SHARP_SMOOTH_THR_DEFAULT 8 43 #define SHARP_NOISE_THR_DEFAULT 2 44 45 #define DPU_NAME_SIZE 12 46 47 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) 48 #define DPU_ZPOS_MAX 255 49 50 /* multirect rect index */ 51 enum { 52 R0, 53 R1, 54 R_MAX 55 }; 56 57 /* 58 * Default Preload Values 59 */ 60 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4 61 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3 62 #define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2 63 #define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4 64 65 #define DEFAULT_REFRESH_RATE 60 66 67 static const uint32_t qcom_compressed_supported_formats[] = { 68 DRM_FORMAT_ABGR8888, 69 DRM_FORMAT_ARGB8888, 70 DRM_FORMAT_XBGR8888, 71 DRM_FORMAT_XRGB8888, 72 DRM_FORMAT_BGR565, 73 74 DRM_FORMAT_NV12, 75 }; 76 77 /** 78 * enum dpu_plane_qos - Different qos configurations for each pipe 79 * 80 * @DPU_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe. 81 * @DPU_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe. 82 * this configuration is mutually exclusive from VBLANK_CTRL. 83 * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. 84 */ 85 enum dpu_plane_qos { 86 DPU_PLANE_QOS_VBLANK_CTRL = BIT(0), 87 DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), 88 DPU_PLANE_QOS_PANIC_CTRL = BIT(2), 89 }; 90 91 /* 92 * struct dpu_plane - local dpu plane structure 93 * @aspace: address space pointer 94 * @mplane_list: List of multirect planes of the same pipe 95 * @catalog: Points to dpu catalog structure 96 * @revalidate: force revalidation of all the plane properties 97 */ 98 struct dpu_plane { 99 struct drm_plane base; 100 101 struct mutex lock; 102 103 enum dpu_sspp pipe; 104 105 struct dpu_hw_pipe *pipe_hw; 106 uint32_t color_fill; 107 bool is_error; 108 bool is_rt_pipe; 109 bool is_virtual; 110 struct list_head mplane_list; 111 const struct dpu_mdss_cfg *catalog; 112 }; 113 114 static const uint64_t supported_format_modifiers[] = { 115 DRM_FORMAT_MOD_QCOM_COMPRESSED, 116 DRM_FORMAT_MOD_LINEAR, 117 DRM_FORMAT_MOD_INVALID 118 }; 119 120 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base) 121 122 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) 123 { 124 struct msm_drm_private *priv = plane->dev->dev_private; 125 126 return to_dpu_kms(priv->kms); 127 } 128 129 /** 130 * _dpu_plane_calc_bw - calculate bandwidth required for a plane 131 * @plane: Pointer to drm plane. 132 * @fb: Pointer to framebuffer associated with the given plane 133 * @pipe_cfg: Pointer to pipe configuration 134 * Result: Updates calculated bandwidth in the plane state. 135 * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest) 136 * Prefill BW Equation: line src bytes * line_time 137 */ 138 static void _dpu_plane_calc_bw(struct drm_plane *plane, 139 struct drm_framebuffer *fb, 140 struct dpu_hw_pipe_cfg *pipe_cfg) 141 { 142 struct dpu_plane_state *pstate; 143 struct drm_display_mode *mode; 144 const struct dpu_format *fmt = NULL; 145 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 146 int src_width, src_height, dst_height, fps; 147 u64 plane_prefill_bw; 148 u64 plane_bw; 149 u32 hw_latency_lines; 150 u64 scale_factor; 151 int vbp, vpw, vfp; 152 153 pstate = to_dpu_plane_state(plane->state); 154 mode = &plane->state->crtc->mode; 155 156 fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier); 157 158 src_width = drm_rect_width(&pipe_cfg->src_rect); 159 src_height = drm_rect_height(&pipe_cfg->src_rect); 160 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 161 fps = drm_mode_vrefresh(mode); 162 vbp = mode->vtotal - mode->vsync_end; 163 vpw = mode->vsync_end - mode->vsync_start; 164 vfp = mode->vsync_start - mode->vdisplay; 165 hw_latency_lines = dpu_kms->catalog->perf->min_prefill_lines; 166 scale_factor = src_height > dst_height ? 167 mult_frac(src_height, 1, dst_height) : 1; 168 169 plane_bw = 170 src_width * mode->vtotal * fps * fmt->bpp * 171 scale_factor; 172 173 plane_prefill_bw = 174 src_width * hw_latency_lines * fps * fmt->bpp * 175 scale_factor * mode->vtotal; 176 177 if ((vbp+vpw) > hw_latency_lines) 178 do_div(plane_prefill_bw, (vbp+vpw)); 179 else if ((vbp+vpw+vfp) < hw_latency_lines) 180 do_div(plane_prefill_bw, (vbp+vpw+vfp)); 181 else 182 do_div(plane_prefill_bw, hw_latency_lines); 183 184 185 pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw); 186 } 187 188 /** 189 * _dpu_plane_calc_clk - calculate clock required for a plane 190 * @plane: Pointer to drm plane. 191 * @pipe_cfg: Pointer to pipe configuration 192 * Result: Updates calculated clock in the plane state. 193 * Clock equation: dst_w * v_total * fps * (src_h / dst_h) 194 */ 195 static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_hw_pipe_cfg *pipe_cfg) 196 { 197 struct dpu_plane_state *pstate; 198 struct drm_display_mode *mode; 199 int dst_width, src_height, dst_height, fps; 200 201 pstate = to_dpu_plane_state(plane->state); 202 mode = &plane->state->crtc->mode; 203 204 src_height = drm_rect_height(&pipe_cfg->src_rect); 205 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 206 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 207 fps = drm_mode_vrefresh(mode); 208 209 pstate->plane_clk = 210 dst_width * mode->vtotal * fps; 211 212 if (src_height > dst_height) { 213 pstate->plane_clk *= src_height; 214 do_div(pstate->plane_clk, dst_height); 215 } 216 } 217 218 /** 219 * _dpu_plane_calc_fill_level - calculate fill level of the given source format 220 * @plane: Pointer to drm plane 221 * @fmt: Pointer to source buffer format 222 * @src_width: width of source buffer 223 * Return: fill level corresponding to the source buffer/format or 0 if error 224 */ 225 static int _dpu_plane_calc_fill_level(struct drm_plane *plane, 226 const struct dpu_format *fmt, u32 src_width) 227 { 228 struct dpu_plane *pdpu, *tmp; 229 struct dpu_plane_state *pstate; 230 u32 fixed_buff_size; 231 u32 total_fl; 232 233 if (!fmt || !plane->state || !src_width || !fmt->bpp) { 234 DPU_ERROR("invalid arguments\n"); 235 return 0; 236 } 237 238 pdpu = to_dpu_plane(plane); 239 pstate = to_dpu_plane_state(plane->state); 240 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; 241 242 list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) { 243 u32 tmp_width; 244 245 if (!tmp->base.state->visible) 246 continue; 247 tmp_width = drm_rect_width(&tmp->base.state->src) >> 16; 248 DPU_DEBUG("plane%d/%d src_width:%d/%d\n", 249 pdpu->base.base.id, tmp->base.base.id, 250 src_width, 251 tmp_width); 252 src_width = max_t(u32, src_width, 253 tmp_width); 254 } 255 256 if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) { 257 if (fmt->chroma_sample == DPU_CHROMA_420) { 258 /* NV12 */ 259 total_fl = (fixed_buff_size / 2) / 260 ((src_width + 32) * fmt->bpp); 261 } else { 262 /* non NV12 */ 263 total_fl = (fixed_buff_size / 2) * 2 / 264 ((src_width + 32) * fmt->bpp); 265 } 266 } else { 267 if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { 268 total_fl = (fixed_buff_size / 2) * 2 / 269 ((src_width + 32) * fmt->bpp); 270 } else { 271 total_fl = (fixed_buff_size) * 2 / 272 ((src_width + 32) * fmt->bpp); 273 } 274 } 275 276 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n", 277 pdpu->pipe - SSPP_VIG0, 278 (char *)&fmt->base.pixel_format, 279 src_width, total_fl); 280 281 return total_fl; 282 } 283 284 /** 285 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane 286 * @plane: Pointer to drm plane 287 * @fb: Pointer to framebuffer associated with the given plane 288 * @pipe_cfg: Pointer to pipe configuration 289 */ 290 static void _dpu_plane_set_qos_lut(struct drm_plane *plane, 291 struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg) 292 { 293 struct dpu_plane *pdpu = to_dpu_plane(plane); 294 const struct dpu_format *fmt = NULL; 295 u64 qos_lut; 296 u32 total_fl = 0, lut_usage; 297 298 if (!pdpu->is_rt_pipe) { 299 lut_usage = DPU_QOS_LUT_USAGE_NRT; 300 } else { 301 fmt = dpu_get_dpu_format_ext( 302 fb->format->format, 303 fb->modifier); 304 total_fl = _dpu_plane_calc_fill_level(plane, fmt, 305 drm_rect_width(&pipe_cfg->src_rect)); 306 307 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) 308 lut_usage = DPU_QOS_LUT_USAGE_LINEAR; 309 else 310 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; 311 } 312 313 qos_lut = _dpu_hw_get_qos_lut( 314 &pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl); 315 316 trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0, 317 (fmt) ? fmt->base.pixel_format : 0, 318 pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage); 319 320 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", 321 pdpu->pipe - SSPP_VIG0, 322 fmt ? (char *)&fmt->base.pixel_format : NULL, 323 pdpu->is_rt_pipe, total_fl, qos_lut); 324 325 pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut); 326 } 327 328 /** 329 * _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane 330 * @plane: Pointer to drm plane 331 * @fb: Pointer to framebuffer associated with the given plane 332 */ 333 static void _dpu_plane_set_danger_lut(struct drm_plane *plane, 334 struct drm_framebuffer *fb) 335 { 336 struct dpu_plane *pdpu = to_dpu_plane(plane); 337 const struct dpu_format *fmt = NULL; 338 u32 danger_lut, safe_lut; 339 340 if (!pdpu->is_rt_pipe) { 341 danger_lut = pdpu->catalog->perf->danger_lut_tbl 342 [DPU_QOS_LUT_USAGE_NRT]; 343 safe_lut = pdpu->catalog->perf->safe_lut_tbl 344 [DPU_QOS_LUT_USAGE_NRT]; 345 } else { 346 fmt = dpu_get_dpu_format_ext( 347 fb->format->format, 348 fb->modifier); 349 350 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) { 351 danger_lut = pdpu->catalog->perf->danger_lut_tbl 352 [DPU_QOS_LUT_USAGE_LINEAR]; 353 safe_lut = pdpu->catalog->perf->safe_lut_tbl 354 [DPU_QOS_LUT_USAGE_LINEAR]; 355 } else { 356 danger_lut = pdpu->catalog->perf->danger_lut_tbl 357 [DPU_QOS_LUT_USAGE_MACROTILE]; 358 safe_lut = pdpu->catalog->perf->safe_lut_tbl 359 [DPU_QOS_LUT_USAGE_MACROTILE]; 360 } 361 } 362 363 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, 364 (fmt) ? fmt->base.pixel_format : 0, 365 (fmt) ? fmt->fetch_mode : 0, 366 danger_lut, 367 safe_lut); 368 369 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", 370 pdpu->pipe - SSPP_VIG0, 371 fmt ? (char *)&fmt->base.pixel_format : NULL, 372 fmt ? fmt->fetch_mode : -1, 373 danger_lut, 374 safe_lut); 375 376 pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw, 377 danger_lut, safe_lut); 378 } 379 380 /** 381 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane 382 * @plane: Pointer to drm plane 383 * @enable: true to enable QoS control 384 * @flags: QoS control mode (enum dpu_plane_qos) 385 */ 386 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, 387 bool enable, u32 flags) 388 { 389 struct dpu_plane *pdpu = to_dpu_plane(plane); 390 struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; 391 392 memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); 393 394 if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { 395 pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank; 396 pipe_qos_cfg.danger_vblank = 397 pdpu->pipe_hw->cap->sblk->danger_vblank; 398 pipe_qos_cfg.vblank_en = enable; 399 } 400 401 if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) { 402 /* this feature overrules previous VBLANK_CTRL */ 403 pipe_qos_cfg.vblank_en = false; 404 pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ 405 } 406 407 if (flags & DPU_PLANE_QOS_PANIC_CTRL) 408 pipe_qos_cfg.danger_safe_en = enable; 409 410 if (!pdpu->is_rt_pipe) { 411 pipe_qos_cfg.vblank_en = false; 412 pipe_qos_cfg.danger_safe_en = false; 413 } 414 415 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", 416 pdpu->pipe - SSPP_VIG0, 417 pipe_qos_cfg.danger_safe_en, 418 pipe_qos_cfg.vblank_en, 419 pipe_qos_cfg.creq_vblank, 420 pipe_qos_cfg.danger_vblank, 421 pdpu->is_rt_pipe); 422 423 pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw, 424 &pipe_qos_cfg); 425 } 426 427 /** 428 * _dpu_plane_set_ot_limit - set OT limit for the given plane 429 * @plane: Pointer to drm plane 430 * @crtc: Pointer to drm crtc 431 * @pipe_cfg: Pointer to pipe configuration 432 */ 433 static void _dpu_plane_set_ot_limit(struct drm_plane *plane, 434 struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg) 435 { 436 struct dpu_plane *pdpu = to_dpu_plane(plane); 437 struct dpu_vbif_set_ot_params ot_params; 438 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 439 440 memset(&ot_params, 0, sizeof(ot_params)); 441 ot_params.xin_id = pdpu->pipe_hw->cap->xin_id; 442 ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE; 443 ot_params.width = drm_rect_width(&pipe_cfg->src_rect); 444 ot_params.height = drm_rect_height(&pipe_cfg->src_rect); 445 ot_params.is_wfd = !pdpu->is_rt_pipe; 446 ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); 447 ot_params.vbif_idx = VBIF_RT; 448 ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; 449 ot_params.rd = true; 450 451 dpu_vbif_set_ot_limit(dpu_kms, &ot_params); 452 } 453 454 /** 455 * _dpu_plane_set_qos_remap - set vbif QoS for the given plane 456 * @plane: Pointer to drm plane 457 */ 458 static void _dpu_plane_set_qos_remap(struct drm_plane *plane) 459 { 460 struct dpu_plane *pdpu = to_dpu_plane(plane); 461 struct dpu_vbif_set_qos_params qos_params; 462 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 463 464 memset(&qos_params, 0, sizeof(qos_params)); 465 qos_params.vbif_idx = VBIF_RT; 466 qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; 467 qos_params.xin_id = pdpu->pipe_hw->cap->xin_id; 468 qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0; 469 qos_params.is_rt = pdpu->is_rt_pipe; 470 471 DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", 472 qos_params.num, 473 qos_params.vbif_idx, 474 qos_params.xin_id, qos_params.is_rt, 475 qos_params.clk_ctrl); 476 477 dpu_vbif_set_qos_remap(dpu_kms, &qos_params); 478 } 479 480 static void _dpu_plane_set_scanout(struct drm_plane *plane, 481 struct dpu_plane_state *pstate, 482 struct dpu_hw_pipe_cfg *pipe_cfg, 483 struct drm_framebuffer *fb) 484 { 485 struct dpu_plane *pdpu = to_dpu_plane(plane); 486 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 487 struct msm_gem_address_space *aspace = kms->base.aspace; 488 int ret; 489 490 ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); 491 if (ret == -EAGAIN) 492 DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n"); 493 else if (ret) 494 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 495 else if (pdpu->pipe_hw->ops.setup_sourceaddress) { 496 trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx, 497 &pipe_cfg->layout, 498 pstate->multirect_index); 499 pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg, 500 pstate->multirect_index); 501 } 502 } 503 504 static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, 505 struct dpu_plane_state *pstate, 506 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, 507 struct dpu_hw_scaler3_cfg *scale_cfg, 508 const struct dpu_format *fmt, 509 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 510 { 511 uint32_t i; 512 bool inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90; 513 514 /* 515 * For inline rotation cases, scaler config is post-rotation, 516 * so swap the dimensions here. However, pixel extension will 517 * need pre-rotation settings. 518 */ 519 if (inline_rotation) 520 swap(src_w, src_h); 521 522 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = 523 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); 524 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = 525 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h); 526 527 528 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = 529 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; 530 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = 531 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; 532 533 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = 534 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; 535 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = 536 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; 537 538 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = 539 scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; 540 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = 541 scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; 542 543 for (i = 0; i < DPU_MAX_PLANES; i++) { 544 scale_cfg->src_width[i] = src_w; 545 scale_cfg->src_height[i] = src_h; 546 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 547 scale_cfg->src_width[i] /= chroma_subsmpl_h; 548 scale_cfg->src_height[i] /= chroma_subsmpl_v; 549 } 550 551 if (pdpu->pipe_hw->cap->features & 552 BIT(DPU_SSPP_SCALER_QSEED4)) { 553 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; 554 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; 555 } else { 556 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; 557 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; 558 } 559 } 560 if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) 561 && (src_w == dst_w)) 562 return; 563 564 scale_cfg->dst_width = dst_w; 565 scale_cfg->dst_height = dst_h; 566 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; 567 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; 568 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; 569 scale_cfg->lut_flag = 0; 570 scale_cfg->blend_cfg = 1; 571 scale_cfg->enable = 1; 572 } 573 574 static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg, 575 struct dpu_hw_pixel_ext *pixel_ext, 576 uint32_t src_w, uint32_t src_h, 577 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 578 { 579 int i; 580 581 for (i = 0; i < DPU_MAX_PLANES; i++) { 582 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 583 src_w /= chroma_subsmpl_h; 584 src_h /= chroma_subsmpl_v; 585 } 586 587 pixel_ext->num_ext_pxls_top[i] = src_h; 588 pixel_ext->num_ext_pxls_left[i] = src_w; 589 } 590 } 591 592 static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = { 593 { 594 /* S15.16 format */ 595 0x00012A00, 0x00000000, 0x00019880, 596 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 597 0x00012A00, 0x00020480, 0x00000000, 598 }, 599 /* signed bias */ 600 { 0xfff0, 0xff80, 0xff80,}, 601 { 0x0, 0x0, 0x0,}, 602 /* unsigned clamp */ 603 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, 604 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, 605 }; 606 607 static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { 608 { 609 /* S15.16 format */ 610 0x00012A00, 0x00000000, 0x00019880, 611 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 612 0x00012A00, 0x00020480, 0x00000000, 613 }, 614 /* signed bias */ 615 { 0xffc0, 0xfe00, 0xfe00,}, 616 { 0x0, 0x0, 0x0,}, 617 /* unsigned clamp */ 618 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,}, 619 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, 620 }; 621 622 static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt) 623 { 624 const struct dpu_csc_cfg *csc_ptr; 625 626 if (!pdpu) { 627 DPU_ERROR("invalid plane\n"); 628 return NULL; 629 } 630 631 if (!DPU_FORMAT_IS_YUV(fmt)) 632 return NULL; 633 634 if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features) 635 csc_ptr = &dpu_csc10_YUV2RGB_601L; 636 else 637 csc_ptr = &dpu_csc_YUV2RGB_601L; 638 639 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", 640 csc_ptr->csc_mv[0], 641 csc_ptr->csc_mv[1], 642 csc_ptr->csc_mv[2]); 643 644 return csc_ptr; 645 } 646 647 static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, 648 struct dpu_plane_state *pstate, 649 const struct dpu_format *fmt, bool color_fill, 650 struct dpu_hw_pipe_cfg *pipe_cfg) 651 { 652 const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); 653 struct dpu_hw_scaler3_cfg scaler3_cfg; 654 struct dpu_hw_pixel_ext pixel_ext; 655 u32 src_width = drm_rect_width(&pipe_cfg->src_rect); 656 u32 src_height = drm_rect_height(&pipe_cfg->src_rect); 657 u32 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 658 u32 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 659 660 memset(&scaler3_cfg, 0, sizeof(scaler3_cfg)); 661 memset(&pixel_ext, 0, sizeof(pixel_ext)); 662 663 /* don't chroma subsample if decimating */ 664 /* update scaler. calculate default config for QSEED3 */ 665 _dpu_plane_setup_scaler3(pdpu, pstate, 666 src_width, 667 src_height, 668 dst_width, 669 dst_height, 670 &scaler3_cfg, fmt, 671 info->hsub, info->vsub); 672 673 /* configure pixel extension based on scalar config */ 674 _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, 675 src_width, src_height, info->hsub, info->vsub); 676 677 if (pdpu->pipe_hw->ops.setup_pe) 678 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, 679 &pixel_ext); 680 681 /** 682 * when programmed in multirect mode, scalar block will be 683 * bypassed. Still we need to update alpha and bitwidth 684 * ONLY for RECT0 685 */ 686 if (pdpu->pipe_hw->ops.setup_scaler && 687 pstate->multirect_index != DPU_SSPP_RECT_1) 688 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, 689 pipe_cfg, 690 &scaler3_cfg); 691 } 692 693 /** 694 * _dpu_plane_color_fill - enables color fill on plane 695 * @pdpu: Pointer to DPU plane object 696 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 697 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 698 * Returns: 0 on success 699 */ 700 static int _dpu_plane_color_fill(struct dpu_plane *pdpu, 701 uint32_t color, uint32_t alpha) 702 { 703 const struct dpu_format *fmt; 704 const struct drm_plane *plane = &pdpu->base; 705 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 706 struct dpu_hw_pipe_cfg pipe_cfg; 707 708 DPU_DEBUG_PLANE(pdpu, "\n"); 709 710 /* 711 * select fill format to match user property expectation, 712 * h/w only supports RGB variants 713 */ 714 fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); 715 716 /* update sspp */ 717 if (fmt && pdpu->pipe_hw->ops.setup_solidfill) { 718 pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw, 719 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24), 720 pstate->multirect_index); 721 722 /* override scaler/decimation if solid fill */ 723 pipe_cfg.dst_rect = pstate->base.dst; 724 725 pipe_cfg.src_rect.x1 = 0; 726 pipe_cfg.src_rect.y1 = 0; 727 pipe_cfg.src_rect.x2 = 728 drm_rect_width(&pipe_cfg.dst_rect); 729 pipe_cfg.src_rect.y2 = 730 drm_rect_height(&pipe_cfg.dst_rect); 731 732 if (pdpu->pipe_hw->ops.setup_format) 733 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, 734 fmt, DPU_SSPP_SOLID_FILL, 735 pstate->multirect_index); 736 737 if (pdpu->pipe_hw->ops.setup_rects) 738 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, 739 &pipe_cfg, 740 pstate->multirect_index); 741 742 _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg); 743 } 744 745 return 0; 746 } 747 748 void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state) 749 { 750 struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state); 751 752 pstate->multirect_index = DPU_SSPP_RECT_SOLO; 753 pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 754 } 755 756 int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) 757 { 758 struct dpu_plane_state *pstate[R_MAX]; 759 const struct drm_plane_state *drm_state[R_MAX]; 760 struct drm_rect src[R_MAX], dst[R_MAX]; 761 struct dpu_plane *dpu_plane[R_MAX]; 762 const struct dpu_format *fmt[R_MAX]; 763 int i, buffer_lines; 764 unsigned int max_tile_height = 1; 765 bool parallel_fetch_qualified = true; 766 bool has_tiled_rect = false; 767 768 for (i = 0; i < R_MAX; i++) { 769 const struct msm_format *msm_fmt; 770 771 drm_state[i] = i ? plane->r1 : plane->r0; 772 msm_fmt = msm_framebuffer_format(drm_state[i]->fb); 773 fmt[i] = to_dpu_format(msm_fmt); 774 775 if (DPU_FORMAT_IS_UBWC(fmt[i])) { 776 has_tiled_rect = true; 777 if (fmt[i]->tile_height > max_tile_height) 778 max_tile_height = fmt[i]->tile_height; 779 } 780 } 781 782 for (i = 0; i < R_MAX; i++) { 783 int width_threshold; 784 785 pstate[i] = to_dpu_plane_state(drm_state[i]); 786 dpu_plane[i] = to_dpu_plane(drm_state[i]->plane); 787 788 if (pstate[i] == NULL) { 789 DPU_ERROR("DPU plane state of plane id %d is NULL\n", 790 drm_state[i]->plane->base.id); 791 return -EINVAL; 792 } 793 794 src[i].x1 = drm_state[i]->src_x >> 16; 795 src[i].y1 = drm_state[i]->src_y >> 16; 796 src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16); 797 src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16); 798 799 dst[i] = drm_plane_state_dest(drm_state[i]); 800 801 if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 || 802 drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) { 803 DPU_ERROR_PLANE(dpu_plane[i], 804 "scaling is not supported in multirect mode\n"); 805 return -EINVAL; 806 } 807 808 if (DPU_FORMAT_IS_YUV(fmt[i])) { 809 DPU_ERROR_PLANE(dpu_plane[i], 810 "Unsupported format for multirect mode\n"); 811 return -EINVAL; 812 } 813 814 /** 815 * SSPP PD_MEM is split half - one for each RECT. 816 * Tiled formats need 5 lines of buffering while fetching 817 * whereas linear formats need only 2 lines. 818 * So we cannot support more than half of the supported SSPP 819 * width for tiled formats. 820 */ 821 width_threshold = dpu_plane[i]->catalog->caps->max_linewidth; 822 if (has_tiled_rect) 823 width_threshold /= 2; 824 825 if (parallel_fetch_qualified && 826 drm_rect_width(&src[i]) > width_threshold) 827 parallel_fetch_qualified = false; 828 829 } 830 831 /* Validate RECT's and set the mode */ 832 833 /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */ 834 if (parallel_fetch_qualified) { 835 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 836 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 837 838 goto done; 839 } 840 841 /* TIME_MX Mode */ 842 buffer_lines = 2 * max_tile_height; 843 844 if (dst[R1].y1 >= dst[R0].y2 + buffer_lines || 845 dst[R0].y1 >= dst[R1].y2 + buffer_lines) { 846 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 847 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 848 } else { 849 DPU_ERROR( 850 "No multirect mode possible for the planes (%d - %d)\n", 851 drm_state[R0]->plane->base.id, 852 drm_state[R1]->plane->base.id); 853 return -EINVAL; 854 } 855 856 done: 857 if (dpu_plane[R0]->is_virtual) { 858 pstate[R0]->multirect_index = DPU_SSPP_RECT_1; 859 pstate[R1]->multirect_index = DPU_SSPP_RECT_0; 860 } else { 861 pstate[R0]->multirect_index = DPU_SSPP_RECT_0; 862 pstate[R1]->multirect_index = DPU_SSPP_RECT_1; 863 } 864 865 DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n", 866 pstate[R0]->multirect_mode, pstate[R0]->multirect_index); 867 DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n", 868 pstate[R1]->multirect_mode, pstate[R1]->multirect_index); 869 return 0; 870 } 871 872 /** 873 * dpu_plane_get_ctl_flush - get control flush for the given plane 874 * @plane: Pointer to drm plane structure 875 * @ctl: Pointer to hardware control driver 876 * @flush_sspp: Pointer to sspp flush control word 877 */ 878 void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl, 879 u32 *flush_sspp) 880 { 881 *flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane)); 882 } 883 884 static int dpu_plane_prepare_fb(struct drm_plane *plane, 885 struct drm_plane_state *new_state) 886 { 887 struct drm_framebuffer *fb = new_state->fb; 888 struct dpu_plane *pdpu = to_dpu_plane(plane); 889 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state); 890 struct dpu_hw_fmt_layout layout; 891 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 892 int ret; 893 894 if (!new_state->fb) 895 return 0; 896 897 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); 898 899 /* cache aspace */ 900 pstate->aspace = kms->base.aspace; 901 902 /* 903 * TODO: Need to sort out the msm_framebuffer_prepare() call below so 904 * we can use msm_atomic_prepare_fb() instead of doing the 905 * implicit fence and fb prepare by hand here. 906 */ 907 drm_gem_plane_helper_prepare_fb(plane, new_state); 908 909 if (pstate->aspace) { 910 ret = msm_framebuffer_prepare(new_state->fb, 911 pstate->aspace, pstate->needs_dirtyfb); 912 if (ret) { 913 DPU_ERROR("failed to prepare framebuffer\n"); 914 return ret; 915 } 916 } 917 918 /* validate framebuffer layout before commit */ 919 ret = dpu_format_populate_layout(pstate->aspace, 920 new_state->fb, &layout); 921 if (ret) { 922 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 923 return ret; 924 } 925 926 return 0; 927 } 928 929 static void dpu_plane_cleanup_fb(struct drm_plane *plane, 930 struct drm_plane_state *old_state) 931 { 932 struct dpu_plane *pdpu = to_dpu_plane(plane); 933 struct dpu_plane_state *old_pstate; 934 935 if (!old_state || !old_state->fb) 936 return; 937 938 old_pstate = to_dpu_plane_state(old_state); 939 940 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id); 941 942 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace, 943 old_pstate->needs_dirtyfb); 944 } 945 946 static bool dpu_plane_validate_src(struct drm_rect *src, 947 struct drm_rect *fb_rect, 948 uint32_t min_src_size) 949 { 950 /* Ensure fb size is supported */ 951 if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH || 952 drm_rect_height(fb_rect) > MAX_IMG_HEIGHT) 953 return false; 954 955 /* Ensure src rect is above the minimum size */ 956 if (drm_rect_width(src) < min_src_size || 957 drm_rect_height(src) < min_src_size) 958 return false; 959 960 /* Ensure src is fully encapsulated in fb */ 961 return drm_rect_intersect(fb_rect, src) && 962 drm_rect_equals(fb_rect, src); 963 } 964 965 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, 966 const struct dpu_sspp_sub_blks *sblk, 967 struct drm_rect src, const struct dpu_format *fmt) 968 { 969 size_t num_formats; 970 const u32 *supported_formats; 971 972 if (!sblk->rotation_cfg) { 973 DPU_ERROR("invalid rotation cfg\n"); 974 return -EINVAL; 975 } 976 977 if (drm_rect_width(&src) > sblk->rotation_cfg->rot_maxheight) { 978 DPU_DEBUG_PLANE(pdpu, "invalid height for inline rot:%d max:%d\n", 979 src.y2, sblk->rotation_cfg->rot_maxheight); 980 return -EINVAL; 981 } 982 983 supported_formats = sblk->rotation_cfg->rot_format_list; 984 num_formats = sblk->rotation_cfg->rot_num_formats; 985 986 if (!DPU_FORMAT_IS_UBWC(fmt) || 987 !dpu_find_format(fmt->base.pixel_format, supported_formats, num_formats)) 988 return -EINVAL; 989 990 return 0; 991 } 992 993 static int dpu_plane_atomic_check(struct drm_plane *plane, 994 struct drm_atomic_state *state) 995 { 996 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 997 plane); 998 int ret = 0, min_scale; 999 struct dpu_plane *pdpu = to_dpu_plane(plane); 1000 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 1001 const struct drm_crtc_state *crtc_state = NULL; 1002 const struct dpu_format *fmt; 1003 struct drm_rect src, dst, fb_rect = { 0 }; 1004 uint32_t min_src_size, max_linewidth; 1005 unsigned int rotation; 1006 uint32_t supported_rotations; 1007 const struct dpu_sspp_cfg *pipe_hw_caps = pdpu->pipe_hw->cap; 1008 const struct dpu_sspp_sub_blks *sblk = pdpu->pipe_hw->cap->sblk; 1009 1010 if (new_plane_state->crtc) 1011 crtc_state = drm_atomic_get_new_crtc_state(state, 1012 new_plane_state->crtc); 1013 1014 min_scale = FRAC_16_16(1, sblk->maxupscale); 1015 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 1016 min_scale, 1017 sblk->maxdwnscale << 16, 1018 true, true); 1019 if (ret) { 1020 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); 1021 return ret; 1022 } 1023 if (!new_plane_state->visible) 1024 return 0; 1025 1026 src.x1 = new_plane_state->src_x >> 16; 1027 src.y1 = new_plane_state->src_y >> 16; 1028 src.x2 = src.x1 + (new_plane_state->src_w >> 16); 1029 src.y2 = src.y1 + (new_plane_state->src_h >> 16); 1030 1031 dst = drm_plane_state_dest(new_plane_state); 1032 1033 fb_rect.x2 = new_plane_state->fb->width; 1034 fb_rect.y2 = new_plane_state->fb->height; 1035 1036 max_linewidth = pdpu->catalog->caps->max_linewidth; 1037 1038 fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); 1039 1040 min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; 1041 1042 if (DPU_FORMAT_IS_YUV(fmt) && 1043 (!(pipe_hw_caps->features & DPU_SSPP_SCALER) || 1044 !(pipe_hw_caps->features & DPU_SSPP_CSC_ANY))) { 1045 DPU_DEBUG_PLANE(pdpu, 1046 "plane doesn't have scaler/csc for yuv\n"); 1047 return -EINVAL; 1048 1049 /* check src bounds */ 1050 } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) { 1051 DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", 1052 DRM_RECT_ARG(&src)); 1053 return -E2BIG; 1054 1055 /* valid yuv image */ 1056 } else if (DPU_FORMAT_IS_YUV(fmt) && 1057 (src.x1 & 0x1 || src.y1 & 0x1 || 1058 drm_rect_width(&src) & 0x1 || 1059 drm_rect_height(&src) & 0x1)) { 1060 DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", 1061 DRM_RECT_ARG(&src)); 1062 return -EINVAL; 1063 1064 /* min dst support */ 1065 } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) { 1066 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 1067 DRM_RECT_ARG(&dst)); 1068 return -EINVAL; 1069 1070 /* check decimated source width */ 1071 } else if (drm_rect_width(&src) > max_linewidth) { 1072 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 1073 DRM_RECT_ARG(&src), max_linewidth); 1074 return -E2BIG; 1075 } 1076 1077 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; 1078 1079 if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) 1080 supported_rotations |= DRM_MODE_ROTATE_90; 1081 1082 rotation = drm_rotation_simplify(new_plane_state->rotation, 1083 supported_rotations); 1084 1085 if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) && 1086 (rotation & DRM_MODE_ROTATE_90)) { 1087 ret = dpu_plane_check_inline_rotation(pdpu, sblk, src, fmt); 1088 if (ret) 1089 return ret; 1090 } 1091 1092 pstate->rotation = rotation; 1093 pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); 1094 1095 return 0; 1096 } 1097 1098 void dpu_plane_flush(struct drm_plane *plane) 1099 { 1100 struct dpu_plane *pdpu; 1101 struct dpu_plane_state *pstate; 1102 1103 if (!plane || !plane->state) { 1104 DPU_ERROR("invalid plane\n"); 1105 return; 1106 } 1107 1108 pdpu = to_dpu_plane(plane); 1109 pstate = to_dpu_plane_state(plane->state); 1110 1111 /* 1112 * These updates have to be done immediately before the plane flush 1113 * timing, and may not be moved to the atomic_update/mode_set functions. 1114 */ 1115 if (pdpu->is_error) 1116 /* force white frame with 100% alpha pipe output on error */ 1117 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF); 1118 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) 1119 /* force 100% alpha */ 1120 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 1121 else if (pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_csc) { 1122 const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb)); 1123 const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt); 1124 1125 if (csc_ptr) 1126 pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, csc_ptr); 1127 } 1128 1129 /* flag h/w flush complete */ 1130 if (plane->state) 1131 pstate->pending = false; 1132 } 1133 1134 /** 1135 * dpu_plane_set_error: enable/disable error condition 1136 * @plane: pointer to drm_plane structure 1137 * @error: error value to set 1138 */ 1139 void dpu_plane_set_error(struct drm_plane *plane, bool error) 1140 { 1141 struct dpu_plane *pdpu; 1142 1143 if (!plane) 1144 return; 1145 1146 pdpu = to_dpu_plane(plane); 1147 pdpu->is_error = error; 1148 } 1149 1150 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) 1151 { 1152 uint32_t src_flags; 1153 struct dpu_plane *pdpu = to_dpu_plane(plane); 1154 struct drm_plane_state *state = plane->state; 1155 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1156 struct drm_crtc *crtc = state->crtc; 1157 struct drm_framebuffer *fb = state->fb; 1158 bool is_rt_pipe, update_qos_remap; 1159 const struct dpu_format *fmt = 1160 to_dpu_format(msm_framebuffer_format(fb)); 1161 struct dpu_hw_pipe_cfg pipe_cfg; 1162 1163 memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg)); 1164 1165 _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb); 1166 1167 pstate->pending = true; 1168 1169 is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); 1170 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); 1171 1172 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT 1173 ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 1174 crtc->base.id, DRM_RECT_ARG(&state->dst), 1175 (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); 1176 1177 pipe_cfg.src_rect = state->src; 1178 1179 /* state->src is 16.16, src_rect is not */ 1180 pipe_cfg.src_rect.x1 >>= 16; 1181 pipe_cfg.src_rect.x2 >>= 16; 1182 pipe_cfg.src_rect.y1 >>= 16; 1183 pipe_cfg.src_rect.y2 >>= 16; 1184 1185 pipe_cfg.dst_rect = state->dst; 1186 1187 /* override for color fill */ 1188 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { 1189 /* skip remaining processing on color fill */ 1190 return; 1191 } 1192 1193 if (pdpu->pipe_hw->ops.setup_rects) { 1194 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, 1195 &pipe_cfg, 1196 pstate->multirect_index); 1197 } 1198 1199 _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg); 1200 1201 if (pdpu->pipe_hw->ops.setup_multirect) 1202 pdpu->pipe_hw->ops.setup_multirect( 1203 pdpu->pipe_hw, 1204 pstate->multirect_index, 1205 pstate->multirect_mode); 1206 1207 if (pdpu->pipe_hw->ops.setup_format) { 1208 unsigned int rotation = pstate->rotation; 1209 1210 src_flags = 0x0; 1211 1212 if (rotation & DRM_MODE_REFLECT_X) 1213 src_flags |= DPU_SSPP_FLIP_LR; 1214 1215 if (rotation & DRM_MODE_REFLECT_Y) 1216 src_flags |= DPU_SSPP_FLIP_UD; 1217 1218 if (rotation & DRM_MODE_ROTATE_90) 1219 src_flags |= DPU_SSPP_ROT_90; 1220 1221 /* update format */ 1222 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags, 1223 pstate->multirect_index); 1224 1225 if (pdpu->pipe_hw->ops.setup_cdp) { 1226 struct dpu_hw_cdp_cfg cdp_cfg; 1227 1228 memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg)); 1229 1230 cdp_cfg.enable = pdpu->catalog->perf->cdp_cfg 1231 [DPU_PERF_CDP_USAGE_RT].rd_enable; 1232 cdp_cfg.ubwc_meta_enable = 1233 DPU_FORMAT_IS_UBWC(fmt); 1234 cdp_cfg.tile_amortize_enable = 1235 DPU_FORMAT_IS_UBWC(fmt) || 1236 DPU_FORMAT_IS_TILE(fmt); 1237 cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64; 1238 1239 pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, &cdp_cfg, pstate->multirect_index); 1240 } 1241 } 1242 1243 _dpu_plane_set_qos_lut(plane, fb, &pipe_cfg); 1244 _dpu_plane_set_danger_lut(plane, fb); 1245 1246 if (plane->type != DRM_PLANE_TYPE_CURSOR) { 1247 _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL); 1248 _dpu_plane_set_ot_limit(plane, crtc, &pipe_cfg); 1249 } 1250 1251 update_qos_remap = (is_rt_pipe != pdpu->is_rt_pipe) || 1252 pstate->needs_qos_remap; 1253 1254 if (update_qos_remap) { 1255 if (is_rt_pipe != pdpu->is_rt_pipe) 1256 pdpu->is_rt_pipe = is_rt_pipe; 1257 else if (pstate->needs_qos_remap) 1258 pstate->needs_qos_remap = false; 1259 _dpu_plane_set_qos_remap(plane); 1260 } 1261 1262 _dpu_plane_calc_bw(plane, fb, &pipe_cfg); 1263 1264 _dpu_plane_calc_clk(plane, &pipe_cfg); 1265 } 1266 1267 static void _dpu_plane_atomic_disable(struct drm_plane *plane) 1268 { 1269 struct dpu_plane *pdpu = to_dpu_plane(plane); 1270 struct drm_plane_state *state = plane->state; 1271 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1272 1273 trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane), 1274 pstate->multirect_mode); 1275 1276 pstate->pending = true; 1277 1278 if (is_dpu_plane_virtual(plane) && 1279 pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_multirect) 1280 pdpu->pipe_hw->ops.setup_multirect(pdpu->pipe_hw, 1281 DPU_SSPP_RECT_SOLO, DPU_SSPP_MULTIRECT_NONE); 1282 } 1283 1284 static void dpu_plane_atomic_update(struct drm_plane *plane, 1285 struct drm_atomic_state *state) 1286 { 1287 struct dpu_plane *pdpu = to_dpu_plane(plane); 1288 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1289 plane); 1290 1291 pdpu->is_error = false; 1292 1293 DPU_DEBUG_PLANE(pdpu, "\n"); 1294 1295 if (!new_state->visible) { 1296 _dpu_plane_atomic_disable(plane); 1297 } else { 1298 dpu_plane_sspp_atomic_update(plane); 1299 } 1300 } 1301 1302 static void dpu_plane_destroy(struct drm_plane *plane) 1303 { 1304 struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL; 1305 1306 DPU_DEBUG_PLANE(pdpu, "\n"); 1307 1308 if (pdpu) { 1309 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); 1310 1311 mutex_destroy(&pdpu->lock); 1312 1313 /* this will destroy the states as well */ 1314 drm_plane_cleanup(plane); 1315 1316 dpu_hw_sspp_destroy(pdpu->pipe_hw); 1317 1318 kfree(pdpu); 1319 } 1320 } 1321 1322 static void dpu_plane_destroy_state(struct drm_plane *plane, 1323 struct drm_plane_state *state) 1324 { 1325 __drm_atomic_helper_plane_destroy_state(state); 1326 kfree(to_dpu_plane_state(state)); 1327 } 1328 1329 static struct drm_plane_state * 1330 dpu_plane_duplicate_state(struct drm_plane *plane) 1331 { 1332 struct dpu_plane *pdpu; 1333 struct dpu_plane_state *pstate; 1334 struct dpu_plane_state *old_state; 1335 1336 if (!plane) { 1337 DPU_ERROR("invalid plane\n"); 1338 return NULL; 1339 } else if (!plane->state) { 1340 DPU_ERROR("invalid plane state\n"); 1341 return NULL; 1342 } 1343 1344 old_state = to_dpu_plane_state(plane->state); 1345 pdpu = to_dpu_plane(plane); 1346 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL); 1347 if (!pstate) { 1348 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1349 return NULL; 1350 } 1351 1352 DPU_DEBUG_PLANE(pdpu, "\n"); 1353 1354 pstate->pending = false; 1355 1356 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base); 1357 1358 return &pstate->base; 1359 } 1360 1361 static const char * const multirect_mode_name[] = { 1362 [DPU_SSPP_MULTIRECT_NONE] = "none", 1363 [DPU_SSPP_MULTIRECT_PARALLEL] = "parallel", 1364 [DPU_SSPP_MULTIRECT_TIME_MX] = "time_mx", 1365 }; 1366 1367 static const char * const multirect_index_name[] = { 1368 [DPU_SSPP_RECT_SOLO] = "solo", 1369 [DPU_SSPP_RECT_0] = "rect_0", 1370 [DPU_SSPP_RECT_1] = "rect_1", 1371 }; 1372 1373 static const char *dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode) 1374 { 1375 if (WARN_ON(mode >= ARRAY_SIZE(multirect_mode_name))) 1376 return "unknown"; 1377 1378 return multirect_mode_name[mode]; 1379 } 1380 1381 static const char *dpu_get_multirect_index(enum dpu_sspp_multirect_index index) 1382 { 1383 if (WARN_ON(index >= ARRAY_SIZE(multirect_index_name))) 1384 return "unknown"; 1385 1386 return multirect_index_name[index]; 1387 } 1388 1389 static void dpu_plane_atomic_print_state(struct drm_printer *p, 1390 const struct drm_plane_state *state) 1391 { 1392 const struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1393 const struct dpu_plane *pdpu = to_dpu_plane(state->plane); 1394 1395 drm_printf(p, "\tstage=%d\n", pstate->stage); 1396 drm_printf(p, "\tsspp=%s\n", pdpu->pipe_hw->cap->name); 1397 drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->multirect_mode)); 1398 drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->multirect_index)); 1399 } 1400 1401 static void dpu_plane_reset(struct drm_plane *plane) 1402 { 1403 struct dpu_plane *pdpu; 1404 struct dpu_plane_state *pstate; 1405 1406 if (!plane) { 1407 DPU_ERROR("invalid plane\n"); 1408 return; 1409 } 1410 1411 pdpu = to_dpu_plane(plane); 1412 DPU_DEBUG_PLANE(pdpu, "\n"); 1413 1414 /* remove previous state, if present */ 1415 if (plane->state) { 1416 dpu_plane_destroy_state(plane, plane->state); 1417 plane->state = NULL; 1418 } 1419 1420 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); 1421 if (!pstate) { 1422 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1423 return; 1424 } 1425 1426 __drm_atomic_helper_plane_reset(plane, &pstate->base); 1427 } 1428 1429 #ifdef CONFIG_DEBUG_FS 1430 void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) 1431 { 1432 struct dpu_plane *pdpu = to_dpu_plane(plane); 1433 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1434 1435 if (!pdpu->is_rt_pipe) 1436 return; 1437 1438 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1439 _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL); 1440 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1441 } 1442 1443 /* SSPP live inside dpu_plane private data only. Enumerate them here. */ 1444 void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root) 1445 { 1446 struct drm_plane *plane; 1447 struct dentry *entry = debugfs_create_dir("sspp", debugfs_root); 1448 1449 if (IS_ERR(entry)) 1450 return; 1451 1452 drm_for_each_plane(plane, dpu_kms->dev) { 1453 struct dpu_plane *pdpu = to_dpu_plane(plane); 1454 1455 _dpu_hw_sspp_init_debugfs(pdpu->pipe_hw, dpu_kms, entry); 1456 } 1457 } 1458 #endif 1459 1460 static bool dpu_plane_format_mod_supported(struct drm_plane *plane, 1461 uint32_t format, uint64_t modifier) 1462 { 1463 if (modifier == DRM_FORMAT_MOD_LINEAR) 1464 return true; 1465 1466 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) 1467 return dpu_find_format(format, qcom_compressed_supported_formats, 1468 ARRAY_SIZE(qcom_compressed_supported_formats)); 1469 1470 return false; 1471 } 1472 1473 static const struct drm_plane_funcs dpu_plane_funcs = { 1474 .update_plane = drm_atomic_helper_update_plane, 1475 .disable_plane = drm_atomic_helper_disable_plane, 1476 .destroy = dpu_plane_destroy, 1477 .reset = dpu_plane_reset, 1478 .atomic_duplicate_state = dpu_plane_duplicate_state, 1479 .atomic_destroy_state = dpu_plane_destroy_state, 1480 .atomic_print_state = dpu_plane_atomic_print_state, 1481 .format_mod_supported = dpu_plane_format_mod_supported, 1482 }; 1483 1484 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { 1485 .prepare_fb = dpu_plane_prepare_fb, 1486 .cleanup_fb = dpu_plane_cleanup_fb, 1487 .atomic_check = dpu_plane_atomic_check, 1488 .atomic_update = dpu_plane_atomic_update, 1489 }; 1490 1491 enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane) 1492 { 1493 return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE; 1494 } 1495 1496 bool is_dpu_plane_virtual(struct drm_plane *plane) 1497 { 1498 return plane ? to_dpu_plane(plane)->is_virtual : false; 1499 } 1500 1501 /* initialize plane */ 1502 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1503 uint32_t pipe, enum drm_plane_type type, 1504 unsigned long possible_crtcs, u32 master_plane_id) 1505 { 1506 struct drm_plane *plane = NULL, *master_plane = NULL; 1507 const uint32_t *format_list; 1508 struct dpu_plane *pdpu; 1509 struct msm_drm_private *priv = dev->dev_private; 1510 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1511 int zpos_max = DPU_ZPOS_MAX; 1512 uint32_t num_formats; 1513 uint32_t supported_rotations; 1514 int ret = -EINVAL; 1515 1516 /* create and zero local structure */ 1517 pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL); 1518 if (!pdpu) { 1519 DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe); 1520 ret = -ENOMEM; 1521 return ERR_PTR(ret); 1522 } 1523 1524 /* cache local stuff for later */ 1525 plane = &pdpu->base; 1526 pdpu->pipe = pipe; 1527 pdpu->is_virtual = (master_plane_id != 0); 1528 INIT_LIST_HEAD(&pdpu->mplane_list); 1529 master_plane = drm_plane_find(dev, NULL, master_plane_id); 1530 if (master_plane) { 1531 struct dpu_plane *mpdpu = to_dpu_plane(master_plane); 1532 1533 list_add_tail(&pdpu->mplane_list, &mpdpu->mplane_list); 1534 } 1535 1536 /* initialize underlying h/w driver */ 1537 pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog, 1538 master_plane_id != 0); 1539 if (IS_ERR(pdpu->pipe_hw)) { 1540 DPU_ERROR("[%u]SSPP init failed\n", pipe); 1541 ret = PTR_ERR(pdpu->pipe_hw); 1542 goto clean_plane; 1543 } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) { 1544 DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); 1545 goto clean_sspp; 1546 } 1547 1548 if (pdpu->is_virtual) { 1549 format_list = pdpu->pipe_hw->cap->sblk->virt_format_list; 1550 num_formats = pdpu->pipe_hw->cap->sblk->virt_num_formats; 1551 } 1552 else { 1553 format_list = pdpu->pipe_hw->cap->sblk->format_list; 1554 num_formats = pdpu->pipe_hw->cap->sblk->num_formats; 1555 } 1556 1557 ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, 1558 format_list, num_formats, 1559 supported_format_modifiers, type, NULL); 1560 if (ret) 1561 goto clean_sspp; 1562 1563 pdpu->catalog = kms->catalog; 1564 1565 if (kms->catalog->mixer_count && 1566 kms->catalog->mixer[0].sblk->maxblendstages) { 1567 zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1; 1568 if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1) 1569 zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1; 1570 } 1571 1572 ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max); 1573 if (ret) 1574 DPU_ERROR("failed to install zpos property, rc = %d\n", ret); 1575 1576 drm_plane_create_alpha_property(plane); 1577 drm_plane_create_blend_mode_property(plane, 1578 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1579 BIT(DRM_MODE_BLEND_PREMULTI) | 1580 BIT(DRM_MODE_BLEND_COVERAGE)); 1581 1582 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 1583 1584 if (pdpu->pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) 1585 supported_rotations |= DRM_MODE_ROTATE_MASK; 1586 1587 drm_plane_create_rotation_property(plane, 1588 DRM_MODE_ROTATE_0, supported_rotations); 1589 1590 drm_plane_enable_fb_damage_clips(plane); 1591 1592 /* success! finalize initialization */ 1593 drm_plane_helper_add(plane, &dpu_plane_helper_funcs); 1594 1595 mutex_init(&pdpu->lock); 1596 1597 DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", plane->name, 1598 pipe, plane->base.id, master_plane_id); 1599 return plane; 1600 1601 clean_sspp: 1602 if (pdpu && pdpu->pipe_hw) 1603 dpu_hw_sspp_destroy(pdpu->pipe_hw); 1604 clean_plane: 1605 list_del(&pdpu->mplane_list); 1606 kfree(pdpu); 1607 return ERR_PTR(ret); 1608 } 1609