1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_3_0_offset.h" 34 #include "gc/gc_10_3_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h" 38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h" 39 40 #include "soc15_common.h" 41 #include "soc15.h" 42 #include "navi10_sdma_pkt_open.h" 43 #include "nbio_v2_3.h" 44 #include "sdma_common.h" 45 #include "sdma_v5_2.h" 46 47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); 48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin"); 50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin"); 51 52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin"); 54 MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin"); 55 MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin"); 56 57 #define SDMA1_REG_OFFSET 0x600 58 #define SDMA3_REG_OFFSET 0x400 59 #define SDMA0_HYP_DEC_REG_START 0x5880 60 #define SDMA0_HYP_DEC_REG_END 0x5893 61 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 62 63 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); 64 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); 65 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); 66 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); 67 68 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 69 { 70 u32 base; 71 72 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 73 internal_offset <= SDMA0_HYP_DEC_REG_END) { 74 base = adev->reg_offset[GC_HWIP][0][1]; 75 if (instance != 0) 76 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 77 } else { 78 if (instance < 2) { 79 base = adev->reg_offset[GC_HWIP][0][0]; 80 if (instance == 1) 81 internal_offset += SDMA1_REG_OFFSET; 82 } else { 83 base = adev->reg_offset[GC_HWIP][0][2]; 84 if (instance == 3) 85 internal_offset += SDMA3_REG_OFFSET; 86 } 87 } 88 89 return base + internal_offset; 90 } 91 92 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 93 { 94 int err = 0; 95 const struct sdma_firmware_header_v1_0 *hdr; 96 97 err = amdgpu_ucode_validate(sdma_inst->fw); 98 if (err) 99 return err; 100 101 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; 102 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 103 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 104 105 if (sdma_inst->feature_version >= 20) 106 sdma_inst->burst_nop = true; 107 108 return 0; 109 } 110 111 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev) 112 { 113 release_firmware(adev->sdma.instance[0].fw); 114 115 memset((void *)adev->sdma.instance, 0, 116 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 117 } 118 119 /** 120 * sdma_v5_2_init_microcode - load ucode images from disk 121 * 122 * @adev: amdgpu_device pointer 123 * 124 * Use the firmware interface to load the ucode images into 125 * the driver (not loaded into hw). 126 * Returns 0 on success, error on failure. 127 */ 128 129 // emulation only, won't work on real chip 130 // navi10 real chip need to use PSP to load firmware 131 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) 132 { 133 const char *chip_name; 134 char fw_name[40]; 135 int err = 0, i; 136 struct amdgpu_firmware_info *info = NULL; 137 const struct common_firmware_header *header = NULL; 138 139 DRM_DEBUG("\n"); 140 141 switch (adev->ip_versions[SDMA0_HWIP][0]) { 142 case IP_VERSION(5, 2, 0): 143 chip_name = "sienna_cichlid_sdma"; 144 break; 145 case IP_VERSION(5, 2, 2): 146 chip_name = "navy_flounder_sdma"; 147 break; 148 case IP_VERSION(5, 2, 1): 149 chip_name = "vangogh_sdma"; 150 break; 151 case IP_VERSION(5, 2, 4): 152 chip_name = "dimgrey_cavefish_sdma"; 153 break; 154 case IP_VERSION(5, 2, 5): 155 chip_name = "beige_goby_sdma"; 156 break; 157 case IP_VERSION(5, 2, 3): 158 chip_name = "yellow_carp_sdma"; 159 break; 160 case IP_VERSION(5, 2, 6): 161 chip_name = "sdma_5_2_6"; 162 break; 163 case IP_VERSION(5, 2, 7): 164 chip_name = "sdma_5_2_7"; 165 break; 166 default: 167 BUG(); 168 } 169 170 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name); 171 172 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 173 if (err) 174 goto out; 175 176 err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]); 177 if (err) 178 goto out; 179 180 for (i = 1; i < adev->sdma.num_instances; i++) 181 memcpy((void *)&adev->sdma.instance[i], 182 (void *)&adev->sdma.instance[0], 183 sizeof(struct amdgpu_sdma_instance)); 184 185 if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0))) 186 return 0; 187 188 DRM_DEBUG("psp_load == '%s'\n", 189 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 190 191 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 192 for (i = 0; i < adev->sdma.num_instances; i++) { 193 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 194 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 195 info->fw = adev->sdma.instance[i].fw; 196 header = (const struct common_firmware_header *)info->fw->data; 197 adev->firmware.fw_size += 198 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 199 } 200 } 201 202 out: 203 if (err) { 204 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name); 205 sdma_v5_2_destroy_inst_ctx(adev); 206 } 207 return err; 208 } 209 210 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring) 211 { 212 unsigned ret; 213 214 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 215 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 216 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 217 amdgpu_ring_write(ring, 1); 218 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 219 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 220 221 return ret; 222 } 223 224 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring, 225 unsigned offset) 226 { 227 unsigned cur; 228 229 BUG_ON(offset > ring->buf_mask); 230 BUG_ON(ring->ring[offset] != 0x55aa55aa); 231 232 cur = (ring->wptr - 1) & ring->buf_mask; 233 if (cur > offset) 234 ring->ring[offset] = cur - offset; 235 else 236 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 237 } 238 239 /** 240 * sdma_v5_2_ring_get_rptr - get the current read pointer 241 * 242 * @ring: amdgpu ring pointer 243 * 244 * Get the current rptr from the hardware (NAVI10+). 245 */ 246 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring) 247 { 248 u64 *rptr; 249 250 /* XXX check if swapping is necessary on BE */ 251 rptr = (u64 *)ring->rptr_cpu_addr; 252 253 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 254 return ((*rptr) >> 2); 255 } 256 257 /** 258 * sdma_v5_2_ring_get_wptr - get the current write pointer 259 * 260 * @ring: amdgpu ring pointer 261 * 262 * Get the current wptr from the hardware (NAVI10+). 263 */ 264 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring) 265 { 266 struct amdgpu_device *adev = ring->adev; 267 u64 wptr; 268 269 if (ring->use_doorbell) { 270 /* XXX check if swapping is necessary on BE */ 271 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 272 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 273 } else { 274 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 275 wptr = wptr << 32; 276 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 277 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 278 } 279 280 return wptr >> 2; 281 } 282 283 /** 284 * sdma_v5_2_ring_set_wptr - commit the write pointer 285 * 286 * @ring: amdgpu ring pointer 287 * 288 * Write the wptr back to the hardware (NAVI10+). 289 */ 290 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring) 291 { 292 struct amdgpu_device *adev = ring->adev; 293 294 DRM_DEBUG("Setting write pointer\n"); 295 if (ring->use_doorbell) { 296 DRM_DEBUG("Using doorbell -- " 297 "wptr_offs == 0x%08x " 298 "lower_32_bits(ring->wptr << 2) == 0x%08x " 299 "upper_32_bits(ring->wptr << 2) == 0x%08x\n", 300 ring->wptr_offs, 301 lower_32_bits(ring->wptr << 2), 302 upper_32_bits(ring->wptr << 2)); 303 /* XXX check if swapping is necessary on BE */ 304 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 305 ring->wptr << 2); 306 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 307 ring->doorbell_index, ring->wptr << 2); 308 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 309 } else { 310 DRM_DEBUG("Not using doorbell -- " 311 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 312 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 313 ring->me, 314 lower_32_bits(ring->wptr << 2), 315 ring->me, 316 upper_32_bits(ring->wptr << 2)); 317 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 318 lower_32_bits(ring->wptr << 2)); 319 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 320 upper_32_bits(ring->wptr << 2)); 321 } 322 } 323 324 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 325 { 326 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 327 int i; 328 329 for (i = 0; i < count; i++) 330 if (sdma && sdma->burst_nop && (i == 0)) 331 amdgpu_ring_write(ring, ring->funcs->nop | 332 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 333 else 334 amdgpu_ring_write(ring, ring->funcs->nop); 335 } 336 337 /** 338 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine 339 * 340 * @ring: amdgpu ring pointer 341 * @job: job to retrieve vmid from 342 * @ib: IB object to schedule 343 * @flags: unused 344 * 345 * Schedule an IB in the DMA ring. 346 */ 347 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring, 348 struct amdgpu_job *job, 349 struct amdgpu_ib *ib, 350 uint32_t flags) 351 { 352 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 353 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 354 355 /* An IB packet must end on a 8 DW boundary--the next dword 356 * must be on a 8-dword boundary. Our IB packet below is 6 357 * dwords long, thus add x number of NOPs, such that, in 358 * modular arithmetic, 359 * wptr + 6 + x = 8k, k >= 0, which in C is, 360 * (wptr + 6 + x) % 8 = 0. 361 * The expression below, is a solution of x. 362 */ 363 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 364 365 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 366 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 367 /* base must be 32 byte aligned */ 368 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 369 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 370 amdgpu_ring_write(ring, ib->length_dw); 371 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 372 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 373 } 374 375 /** 376 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse 377 * 378 * @ring: amdgpu ring pointer 379 * 380 * flush the IB by graphics cache rinse. 381 */ 382 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring) 383 { 384 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | 385 SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV | 386 SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 387 SDMA_GCR_GLI_INV(1); 388 389 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 390 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 391 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 392 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 393 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 394 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 395 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 396 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 397 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 398 } 399 400 /** 401 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 402 * 403 * @ring: amdgpu ring pointer 404 * 405 * Emit an hdp flush packet on the requested DMA ring. 406 */ 407 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 408 { 409 struct amdgpu_device *adev = ring->adev; 410 u32 ref_and_mask = 0; 411 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 412 413 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 414 415 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 416 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 417 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 418 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 419 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 420 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 421 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 422 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 423 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 424 } 425 426 /** 427 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring 428 * 429 * @ring: amdgpu ring pointer 430 * @addr: address 431 * @seq: sequence number 432 * @flags: fence related flags 433 * 434 * Add a DMA fence packet to the ring to write 435 * the fence seq number and DMA trap packet to generate 436 * an interrupt if needed. 437 */ 438 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 439 unsigned flags) 440 { 441 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 442 /* write the fence */ 443 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 444 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 445 /* zero in first two bits */ 446 BUG_ON(addr & 0x3); 447 amdgpu_ring_write(ring, lower_32_bits(addr)); 448 amdgpu_ring_write(ring, upper_32_bits(addr)); 449 amdgpu_ring_write(ring, lower_32_bits(seq)); 450 451 /* optionally write high bits as well */ 452 if (write64bit) { 453 addr += 4; 454 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 455 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 456 /* zero in first two bits */ 457 BUG_ON(addr & 0x3); 458 amdgpu_ring_write(ring, lower_32_bits(addr)); 459 amdgpu_ring_write(ring, upper_32_bits(addr)); 460 amdgpu_ring_write(ring, upper_32_bits(seq)); 461 } 462 463 if ((flags & AMDGPU_FENCE_FLAG_INT)) { 464 uint32_t ctx = ring->is_mes_queue ? 465 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 466 /* generate an interrupt */ 467 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 468 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 469 } 470 } 471 472 /** 473 * sdma_v5_2_gfx_stop - stop the gfx async dma engines 474 * 475 * @adev: amdgpu_device pointer 476 * 477 * Stop the gfx async dma ring buffers. 478 */ 479 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev) 480 { 481 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 482 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 483 struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring; 484 struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring; 485 u32 rb_cntl, ib_cntl; 486 int i; 487 488 if ((adev->mman.buffer_funcs_ring == sdma0) || 489 (adev->mman.buffer_funcs_ring == sdma1) || 490 (adev->mman.buffer_funcs_ring == sdma2) || 491 (adev->mman.buffer_funcs_ring == sdma3)) 492 amdgpu_ttm_set_buffer_funcs_status(adev, false); 493 494 for (i = 0; i < adev->sdma.num_instances; i++) { 495 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 496 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 497 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 498 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 499 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 500 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 501 } 502 } 503 504 /** 505 * sdma_v5_2_rlc_stop - stop the compute async dma engines 506 * 507 * @adev: amdgpu_device pointer 508 * 509 * Stop the compute async dma queues. 510 */ 511 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) 512 { 513 /* XXX todo */ 514 } 515 516 /** 517 * sdma_v5_2_ctx_switch_enable_for_instance - start the async dma engines 518 * context switch for an instance 519 * 520 * @adev: amdgpu_device pointer 521 * @instance_idx: the index of the SDMA instance 522 * 523 * Unhalt the async dma engines context switch. 524 */ 525 static void sdma_v5_2_ctx_switch_enable_for_instance(struct amdgpu_device *adev, int instance_idx) 526 { 527 u32 f32_cntl, phase_quantum = 0; 528 529 if (WARN_ON(instance_idx >= adev->sdma.num_instances)) { 530 return; 531 } 532 533 if (amdgpu_sdma_phase_quantum) { 534 unsigned value = amdgpu_sdma_phase_quantum; 535 unsigned unit = 0; 536 537 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 538 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 539 value = (value + 1) >> 1; 540 unit++; 541 } 542 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 543 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 544 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 545 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 546 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 547 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 548 WARN_ONCE(1, 549 "clamping sdma_phase_quantum to %uK clock cycles\n", 550 value << unit); 551 } 552 phase_quantum = 553 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 554 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 555 556 WREG32_SOC15_IP(GC, 557 sdma_v5_2_get_reg_offset(adev, instance_idx, mmSDMA0_PHASE0_QUANTUM), 558 phase_quantum); 559 WREG32_SOC15_IP(GC, 560 sdma_v5_2_get_reg_offset(adev, instance_idx, mmSDMA0_PHASE1_QUANTUM), 561 phase_quantum); 562 WREG32_SOC15_IP(GC, 563 sdma_v5_2_get_reg_offset(adev, instance_idx, mmSDMA0_PHASE2_QUANTUM), 564 phase_quantum); 565 } 566 567 if (!amdgpu_sriov_vf(adev)) { 568 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, instance_idx, mmSDMA0_CNTL)); 569 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 570 AUTO_CTXSW_ENABLE, 1); 571 WREG32(sdma_v5_2_get_reg_offset(adev, instance_idx, mmSDMA0_CNTL), f32_cntl); 572 } 573 } 574 575 /** 576 * sdma_v5_2_ctx_switch_disable_all - stop the async dma engines context switch 577 * 578 * @adev: amdgpu_device pointer 579 * 580 * Halt the async dma engines context switch. 581 */ 582 static void sdma_v5_2_ctx_switch_disable_all(struct amdgpu_device *adev) 583 { 584 u32 f32_cntl; 585 int i; 586 587 if (amdgpu_sriov_vf(adev)) 588 return; 589 590 for (i = 0; i < adev->sdma.num_instances; i++) { 591 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 592 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 593 AUTO_CTXSW_ENABLE, 0); 594 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 595 } 596 } 597 598 /** 599 * sdma_v5_2_halt - stop the async dma engines 600 * 601 * @adev: amdgpu_device pointer 602 * 603 * Halt the async dma engines. 604 */ 605 static void sdma_v5_2_halt(struct amdgpu_device *adev) 606 { 607 int i; 608 u32 f32_cntl; 609 610 sdma_v5_2_gfx_stop(adev); 611 sdma_v5_2_rlc_stop(adev); 612 613 if (!amdgpu_sriov_vf(adev)) { 614 for (i = 0; i < adev->sdma.num_instances; i++) { 615 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 616 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 617 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 618 } 619 } 620 } 621 622 /** 623 * sdma_v5_2_gfx_resume - setup and start the async dma engines 624 * 625 * @adev: amdgpu_device pointer 626 * 627 * Set up the gfx DMA ring buffers and enable them. 628 * It assumes that the dma engine is stopped for each instance. 629 * The function enables the engine and preemptions sequentially for each instance. 630 * 631 * Returns 0 for success, error for failure. 632 */ 633 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) 634 { 635 struct amdgpu_ring *ring; 636 u32 rb_cntl, ib_cntl; 637 u32 rb_bufsz; 638 u32 doorbell; 639 u32 doorbell_offset; 640 u32 temp; 641 u32 wptr_poll_cntl; 642 u64 wptr_gpu_addr; 643 int i, r; 644 645 for (i = 0; i < adev->sdma.num_instances; i++) { 646 ring = &adev->sdma.instance[i].ring; 647 648 if (!amdgpu_sriov_vf(adev)) 649 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 650 651 /* Set ring buffer size in dwords */ 652 rb_bufsz = order_base_2(ring->ring_size / 4); 653 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 654 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 655 #ifdef __BIG_ENDIAN 656 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 657 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 658 RPTR_WRITEBACK_SWAP_ENABLE, 1); 659 #endif 660 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 661 662 /* Initialize the ring buffer's read and write pointers */ 663 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 664 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 665 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 666 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 667 668 /* setup the wptr shadow polling */ 669 wptr_gpu_addr = ring->wptr_gpu_addr; 670 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 671 lower_32_bits(wptr_gpu_addr)); 672 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 673 upper_32_bits(wptr_gpu_addr)); 674 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 675 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 676 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 677 SDMA0_GFX_RB_WPTR_POLL_CNTL, 678 F32_POLL_ENABLE, 1); 679 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 680 wptr_poll_cntl); 681 682 /* set the wb address whether it's enabled or not */ 683 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 684 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 685 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 686 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 687 688 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 689 690 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 691 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 692 693 ring->wptr = 0; 694 695 /* before programing wptr to a less value, need set minor_ptr_update first */ 696 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 697 698 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 699 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 700 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 701 } 702 703 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 704 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 705 706 if (ring->use_doorbell) { 707 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 708 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 709 OFFSET, ring->doorbell_index); 710 } else { 711 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 712 } 713 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 714 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 715 716 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 717 ring->doorbell_index, 718 adev->doorbell_index.sdma_doorbell_range); 719 720 if (amdgpu_sriov_vf(adev)) 721 sdma_v5_2_ring_set_wptr(ring); 722 723 /* set minor_ptr_update to 0 after wptr programed */ 724 725 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 726 727 /* SRIOV VF has no control of any of registers below */ 728 if (!amdgpu_sriov_vf(adev)) { 729 /* set utc l1 enable flag always to 1 */ 730 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 731 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 732 733 /* enable MCBP */ 734 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 735 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 736 737 /* Set up RESP_MODE to non-copy addresses */ 738 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 739 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 740 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 741 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 742 743 /* program default cache read and write policy */ 744 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 745 /* clean read policy and write policy bits */ 746 temp &= 0xFF0FFF; 747 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 748 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 749 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 750 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 751 752 /* unhalt engine */ 753 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 754 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 755 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 756 } 757 758 /* enable DMA RB */ 759 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 760 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 761 762 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 763 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 764 #ifdef __BIG_ENDIAN 765 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 766 #endif 767 /* enable DMA IBs */ 768 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 769 770 ring->sched.ready = true; 771 772 sdma_v5_2_ctx_switch_enable_for_instance(adev, i); 773 774 r = amdgpu_ring_test_ring(ring); 775 if (r) { 776 ring->sched.ready = false; 777 return r; 778 } 779 780 if (adev->mman.buffer_funcs_ring == ring) 781 amdgpu_ttm_set_buffer_funcs_status(adev, true); 782 } 783 784 return 0; 785 } 786 787 /** 788 * sdma_v5_2_rlc_resume - setup and start the async dma engines 789 * 790 * @adev: amdgpu_device pointer 791 * 792 * Set up the compute DMA queues and enable them. 793 * Returns 0 for success, error for failure. 794 */ 795 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev) 796 { 797 return 0; 798 } 799 800 /** 801 * sdma_v5_2_load_microcode - load the sDMA ME ucode 802 * 803 * @adev: amdgpu_device pointer 804 * 805 * Loads the sDMA0/1/2/3 ucode. 806 * Returns 0 for success, -EINVAL if the ucode is not available. 807 */ 808 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) 809 { 810 const struct sdma_firmware_header_v1_0 *hdr; 811 const __le32 *fw_data; 812 u32 fw_size; 813 int i, j; 814 815 /* halt the MEs */ 816 sdma_v5_2_halt(adev); 817 818 for (i = 0; i < adev->sdma.num_instances; i++) { 819 if (!adev->sdma.instance[i].fw) 820 return -EINVAL; 821 822 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 823 amdgpu_ucode_print_sdma_hdr(&hdr->header); 824 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 825 826 fw_data = (const __le32 *) 827 (adev->sdma.instance[i].fw->data + 828 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 829 830 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 831 832 for (j = 0; j < fw_size; j++) { 833 if (amdgpu_emu_mode == 1 && j % 500 == 0) 834 msleep(1); 835 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 836 } 837 838 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 839 } 840 841 return 0; 842 } 843 844 static int sdma_v5_2_soft_reset(void *handle) 845 { 846 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 847 u32 grbm_soft_reset; 848 u32 tmp; 849 int i; 850 851 for (i = 0; i < adev->sdma.num_instances; i++) { 852 grbm_soft_reset = REG_SET_FIELD(0, 853 GRBM_SOFT_RESET, SOFT_RESET_SDMA0, 854 1); 855 grbm_soft_reset <<= i; 856 857 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 858 tmp |= grbm_soft_reset; 859 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp); 860 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 861 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 862 863 udelay(50); 864 865 tmp &= ~grbm_soft_reset; 866 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 867 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 868 869 udelay(50); 870 } 871 872 return 0; 873 } 874 875 /** 876 * sdma_v5_2_start - setup and start the async dma engines 877 * 878 * @adev: amdgpu_device pointer 879 * 880 * Set up the DMA engines and enable them. 881 * Returns 0 for success, error for failure. 882 */ 883 static int sdma_v5_2_start(struct amdgpu_device *adev) 884 { 885 int r = 0; 886 887 if (amdgpu_sriov_vf(adev)) { 888 sdma_v5_2_ctx_switch_disable_all(adev); 889 sdma_v5_2_halt(adev); 890 891 /* set RB registers */ 892 r = sdma_v5_2_gfx_resume(adev); 893 return r; 894 } 895 896 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 897 r = sdma_v5_2_load_microcode(adev); 898 if (r) 899 return r; 900 901 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 902 if (amdgpu_emu_mode == 1) 903 msleep(1000); 904 } 905 906 /* TODO: check whether can submit a doorbell request to raise 907 * a doorbell fence to exit gfxoff. 908 */ 909 if (adev->in_s0ix) 910 amdgpu_gfx_off_ctrl(adev, false); 911 912 sdma_v5_2_soft_reset(adev); 913 914 /* Soft reset supposes to disable the dma engine and preemption. 915 * Now start the gfx rings and rlc compute queues. 916 */ 917 r = sdma_v5_2_gfx_resume(adev); 918 if (adev->in_s0ix) 919 amdgpu_gfx_off_ctrl(adev, true); 920 if (r) 921 return r; 922 r = sdma_v5_2_rlc_resume(adev); 923 924 return r; 925 } 926 927 static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd, 928 struct amdgpu_mqd_prop *prop) 929 { 930 struct v10_sdma_mqd *m = mqd; 931 uint64_t wb_gpu_addr; 932 933 m->sdmax_rlcx_rb_cntl = 934 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 935 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 936 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 937 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT; 938 939 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 940 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 941 942 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0, 943 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 944 945 wb_gpu_addr = prop->wptr_gpu_addr; 946 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 947 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 948 949 wb_gpu_addr = prop->rptr_gpu_addr; 950 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 951 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 952 953 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0, 954 mmSDMA0_GFX_IB_CNTL)); 955 956 m->sdmax_rlcx_doorbell_offset = 957 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 958 959 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1); 960 961 return 0; 962 } 963 964 static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev) 965 { 966 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd); 967 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_2_mqd_init; 968 } 969 970 /** 971 * sdma_v5_2_ring_test_ring - simple async dma engine test 972 * 973 * @ring: amdgpu_ring structure holding ring information 974 * 975 * Test the DMA engine by writing using it to write an 976 * value to memory. 977 * Returns 0 for success, error for failure. 978 */ 979 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) 980 { 981 struct amdgpu_device *adev = ring->adev; 982 unsigned i; 983 unsigned index; 984 int r; 985 u32 tmp; 986 u64 gpu_addr; 987 volatile uint32_t *cpu_ptr = NULL; 988 989 tmp = 0xCAFEDEAD; 990 991 if (ring->is_mes_queue) { 992 uint32_t offset = 0; 993 offset = amdgpu_mes_ctx_get_offs(ring, 994 AMDGPU_MES_CTX_PADDING_OFFS); 995 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 996 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 997 *cpu_ptr = tmp; 998 } else { 999 r = amdgpu_device_wb_get(adev, &index); 1000 if (r) { 1001 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 1002 return r; 1003 } 1004 1005 gpu_addr = adev->wb.gpu_addr + (index * 4); 1006 adev->wb.wb[index] = cpu_to_le32(tmp); 1007 } 1008 1009 r = amdgpu_ring_alloc(ring, 20); 1010 if (r) { 1011 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 1012 amdgpu_device_wb_free(adev, index); 1013 return r; 1014 } 1015 1016 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1017 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1018 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1019 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1020 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1021 amdgpu_ring_write(ring, 0xDEADBEEF); 1022 amdgpu_ring_commit(ring); 1023 1024 for (i = 0; i < adev->usec_timeout; i++) { 1025 if (ring->is_mes_queue) 1026 tmp = le32_to_cpu(*cpu_ptr); 1027 else 1028 tmp = le32_to_cpu(adev->wb.wb[index]); 1029 if (tmp == 0xDEADBEEF) 1030 break; 1031 if (amdgpu_emu_mode == 1) 1032 msleep(1); 1033 else 1034 udelay(1); 1035 } 1036 1037 if (i >= adev->usec_timeout) 1038 r = -ETIMEDOUT; 1039 1040 if (!ring->is_mes_queue) 1041 amdgpu_device_wb_free(adev, index); 1042 1043 return r; 1044 } 1045 1046 /** 1047 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine 1048 * 1049 * @ring: amdgpu_ring structure holding ring information 1050 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1051 * 1052 * Test a simple IB in the DMA ring. 1053 * Returns 0 on success, error on failure. 1054 */ 1055 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1056 { 1057 struct amdgpu_device *adev = ring->adev; 1058 struct amdgpu_ib ib; 1059 struct dma_fence *f = NULL; 1060 unsigned index; 1061 long r; 1062 u32 tmp = 0; 1063 u64 gpu_addr; 1064 volatile uint32_t *cpu_ptr = NULL; 1065 1066 tmp = 0xCAFEDEAD; 1067 memset(&ib, 0, sizeof(ib)); 1068 1069 if (ring->is_mes_queue) { 1070 uint32_t offset = 0; 1071 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 1072 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 1073 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 1074 1075 offset = amdgpu_mes_ctx_get_offs(ring, 1076 AMDGPU_MES_CTX_PADDING_OFFS); 1077 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 1078 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 1079 *cpu_ptr = tmp; 1080 } else { 1081 r = amdgpu_device_wb_get(adev, &index); 1082 if (r) { 1083 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 1084 return r; 1085 } 1086 1087 gpu_addr = adev->wb.gpu_addr + (index * 4); 1088 adev->wb.wb[index] = cpu_to_le32(tmp); 1089 1090 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 1091 if (r) { 1092 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1093 goto err0; 1094 } 1095 } 1096 1097 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1098 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1099 ib.ptr[1] = lower_32_bits(gpu_addr); 1100 ib.ptr[2] = upper_32_bits(gpu_addr); 1101 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1102 ib.ptr[4] = 0xDEADBEEF; 1103 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1104 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1105 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1106 ib.length_dw = 8; 1107 1108 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1109 if (r) 1110 goto err1; 1111 1112 r = dma_fence_wait_timeout(f, false, timeout); 1113 if (r == 0) { 1114 DRM_ERROR("amdgpu: IB test timed out\n"); 1115 r = -ETIMEDOUT; 1116 goto err1; 1117 } else if (r < 0) { 1118 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1119 goto err1; 1120 } 1121 1122 if (ring->is_mes_queue) 1123 tmp = le32_to_cpu(*cpu_ptr); 1124 else 1125 tmp = le32_to_cpu(adev->wb.wb[index]); 1126 1127 if (tmp == 0xDEADBEEF) 1128 r = 0; 1129 else 1130 r = -EINVAL; 1131 1132 err1: 1133 amdgpu_ib_free(adev, &ib, NULL); 1134 dma_fence_put(f); 1135 err0: 1136 if (!ring->is_mes_queue) 1137 amdgpu_device_wb_free(adev, index); 1138 return r; 1139 } 1140 1141 1142 /** 1143 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART 1144 * 1145 * @ib: indirect buffer to fill with commands 1146 * @pe: addr of the page entry 1147 * @src: src addr to copy from 1148 * @count: number of page entries to update 1149 * 1150 * Update PTEs by copying them from the GART using sDMA. 1151 */ 1152 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib, 1153 uint64_t pe, uint64_t src, 1154 unsigned count) 1155 { 1156 unsigned bytes = count * 8; 1157 1158 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1159 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1160 ib->ptr[ib->length_dw++] = bytes - 1; 1161 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1162 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1163 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1164 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1165 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1166 1167 } 1168 1169 /** 1170 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually 1171 * 1172 * @ib: indirect buffer to fill with commands 1173 * @pe: addr of the page entry 1174 * @value: dst addr to write into pe 1175 * @count: number of page entries to update 1176 * @incr: increase next addr by incr bytes 1177 * 1178 * Update PTEs by writing them manually using sDMA. 1179 */ 1180 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1181 uint64_t value, unsigned count, 1182 uint32_t incr) 1183 { 1184 unsigned ndw = count * 2; 1185 1186 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1187 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1188 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1189 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1190 ib->ptr[ib->length_dw++] = ndw - 1; 1191 for (; ndw > 0; ndw -= 2) { 1192 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1193 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1194 value += incr; 1195 } 1196 } 1197 1198 /** 1199 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA 1200 * 1201 * @ib: indirect buffer to fill with commands 1202 * @pe: addr of the page entry 1203 * @addr: dst addr to write into pe 1204 * @count: number of page entries to update 1205 * @incr: increase next addr by incr bytes 1206 * @flags: access flags 1207 * 1208 * Update the page tables using sDMA. 1209 */ 1210 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1211 uint64_t pe, 1212 uint64_t addr, unsigned count, 1213 uint32_t incr, uint64_t flags) 1214 { 1215 /* for physically contiguous pages (vram) */ 1216 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1217 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1218 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1219 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1220 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1221 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1222 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1223 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1224 ib->ptr[ib->length_dw++] = 0; 1225 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1226 } 1227 1228 /** 1229 * sdma_v5_2_ring_pad_ib - pad the IB 1230 * 1231 * @ib: indirect buffer to fill with padding 1232 * @ring: amdgpu_ring structure holding ring information 1233 * 1234 * Pad the IB with NOPs to a boundary multiple of 8. 1235 */ 1236 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1237 { 1238 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1239 u32 pad_count; 1240 int i; 1241 1242 pad_count = (-ib->length_dw) & 0x7; 1243 for (i = 0; i < pad_count; i++) 1244 if (sdma && sdma->burst_nop && (i == 0)) 1245 ib->ptr[ib->length_dw++] = 1246 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1247 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1248 else 1249 ib->ptr[ib->length_dw++] = 1250 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1251 } 1252 1253 1254 /** 1255 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline 1256 * 1257 * @ring: amdgpu_ring pointer 1258 * 1259 * Make sure all previous operations are completed (CIK). 1260 */ 1261 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1262 { 1263 uint32_t seq = ring->fence_drv.sync_seq; 1264 uint64_t addr = ring->fence_drv.gpu_addr; 1265 1266 /* wait for idle */ 1267 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1268 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1269 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1270 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1271 amdgpu_ring_write(ring, addr & 0xfffffffc); 1272 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1273 amdgpu_ring_write(ring, seq); /* reference */ 1274 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1275 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1276 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1277 } 1278 1279 1280 /** 1281 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA 1282 * 1283 * @ring: amdgpu_ring pointer 1284 * @vmid: vmid number to use 1285 * @pd_addr: address 1286 * 1287 * Update the page table base and flush the VM TLB 1288 * using sDMA. 1289 */ 1290 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1291 unsigned vmid, uint64_t pd_addr) 1292 { 1293 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1294 } 1295 1296 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring, 1297 uint32_t reg, uint32_t val) 1298 { 1299 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1300 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1301 amdgpu_ring_write(ring, reg); 1302 amdgpu_ring_write(ring, val); 1303 } 1304 1305 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1306 uint32_t val, uint32_t mask) 1307 { 1308 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1309 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1310 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1311 amdgpu_ring_write(ring, reg << 2); 1312 amdgpu_ring_write(ring, 0); 1313 amdgpu_ring_write(ring, val); /* reference */ 1314 amdgpu_ring_write(ring, mask); /* mask */ 1315 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1316 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1317 } 1318 1319 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1320 uint32_t reg0, uint32_t reg1, 1321 uint32_t ref, uint32_t mask) 1322 { 1323 amdgpu_ring_emit_wreg(ring, reg0, ref); 1324 /* wait for a cycle to reset vm_inv_eng*_ack */ 1325 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1326 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1327 } 1328 1329 static int sdma_v5_2_early_init(void *handle) 1330 { 1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1332 1333 sdma_v5_2_set_ring_funcs(adev); 1334 sdma_v5_2_set_buffer_funcs(adev); 1335 sdma_v5_2_set_vm_pte_funcs(adev); 1336 sdma_v5_2_set_irq_funcs(adev); 1337 sdma_v5_2_set_mqd_funcs(adev); 1338 1339 return 0; 1340 } 1341 1342 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num) 1343 { 1344 switch (seq_num) { 1345 case 0: 1346 return SOC15_IH_CLIENTID_SDMA0; 1347 case 1: 1348 return SOC15_IH_CLIENTID_SDMA1; 1349 case 2: 1350 return SOC15_IH_CLIENTID_SDMA2; 1351 case 3: 1352 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid; 1353 default: 1354 break; 1355 } 1356 return -EINVAL; 1357 } 1358 1359 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num) 1360 { 1361 switch (seq_num) { 1362 case 0: 1363 return SDMA0_5_0__SRCID__SDMA_TRAP; 1364 case 1: 1365 return SDMA1_5_0__SRCID__SDMA_TRAP; 1366 case 2: 1367 return SDMA2_5_0__SRCID__SDMA_TRAP; 1368 case 3: 1369 return SDMA3_5_0__SRCID__SDMA_TRAP; 1370 default: 1371 break; 1372 } 1373 return -EINVAL; 1374 } 1375 1376 static int sdma_v5_2_sw_init(void *handle) 1377 { 1378 struct amdgpu_ring *ring; 1379 int r, i; 1380 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1381 1382 /* SDMA trap event */ 1383 for (i = 0; i < adev->sdma.num_instances; i++) { 1384 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i), 1385 sdma_v5_2_seq_to_trap_id(i), 1386 &adev->sdma.trap_irq); 1387 if (r) 1388 return r; 1389 } 1390 1391 r = sdma_v5_2_init_microcode(adev); 1392 if (r) { 1393 DRM_ERROR("Failed to load sdma firmware!\n"); 1394 return r; 1395 } 1396 1397 for (i = 0; i < adev->sdma.num_instances; i++) { 1398 ring = &adev->sdma.instance[i].ring; 1399 ring->ring_obj = NULL; 1400 ring->use_doorbell = true; 1401 ring->me = i; 1402 1403 DRM_INFO("use_doorbell being set to: [%s]\n", 1404 ring->use_doorbell?"true":"false"); 1405 1406 ring->doorbell_index = 1407 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset 1408 1409 sprintf(ring->name, "sdma%d", i); 1410 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1411 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1412 AMDGPU_RING_PRIO_DEFAULT, NULL); 1413 if (r) 1414 return r; 1415 } 1416 1417 return r; 1418 } 1419 1420 static int sdma_v5_2_sw_fini(void *handle) 1421 { 1422 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1423 int i; 1424 1425 for (i = 0; i < adev->sdma.num_instances; i++) 1426 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1427 1428 sdma_v5_2_destroy_inst_ctx(adev); 1429 1430 return 0; 1431 } 1432 1433 static int sdma_v5_2_hw_init(void *handle) 1434 { 1435 int r; 1436 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1437 1438 r = sdma_v5_2_start(adev); 1439 1440 return r; 1441 } 1442 1443 static int sdma_v5_2_hw_fini(void *handle) 1444 { 1445 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1446 1447 if (amdgpu_sriov_vf(adev)) 1448 return 0; 1449 1450 sdma_v5_2_ctx_switch_disable_all(adev); 1451 sdma_v5_2_halt(adev); 1452 1453 return 0; 1454 } 1455 1456 static int sdma_v5_2_suspend(void *handle) 1457 { 1458 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1459 1460 return sdma_v5_2_hw_fini(adev); 1461 } 1462 1463 static int sdma_v5_2_resume(void *handle) 1464 { 1465 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1466 1467 return sdma_v5_2_hw_init(adev); 1468 } 1469 1470 static bool sdma_v5_2_is_idle(void *handle) 1471 { 1472 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1473 u32 i; 1474 1475 for (i = 0; i < adev->sdma.num_instances; i++) { 1476 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1477 1478 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1479 return false; 1480 } 1481 1482 return true; 1483 } 1484 1485 static int sdma_v5_2_wait_for_idle(void *handle) 1486 { 1487 unsigned i; 1488 u32 sdma0, sdma1, sdma2, sdma3; 1489 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1490 1491 for (i = 0; i < adev->usec_timeout; i++) { 1492 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1493 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1494 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG)); 1495 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG)); 1496 1497 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK) 1498 return 0; 1499 udelay(1); 1500 } 1501 return -ETIMEDOUT; 1502 } 1503 1504 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) 1505 { 1506 int i, r = 0; 1507 struct amdgpu_device *adev = ring->adev; 1508 u32 index = 0; 1509 u64 sdma_gfx_preempt; 1510 1511 amdgpu_sdma_get_index_from_ring(ring, &index); 1512 sdma_gfx_preempt = 1513 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT); 1514 1515 /* assert preemption condition */ 1516 amdgpu_ring_set_preempt_cond_exec(ring, false); 1517 1518 /* emit the trailing fence */ 1519 ring->trail_seq += 1; 1520 amdgpu_ring_alloc(ring, 10); 1521 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1522 ring->trail_seq, 0); 1523 amdgpu_ring_commit(ring); 1524 1525 /* assert IB preemption */ 1526 WREG32(sdma_gfx_preempt, 1); 1527 1528 /* poll the trailing fence */ 1529 for (i = 0; i < adev->usec_timeout; i++) { 1530 if (ring->trail_seq == 1531 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1532 break; 1533 udelay(1); 1534 } 1535 1536 if (i >= adev->usec_timeout) { 1537 r = -EINVAL; 1538 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1539 } 1540 1541 /* deassert IB preemption */ 1542 WREG32(sdma_gfx_preempt, 0); 1543 1544 /* deassert the preemption condition */ 1545 amdgpu_ring_set_preempt_cond_exec(ring, true); 1546 return r; 1547 } 1548 1549 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev, 1550 struct amdgpu_irq_src *source, 1551 unsigned type, 1552 enum amdgpu_interrupt_state state) 1553 { 1554 u32 sdma_cntl; 1555 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); 1556 1557 if (!amdgpu_sriov_vf(adev)) { 1558 sdma_cntl = RREG32(reg_offset); 1559 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1560 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1561 WREG32(reg_offset, sdma_cntl); 1562 } 1563 1564 return 0; 1565 } 1566 1567 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, 1568 struct amdgpu_irq_src *source, 1569 struct amdgpu_iv_entry *entry) 1570 { 1571 uint32_t mes_queue_id = entry->src_data[0]; 1572 1573 DRM_DEBUG("IH: SDMA trap\n"); 1574 1575 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1576 struct amdgpu_mes_queue *queue; 1577 1578 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1579 1580 spin_lock(&adev->mes.queue_id_lock); 1581 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1582 if (queue) { 1583 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1584 amdgpu_fence_process(queue->ring); 1585 } 1586 spin_unlock(&adev->mes.queue_id_lock); 1587 return 0; 1588 } 1589 1590 switch (entry->client_id) { 1591 case SOC15_IH_CLIENTID_SDMA0: 1592 switch (entry->ring_id) { 1593 case 0: 1594 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1595 break; 1596 case 1: 1597 /* XXX compute */ 1598 break; 1599 case 2: 1600 /* XXX compute */ 1601 break; 1602 case 3: 1603 /* XXX page queue*/ 1604 break; 1605 } 1606 break; 1607 case SOC15_IH_CLIENTID_SDMA1: 1608 switch (entry->ring_id) { 1609 case 0: 1610 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1611 break; 1612 case 1: 1613 /* XXX compute */ 1614 break; 1615 case 2: 1616 /* XXX compute */ 1617 break; 1618 case 3: 1619 /* XXX page queue*/ 1620 break; 1621 } 1622 break; 1623 case SOC15_IH_CLIENTID_SDMA2: 1624 switch (entry->ring_id) { 1625 case 0: 1626 amdgpu_fence_process(&adev->sdma.instance[2].ring); 1627 break; 1628 case 1: 1629 /* XXX compute */ 1630 break; 1631 case 2: 1632 /* XXX compute */ 1633 break; 1634 case 3: 1635 /* XXX page queue*/ 1636 break; 1637 } 1638 break; 1639 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid: 1640 switch (entry->ring_id) { 1641 case 0: 1642 amdgpu_fence_process(&adev->sdma.instance[3].ring); 1643 break; 1644 case 1: 1645 /* XXX compute */ 1646 break; 1647 case 2: 1648 /* XXX compute */ 1649 break; 1650 case 3: 1651 /* XXX page queue*/ 1652 break; 1653 } 1654 break; 1655 } 1656 return 0; 1657 } 1658 1659 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1660 struct amdgpu_irq_src *source, 1661 struct amdgpu_iv_entry *entry) 1662 { 1663 return 0; 1664 } 1665 1666 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1667 bool enable) 1668 { 1669 uint32_t data, def; 1670 int i; 1671 1672 for (i = 0; i < adev->sdma.num_instances; i++) { 1673 1674 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1)) 1675 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG; 1676 1677 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1678 /* Enable sdma clock gating */ 1679 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1680 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1681 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1682 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1683 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1684 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1685 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1686 if (def != data) 1687 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1688 } else { 1689 /* Disable sdma clock gating */ 1690 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1691 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1692 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1693 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1694 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1695 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1696 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1697 if (def != data) 1698 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1699 } 1700 } 1701 } 1702 1703 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1704 bool enable) 1705 { 1706 uint32_t data, def; 1707 int i; 1708 1709 for (i = 0; i < adev->sdma.num_instances; i++) { 1710 1711 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1)) 1712 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS; 1713 1714 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1715 /* Enable sdma mem light sleep */ 1716 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1717 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1718 if (def != data) 1719 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1720 1721 } else { 1722 /* Disable sdma mem light sleep */ 1723 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1724 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1725 if (def != data) 1726 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1727 1728 } 1729 } 1730 } 1731 1732 static int sdma_v5_2_set_clockgating_state(void *handle, 1733 enum amd_clockgating_state state) 1734 { 1735 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1736 1737 if (amdgpu_sriov_vf(adev)) 1738 return 0; 1739 1740 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1741 case IP_VERSION(5, 2, 0): 1742 case IP_VERSION(5, 2, 2): 1743 case IP_VERSION(5, 2, 1): 1744 case IP_VERSION(5, 2, 4): 1745 case IP_VERSION(5, 2, 5): 1746 case IP_VERSION(5, 2, 6): 1747 case IP_VERSION(5, 2, 3): 1748 sdma_v5_2_update_medium_grain_clock_gating(adev, 1749 state == AMD_CG_STATE_GATE); 1750 sdma_v5_2_update_medium_grain_light_sleep(adev, 1751 state == AMD_CG_STATE_GATE); 1752 break; 1753 default: 1754 break; 1755 } 1756 1757 return 0; 1758 } 1759 1760 static int sdma_v5_2_set_powergating_state(void *handle, 1761 enum amd_powergating_state state) 1762 { 1763 return 0; 1764 } 1765 1766 static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags) 1767 { 1768 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1769 int data; 1770 1771 if (amdgpu_sriov_vf(adev)) 1772 *flags = 0; 1773 1774 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1775 data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1776 if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK)) 1777 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1778 1779 /* AMD_CG_SUPPORT_SDMA_LS */ 1780 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1781 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1782 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1783 } 1784 1785 const struct amd_ip_funcs sdma_v5_2_ip_funcs = { 1786 .name = "sdma_v5_2", 1787 .early_init = sdma_v5_2_early_init, 1788 .late_init = NULL, 1789 .sw_init = sdma_v5_2_sw_init, 1790 .sw_fini = sdma_v5_2_sw_fini, 1791 .hw_init = sdma_v5_2_hw_init, 1792 .hw_fini = sdma_v5_2_hw_fini, 1793 .suspend = sdma_v5_2_suspend, 1794 .resume = sdma_v5_2_resume, 1795 .is_idle = sdma_v5_2_is_idle, 1796 .wait_for_idle = sdma_v5_2_wait_for_idle, 1797 .soft_reset = sdma_v5_2_soft_reset, 1798 .set_clockgating_state = sdma_v5_2_set_clockgating_state, 1799 .set_powergating_state = sdma_v5_2_set_powergating_state, 1800 .get_clockgating_state = sdma_v5_2_get_clockgating_state, 1801 }; 1802 1803 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { 1804 .type = AMDGPU_RING_TYPE_SDMA, 1805 .align_mask = 0xf, 1806 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1807 .support_64bit_ptrs = true, 1808 .secure_submission_supported = true, 1809 .vmhub = AMDGPU_GFXHUB_0, 1810 .get_rptr = sdma_v5_2_ring_get_rptr, 1811 .get_wptr = sdma_v5_2_ring_get_wptr, 1812 .set_wptr = sdma_v5_2_ring_set_wptr, 1813 .emit_frame_size = 1814 5 + /* sdma_v5_2_ring_init_cond_exec */ 1815 6 + /* sdma_v5_2_ring_emit_hdp_flush */ 1816 3 + /* hdp_invalidate */ 1817 6 + /* sdma_v5_2_ring_emit_pipeline_sync */ 1818 /* sdma_v5_2_ring_emit_vm_flush */ 1819 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1820 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1821 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */ 1822 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */ 1823 .emit_ib = sdma_v5_2_ring_emit_ib, 1824 .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync, 1825 .emit_fence = sdma_v5_2_ring_emit_fence, 1826 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync, 1827 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush, 1828 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush, 1829 .test_ring = sdma_v5_2_ring_test_ring, 1830 .test_ib = sdma_v5_2_ring_test_ib, 1831 .insert_nop = sdma_v5_2_ring_insert_nop, 1832 .pad_ib = sdma_v5_2_ring_pad_ib, 1833 .emit_wreg = sdma_v5_2_ring_emit_wreg, 1834 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait, 1835 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait, 1836 .init_cond_exec = sdma_v5_2_ring_init_cond_exec, 1837 .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec, 1838 .preempt_ib = sdma_v5_2_ring_preempt_ib, 1839 }; 1840 1841 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev) 1842 { 1843 int i; 1844 1845 for (i = 0; i < adev->sdma.num_instances; i++) { 1846 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs; 1847 adev->sdma.instance[i].ring.me = i; 1848 } 1849 } 1850 1851 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = { 1852 .set = sdma_v5_2_set_trap_irq_state, 1853 .process = sdma_v5_2_process_trap_irq, 1854 }; 1855 1856 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = { 1857 .process = sdma_v5_2_process_illegal_inst_irq, 1858 }; 1859 1860 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev) 1861 { 1862 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1863 adev->sdma.num_instances; 1864 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs; 1865 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs; 1866 } 1867 1868 /** 1869 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine 1870 * 1871 * @ib: indirect buffer to copy to 1872 * @src_offset: src GPU address 1873 * @dst_offset: dst GPU address 1874 * @byte_count: number of bytes to xfer 1875 * @tmz: if a secure copy should be used 1876 * 1877 * Copy GPU buffers using the DMA engine. 1878 * Used by the amdgpu ttm implementation to move pages if 1879 * registered as the asic copy callback. 1880 */ 1881 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib, 1882 uint64_t src_offset, 1883 uint64_t dst_offset, 1884 uint32_t byte_count, 1885 bool tmz) 1886 { 1887 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1888 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1889 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1890 ib->ptr[ib->length_dw++] = byte_count - 1; 1891 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1892 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1893 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1894 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1895 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1896 } 1897 1898 /** 1899 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine 1900 * 1901 * @ib: indirect buffer to fill 1902 * @src_data: value to write to buffer 1903 * @dst_offset: dst GPU address 1904 * @byte_count: number of bytes to xfer 1905 * 1906 * Fill GPU buffers using the DMA engine. 1907 */ 1908 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, 1909 uint32_t src_data, 1910 uint64_t dst_offset, 1911 uint32_t byte_count) 1912 { 1913 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1914 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1915 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1916 ib->ptr[ib->length_dw++] = src_data; 1917 ib->ptr[ib->length_dw++] = byte_count - 1; 1918 } 1919 1920 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { 1921 .copy_max_bytes = 0x400000, 1922 .copy_num_dw = 7, 1923 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer, 1924 1925 .fill_max_bytes = 0x400000, 1926 .fill_num_dw = 5, 1927 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer, 1928 }; 1929 1930 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) 1931 { 1932 if (adev->mman.buffer_funcs == NULL) { 1933 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; 1934 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1935 } 1936 } 1937 1938 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { 1939 .copy_pte_num_dw = 7, 1940 .copy_pte = sdma_v5_2_vm_copy_pte, 1941 .write_pte = sdma_v5_2_vm_write_pte, 1942 .set_pte_pde = sdma_v5_2_vm_set_pte_pde, 1943 }; 1944 1945 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) 1946 { 1947 unsigned i; 1948 1949 if (adev->vm_manager.vm_pte_funcs == NULL) { 1950 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; 1951 for (i = 0; i < adev->sdma.num_instances; i++) { 1952 adev->vm_manager.vm_pte_scheds[i] = 1953 &adev->sdma.instance[i].ring.sched; 1954 } 1955 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1956 } 1957 } 1958 1959 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { 1960 .type = AMD_IP_BLOCK_TYPE_SDMA, 1961 .major = 5, 1962 .minor = 2, 1963 .rev = 0, 1964 .funcs = &sdma_v5_2_ip_funcs, 1965 }; 1966