1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gcc-sdm845.h> 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12#include <dt-bindings/clock/qcom,lpass-sdm845.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sdm845.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/firmware/qcom,scm.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/interconnect/qcom,osm-l3.h> 19#include <dt-bindings/interconnect/qcom,sdm845.h> 20#include <dt-bindings/interrupt-controller/arm-gic.h> 21#include <dt-bindings/phy/phy-qcom-qusb2.h> 22#include <dt-bindings/power/qcom-rpmpd.h> 23#include <dt-bindings/reset/qcom,sdm845-aoss.h> 24#include <dt-bindings/reset/qcom,sdm845-pdc.h> 25#include <dt-bindings/soc/qcom,apr.h> 26#include <dt-bindings/soc/qcom,rpmh-rsc.h> 27#include <dt-bindings/clock/qcom,gcc-sdm845.h> 28#include <dt-bindings/thermal/thermal.h> 29 30/ { 31 interrupt-parent = <&intc>; 32 33 #address-cells = <2>; 34 #size-cells = <2>; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 spi0 = &spi0; 54 spi1 = &spi1; 55 spi2 = &spi2; 56 spi3 = &spi3; 57 spi4 = &spi4; 58 spi5 = &spi5; 59 spi6 = &spi6; 60 spi7 = &spi7; 61 spi8 = &spi8; 62 spi9 = &spi9; 63 spi10 = &spi10; 64 spi11 = &spi11; 65 spi12 = &spi12; 66 spi13 = &spi13; 67 spi14 = &spi14; 68 spi15 = &spi15; 69 }; 70 71 chosen { }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <38400000>; 78 clock-output-names = "xo_board"; 79 }; 80 81 sleep_clk: sleep-clk { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <32764>; 85 }; 86 }; 87 88 cpus: cpus { 89 #address-cells = <2>; 90 #size-cells = <0>; 91 92 CPU0: cpu@0 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo385"; 95 reg = <0x0 0x0>; 96 clocks = <&cpufreq_hw 0>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <611>; 99 dynamic-power-coefficient = <154>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 operating-points-v2 = <&cpu0_opp_table>; 102 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 104 power-domains = <&CPU_PD0>; 105 power-domain-names = "psci"; 106 #cooling-cells = <2>; 107 next-level-cache = <&L2_0>; 108 L2_0: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 next-level-cache = <&L3_0>; 112 L3_0: l3-cache { 113 compatible = "cache"; 114 cache-level = <3>; 115 }; 116 }; 117 }; 118 119 CPU1: cpu@100 { 120 device_type = "cpu"; 121 compatible = "qcom,kryo385"; 122 reg = <0x0 0x100>; 123 clocks = <&cpufreq_hw 0>; 124 enable-method = "psci"; 125 capacity-dmips-mhz = <611>; 126 dynamic-power-coefficient = <154>; 127 qcom,freq-domain = <&cpufreq_hw 0>; 128 operating-points-v2 = <&cpu0_opp_table>; 129 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 130 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 131 power-domains = <&CPU_PD1>; 132 power-domain-names = "psci"; 133 #cooling-cells = <2>; 134 next-level-cache = <&L2_100>; 135 L2_100: l2-cache { 136 compatible = "cache"; 137 cache-level = <2>; 138 next-level-cache = <&L3_0>; 139 }; 140 }; 141 142 CPU2: cpu@200 { 143 device_type = "cpu"; 144 compatible = "qcom,kryo385"; 145 reg = <0x0 0x200>; 146 clocks = <&cpufreq_hw 0>; 147 enable-method = "psci"; 148 capacity-dmips-mhz = <611>; 149 dynamic-power-coefficient = <154>; 150 qcom,freq-domain = <&cpufreq_hw 0>; 151 operating-points-v2 = <&cpu0_opp_table>; 152 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 153 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 154 power-domains = <&CPU_PD2>; 155 power-domain-names = "psci"; 156 #cooling-cells = <2>; 157 next-level-cache = <&L2_200>; 158 L2_200: l2-cache { 159 compatible = "cache"; 160 cache-level = <2>; 161 next-level-cache = <&L3_0>; 162 }; 163 }; 164 165 CPU3: cpu@300 { 166 device_type = "cpu"; 167 compatible = "qcom,kryo385"; 168 reg = <0x0 0x300>; 169 clocks = <&cpufreq_hw 0>; 170 enable-method = "psci"; 171 capacity-dmips-mhz = <611>; 172 dynamic-power-coefficient = <154>; 173 qcom,freq-domain = <&cpufreq_hw 0>; 174 operating-points-v2 = <&cpu0_opp_table>; 175 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 176 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 177 #cooling-cells = <2>; 178 power-domains = <&CPU_PD3>; 179 power-domain-names = "psci"; 180 next-level-cache = <&L2_300>; 181 L2_300: l2-cache { 182 compatible = "cache"; 183 cache-level = <2>; 184 next-level-cache = <&L3_0>; 185 }; 186 }; 187 188 CPU4: cpu@400 { 189 device_type = "cpu"; 190 compatible = "qcom,kryo385"; 191 reg = <0x0 0x400>; 192 clocks = <&cpufreq_hw 1>; 193 enable-method = "psci"; 194 capacity-dmips-mhz = <1024>; 195 dynamic-power-coefficient = <442>; 196 qcom,freq-domain = <&cpufreq_hw 1>; 197 operating-points-v2 = <&cpu4_opp_table>; 198 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 199 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 200 power-domains = <&CPU_PD4>; 201 power-domain-names = "psci"; 202 #cooling-cells = <2>; 203 next-level-cache = <&L2_400>; 204 L2_400: l2-cache { 205 compatible = "cache"; 206 cache-level = <2>; 207 next-level-cache = <&L3_0>; 208 }; 209 }; 210 211 CPU5: cpu@500 { 212 device_type = "cpu"; 213 compatible = "qcom,kryo385"; 214 reg = <0x0 0x500>; 215 clocks = <&cpufreq_hw 1>; 216 enable-method = "psci"; 217 capacity-dmips-mhz = <1024>; 218 dynamic-power-coefficient = <442>; 219 qcom,freq-domain = <&cpufreq_hw 1>; 220 operating-points-v2 = <&cpu4_opp_table>; 221 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 222 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 223 power-domains = <&CPU_PD5>; 224 power-domain-names = "psci"; 225 #cooling-cells = <2>; 226 next-level-cache = <&L2_500>; 227 L2_500: l2-cache { 228 compatible = "cache"; 229 cache-level = <2>; 230 next-level-cache = <&L3_0>; 231 }; 232 }; 233 234 CPU6: cpu@600 { 235 device_type = "cpu"; 236 compatible = "qcom,kryo385"; 237 reg = <0x0 0x600>; 238 clocks = <&cpufreq_hw 1>; 239 enable-method = "psci"; 240 capacity-dmips-mhz = <1024>; 241 dynamic-power-coefficient = <442>; 242 qcom,freq-domain = <&cpufreq_hw 1>; 243 operating-points-v2 = <&cpu4_opp_table>; 244 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 245 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 246 power-domains = <&CPU_PD6>; 247 power-domain-names = "psci"; 248 #cooling-cells = <2>; 249 next-level-cache = <&L2_600>; 250 L2_600: l2-cache { 251 compatible = "cache"; 252 cache-level = <2>; 253 next-level-cache = <&L3_0>; 254 }; 255 }; 256 257 CPU7: cpu@700 { 258 device_type = "cpu"; 259 compatible = "qcom,kryo385"; 260 reg = <0x0 0x700>; 261 clocks = <&cpufreq_hw 1>; 262 enable-method = "psci"; 263 capacity-dmips-mhz = <1024>; 264 dynamic-power-coefficient = <442>; 265 qcom,freq-domain = <&cpufreq_hw 1>; 266 operating-points-v2 = <&cpu4_opp_table>; 267 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 268 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 269 power-domains = <&CPU_PD7>; 270 power-domain-names = "psci"; 271 #cooling-cells = <2>; 272 next-level-cache = <&L2_700>; 273 L2_700: l2-cache { 274 compatible = "cache"; 275 cache-level = <2>; 276 next-level-cache = <&L3_0>; 277 }; 278 }; 279 280 cpu-map { 281 cluster0 { 282 core0 { 283 cpu = <&CPU0>; 284 }; 285 286 core1 { 287 cpu = <&CPU1>; 288 }; 289 290 core2 { 291 cpu = <&CPU2>; 292 }; 293 294 core3 { 295 cpu = <&CPU3>; 296 }; 297 298 core4 { 299 cpu = <&CPU4>; 300 }; 301 302 core5 { 303 cpu = <&CPU5>; 304 }; 305 306 core6 { 307 cpu = <&CPU6>; 308 }; 309 310 core7 { 311 cpu = <&CPU7>; 312 }; 313 }; 314 }; 315 316 cpu_idle_states: idle-states { 317 entry-method = "psci"; 318 319 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 320 compatible = "arm,idle-state"; 321 idle-state-name = "little-rail-power-collapse"; 322 arm,psci-suspend-param = <0x40000004>; 323 entry-latency-us = <350>; 324 exit-latency-us = <461>; 325 min-residency-us = <1890>; 326 local-timer-stop; 327 }; 328 329 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 330 compatible = "arm,idle-state"; 331 idle-state-name = "big-rail-power-collapse"; 332 arm,psci-suspend-param = <0x40000004>; 333 entry-latency-us = <264>; 334 exit-latency-us = <621>; 335 min-residency-us = <952>; 336 local-timer-stop; 337 }; 338 }; 339 340 domain-idle-states { 341 CLUSTER_SLEEP_0: cluster-sleep-0 { 342 compatible = "domain-idle-state"; 343 arm,psci-suspend-param = <0x4100c244>; 344 entry-latency-us = <3263>; 345 exit-latency-us = <6562>; 346 min-residency-us = <9987>; 347 }; 348 }; 349 }; 350 351 firmware { 352 scm { 353 compatible = "qcom,scm-sdm845", "qcom,scm"; 354 }; 355 }; 356 357 memory@80000000 { 358 device_type = "memory"; 359 /* We expect the bootloader to fill in the size */ 360 reg = <0 0x80000000 0 0>; 361 }; 362 363 cpu0_opp_table: opp-table-cpu0 { 364 compatible = "operating-points-v2"; 365 opp-shared; 366 367 cpu0_opp1: opp-300000000 { 368 opp-hz = /bits/ 64 <300000000>; 369 opp-peak-kBps = <800000 4800000>; 370 }; 371 372 cpu0_opp2: opp-403200000 { 373 opp-hz = /bits/ 64 <403200000>; 374 opp-peak-kBps = <800000 4800000>; 375 }; 376 377 cpu0_opp3: opp-480000000 { 378 opp-hz = /bits/ 64 <480000000>; 379 opp-peak-kBps = <800000 6451200>; 380 }; 381 382 cpu0_opp4: opp-576000000 { 383 opp-hz = /bits/ 64 <576000000>; 384 opp-peak-kBps = <800000 6451200>; 385 }; 386 387 cpu0_opp5: opp-652800000 { 388 opp-hz = /bits/ 64 <652800000>; 389 opp-peak-kBps = <800000 7680000>; 390 }; 391 392 cpu0_opp6: opp-748800000 { 393 opp-hz = /bits/ 64 <748800000>; 394 opp-peak-kBps = <1804000 9216000>; 395 }; 396 397 cpu0_opp7: opp-825600000 { 398 opp-hz = /bits/ 64 <825600000>; 399 opp-peak-kBps = <1804000 9216000>; 400 }; 401 402 cpu0_opp8: opp-902400000 { 403 opp-hz = /bits/ 64 <902400000>; 404 opp-peak-kBps = <1804000 10444800>; 405 }; 406 407 cpu0_opp9: opp-979200000 { 408 opp-hz = /bits/ 64 <979200000>; 409 opp-peak-kBps = <1804000 11980800>; 410 }; 411 412 cpu0_opp10: opp-1056000000 { 413 opp-hz = /bits/ 64 <1056000000>; 414 opp-peak-kBps = <1804000 11980800>; 415 }; 416 417 cpu0_opp11: opp-1132800000 { 418 opp-hz = /bits/ 64 <1132800000>; 419 opp-peak-kBps = <2188000 13516800>; 420 }; 421 422 cpu0_opp12: opp-1228800000 { 423 opp-hz = /bits/ 64 <1228800000>; 424 opp-peak-kBps = <2188000 15052800>; 425 }; 426 427 cpu0_opp13: opp-1324800000 { 428 opp-hz = /bits/ 64 <1324800000>; 429 opp-peak-kBps = <2188000 16588800>; 430 }; 431 432 cpu0_opp14: opp-1420800000 { 433 opp-hz = /bits/ 64 <1420800000>; 434 opp-peak-kBps = <3072000 18124800>; 435 }; 436 437 cpu0_opp15: opp-1516800000 { 438 opp-hz = /bits/ 64 <1516800000>; 439 opp-peak-kBps = <3072000 19353600>; 440 }; 441 442 cpu0_opp16: opp-1612800000 { 443 opp-hz = /bits/ 64 <1612800000>; 444 opp-peak-kBps = <4068000 19353600>; 445 }; 446 447 cpu0_opp17: opp-1689600000 { 448 opp-hz = /bits/ 64 <1689600000>; 449 opp-peak-kBps = <4068000 20889600>; 450 }; 451 452 cpu0_opp18: opp-1766400000 { 453 opp-hz = /bits/ 64 <1766400000>; 454 opp-peak-kBps = <4068000 22425600>; 455 }; 456 }; 457 458 cpu4_opp_table: opp-table-cpu4 { 459 compatible = "operating-points-v2"; 460 opp-shared; 461 462 cpu4_opp1: opp-300000000 { 463 opp-hz = /bits/ 64 <300000000>; 464 opp-peak-kBps = <800000 4800000>; 465 }; 466 467 cpu4_opp2: opp-403200000 { 468 opp-hz = /bits/ 64 <403200000>; 469 opp-peak-kBps = <800000 4800000>; 470 }; 471 472 cpu4_opp3: opp-480000000 { 473 opp-hz = /bits/ 64 <480000000>; 474 opp-peak-kBps = <1804000 4800000>; 475 }; 476 477 cpu4_opp4: opp-576000000 { 478 opp-hz = /bits/ 64 <576000000>; 479 opp-peak-kBps = <1804000 4800000>; 480 }; 481 482 cpu4_opp5: opp-652800000 { 483 opp-hz = /bits/ 64 <652800000>; 484 opp-peak-kBps = <1804000 4800000>; 485 }; 486 487 cpu4_opp6: opp-748800000 { 488 opp-hz = /bits/ 64 <748800000>; 489 opp-peak-kBps = <1804000 4800000>; 490 }; 491 492 cpu4_opp7: opp-825600000 { 493 opp-hz = /bits/ 64 <825600000>; 494 opp-peak-kBps = <2188000 9216000>; 495 }; 496 497 cpu4_opp8: opp-902400000 { 498 opp-hz = /bits/ 64 <902400000>; 499 opp-peak-kBps = <2188000 9216000>; 500 }; 501 502 cpu4_opp9: opp-979200000 { 503 opp-hz = /bits/ 64 <979200000>; 504 opp-peak-kBps = <2188000 9216000>; 505 }; 506 507 cpu4_opp10: opp-1056000000 { 508 opp-hz = /bits/ 64 <1056000000>; 509 opp-peak-kBps = <3072000 9216000>; 510 }; 511 512 cpu4_opp11: opp-1132800000 { 513 opp-hz = /bits/ 64 <1132800000>; 514 opp-peak-kBps = <3072000 11980800>; 515 }; 516 517 cpu4_opp12: opp-1209600000 { 518 opp-hz = /bits/ 64 <1209600000>; 519 opp-peak-kBps = <4068000 11980800>; 520 }; 521 522 cpu4_opp13: opp-1286400000 { 523 opp-hz = /bits/ 64 <1286400000>; 524 opp-peak-kBps = <4068000 11980800>; 525 }; 526 527 cpu4_opp14: opp-1363200000 { 528 opp-hz = /bits/ 64 <1363200000>; 529 opp-peak-kBps = <4068000 15052800>; 530 }; 531 532 cpu4_opp15: opp-1459200000 { 533 opp-hz = /bits/ 64 <1459200000>; 534 opp-peak-kBps = <4068000 15052800>; 535 }; 536 537 cpu4_opp16: opp-1536000000 { 538 opp-hz = /bits/ 64 <1536000000>; 539 opp-peak-kBps = <5412000 15052800>; 540 }; 541 542 cpu4_opp17: opp-1612800000 { 543 opp-hz = /bits/ 64 <1612800000>; 544 opp-peak-kBps = <5412000 15052800>; 545 }; 546 547 cpu4_opp18: opp-1689600000 { 548 opp-hz = /bits/ 64 <1689600000>; 549 opp-peak-kBps = <5412000 19353600>; 550 }; 551 552 cpu4_opp19: opp-1766400000 { 553 opp-hz = /bits/ 64 <1766400000>; 554 opp-peak-kBps = <6220000 19353600>; 555 }; 556 557 cpu4_opp20: opp-1843200000 { 558 opp-hz = /bits/ 64 <1843200000>; 559 opp-peak-kBps = <6220000 19353600>; 560 }; 561 562 cpu4_opp21: opp-1920000000 { 563 opp-hz = /bits/ 64 <1920000000>; 564 opp-peak-kBps = <7216000 19353600>; 565 }; 566 567 cpu4_opp22: opp-1996800000 { 568 opp-hz = /bits/ 64 <1996800000>; 569 opp-peak-kBps = <7216000 20889600>; 570 }; 571 572 cpu4_opp23: opp-2092800000 { 573 opp-hz = /bits/ 64 <2092800000>; 574 opp-peak-kBps = <7216000 20889600>; 575 }; 576 577 cpu4_opp24: opp-2169600000 { 578 opp-hz = /bits/ 64 <2169600000>; 579 opp-peak-kBps = <7216000 20889600>; 580 }; 581 582 cpu4_opp25: opp-2246400000 { 583 opp-hz = /bits/ 64 <2246400000>; 584 opp-peak-kBps = <7216000 20889600>; 585 }; 586 587 cpu4_opp26: opp-2323200000 { 588 opp-hz = /bits/ 64 <2323200000>; 589 opp-peak-kBps = <7216000 20889600>; 590 }; 591 592 cpu4_opp27: opp-2400000000 { 593 opp-hz = /bits/ 64 <2400000000>; 594 opp-peak-kBps = <7216000 22425600>; 595 }; 596 597 cpu4_opp28: opp-2476800000 { 598 opp-hz = /bits/ 64 <2476800000>; 599 opp-peak-kBps = <7216000 22425600>; 600 }; 601 602 cpu4_opp29: opp-2553600000 { 603 opp-hz = /bits/ 64 <2553600000>; 604 opp-peak-kBps = <7216000 22425600>; 605 }; 606 607 cpu4_opp30: opp-2649600000 { 608 opp-hz = /bits/ 64 <2649600000>; 609 opp-peak-kBps = <7216000 22425600>; 610 }; 611 612 cpu4_opp31: opp-2745600000 { 613 opp-hz = /bits/ 64 <2745600000>; 614 opp-peak-kBps = <7216000 25497600>; 615 }; 616 617 cpu4_opp32: opp-2803200000 { 618 opp-hz = /bits/ 64 <2803200000>; 619 opp-peak-kBps = <7216000 25497600>; 620 }; 621 }; 622 623 dsi_opp_table: opp-table-dsi { 624 compatible = "operating-points-v2"; 625 626 opp-19200000 { 627 opp-hz = /bits/ 64 <19200000>; 628 required-opps = <&rpmhpd_opp_min_svs>; 629 }; 630 631 opp-180000000 { 632 opp-hz = /bits/ 64 <180000000>; 633 required-opps = <&rpmhpd_opp_low_svs>; 634 }; 635 636 opp-275000000 { 637 opp-hz = /bits/ 64 <275000000>; 638 required-opps = <&rpmhpd_opp_svs>; 639 }; 640 641 opp-328580000 { 642 opp-hz = /bits/ 64 <328580000>; 643 required-opps = <&rpmhpd_opp_svs_l1>; 644 }; 645 646 opp-358000000 { 647 opp-hz = /bits/ 64 <358000000>; 648 required-opps = <&rpmhpd_opp_nom>; 649 }; 650 }; 651 652 qspi_opp_table: opp-table-qspi { 653 compatible = "operating-points-v2"; 654 655 opp-19200000 { 656 opp-hz = /bits/ 64 <19200000>; 657 required-opps = <&rpmhpd_opp_min_svs>; 658 }; 659 660 opp-100000000 { 661 opp-hz = /bits/ 64 <100000000>; 662 required-opps = <&rpmhpd_opp_low_svs>; 663 }; 664 665 opp-150000000 { 666 opp-hz = /bits/ 64 <150000000>; 667 required-opps = <&rpmhpd_opp_svs>; 668 }; 669 670 opp-300000000 { 671 opp-hz = /bits/ 64 <300000000>; 672 required-opps = <&rpmhpd_opp_nom>; 673 }; 674 }; 675 676 qup_opp_table: opp-table-qup { 677 compatible = "operating-points-v2"; 678 679 opp-50000000 { 680 opp-hz = /bits/ 64 <50000000>; 681 required-opps = <&rpmhpd_opp_min_svs>; 682 }; 683 684 opp-75000000 { 685 opp-hz = /bits/ 64 <75000000>; 686 required-opps = <&rpmhpd_opp_low_svs>; 687 }; 688 689 opp-100000000 { 690 opp-hz = /bits/ 64 <100000000>; 691 required-opps = <&rpmhpd_opp_svs>; 692 }; 693 694 opp-128000000 { 695 opp-hz = /bits/ 64 <128000000>; 696 required-opps = <&rpmhpd_opp_nom>; 697 }; 698 }; 699 700 pmu { 701 compatible = "arm,armv8-pmuv3"; 702 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 703 }; 704 705 psci: psci { 706 compatible = "arm,psci-1.0"; 707 method = "smc"; 708 709 CPU_PD0: power-domain-cpu0 { 710 #power-domain-cells = <0>; 711 power-domains = <&CLUSTER_PD>; 712 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 713 }; 714 715 CPU_PD1: power-domain-cpu1 { 716 #power-domain-cells = <0>; 717 power-domains = <&CLUSTER_PD>; 718 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 719 }; 720 721 CPU_PD2: power-domain-cpu2 { 722 #power-domain-cells = <0>; 723 power-domains = <&CLUSTER_PD>; 724 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 725 }; 726 727 CPU_PD3: power-domain-cpu3 { 728 #power-domain-cells = <0>; 729 power-domains = <&CLUSTER_PD>; 730 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 731 }; 732 733 CPU_PD4: power-domain-cpu4 { 734 #power-domain-cells = <0>; 735 power-domains = <&CLUSTER_PD>; 736 domain-idle-states = <&BIG_CPU_SLEEP_0>; 737 }; 738 739 CPU_PD5: power-domain-cpu5 { 740 #power-domain-cells = <0>; 741 power-domains = <&CLUSTER_PD>; 742 domain-idle-states = <&BIG_CPU_SLEEP_0>; 743 }; 744 745 CPU_PD6: power-domain-cpu6 { 746 #power-domain-cells = <0>; 747 power-domains = <&CLUSTER_PD>; 748 domain-idle-states = <&BIG_CPU_SLEEP_0>; 749 }; 750 751 CPU_PD7: power-domain-cpu7 { 752 #power-domain-cells = <0>; 753 power-domains = <&CLUSTER_PD>; 754 domain-idle-states = <&BIG_CPU_SLEEP_0>; 755 }; 756 757 CLUSTER_PD: power-domain-cluster { 758 #power-domain-cells = <0>; 759 domain-idle-states = <&CLUSTER_SLEEP_0>; 760 }; 761 }; 762 763 reserved-memory { 764 #address-cells = <2>; 765 #size-cells = <2>; 766 ranges; 767 768 hyp_mem: hyp-mem@85700000 { 769 reg = <0 0x85700000 0 0x600000>; 770 no-map; 771 }; 772 773 xbl_mem: xbl-mem@85e00000 { 774 reg = <0 0x85e00000 0 0x100000>; 775 no-map; 776 }; 777 778 aop_mem: aop-mem@85fc0000 { 779 reg = <0 0x85fc0000 0 0x20000>; 780 no-map; 781 }; 782 783 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 784 compatible = "qcom,cmd-db"; 785 reg = <0x0 0x85fe0000 0 0x20000>; 786 no-map; 787 }; 788 789 smem@86000000 { 790 compatible = "qcom,smem"; 791 reg = <0x0 0x86000000 0 0x200000>; 792 no-map; 793 hwlocks = <&tcsr_mutex 3>; 794 }; 795 796 tz_mem: tz@86200000 { 797 reg = <0 0x86200000 0 0x2d00000>; 798 no-map; 799 }; 800 801 rmtfs_mem: rmtfs@88f00000 { 802 compatible = "qcom,rmtfs-mem"; 803 reg = <0 0x88f00000 0 0x200000>; 804 no-map; 805 806 qcom,client-id = <1>; 807 qcom,vmid = <15>; 808 }; 809 810 qseecom_mem: qseecom@8ab00000 { 811 reg = <0 0x8ab00000 0 0x1400000>; 812 no-map; 813 }; 814 815 camera_mem: camera-mem@8bf00000 { 816 reg = <0 0x8bf00000 0 0x500000>; 817 no-map; 818 }; 819 820 ipa_fw_mem: ipa-fw@8c400000 { 821 reg = <0 0x8c400000 0 0x10000>; 822 no-map; 823 }; 824 825 ipa_gsi_mem: ipa-gsi@8c410000 { 826 reg = <0 0x8c410000 0 0x5000>; 827 no-map; 828 }; 829 830 gpu_mem: gpu@8c415000 { 831 reg = <0 0x8c415000 0 0x2000>; 832 no-map; 833 }; 834 835 adsp_mem: adsp@8c500000 { 836 reg = <0 0x8c500000 0 0x1a00000>; 837 no-map; 838 }; 839 840 wlan_msa_mem: wlan-msa@8df00000 { 841 reg = <0 0x8df00000 0 0x100000>; 842 no-map; 843 }; 844 845 mpss_region: mpss@8e000000 { 846 reg = <0 0x8e000000 0 0x7800000>; 847 no-map; 848 }; 849 850 venus_mem: venus@95800000 { 851 reg = <0 0x95800000 0 0x500000>; 852 no-map; 853 }; 854 855 cdsp_mem: cdsp@95d00000 { 856 reg = <0 0x95d00000 0 0x800000>; 857 no-map; 858 }; 859 860 mba_region: mba@96500000 { 861 reg = <0 0x96500000 0 0x200000>; 862 no-map; 863 }; 864 865 slpi_mem: slpi@96700000 { 866 reg = <0 0x96700000 0 0x1400000>; 867 no-map; 868 }; 869 870 spss_mem: spss@97b00000 { 871 reg = <0 0x97b00000 0 0x100000>; 872 no-map; 873 }; 874 875 mdata_mem: mpss-metadata { 876 alloc-ranges = <0 0xa0000000 0 0x20000000>; 877 size = <0 0x4000>; 878 no-map; 879 }; 880 881 fastrpc_mem: fastrpc { 882 compatible = "shared-dma-pool"; 883 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; 884 alignment = <0x0 0x400000>; 885 size = <0x0 0x1000000>; 886 reusable; 887 }; 888 }; 889 890 adsp_pas: remoteproc-adsp { 891 compatible = "qcom,sdm845-adsp-pas"; 892 893 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 894 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 895 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 896 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 897 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 898 interrupt-names = "wdog", "fatal", "ready", 899 "handover", "stop-ack"; 900 901 clocks = <&rpmhcc RPMH_CXO_CLK>; 902 clock-names = "xo"; 903 904 memory-region = <&adsp_mem>; 905 906 qcom,qmp = <&aoss_qmp>; 907 908 qcom,smem-states = <&adsp_smp2p_out 0>; 909 qcom,smem-state-names = "stop"; 910 911 status = "disabled"; 912 913 glink-edge { 914 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 915 label = "lpass"; 916 qcom,remote-pid = <2>; 917 mboxes = <&apss_shared 8>; 918 919 apr { 920 compatible = "qcom,apr-v2"; 921 qcom,glink-channels = "apr_audio_svc"; 922 qcom,domain = <APR_DOMAIN_ADSP>; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 qcom,intents = <512 20>; 926 927 service@3 { 928 reg = <APR_SVC_ADSP_CORE>; 929 compatible = "qcom,q6core"; 930 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 931 }; 932 933 q6afe: service@4 { 934 compatible = "qcom,q6afe"; 935 reg = <APR_SVC_AFE>; 936 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 937 q6afedai: dais { 938 compatible = "qcom,q6afe-dais"; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 #sound-dai-cells = <1>; 942 }; 943 }; 944 945 q6asm: service@7 { 946 compatible = "qcom,q6asm"; 947 reg = <APR_SVC_ASM>; 948 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 949 q6asmdai: dais { 950 compatible = "qcom,q6asm-dais"; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 #sound-dai-cells = <1>; 954 iommus = <&apps_smmu 0x1821 0x0>; 955 }; 956 }; 957 958 q6adm: service@8 { 959 compatible = "qcom,q6adm"; 960 reg = <APR_SVC_ADM>; 961 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 962 q6routing: routing { 963 compatible = "qcom,q6adm-routing"; 964 #sound-dai-cells = <0>; 965 }; 966 }; 967 }; 968 969 fastrpc { 970 compatible = "qcom,fastrpc"; 971 qcom,glink-channels = "fastrpcglink-apps-dsp"; 972 label = "adsp"; 973 qcom,non-secure-domain; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 977 compute-cb@3 { 978 compatible = "qcom,fastrpc-compute-cb"; 979 reg = <3>; 980 iommus = <&apps_smmu 0x1823 0x0>; 981 }; 982 983 compute-cb@4 { 984 compatible = "qcom,fastrpc-compute-cb"; 985 reg = <4>; 986 iommus = <&apps_smmu 0x1824 0x0>; 987 }; 988 }; 989 }; 990 }; 991 992 cdsp_pas: remoteproc-cdsp { 993 compatible = "qcom,sdm845-cdsp-pas"; 994 995 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 996 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 997 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 998 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 999 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1000 interrupt-names = "wdog", "fatal", "ready", 1001 "handover", "stop-ack"; 1002 1003 clocks = <&rpmhcc RPMH_CXO_CLK>; 1004 clock-names = "xo"; 1005 1006 memory-region = <&cdsp_mem>; 1007 1008 qcom,qmp = <&aoss_qmp>; 1009 1010 qcom,smem-states = <&cdsp_smp2p_out 0>; 1011 qcom,smem-state-names = "stop"; 1012 1013 status = "disabled"; 1014 1015 glink-edge { 1016 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 1017 label = "turing"; 1018 qcom,remote-pid = <5>; 1019 mboxes = <&apss_shared 4>; 1020 fastrpc { 1021 compatible = "qcom,fastrpc"; 1022 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1023 label = "cdsp"; 1024 qcom,non-secure-domain; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 1028 compute-cb@1 { 1029 compatible = "qcom,fastrpc-compute-cb"; 1030 reg = <1>; 1031 iommus = <&apps_smmu 0x1401 0x30>; 1032 }; 1033 1034 compute-cb@2 { 1035 compatible = "qcom,fastrpc-compute-cb"; 1036 reg = <2>; 1037 iommus = <&apps_smmu 0x1402 0x30>; 1038 }; 1039 1040 compute-cb@3 { 1041 compatible = "qcom,fastrpc-compute-cb"; 1042 reg = <3>; 1043 iommus = <&apps_smmu 0x1403 0x30>; 1044 }; 1045 1046 compute-cb@4 { 1047 compatible = "qcom,fastrpc-compute-cb"; 1048 reg = <4>; 1049 iommus = <&apps_smmu 0x1404 0x30>; 1050 }; 1051 1052 compute-cb@5 { 1053 compatible = "qcom,fastrpc-compute-cb"; 1054 reg = <5>; 1055 iommus = <&apps_smmu 0x1405 0x30>; 1056 }; 1057 1058 compute-cb@6 { 1059 compatible = "qcom,fastrpc-compute-cb"; 1060 reg = <6>; 1061 iommus = <&apps_smmu 0x1406 0x30>; 1062 }; 1063 1064 compute-cb@7 { 1065 compatible = "qcom,fastrpc-compute-cb"; 1066 reg = <7>; 1067 iommus = <&apps_smmu 0x1407 0x30>; 1068 }; 1069 1070 compute-cb@8 { 1071 compatible = "qcom,fastrpc-compute-cb"; 1072 reg = <8>; 1073 iommus = <&apps_smmu 0x1408 0x30>; 1074 }; 1075 }; 1076 }; 1077 }; 1078 1079 smp2p-cdsp { 1080 compatible = "qcom,smp2p"; 1081 qcom,smem = <94>, <432>; 1082 1083 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 1084 1085 mboxes = <&apss_shared 6>; 1086 1087 qcom,local-pid = <0>; 1088 qcom,remote-pid = <5>; 1089 1090 cdsp_smp2p_out: master-kernel { 1091 qcom,entry-name = "master-kernel"; 1092 #qcom,smem-state-cells = <1>; 1093 }; 1094 1095 cdsp_smp2p_in: slave-kernel { 1096 qcom,entry-name = "slave-kernel"; 1097 1098 interrupt-controller; 1099 #interrupt-cells = <2>; 1100 }; 1101 }; 1102 1103 smp2p-lpass { 1104 compatible = "qcom,smp2p"; 1105 qcom,smem = <443>, <429>; 1106 1107 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1108 1109 mboxes = <&apss_shared 10>; 1110 1111 qcom,local-pid = <0>; 1112 qcom,remote-pid = <2>; 1113 1114 adsp_smp2p_out: master-kernel { 1115 qcom,entry-name = "master-kernel"; 1116 #qcom,smem-state-cells = <1>; 1117 }; 1118 1119 adsp_smp2p_in: slave-kernel { 1120 qcom,entry-name = "slave-kernel"; 1121 1122 interrupt-controller; 1123 #interrupt-cells = <2>; 1124 }; 1125 }; 1126 1127 smp2p-mpss { 1128 compatible = "qcom,smp2p"; 1129 qcom,smem = <435>, <428>; 1130 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1131 mboxes = <&apss_shared 14>; 1132 qcom,local-pid = <0>; 1133 qcom,remote-pid = <1>; 1134 1135 modem_smp2p_out: master-kernel { 1136 qcom,entry-name = "master-kernel"; 1137 #qcom,smem-state-cells = <1>; 1138 }; 1139 1140 modem_smp2p_in: slave-kernel { 1141 qcom,entry-name = "slave-kernel"; 1142 interrupt-controller; 1143 #interrupt-cells = <2>; 1144 }; 1145 1146 ipa_smp2p_out: ipa-ap-to-modem { 1147 qcom,entry-name = "ipa"; 1148 #qcom,smem-state-cells = <1>; 1149 }; 1150 1151 ipa_smp2p_in: ipa-modem-to-ap { 1152 qcom,entry-name = "ipa"; 1153 interrupt-controller; 1154 #interrupt-cells = <2>; 1155 }; 1156 }; 1157 1158 smp2p-slpi { 1159 compatible = "qcom,smp2p"; 1160 qcom,smem = <481>, <430>; 1161 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1162 mboxes = <&apss_shared 26>; 1163 qcom,local-pid = <0>; 1164 qcom,remote-pid = <3>; 1165 1166 slpi_smp2p_out: master-kernel { 1167 qcom,entry-name = "master-kernel"; 1168 #qcom,smem-state-cells = <1>; 1169 }; 1170 1171 slpi_smp2p_in: slave-kernel { 1172 qcom,entry-name = "slave-kernel"; 1173 interrupt-controller; 1174 #interrupt-cells = <2>; 1175 }; 1176 }; 1177 1178 soc: soc@0 { 1179 #address-cells = <2>; 1180 #size-cells = <2>; 1181 ranges = <0 0 0 0 0x10 0>; 1182 dma-ranges = <0 0 0 0 0x10 0>; 1183 compatible = "simple-bus"; 1184 1185 gcc: clock-controller@100000 { 1186 compatible = "qcom,gcc-sdm845"; 1187 reg = <0 0x00100000 0 0x1f0000>; 1188 clocks = <&rpmhcc RPMH_CXO_CLK>, 1189 <&rpmhcc RPMH_CXO_CLK_A>, 1190 <&sleep_clk>, 1191 <&pcie0_lane>, 1192 <&pcie1_lane>; 1193 clock-names = "bi_tcxo", 1194 "bi_tcxo_ao", 1195 "sleep_clk", 1196 "pcie_0_pipe_clk", 1197 "pcie_1_pipe_clk"; 1198 #clock-cells = <1>; 1199 #reset-cells = <1>; 1200 #power-domain-cells = <1>; 1201 }; 1202 1203 qfprom@784000 { 1204 compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; 1205 reg = <0 0x00784000 0 0x8ff>; 1206 #address-cells = <1>; 1207 #size-cells = <1>; 1208 1209 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1210 reg = <0x1eb 0x1>; 1211 bits = <1 4>; 1212 }; 1213 1214 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1215 reg = <0x1eb 0x2>; 1216 bits = <6 4>; 1217 }; 1218 }; 1219 1220 rng: rng@793000 { 1221 compatible = "qcom,prng-ee"; 1222 reg = <0 0x00793000 0 0x1000>; 1223 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1224 clock-names = "core"; 1225 }; 1226 1227 gpi_dma0: dma-controller@800000 { 1228 #dma-cells = <3>; 1229 compatible = "qcom,sdm845-gpi-dma"; 1230 reg = <0 0x00800000 0 0x60000>; 1231 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1244 dma-channels = <13>; 1245 dma-channel-mask = <0xfa>; 1246 iommus = <&apps_smmu 0x0016 0x0>; 1247 status = "disabled"; 1248 }; 1249 1250 qupv3_id_0: geniqup@8c0000 { 1251 compatible = "qcom,geni-se-qup"; 1252 reg = <0 0x008c0000 0 0x6000>; 1253 clock-names = "m-ahb", "s-ahb"; 1254 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1255 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1256 iommus = <&apps_smmu 0x3 0x0>; 1257 #address-cells = <2>; 1258 #size-cells = <2>; 1259 ranges; 1260 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; 1261 interconnect-names = "qup-core"; 1262 status = "disabled"; 1263 1264 i2c0: i2c@880000 { 1265 compatible = "qcom,geni-i2c"; 1266 reg = <0 0x00880000 0 0x4000>; 1267 clock-names = "se"; 1268 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1269 pinctrl-names = "default"; 1270 pinctrl-0 = <&qup_i2c0_default>; 1271 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 power-domains = <&rpmhpd SDM845_CX>; 1275 operating-points-v2 = <&qup_opp_table>; 1276 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1277 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1278 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1279 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1280 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1281 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1282 dma-names = "tx", "rx"; 1283 status = "disabled"; 1284 }; 1285 1286 spi0: spi@880000 { 1287 compatible = "qcom,geni-spi"; 1288 reg = <0 0x00880000 0 0x4000>; 1289 clock-names = "se"; 1290 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1291 pinctrl-names = "default"; 1292 pinctrl-0 = <&qup_spi0_default>; 1293 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1297 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1298 interconnect-names = "qup-core", "qup-config"; 1299 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1300 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1301 dma-names = "tx", "rx"; 1302 status = "disabled"; 1303 }; 1304 1305 uart0: serial@880000 { 1306 compatible = "qcom,geni-uart"; 1307 reg = <0 0x00880000 0 0x4000>; 1308 clock-names = "se"; 1309 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1310 pinctrl-names = "default"; 1311 pinctrl-0 = <&qup_uart0_default>; 1312 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1313 power-domains = <&rpmhpd SDM845_CX>; 1314 operating-points-v2 = <&qup_opp_table>; 1315 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1316 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1317 interconnect-names = "qup-core", "qup-config"; 1318 status = "disabled"; 1319 }; 1320 1321 i2c1: i2c@884000 { 1322 compatible = "qcom,geni-i2c"; 1323 reg = <0 0x00884000 0 0x4000>; 1324 clock-names = "se"; 1325 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1326 pinctrl-names = "default"; 1327 pinctrl-0 = <&qup_i2c1_default>; 1328 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1329 #address-cells = <1>; 1330 #size-cells = <0>; 1331 power-domains = <&rpmhpd SDM845_CX>; 1332 operating-points-v2 = <&qup_opp_table>; 1333 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1334 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1335 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1336 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1337 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1338 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1339 dma-names = "tx", "rx"; 1340 status = "disabled"; 1341 }; 1342 1343 spi1: spi@884000 { 1344 compatible = "qcom,geni-spi"; 1345 reg = <0 0x00884000 0 0x4000>; 1346 clock-names = "se"; 1347 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1348 pinctrl-names = "default"; 1349 pinctrl-0 = <&qup_spi1_default>; 1350 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1351 #address-cells = <1>; 1352 #size-cells = <0>; 1353 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1354 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1355 interconnect-names = "qup-core", "qup-config"; 1356 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1357 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1358 dma-names = "tx", "rx"; 1359 status = "disabled"; 1360 }; 1361 1362 uart1: serial@884000 { 1363 compatible = "qcom,geni-uart"; 1364 reg = <0 0x00884000 0 0x4000>; 1365 clock-names = "se"; 1366 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1367 pinctrl-names = "default"; 1368 pinctrl-0 = <&qup_uart1_default>; 1369 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1370 power-domains = <&rpmhpd SDM845_CX>; 1371 operating-points-v2 = <&qup_opp_table>; 1372 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1373 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1374 interconnect-names = "qup-core", "qup-config"; 1375 status = "disabled"; 1376 }; 1377 1378 i2c2: i2c@888000 { 1379 compatible = "qcom,geni-i2c"; 1380 reg = <0 0x00888000 0 0x4000>; 1381 clock-names = "se"; 1382 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_i2c2_default>; 1385 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 power-domains = <&rpmhpd SDM845_CX>; 1389 operating-points-v2 = <&qup_opp_table>; 1390 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1391 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1392 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1393 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1394 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1395 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1396 dma-names = "tx", "rx"; 1397 status = "disabled"; 1398 }; 1399 1400 spi2: spi@888000 { 1401 compatible = "qcom,geni-spi"; 1402 reg = <0 0x00888000 0 0x4000>; 1403 clock-names = "se"; 1404 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1405 pinctrl-names = "default"; 1406 pinctrl-0 = <&qup_spi2_default>; 1407 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1408 #address-cells = <1>; 1409 #size-cells = <0>; 1410 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1411 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1412 interconnect-names = "qup-core", "qup-config"; 1413 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1414 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1415 dma-names = "tx", "rx"; 1416 status = "disabled"; 1417 }; 1418 1419 uart2: serial@888000 { 1420 compatible = "qcom,geni-uart"; 1421 reg = <0 0x00888000 0 0x4000>; 1422 clock-names = "se"; 1423 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1424 pinctrl-names = "default"; 1425 pinctrl-0 = <&qup_uart2_default>; 1426 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1427 power-domains = <&rpmhpd SDM845_CX>; 1428 operating-points-v2 = <&qup_opp_table>; 1429 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1430 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1431 interconnect-names = "qup-core", "qup-config"; 1432 status = "disabled"; 1433 }; 1434 1435 i2c3: i2c@88c000 { 1436 compatible = "qcom,geni-i2c"; 1437 reg = <0 0x0088c000 0 0x4000>; 1438 clock-names = "se"; 1439 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&qup_i2c3_default>; 1442 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 power-domains = <&rpmhpd SDM845_CX>; 1446 operating-points-v2 = <&qup_opp_table>; 1447 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1448 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1449 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1450 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1451 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1452 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1453 dma-names = "tx", "rx"; 1454 status = "disabled"; 1455 }; 1456 1457 spi3: spi@88c000 { 1458 compatible = "qcom,geni-spi"; 1459 reg = <0 0x0088c000 0 0x4000>; 1460 clock-names = "se"; 1461 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1462 pinctrl-names = "default"; 1463 pinctrl-0 = <&qup_spi3_default>; 1464 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1465 #address-cells = <1>; 1466 #size-cells = <0>; 1467 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1468 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1469 interconnect-names = "qup-core", "qup-config"; 1470 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1471 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1472 dma-names = "tx", "rx"; 1473 status = "disabled"; 1474 }; 1475 1476 uart3: serial@88c000 { 1477 compatible = "qcom,geni-uart"; 1478 reg = <0 0x0088c000 0 0x4000>; 1479 clock-names = "se"; 1480 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1481 pinctrl-names = "default"; 1482 pinctrl-0 = <&qup_uart3_default>; 1483 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1484 power-domains = <&rpmhpd SDM845_CX>; 1485 operating-points-v2 = <&qup_opp_table>; 1486 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1487 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1488 interconnect-names = "qup-core", "qup-config"; 1489 status = "disabled"; 1490 }; 1491 1492 i2c4: i2c@890000 { 1493 compatible = "qcom,geni-i2c"; 1494 reg = <0 0x00890000 0 0x4000>; 1495 clock-names = "se"; 1496 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1497 pinctrl-names = "default"; 1498 pinctrl-0 = <&qup_i2c4_default>; 1499 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 power-domains = <&rpmhpd SDM845_CX>; 1503 operating-points-v2 = <&qup_opp_table>; 1504 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1505 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1506 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1507 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1508 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1509 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1510 dma-names = "tx", "rx"; 1511 status = "disabled"; 1512 }; 1513 1514 spi4: spi@890000 { 1515 compatible = "qcom,geni-spi"; 1516 reg = <0 0x00890000 0 0x4000>; 1517 clock-names = "se"; 1518 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1519 pinctrl-names = "default"; 1520 pinctrl-0 = <&qup_spi4_default>; 1521 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1522 #address-cells = <1>; 1523 #size-cells = <0>; 1524 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1525 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1526 interconnect-names = "qup-core", "qup-config"; 1527 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1528 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1529 dma-names = "tx", "rx"; 1530 status = "disabled"; 1531 }; 1532 1533 uart4: serial@890000 { 1534 compatible = "qcom,geni-uart"; 1535 reg = <0 0x00890000 0 0x4000>; 1536 clock-names = "se"; 1537 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1538 pinctrl-names = "default"; 1539 pinctrl-0 = <&qup_uart4_default>; 1540 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1541 power-domains = <&rpmhpd SDM845_CX>; 1542 operating-points-v2 = <&qup_opp_table>; 1543 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1544 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1545 interconnect-names = "qup-core", "qup-config"; 1546 status = "disabled"; 1547 }; 1548 1549 i2c5: i2c@894000 { 1550 compatible = "qcom,geni-i2c"; 1551 reg = <0 0x00894000 0 0x4000>; 1552 clock-names = "se"; 1553 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1554 pinctrl-names = "default"; 1555 pinctrl-0 = <&qup_i2c5_default>; 1556 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1557 #address-cells = <1>; 1558 #size-cells = <0>; 1559 power-domains = <&rpmhpd SDM845_CX>; 1560 operating-points-v2 = <&qup_opp_table>; 1561 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1562 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1563 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1564 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1565 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1566 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1567 dma-names = "tx", "rx"; 1568 status = "disabled"; 1569 }; 1570 1571 spi5: spi@894000 { 1572 compatible = "qcom,geni-spi"; 1573 reg = <0 0x00894000 0 0x4000>; 1574 clock-names = "se"; 1575 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1576 pinctrl-names = "default"; 1577 pinctrl-0 = <&qup_spi5_default>; 1578 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1579 #address-cells = <1>; 1580 #size-cells = <0>; 1581 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1582 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1583 interconnect-names = "qup-core", "qup-config"; 1584 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1585 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1586 dma-names = "tx", "rx"; 1587 status = "disabled"; 1588 }; 1589 1590 uart5: serial@894000 { 1591 compatible = "qcom,geni-uart"; 1592 reg = <0 0x00894000 0 0x4000>; 1593 clock-names = "se"; 1594 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1595 pinctrl-names = "default"; 1596 pinctrl-0 = <&qup_uart5_default>; 1597 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1598 power-domains = <&rpmhpd SDM845_CX>; 1599 operating-points-v2 = <&qup_opp_table>; 1600 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1601 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1602 interconnect-names = "qup-core", "qup-config"; 1603 status = "disabled"; 1604 }; 1605 1606 i2c6: i2c@898000 { 1607 compatible = "qcom,geni-i2c"; 1608 reg = <0 0x00898000 0 0x4000>; 1609 clock-names = "se"; 1610 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1611 pinctrl-names = "default"; 1612 pinctrl-0 = <&qup_i2c6_default>; 1613 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 power-domains = <&rpmhpd SDM845_CX>; 1617 operating-points-v2 = <&qup_opp_table>; 1618 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1619 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1620 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1621 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1622 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1623 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1624 dma-names = "tx", "rx"; 1625 status = "disabled"; 1626 }; 1627 1628 spi6: spi@898000 { 1629 compatible = "qcom,geni-spi"; 1630 reg = <0 0x00898000 0 0x4000>; 1631 clock-names = "se"; 1632 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1633 pinctrl-names = "default"; 1634 pinctrl-0 = <&qup_spi6_default>; 1635 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1639 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1640 interconnect-names = "qup-core", "qup-config"; 1641 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1642 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1643 dma-names = "tx", "rx"; 1644 status = "disabled"; 1645 }; 1646 1647 uart6: serial@898000 { 1648 compatible = "qcom,geni-uart"; 1649 reg = <0 0x00898000 0 0x4000>; 1650 clock-names = "se"; 1651 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1652 pinctrl-names = "default"; 1653 pinctrl-0 = <&qup_uart6_default>; 1654 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1655 power-domains = <&rpmhpd SDM845_CX>; 1656 operating-points-v2 = <&qup_opp_table>; 1657 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1658 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1659 interconnect-names = "qup-core", "qup-config"; 1660 status = "disabled"; 1661 }; 1662 1663 i2c7: i2c@89c000 { 1664 compatible = "qcom,geni-i2c"; 1665 reg = <0 0x0089c000 0 0x4000>; 1666 clock-names = "se"; 1667 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1668 pinctrl-names = "default"; 1669 pinctrl-0 = <&qup_i2c7_default>; 1670 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 power-domains = <&rpmhpd SDM845_CX>; 1674 operating-points-v2 = <&qup_opp_table>; 1675 status = "disabled"; 1676 }; 1677 1678 spi7: spi@89c000 { 1679 compatible = "qcom,geni-spi"; 1680 reg = <0 0x0089c000 0 0x4000>; 1681 clock-names = "se"; 1682 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1683 pinctrl-names = "default"; 1684 pinctrl-0 = <&qup_spi7_default>; 1685 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1686 #address-cells = <1>; 1687 #size-cells = <0>; 1688 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1689 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1690 interconnect-names = "qup-core", "qup-config"; 1691 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1692 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1693 dma-names = "tx", "rx"; 1694 status = "disabled"; 1695 }; 1696 1697 uart7: serial@89c000 { 1698 compatible = "qcom,geni-uart"; 1699 reg = <0 0x0089c000 0 0x4000>; 1700 clock-names = "se"; 1701 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1702 pinctrl-names = "default"; 1703 pinctrl-0 = <&qup_uart7_default>; 1704 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1705 power-domains = <&rpmhpd SDM845_CX>; 1706 operating-points-v2 = <&qup_opp_table>; 1707 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1708 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1709 interconnect-names = "qup-core", "qup-config"; 1710 status = "disabled"; 1711 }; 1712 }; 1713 1714 gpi_dma1: dma-controller@a00000 { 1715 #dma-cells = <3>; 1716 compatible = "qcom,sdm845-gpi-dma"; 1717 reg = <0 0x00a00000 0 0x60000>; 1718 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1719 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1720 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1731 dma-channels = <13>; 1732 dma-channel-mask = <0xfa>; 1733 iommus = <&apps_smmu 0x06d6 0x0>; 1734 status = "disabled"; 1735 }; 1736 1737 qupv3_id_1: geniqup@ac0000 { 1738 compatible = "qcom,geni-se-qup"; 1739 reg = <0 0x00ac0000 0 0x6000>; 1740 clock-names = "m-ahb", "s-ahb"; 1741 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1742 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1743 iommus = <&apps_smmu 0x6c3 0x0>; 1744 #address-cells = <2>; 1745 #size-cells = <2>; 1746 ranges; 1747 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; 1748 interconnect-names = "qup-core"; 1749 status = "disabled"; 1750 1751 i2c8: i2c@a80000 { 1752 compatible = "qcom,geni-i2c"; 1753 reg = <0 0x00a80000 0 0x4000>; 1754 clock-names = "se"; 1755 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1756 pinctrl-names = "default"; 1757 pinctrl-0 = <&qup_i2c8_default>; 1758 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1759 #address-cells = <1>; 1760 #size-cells = <0>; 1761 power-domains = <&rpmhpd SDM845_CX>; 1762 operating-points-v2 = <&qup_opp_table>; 1763 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1764 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1765 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1766 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1767 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1768 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1769 dma-names = "tx", "rx"; 1770 status = "disabled"; 1771 }; 1772 1773 spi8: spi@a80000 { 1774 compatible = "qcom,geni-spi"; 1775 reg = <0 0x00a80000 0 0x4000>; 1776 clock-names = "se"; 1777 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1778 pinctrl-names = "default"; 1779 pinctrl-0 = <&qup_spi8_default>; 1780 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1781 #address-cells = <1>; 1782 #size-cells = <0>; 1783 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1784 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1785 interconnect-names = "qup-core", "qup-config"; 1786 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1787 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1788 dma-names = "tx", "rx"; 1789 status = "disabled"; 1790 }; 1791 1792 uart8: serial@a80000 { 1793 compatible = "qcom,geni-uart"; 1794 reg = <0 0x00a80000 0 0x4000>; 1795 clock-names = "se"; 1796 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1797 pinctrl-names = "default"; 1798 pinctrl-0 = <&qup_uart8_default>; 1799 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1800 power-domains = <&rpmhpd SDM845_CX>; 1801 operating-points-v2 = <&qup_opp_table>; 1802 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1803 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1804 interconnect-names = "qup-core", "qup-config"; 1805 status = "disabled"; 1806 }; 1807 1808 i2c9: i2c@a84000 { 1809 compatible = "qcom,geni-i2c"; 1810 reg = <0 0x00a84000 0 0x4000>; 1811 clock-names = "se"; 1812 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1813 pinctrl-names = "default"; 1814 pinctrl-0 = <&qup_i2c9_default>; 1815 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1816 #address-cells = <1>; 1817 #size-cells = <0>; 1818 power-domains = <&rpmhpd SDM845_CX>; 1819 operating-points-v2 = <&qup_opp_table>; 1820 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1821 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1822 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1823 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1824 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1825 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1826 dma-names = "tx", "rx"; 1827 status = "disabled"; 1828 }; 1829 1830 spi9: spi@a84000 { 1831 compatible = "qcom,geni-spi"; 1832 reg = <0 0x00a84000 0 0x4000>; 1833 clock-names = "se"; 1834 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1835 pinctrl-names = "default"; 1836 pinctrl-0 = <&qup_spi9_default>; 1837 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1838 #address-cells = <1>; 1839 #size-cells = <0>; 1840 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1841 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1842 interconnect-names = "qup-core", "qup-config"; 1843 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1844 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1845 dma-names = "tx", "rx"; 1846 status = "disabled"; 1847 }; 1848 1849 uart9: serial@a84000 { 1850 compatible = "qcom,geni-debug-uart"; 1851 reg = <0 0x00a84000 0 0x4000>; 1852 clock-names = "se"; 1853 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1854 pinctrl-names = "default"; 1855 pinctrl-0 = <&qup_uart9_default>; 1856 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1857 power-domains = <&rpmhpd SDM845_CX>; 1858 operating-points-v2 = <&qup_opp_table>; 1859 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1860 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1861 interconnect-names = "qup-core", "qup-config"; 1862 status = "disabled"; 1863 }; 1864 1865 i2c10: i2c@a88000 { 1866 compatible = "qcom,geni-i2c"; 1867 reg = <0 0x00a88000 0 0x4000>; 1868 clock-names = "se"; 1869 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1870 pinctrl-names = "default"; 1871 pinctrl-0 = <&qup_i2c10_default>; 1872 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1873 #address-cells = <1>; 1874 #size-cells = <0>; 1875 power-domains = <&rpmhpd SDM845_CX>; 1876 operating-points-v2 = <&qup_opp_table>; 1877 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1878 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1879 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1880 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1881 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1882 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1883 dma-names = "tx", "rx"; 1884 status = "disabled"; 1885 }; 1886 1887 spi10: spi@a88000 { 1888 compatible = "qcom,geni-spi"; 1889 reg = <0 0x00a88000 0 0x4000>; 1890 clock-names = "se"; 1891 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1892 pinctrl-names = "default"; 1893 pinctrl-0 = <&qup_spi10_default>; 1894 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1895 #address-cells = <1>; 1896 #size-cells = <0>; 1897 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1898 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1899 interconnect-names = "qup-core", "qup-config"; 1900 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1901 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1902 dma-names = "tx", "rx"; 1903 status = "disabled"; 1904 }; 1905 1906 uart10: serial@a88000 { 1907 compatible = "qcom,geni-uart"; 1908 reg = <0 0x00a88000 0 0x4000>; 1909 clock-names = "se"; 1910 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1911 pinctrl-names = "default"; 1912 pinctrl-0 = <&qup_uart10_default>; 1913 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1914 power-domains = <&rpmhpd SDM845_CX>; 1915 operating-points-v2 = <&qup_opp_table>; 1916 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1917 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1918 interconnect-names = "qup-core", "qup-config"; 1919 status = "disabled"; 1920 }; 1921 1922 i2c11: i2c@a8c000 { 1923 compatible = "qcom,geni-i2c"; 1924 reg = <0 0x00a8c000 0 0x4000>; 1925 clock-names = "se"; 1926 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1927 pinctrl-names = "default"; 1928 pinctrl-0 = <&qup_i2c11_default>; 1929 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1930 #address-cells = <1>; 1931 #size-cells = <0>; 1932 power-domains = <&rpmhpd SDM845_CX>; 1933 operating-points-v2 = <&qup_opp_table>; 1934 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1935 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1936 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1937 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1938 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1939 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1940 dma-names = "tx", "rx"; 1941 status = "disabled"; 1942 }; 1943 1944 spi11: spi@a8c000 { 1945 compatible = "qcom,geni-spi"; 1946 reg = <0 0x00a8c000 0 0x4000>; 1947 clock-names = "se"; 1948 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1949 pinctrl-names = "default"; 1950 pinctrl-0 = <&qup_spi11_default>; 1951 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1952 #address-cells = <1>; 1953 #size-cells = <0>; 1954 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1955 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1956 interconnect-names = "qup-core", "qup-config"; 1957 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1958 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1959 dma-names = "tx", "rx"; 1960 status = "disabled"; 1961 }; 1962 1963 uart11: serial@a8c000 { 1964 compatible = "qcom,geni-uart"; 1965 reg = <0 0x00a8c000 0 0x4000>; 1966 clock-names = "se"; 1967 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1968 pinctrl-names = "default"; 1969 pinctrl-0 = <&qup_uart11_default>; 1970 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1971 power-domains = <&rpmhpd SDM845_CX>; 1972 operating-points-v2 = <&qup_opp_table>; 1973 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1974 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1975 interconnect-names = "qup-core", "qup-config"; 1976 status = "disabled"; 1977 }; 1978 1979 i2c12: i2c@a90000 { 1980 compatible = "qcom,geni-i2c"; 1981 reg = <0 0x00a90000 0 0x4000>; 1982 clock-names = "se"; 1983 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1984 pinctrl-names = "default"; 1985 pinctrl-0 = <&qup_i2c12_default>; 1986 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1987 #address-cells = <1>; 1988 #size-cells = <0>; 1989 power-domains = <&rpmhpd SDM845_CX>; 1990 operating-points-v2 = <&qup_opp_table>; 1991 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1992 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1993 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1994 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1995 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1996 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1997 dma-names = "tx", "rx"; 1998 status = "disabled"; 1999 }; 2000 2001 spi12: spi@a90000 { 2002 compatible = "qcom,geni-spi"; 2003 reg = <0 0x00a90000 0 0x4000>; 2004 clock-names = "se"; 2005 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2006 pinctrl-names = "default"; 2007 pinctrl-0 = <&qup_spi12_default>; 2008 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2009 #address-cells = <1>; 2010 #size-cells = <0>; 2011 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2012 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2013 interconnect-names = "qup-core", "qup-config"; 2014 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2015 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2016 dma-names = "tx", "rx"; 2017 status = "disabled"; 2018 }; 2019 2020 uart12: serial@a90000 { 2021 compatible = "qcom,geni-uart"; 2022 reg = <0 0x00a90000 0 0x4000>; 2023 clock-names = "se"; 2024 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2025 pinctrl-names = "default"; 2026 pinctrl-0 = <&qup_uart12_default>; 2027 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2028 power-domains = <&rpmhpd SDM845_CX>; 2029 operating-points-v2 = <&qup_opp_table>; 2030 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2031 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2032 interconnect-names = "qup-core", "qup-config"; 2033 status = "disabled"; 2034 }; 2035 2036 i2c13: i2c@a94000 { 2037 compatible = "qcom,geni-i2c"; 2038 reg = <0 0x00a94000 0 0x4000>; 2039 clock-names = "se"; 2040 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2041 pinctrl-names = "default"; 2042 pinctrl-0 = <&qup_i2c13_default>; 2043 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2044 #address-cells = <1>; 2045 #size-cells = <0>; 2046 power-domains = <&rpmhpd SDM845_CX>; 2047 operating-points-v2 = <&qup_opp_table>; 2048 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2049 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2050 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2051 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2052 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2053 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2054 dma-names = "tx", "rx"; 2055 status = "disabled"; 2056 }; 2057 2058 spi13: spi@a94000 { 2059 compatible = "qcom,geni-spi"; 2060 reg = <0 0x00a94000 0 0x4000>; 2061 clock-names = "se"; 2062 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2063 pinctrl-names = "default"; 2064 pinctrl-0 = <&qup_spi13_default>; 2065 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2066 #address-cells = <1>; 2067 #size-cells = <0>; 2068 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2069 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2070 interconnect-names = "qup-core", "qup-config"; 2071 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2072 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2073 dma-names = "tx", "rx"; 2074 status = "disabled"; 2075 }; 2076 2077 uart13: serial@a94000 { 2078 compatible = "qcom,geni-uart"; 2079 reg = <0 0x00a94000 0 0x4000>; 2080 clock-names = "se"; 2081 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2082 pinctrl-names = "default"; 2083 pinctrl-0 = <&qup_uart13_default>; 2084 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2085 power-domains = <&rpmhpd SDM845_CX>; 2086 operating-points-v2 = <&qup_opp_table>; 2087 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2088 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2089 interconnect-names = "qup-core", "qup-config"; 2090 status = "disabled"; 2091 }; 2092 2093 i2c14: i2c@a98000 { 2094 compatible = "qcom,geni-i2c"; 2095 reg = <0 0x00a98000 0 0x4000>; 2096 clock-names = "se"; 2097 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2098 pinctrl-names = "default"; 2099 pinctrl-0 = <&qup_i2c14_default>; 2100 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2101 #address-cells = <1>; 2102 #size-cells = <0>; 2103 power-domains = <&rpmhpd SDM845_CX>; 2104 operating-points-v2 = <&qup_opp_table>; 2105 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2106 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2107 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2108 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2109 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2110 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2111 dma-names = "tx", "rx"; 2112 status = "disabled"; 2113 }; 2114 2115 spi14: spi@a98000 { 2116 compatible = "qcom,geni-spi"; 2117 reg = <0 0x00a98000 0 0x4000>; 2118 clock-names = "se"; 2119 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2120 pinctrl-names = "default"; 2121 pinctrl-0 = <&qup_spi14_default>; 2122 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2123 #address-cells = <1>; 2124 #size-cells = <0>; 2125 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2126 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2127 interconnect-names = "qup-core", "qup-config"; 2128 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2129 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2130 dma-names = "tx", "rx"; 2131 status = "disabled"; 2132 }; 2133 2134 uart14: serial@a98000 { 2135 compatible = "qcom,geni-uart"; 2136 reg = <0 0x00a98000 0 0x4000>; 2137 clock-names = "se"; 2138 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2139 pinctrl-names = "default"; 2140 pinctrl-0 = <&qup_uart14_default>; 2141 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2142 power-domains = <&rpmhpd SDM845_CX>; 2143 operating-points-v2 = <&qup_opp_table>; 2144 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2145 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2146 interconnect-names = "qup-core", "qup-config"; 2147 status = "disabled"; 2148 }; 2149 2150 i2c15: i2c@a9c000 { 2151 compatible = "qcom,geni-i2c"; 2152 reg = <0 0x00a9c000 0 0x4000>; 2153 clock-names = "se"; 2154 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2155 pinctrl-names = "default"; 2156 pinctrl-0 = <&qup_i2c15_default>; 2157 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2158 #address-cells = <1>; 2159 #size-cells = <0>; 2160 power-domains = <&rpmhpd SDM845_CX>; 2161 operating-points-v2 = <&qup_opp_table>; 2162 status = "disabled"; 2163 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2164 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2165 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2166 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2167 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2168 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2169 dma-names = "tx", "rx"; 2170 }; 2171 2172 spi15: spi@a9c000 { 2173 compatible = "qcom,geni-spi"; 2174 reg = <0 0x00a9c000 0 0x4000>; 2175 clock-names = "se"; 2176 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2177 pinctrl-names = "default"; 2178 pinctrl-0 = <&qup_spi15_default>; 2179 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2180 #address-cells = <1>; 2181 #size-cells = <0>; 2182 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2183 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2184 interconnect-names = "qup-core", "qup-config"; 2185 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2186 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2187 dma-names = "tx", "rx"; 2188 status = "disabled"; 2189 }; 2190 2191 uart15: serial@a9c000 { 2192 compatible = "qcom,geni-uart"; 2193 reg = <0 0x00a9c000 0 0x4000>; 2194 clock-names = "se"; 2195 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2196 pinctrl-names = "default"; 2197 pinctrl-0 = <&qup_uart15_default>; 2198 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2199 power-domains = <&rpmhpd SDM845_CX>; 2200 operating-points-v2 = <&qup_opp_table>; 2201 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2202 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2203 interconnect-names = "qup-core", "qup-config"; 2204 status = "disabled"; 2205 }; 2206 }; 2207 2208 llcc: system-cache-controller@1100000 { 2209 compatible = "qcom,sdm845-llcc"; 2210 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, 2211 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, 2212 <0 0x01300000 0 0x50000>; 2213 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2214 "llcc3_base", "llcc_broadcast_base"; 2215 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2216 }; 2217 2218 dma@10a2000 { 2219 compatible = "qcom,sdm845-dcc", "qcom,dcc"; 2220 reg = <0x0 0x010a2000 0x0 0x1000>, 2221 <0x0 0x010ae000 0x0 0x2000>; 2222 }; 2223 2224 pmu@114a000 { 2225 compatible = "qcom,sdm845-llcc-bwmon"; 2226 reg = <0 0x0114a000 0 0x1000>; 2227 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2228 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>; 2229 2230 operating-points-v2 = <&llcc_bwmon_opp_table>; 2231 2232 llcc_bwmon_opp_table: opp-table { 2233 compatible = "operating-points-v2"; 2234 2235 /* 2236 * The interconnect path bandwidth taken from 2237 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc 2238 * interconnect. This also matches the 2239 * bandwidth table of qcom,llccbw (qcom,bw-tbl, 2240 * bus width: 4 bytes) from msm-4.9 downstream 2241 * kernel. 2242 */ 2243 opp-0 { 2244 opp-peak-kBps = <800000>; 2245 }; 2246 opp-1 { 2247 opp-peak-kBps = <1804000>; 2248 }; 2249 opp-2 { 2250 opp-peak-kBps = <3072000>; 2251 }; 2252 opp-3 { 2253 opp-peak-kBps = <5412000>; 2254 }; 2255 opp-4 { 2256 opp-peak-kBps = <7216000>; 2257 }; 2258 }; 2259 }; 2260 2261 pmu@1436400 { 2262 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; 2263 reg = <0 0x01436400 0 0x600>; 2264 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2265 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; 2266 2267 operating-points-v2 = <&cpu_bwmon_opp_table>; 2268 2269 cpu_bwmon_opp_table: opp-table { 2270 compatible = "operating-points-v2"; 2271 2272 /* 2273 * The interconnect path bandwidth taken from 2274 * cpu4_opp_table bandwidth for OSM L3 2275 * interconnect. This also matches the OSM L3 2276 * from bandwidth table of qcom,cpu4-l3lat-mon 2277 * (qcom,core-dev-table, bus width: 16 bytes) 2278 * from msm-4.9 downstream kernel. 2279 */ 2280 opp-0 { 2281 opp-peak-kBps = <4800000>; 2282 }; 2283 opp-1 { 2284 opp-peak-kBps = <9216000>; 2285 }; 2286 opp-2 { 2287 opp-peak-kBps = <15052800>; 2288 }; 2289 opp-3 { 2290 opp-peak-kBps = <20889600>; 2291 }; 2292 opp-4 { 2293 opp-peak-kBps = <25497600>; 2294 }; 2295 }; 2296 }; 2297 2298 pcie0: pci@1c00000 { 2299 compatible = "qcom,pcie-sdm845"; 2300 reg = <0 0x01c00000 0 0x2000>, 2301 <0 0x60000000 0 0xf1d>, 2302 <0 0x60000f20 0 0xa8>, 2303 <0 0x60100000 0 0x100000>, 2304 <0 0x01c07000 0 0x1000>; 2305 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2306 device_type = "pci"; 2307 linux,pci-domain = <0>; 2308 bus-range = <0x00 0xff>; 2309 num-lanes = <1>; 2310 2311 #address-cells = <3>; 2312 #size-cells = <2>; 2313 2314 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2315 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; 2316 2317 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 2318 interrupt-names = "msi"; 2319 #interrupt-cells = <1>; 2320 interrupt-map-mask = <0 0 0 0x7>; 2321 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2322 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2323 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2324 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2325 2326 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2327 <&gcc GCC_PCIE_0_AUX_CLK>, 2328 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2329 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2330 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2331 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2332 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2333 clock-names = "pipe", 2334 "aux", 2335 "cfg", 2336 "bus_master", 2337 "bus_slave", 2338 "slave_q2a", 2339 "tbu"; 2340 2341 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 2342 <0x100 &apps_smmu 0x1c11 0x1>, 2343 <0x200 &apps_smmu 0x1c12 0x1>, 2344 <0x300 &apps_smmu 0x1c13 0x1>, 2345 <0x400 &apps_smmu 0x1c14 0x1>, 2346 <0x500 &apps_smmu 0x1c15 0x1>, 2347 <0x600 &apps_smmu 0x1c16 0x1>, 2348 <0x700 &apps_smmu 0x1c17 0x1>, 2349 <0x800 &apps_smmu 0x1c18 0x1>, 2350 <0x900 &apps_smmu 0x1c19 0x1>, 2351 <0xa00 &apps_smmu 0x1c1a 0x1>, 2352 <0xb00 &apps_smmu 0x1c1b 0x1>, 2353 <0xc00 &apps_smmu 0x1c1c 0x1>, 2354 <0xd00 &apps_smmu 0x1c1d 0x1>, 2355 <0xe00 &apps_smmu 0x1c1e 0x1>, 2356 <0xf00 &apps_smmu 0x1c1f 0x1>; 2357 2358 resets = <&gcc GCC_PCIE_0_BCR>; 2359 reset-names = "pci"; 2360 2361 power-domains = <&gcc PCIE_0_GDSC>; 2362 2363 phys = <&pcie0_lane>; 2364 phy-names = "pciephy"; 2365 2366 status = "disabled"; 2367 }; 2368 2369 pcie0_phy: phy@1c06000 { 2370 compatible = "qcom,sdm845-qmp-pcie-phy"; 2371 reg = <0 0x01c06000 0 0x18c>; 2372 #address-cells = <2>; 2373 #size-cells = <2>; 2374 ranges; 2375 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2376 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2377 <&gcc GCC_PCIE_0_CLKREF_CLK>, 2378 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2379 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2380 2381 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2382 reset-names = "phy"; 2383 2384 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2385 assigned-clock-rates = <100000000>; 2386 2387 status = "disabled"; 2388 2389 pcie0_lane: phy@1c06200 { 2390 reg = <0 0x01c06200 0 0x128>, 2391 <0 0x01c06400 0 0x1fc>, 2392 <0 0x01c06800 0 0x218>, 2393 <0 0x01c06600 0 0x70>; 2394 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 2395 clock-names = "pipe0"; 2396 2397 #clock-cells = <0>; 2398 #phy-cells = <0>; 2399 clock-output-names = "pcie_0_pipe_clk"; 2400 }; 2401 }; 2402 2403 pcie1: pci@1c08000 { 2404 compatible = "qcom,pcie-sdm845"; 2405 reg = <0 0x01c08000 0 0x2000>, 2406 <0 0x40000000 0 0xf1d>, 2407 <0 0x40000f20 0 0xa8>, 2408 <0 0x40100000 0 0x100000>, 2409 <0 0x01c0c000 0 0x1000>; 2410 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2411 device_type = "pci"; 2412 linux,pci-domain = <1>; 2413 bus-range = <0x00 0xff>; 2414 num-lanes = <1>; 2415 2416 #address-cells = <3>; 2417 #size-cells = <2>; 2418 2419 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2420 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2421 2422 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 2423 interrupt-names = "msi"; 2424 #interrupt-cells = <1>; 2425 interrupt-map-mask = <0 0 0 0x7>; 2426 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2427 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2428 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2429 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2430 2431 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2432 <&gcc GCC_PCIE_1_AUX_CLK>, 2433 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2434 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2435 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2436 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2437 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2438 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2439 clock-names = "pipe", 2440 "aux", 2441 "cfg", 2442 "bus_master", 2443 "bus_slave", 2444 "slave_q2a", 2445 "ref", 2446 "tbu"; 2447 2448 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2449 assigned-clock-rates = <19200000>; 2450 2451 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2452 <0x100 &apps_smmu 0x1c01 0x1>, 2453 <0x200 &apps_smmu 0x1c02 0x1>, 2454 <0x300 &apps_smmu 0x1c03 0x1>, 2455 <0x400 &apps_smmu 0x1c04 0x1>, 2456 <0x500 &apps_smmu 0x1c05 0x1>, 2457 <0x600 &apps_smmu 0x1c06 0x1>, 2458 <0x700 &apps_smmu 0x1c07 0x1>, 2459 <0x800 &apps_smmu 0x1c08 0x1>, 2460 <0x900 &apps_smmu 0x1c09 0x1>, 2461 <0xa00 &apps_smmu 0x1c0a 0x1>, 2462 <0xb00 &apps_smmu 0x1c0b 0x1>, 2463 <0xc00 &apps_smmu 0x1c0c 0x1>, 2464 <0xd00 &apps_smmu 0x1c0d 0x1>, 2465 <0xe00 &apps_smmu 0x1c0e 0x1>, 2466 <0xf00 &apps_smmu 0x1c0f 0x1>; 2467 2468 resets = <&gcc GCC_PCIE_1_BCR>; 2469 reset-names = "pci"; 2470 2471 power-domains = <&gcc PCIE_1_GDSC>; 2472 2473 phys = <&pcie1_lane>; 2474 phy-names = "pciephy"; 2475 2476 status = "disabled"; 2477 }; 2478 2479 pcie1_phy: phy@1c0a000 { 2480 compatible = "qcom,sdm845-qhp-pcie-phy"; 2481 reg = <0 0x01c0a000 0 0x800>; 2482 #address-cells = <2>; 2483 #size-cells = <2>; 2484 ranges; 2485 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2486 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2487 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2488 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2489 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2490 2491 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2492 reset-names = "phy"; 2493 2494 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2495 assigned-clock-rates = <100000000>; 2496 2497 status = "disabled"; 2498 2499 pcie1_lane: phy@1c06200 { 2500 reg = <0 0x01c0a800 0 0x800>, 2501 <0 0x01c0a800 0 0x800>, 2502 <0 0x01c0b800 0 0x400>; 2503 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2504 clock-names = "pipe0"; 2505 2506 #clock-cells = <0>; 2507 #phy-cells = <0>; 2508 clock-output-names = "pcie_1_pipe_clk"; 2509 }; 2510 }; 2511 2512 mem_noc: interconnect@1380000 { 2513 compatible = "qcom,sdm845-mem-noc"; 2514 reg = <0 0x01380000 0 0x27200>; 2515 #interconnect-cells = <2>; 2516 qcom,bcm-voters = <&apps_bcm_voter>; 2517 }; 2518 2519 dc_noc: interconnect@14e0000 { 2520 compatible = "qcom,sdm845-dc-noc"; 2521 reg = <0 0x014e0000 0 0x400>; 2522 #interconnect-cells = <2>; 2523 qcom,bcm-voters = <&apps_bcm_voter>; 2524 }; 2525 2526 config_noc: interconnect@1500000 { 2527 compatible = "qcom,sdm845-config-noc"; 2528 reg = <0 0x01500000 0 0x5080>; 2529 #interconnect-cells = <2>; 2530 qcom,bcm-voters = <&apps_bcm_voter>; 2531 }; 2532 2533 system_noc: interconnect@1620000 { 2534 compatible = "qcom,sdm845-system-noc"; 2535 reg = <0 0x01620000 0 0x18080>; 2536 #interconnect-cells = <2>; 2537 qcom,bcm-voters = <&apps_bcm_voter>; 2538 }; 2539 2540 aggre1_noc: interconnect@16e0000 { 2541 compatible = "qcom,sdm845-aggre1-noc"; 2542 reg = <0 0x016e0000 0 0x15080>; 2543 #interconnect-cells = <2>; 2544 qcom,bcm-voters = <&apps_bcm_voter>; 2545 }; 2546 2547 aggre2_noc: interconnect@1700000 { 2548 compatible = "qcom,sdm845-aggre2-noc"; 2549 reg = <0 0x01700000 0 0x1f300>; 2550 #interconnect-cells = <2>; 2551 qcom,bcm-voters = <&apps_bcm_voter>; 2552 }; 2553 2554 mmss_noc: interconnect@1740000 { 2555 compatible = "qcom,sdm845-mmss-noc"; 2556 reg = <0 0x01740000 0 0x1c100>; 2557 #interconnect-cells = <2>; 2558 qcom,bcm-voters = <&apps_bcm_voter>; 2559 }; 2560 2561 ufs_mem_hc: ufshc@1d84000 { 2562 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2563 "jedec,ufs-2.0"; 2564 reg = <0 0x01d84000 0 0x2500>, 2565 <0 0x01d90000 0 0x8000>; 2566 reg-names = "std", "ice"; 2567 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2568 phys = <&ufs_mem_phy_lanes>; 2569 phy-names = "ufsphy"; 2570 lanes-per-direction = <2>; 2571 power-domains = <&gcc UFS_PHY_GDSC>; 2572 #reset-cells = <1>; 2573 resets = <&gcc GCC_UFS_PHY_BCR>; 2574 reset-names = "rst"; 2575 2576 iommus = <&apps_smmu 0x100 0xf>; 2577 2578 clock-names = 2579 "core_clk", 2580 "bus_aggr_clk", 2581 "iface_clk", 2582 "core_clk_unipro", 2583 "ref_clk", 2584 "tx_lane0_sync_clk", 2585 "rx_lane0_sync_clk", 2586 "rx_lane1_sync_clk", 2587 "ice_core_clk"; 2588 clocks = 2589 <&gcc GCC_UFS_PHY_AXI_CLK>, 2590 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2591 <&gcc GCC_UFS_PHY_AHB_CLK>, 2592 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2593 <&rpmhcc RPMH_CXO_CLK>, 2594 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2595 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2596 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2597 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2598 freq-table-hz = 2599 <50000000 200000000>, 2600 <0 0>, 2601 <0 0>, 2602 <37500000 150000000>, 2603 <0 0>, 2604 <0 0>, 2605 <0 0>, 2606 <0 0>, 2607 <0 300000000>; 2608 2609 status = "disabled"; 2610 }; 2611 2612 ufs_mem_phy: phy@1d87000 { 2613 compatible = "qcom,sdm845-qmp-ufs-phy"; 2614 reg = <0 0x01d87000 0 0x18c>; 2615 #address-cells = <2>; 2616 #size-cells = <2>; 2617 ranges; 2618 clock-names = "ref", 2619 "ref_aux"; 2620 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2621 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2622 2623 resets = <&ufs_mem_hc 0>; 2624 reset-names = "ufsphy"; 2625 status = "disabled"; 2626 2627 ufs_mem_phy_lanes: phy@1d87400 { 2628 reg = <0 0x01d87400 0 0x108>, 2629 <0 0x01d87600 0 0x1e0>, 2630 <0 0x01d87c00 0 0x1dc>, 2631 <0 0x01d87800 0 0x108>, 2632 <0 0x01d87a00 0 0x1e0>; 2633 #phy-cells = <0>; 2634 }; 2635 }; 2636 2637 cryptobam: dma-controller@1dc4000 { 2638 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2639 reg = <0 0x01dc4000 0 0x24000>; 2640 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2641 clocks = <&rpmhcc RPMH_CE_CLK>; 2642 clock-names = "bam_clk"; 2643 #dma-cells = <1>; 2644 qcom,ee = <0>; 2645 qcom,controlled-remotely; 2646 iommus = <&apps_smmu 0x704 0x1>, 2647 <&apps_smmu 0x706 0x1>, 2648 <&apps_smmu 0x714 0x1>, 2649 <&apps_smmu 0x716 0x1>; 2650 }; 2651 2652 crypto: crypto@1dfa000 { 2653 compatible = "qcom,crypto-v5.4"; 2654 reg = <0 0x01dfa000 0 0x6000>; 2655 clocks = <&gcc GCC_CE1_AHB_CLK>, 2656 <&gcc GCC_CE1_AXI_CLK>, 2657 <&rpmhcc RPMH_CE_CLK>; 2658 clock-names = "iface", "bus", "core"; 2659 dmas = <&cryptobam 6>, <&cryptobam 7>; 2660 dma-names = "rx", "tx"; 2661 iommus = <&apps_smmu 0x704 0x1>, 2662 <&apps_smmu 0x706 0x1>, 2663 <&apps_smmu 0x714 0x1>, 2664 <&apps_smmu 0x716 0x1>; 2665 }; 2666 2667 ipa: ipa@1e40000 { 2668 compatible = "qcom,sdm845-ipa"; 2669 2670 iommus = <&apps_smmu 0x720 0x0>, 2671 <&apps_smmu 0x722 0x0>; 2672 reg = <0 0x01e40000 0 0x7000>, 2673 <0 0x01e47000 0 0x2000>, 2674 <0 0x01e04000 0 0x2c000>; 2675 reg-names = "ipa-reg", 2676 "ipa-shared", 2677 "gsi"; 2678 2679 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 2680 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2681 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2682 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2683 interrupt-names = "ipa", 2684 "gsi", 2685 "ipa-clock-query", 2686 "ipa-setup-ready"; 2687 2688 clocks = <&rpmhcc RPMH_IPA_CLK>; 2689 clock-names = "core"; 2690 2691 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2692 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2693 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2694 interconnect-names = "memory", 2695 "imem", 2696 "config"; 2697 2698 qcom,smem-states = <&ipa_smp2p_out 0>, 2699 <&ipa_smp2p_out 1>; 2700 qcom,smem-state-names = "ipa-clock-enabled-valid", 2701 "ipa-clock-enabled"; 2702 2703 status = "disabled"; 2704 }; 2705 2706 tcsr_mutex: hwlock@1f40000 { 2707 compatible = "qcom,tcsr-mutex"; 2708 reg = <0 0x01f40000 0 0x20000>; 2709 #hwlock-cells = <1>; 2710 }; 2711 2712 tcsr_regs_1: syscon@1f60000 { 2713 compatible = "qcom,sdm845-tcsr", "syscon"; 2714 reg = <0 0x01f60000 0 0x20000>; 2715 }; 2716 2717 tlmm: pinctrl@3400000 { 2718 compatible = "qcom,sdm845-pinctrl"; 2719 reg = <0 0x03400000 0 0xc00000>; 2720 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2721 gpio-controller; 2722 #gpio-cells = <2>; 2723 interrupt-controller; 2724 #interrupt-cells = <2>; 2725 gpio-ranges = <&tlmm 0 0 151>; 2726 wakeup-parent = <&pdc_intc>; 2727 2728 cci0_default: cci0-default-state { 2729 /* SDA, SCL */ 2730 pins = "gpio17", "gpio18"; 2731 function = "cci_i2c"; 2732 2733 bias-pull-up; 2734 drive-strength = <2>; /* 2 mA */ 2735 }; 2736 2737 cci0_sleep: cci0-sleep-state { 2738 /* SDA, SCL */ 2739 pins = "gpio17", "gpio18"; 2740 function = "cci_i2c"; 2741 2742 drive-strength = <2>; /* 2 mA */ 2743 bias-pull-down; 2744 }; 2745 2746 cci1_default: cci1-default-state { 2747 /* SDA, SCL */ 2748 pins = "gpio19", "gpio20"; 2749 function = "cci_i2c"; 2750 2751 bias-pull-up; 2752 drive-strength = <2>; /* 2 mA */ 2753 }; 2754 2755 cci1_sleep: cci1-sleep-state { 2756 /* SDA, SCL */ 2757 pins = "gpio19", "gpio20"; 2758 function = "cci_i2c"; 2759 2760 drive-strength = <2>; /* 2 mA */ 2761 bias-pull-down; 2762 }; 2763 2764 qspi_clk: qspi-clk-state { 2765 pins = "gpio95"; 2766 function = "qspi_clk"; 2767 }; 2768 2769 qspi_cs0: qspi-cs0-state { 2770 pins = "gpio90"; 2771 function = "qspi_cs"; 2772 }; 2773 2774 qspi_cs1: qspi-cs1-state { 2775 pins = "gpio89"; 2776 function = "qspi_cs"; 2777 }; 2778 2779 qspi_data0: qspi-data0-state { 2780 pins = "gpio91"; 2781 function = "qspi_data"; 2782 }; 2783 2784 qspi_data1: qspi-data1-state { 2785 pins = "gpio92"; 2786 function = "qspi_data"; 2787 }; 2788 2789 qspi_data23: qspi-data23-state { 2790 pins = "gpio93", "gpio94"; 2791 function = "qspi_data"; 2792 }; 2793 2794 qup_i2c0_default: qup-i2c0-default-state { 2795 pins = "gpio0", "gpio1"; 2796 function = "qup0"; 2797 }; 2798 2799 qup_i2c1_default: qup-i2c1-default-state { 2800 pins = "gpio17", "gpio18"; 2801 function = "qup1"; 2802 }; 2803 2804 qup_i2c2_default: qup-i2c2-default-state { 2805 pins = "gpio27", "gpio28"; 2806 function = "qup2"; 2807 }; 2808 2809 qup_i2c3_default: qup-i2c3-default-state { 2810 pins = "gpio41", "gpio42"; 2811 function = "qup3"; 2812 }; 2813 2814 qup_i2c4_default: qup-i2c4-default-state { 2815 pins = "gpio89", "gpio90"; 2816 function = "qup4"; 2817 }; 2818 2819 qup_i2c5_default: qup-i2c5-default-state { 2820 pins = "gpio85", "gpio86"; 2821 function = "qup5"; 2822 }; 2823 2824 qup_i2c6_default: qup-i2c6-default-state { 2825 pins = "gpio45", "gpio46"; 2826 function = "qup6"; 2827 }; 2828 2829 qup_i2c7_default: qup-i2c7-default-state { 2830 pins = "gpio93", "gpio94"; 2831 function = "qup7"; 2832 }; 2833 2834 qup_i2c8_default: qup-i2c8-default-state { 2835 pins = "gpio65", "gpio66"; 2836 function = "qup8"; 2837 }; 2838 2839 qup_i2c9_default: qup-i2c9-default-state { 2840 pins = "gpio6", "gpio7"; 2841 function = "qup9"; 2842 }; 2843 2844 qup_i2c10_default: qup-i2c10-default-state { 2845 pins = "gpio55", "gpio56"; 2846 function = "qup10"; 2847 }; 2848 2849 qup_i2c11_default: qup-i2c11-default-state { 2850 pins = "gpio31", "gpio32"; 2851 function = "qup11"; 2852 }; 2853 2854 qup_i2c12_default: qup-i2c12-default-state { 2855 pins = "gpio49", "gpio50"; 2856 function = "qup12"; 2857 }; 2858 2859 qup_i2c13_default: qup-i2c13-default-state { 2860 pins = "gpio105", "gpio106"; 2861 function = "qup13"; 2862 }; 2863 2864 qup_i2c14_default: qup-i2c14-default-state { 2865 pins = "gpio33", "gpio34"; 2866 function = "qup14"; 2867 }; 2868 2869 qup_i2c15_default: qup-i2c15-default-state { 2870 pins = "gpio81", "gpio82"; 2871 function = "qup15"; 2872 }; 2873 2874 qup_spi0_default: qup-spi0-default-state { 2875 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2876 function = "qup0"; 2877 }; 2878 2879 qup_spi1_default: qup-spi1-default-state { 2880 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 2881 function = "qup1"; 2882 }; 2883 2884 qup_spi2_default: qup-spi2-default-state { 2885 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2886 function = "qup2"; 2887 }; 2888 2889 qup_spi3_default: qup-spi3-default-state { 2890 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 2891 function = "qup3"; 2892 }; 2893 2894 qup_spi4_default: qup-spi4-default-state { 2895 pins = "gpio89", "gpio90", "gpio91", "gpio92"; 2896 function = "qup4"; 2897 }; 2898 2899 qup_spi5_default: qup-spi5-default-state { 2900 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 2901 function = "qup5"; 2902 }; 2903 2904 qup_spi6_default: qup-spi6-default-state { 2905 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 2906 function = "qup6"; 2907 }; 2908 2909 qup_spi7_default: qup-spi7-default-state { 2910 pins = "gpio93", "gpio94", "gpio95", "gpio96"; 2911 function = "qup7"; 2912 }; 2913 2914 qup_spi8_default: qup-spi8-default-state { 2915 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 2916 function = "qup8"; 2917 }; 2918 2919 qup_spi9_default: qup-spi9-default-state { 2920 pins = "gpio6", "gpio7", "gpio4", "gpio5"; 2921 function = "qup9"; 2922 }; 2923 2924 qup_spi10_default: qup-spi10-default-state { 2925 pins = "gpio55", "gpio56", "gpio53", "gpio54"; 2926 function = "qup10"; 2927 }; 2928 2929 qup_spi11_default: qup-spi11-default-state { 2930 pins = "gpio31", "gpio32", "gpio33", "gpio34"; 2931 function = "qup11"; 2932 }; 2933 2934 qup_spi12_default: qup-spi12-default-state { 2935 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 2936 function = "qup12"; 2937 }; 2938 2939 qup_spi13_default: qup-spi13-default-state { 2940 pins = "gpio105", "gpio106", "gpio107", "gpio108"; 2941 function = "qup13"; 2942 }; 2943 2944 qup_spi14_default: qup-spi14-default-state { 2945 pins = "gpio33", "gpio34", "gpio31", "gpio32"; 2946 function = "qup14"; 2947 }; 2948 2949 qup_spi15_default: qup-spi15-default-state { 2950 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 2951 function = "qup15"; 2952 }; 2953 2954 qup_uart0_default: qup-uart0-default-state { 2955 qup_uart0_tx: tx-pins { 2956 pins = "gpio2"; 2957 function = "qup0"; 2958 }; 2959 2960 qup_uart0_rx: rx-pins { 2961 pins = "gpio3"; 2962 function = "qup0"; 2963 }; 2964 }; 2965 2966 qup_uart1_default: qup-uart1-default-state { 2967 qup_uart1_tx: tx-pins { 2968 pins = "gpio19"; 2969 function = "qup1"; 2970 }; 2971 2972 qup_uart1_rx: rx-pins { 2973 pins = "gpio20"; 2974 function = "qup1"; 2975 }; 2976 }; 2977 2978 qup_uart2_default: qup-uart2-default-state { 2979 qup_uart2_tx: tx-pins { 2980 pins = "gpio29"; 2981 function = "qup2"; 2982 }; 2983 2984 qup_uart2_rx: rx-pins { 2985 pins = "gpio30"; 2986 function = "qup2"; 2987 }; 2988 }; 2989 2990 qup_uart3_default: qup-uart3-default-state { 2991 qup_uart3_tx: tx-pins { 2992 pins = "gpio43"; 2993 function = "qup3"; 2994 }; 2995 2996 qup_uart3_rx: rx-pins { 2997 pins = "gpio44"; 2998 function = "qup3"; 2999 }; 3000 }; 3001 3002 qup_uart3_4pin: qup-uart3-4pin-state { 3003 qup_uart3_4pin_cts: cts-pins { 3004 pins = "gpio41"; 3005 function = "qup3"; 3006 }; 3007 3008 qup_uart3_4pin_rts_tx: rts-tx-pins { 3009 pins = "gpio42", "gpio43"; 3010 function = "qup3"; 3011 }; 3012 3013 qup_uart3_4pin_rx: rx-pins { 3014 pins = "gpio44"; 3015 function = "qup3"; 3016 }; 3017 }; 3018 3019 qup_uart4_default: qup-uart4-default-state { 3020 qup_uart4_tx: tx-pins { 3021 pins = "gpio91"; 3022 function = "qup4"; 3023 }; 3024 3025 qup_uart4_rx: rx-pins { 3026 pins = "gpio92"; 3027 function = "qup4"; 3028 }; 3029 }; 3030 3031 qup_uart5_default: qup-uart5-default-state { 3032 qup_uart5_tx: tx-pins { 3033 pins = "gpio87"; 3034 function = "qup5"; 3035 }; 3036 3037 qup_uart5_rx: rx-pins { 3038 pins = "gpio88"; 3039 function = "qup5"; 3040 }; 3041 }; 3042 3043 qup_uart6_default: qup-uart6-default-state { 3044 qup_uart6_tx: tx-pins { 3045 pins = "gpio47"; 3046 function = "qup6"; 3047 }; 3048 3049 qup_uart6_rx: rx-pins { 3050 pins = "gpio48"; 3051 function = "qup6"; 3052 }; 3053 }; 3054 3055 qup_uart6_4pin: qup-uart6-4pin-state { 3056 qup_uart6_4pin_cts: cts-pins { 3057 pins = "gpio45"; 3058 function = "qup6"; 3059 bias-pull-down; 3060 }; 3061 3062 qup_uart6_4pin_rts_tx: rts-tx-pins { 3063 pins = "gpio46", "gpio47"; 3064 function = "qup6"; 3065 drive-strength = <2>; 3066 bias-disable; 3067 }; 3068 3069 qup_uart6_4pin_rx: rx-pins { 3070 pins = "gpio48"; 3071 function = "qup6"; 3072 bias-pull-up; 3073 }; 3074 }; 3075 3076 qup_uart7_default: qup-uart7-default-state { 3077 qup_uart7_tx: tx-pins { 3078 pins = "gpio95"; 3079 function = "qup7"; 3080 }; 3081 3082 qup_uart7_rx: rx-pins { 3083 pins = "gpio96"; 3084 function = "qup7"; 3085 }; 3086 }; 3087 3088 qup_uart8_default: qup-uart8-default-state { 3089 qup_uart8_tx: tx-pins { 3090 pins = "gpio67"; 3091 function = "qup8"; 3092 }; 3093 3094 qup_uart8_rx: rx-pins { 3095 pins = "gpio68"; 3096 function = "qup8"; 3097 }; 3098 }; 3099 3100 qup_uart9_default: qup-uart9-default-state { 3101 qup_uart9_tx: tx-pins { 3102 pins = "gpio4"; 3103 function = "qup9"; 3104 }; 3105 3106 qup_uart9_rx: rx-pins { 3107 pins = "gpio5"; 3108 function = "qup9"; 3109 }; 3110 }; 3111 3112 qup_uart10_default: qup-uart10-default-state { 3113 qup_uart10_tx: tx-pins { 3114 pins = "gpio53"; 3115 function = "qup10"; 3116 }; 3117 3118 qup_uart10_rx: rx-pins { 3119 pins = "gpio54"; 3120 function = "qup10"; 3121 }; 3122 }; 3123 3124 qup_uart11_default: qup-uart11-default-state { 3125 qup_uart11_tx: tx-pins { 3126 pins = "gpio33"; 3127 function = "qup11"; 3128 }; 3129 3130 qup_uart11_rx: rx-pins { 3131 pins = "gpio34"; 3132 function = "qup11"; 3133 }; 3134 }; 3135 3136 qup_uart12_default: qup-uart12-default-state { 3137 qup_uart12_tx: tx-pins { 3138 pins = "gpio51"; 3139 function = "qup0"; 3140 }; 3141 3142 qup_uart12_rx: rx-pins { 3143 pins = "gpio52"; 3144 function = "qup0"; 3145 }; 3146 }; 3147 3148 qup_uart13_default: qup-uart13-default-state { 3149 qup_uart13_tx: tx-pins { 3150 pins = "gpio107"; 3151 function = "qup13"; 3152 }; 3153 3154 qup_uart13_rx: rx-pins { 3155 pins = "gpio108"; 3156 function = "qup13"; 3157 }; 3158 }; 3159 3160 qup_uart14_default: qup-uart14-default-state { 3161 qup_uart14_tx: tx-pins { 3162 pins = "gpio31"; 3163 function = "qup14"; 3164 }; 3165 3166 qup_uart14_rx: rx-pins { 3167 pins = "gpio32"; 3168 function = "qup14"; 3169 }; 3170 }; 3171 3172 qup_uart15_default: qup-uart15-default-state { 3173 qup_uart15_tx: tx-pins { 3174 pins = "gpio83"; 3175 function = "qup15"; 3176 }; 3177 3178 qup_uart15_rx: rx-pins { 3179 pins = "gpio84"; 3180 function = "qup15"; 3181 }; 3182 }; 3183 3184 quat_mi2s_sleep: quat-mi2s-sleep-state { 3185 pins = "gpio58", "gpio59"; 3186 function = "gpio"; 3187 drive-strength = <2>; 3188 bias-pull-down; 3189 }; 3190 3191 quat_mi2s_active: quat-mi2s-active-state { 3192 pins = "gpio58", "gpio59"; 3193 function = "qua_mi2s"; 3194 drive-strength = <8>; 3195 bias-disable; 3196 output-high; 3197 }; 3198 3199 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { 3200 pins = "gpio60"; 3201 function = "gpio"; 3202 drive-strength = <2>; 3203 bias-pull-down; 3204 }; 3205 3206 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { 3207 pins = "gpio60"; 3208 function = "qua_mi2s"; 3209 drive-strength = <8>; 3210 bias-disable; 3211 }; 3212 3213 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { 3214 pins = "gpio61"; 3215 function = "gpio"; 3216 drive-strength = <2>; 3217 bias-pull-down; 3218 }; 3219 3220 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { 3221 pins = "gpio61"; 3222 function = "qua_mi2s"; 3223 drive-strength = <8>; 3224 bias-disable; 3225 }; 3226 3227 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { 3228 pins = "gpio62"; 3229 function = "gpio"; 3230 drive-strength = <2>; 3231 bias-pull-down; 3232 }; 3233 3234 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { 3235 pins = "gpio62"; 3236 function = "qua_mi2s"; 3237 drive-strength = <8>; 3238 bias-disable; 3239 }; 3240 3241 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { 3242 pins = "gpio63"; 3243 function = "gpio"; 3244 drive-strength = <2>; 3245 bias-pull-down; 3246 }; 3247 3248 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { 3249 pins = "gpio63"; 3250 function = "qua_mi2s"; 3251 drive-strength = <8>; 3252 bias-disable; 3253 }; 3254 }; 3255 3256 mss_pil: remoteproc@4080000 { 3257 compatible = "qcom,sdm845-mss-pil"; 3258 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 3259 reg-names = "qdsp6", "rmb"; 3260 3261 interrupts-extended = 3262 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 3263 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3264 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3265 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3266 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3267 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3268 interrupt-names = "wdog", "fatal", "ready", 3269 "handover", "stop-ack", 3270 "shutdown-ack"; 3271 3272 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 3273 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 3274 <&gcc GCC_BOOT_ROM_AHB_CLK>, 3275 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 3276 <&gcc GCC_MSS_SNOC_AXI_CLK>, 3277 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 3278 <&gcc GCC_PRNG_AHB_CLK>, 3279 <&rpmhcc RPMH_CXO_CLK>; 3280 clock-names = "iface", "bus", "mem", "gpll0_mss", 3281 "snoc_axi", "mnoc_axi", "prng", "xo"; 3282 3283 qcom,qmp = <&aoss_qmp>; 3284 3285 qcom,smem-states = <&modem_smp2p_out 0>; 3286 qcom,smem-state-names = "stop"; 3287 3288 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 3289 <&pdc_reset PDC_MODEM_SYNC_RESET>; 3290 reset-names = "mss_restart", "pdc_reset"; 3291 3292 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 3293 3294 power-domains = <&rpmhpd SDM845_CX>, 3295 <&rpmhpd SDM845_MX>, 3296 <&rpmhpd SDM845_MSS>; 3297 power-domain-names = "cx", "mx", "mss"; 3298 3299 status = "disabled"; 3300 3301 mba { 3302 memory-region = <&mba_region>; 3303 }; 3304 3305 mpss { 3306 memory-region = <&mpss_region>; 3307 }; 3308 3309 metadata { 3310 memory-region = <&mdata_mem>; 3311 }; 3312 3313 glink-edge { 3314 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 3315 label = "modem"; 3316 qcom,remote-pid = <1>; 3317 mboxes = <&apss_shared 12>; 3318 }; 3319 }; 3320 3321 gpucc: clock-controller@5090000 { 3322 compatible = "qcom,sdm845-gpucc"; 3323 reg = <0 0x05090000 0 0x9000>; 3324 #clock-cells = <1>; 3325 #reset-cells = <1>; 3326 #power-domain-cells = <1>; 3327 clocks = <&rpmhcc RPMH_CXO_CLK>, 3328 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3329 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3330 clock-names = "bi_tcxo", 3331 "gcc_gpu_gpll0_clk_src", 3332 "gcc_gpu_gpll0_div_clk_src"; 3333 }; 3334 3335 slpi_pas: remoteproc@5c00000 { 3336 compatible = "qcom,sdm845-slpi-pas"; 3337 reg = <0 0x5c00000 0 0x4000>; 3338 3339 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 3340 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3341 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3342 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3343 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3344 interrupt-names = "wdog", "fatal", "ready", 3345 "handover", "stop-ack"; 3346 3347 clocks = <&rpmhcc RPMH_CXO_CLK>; 3348 clock-names = "xo"; 3349 3350 qcom,qmp = <&aoss_qmp>; 3351 3352 power-domains = <&rpmhpd SDM845_CX>, 3353 <&rpmhpd SDM845_MX>; 3354 power-domain-names = "lcx", "lmx"; 3355 3356 memory-region = <&slpi_mem>; 3357 3358 qcom,smem-states = <&slpi_smp2p_out 0>; 3359 qcom,smem-state-names = "stop"; 3360 3361 status = "disabled"; 3362 3363 glink-edge { 3364 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 3365 label = "dsps"; 3366 qcom,remote-pid = <3>; 3367 mboxes = <&apss_shared 24>; 3368 3369 fastrpc { 3370 compatible = "qcom,fastrpc"; 3371 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3372 label = "sdsp"; 3373 qcom,non-secure-domain; 3374 qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA 3375 QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>; 3376 memory-region = <&fastrpc_mem>; 3377 #address-cells = <1>; 3378 #size-cells = <0>; 3379 3380 compute-cb@0 { 3381 compatible = "qcom,fastrpc-compute-cb"; 3382 reg = <0>; 3383 }; 3384 }; 3385 }; 3386 }; 3387 3388 stm@6002000 { 3389 compatible = "arm,coresight-stm", "arm,primecell"; 3390 reg = <0 0x06002000 0 0x1000>, 3391 <0 0x16280000 0 0x180000>; 3392 reg-names = "stm-base", "stm-stimulus-base"; 3393 3394 clocks = <&aoss_qmp>; 3395 clock-names = "apb_pclk"; 3396 3397 out-ports { 3398 port { 3399 stm_out: endpoint { 3400 remote-endpoint = 3401 <&funnel0_in7>; 3402 }; 3403 }; 3404 }; 3405 }; 3406 3407 funnel@6041000 { 3408 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3409 reg = <0 0x06041000 0 0x1000>; 3410 3411 clocks = <&aoss_qmp>; 3412 clock-names = "apb_pclk"; 3413 3414 out-ports { 3415 port { 3416 funnel0_out: endpoint { 3417 remote-endpoint = 3418 <&merge_funnel_in0>; 3419 }; 3420 }; 3421 }; 3422 3423 in-ports { 3424 #address-cells = <1>; 3425 #size-cells = <0>; 3426 3427 port@7 { 3428 reg = <7>; 3429 funnel0_in7: endpoint { 3430 remote-endpoint = <&stm_out>; 3431 }; 3432 }; 3433 }; 3434 }; 3435 3436 funnel@6043000 { 3437 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3438 reg = <0 0x06043000 0 0x1000>; 3439 3440 clocks = <&aoss_qmp>; 3441 clock-names = "apb_pclk"; 3442 3443 out-ports { 3444 port { 3445 funnel2_out: endpoint { 3446 remote-endpoint = 3447 <&merge_funnel_in2>; 3448 }; 3449 }; 3450 }; 3451 3452 in-ports { 3453 #address-cells = <1>; 3454 #size-cells = <0>; 3455 3456 port@5 { 3457 reg = <5>; 3458 funnel2_in5: endpoint { 3459 remote-endpoint = 3460 <&apss_merge_funnel_out>; 3461 }; 3462 }; 3463 }; 3464 }; 3465 3466 funnel@6045000 { 3467 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3468 reg = <0 0x06045000 0 0x1000>; 3469 3470 clocks = <&aoss_qmp>; 3471 clock-names = "apb_pclk"; 3472 3473 out-ports { 3474 port { 3475 merge_funnel_out: endpoint { 3476 remote-endpoint = <&etf_in>; 3477 }; 3478 }; 3479 }; 3480 3481 in-ports { 3482 #address-cells = <1>; 3483 #size-cells = <0>; 3484 3485 port@0 { 3486 reg = <0>; 3487 merge_funnel_in0: endpoint { 3488 remote-endpoint = 3489 <&funnel0_out>; 3490 }; 3491 }; 3492 3493 port@2 { 3494 reg = <2>; 3495 merge_funnel_in2: endpoint { 3496 remote-endpoint = 3497 <&funnel2_out>; 3498 }; 3499 }; 3500 }; 3501 }; 3502 3503 replicator@6046000 { 3504 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3505 reg = <0 0x06046000 0 0x1000>; 3506 3507 clocks = <&aoss_qmp>; 3508 clock-names = "apb_pclk"; 3509 3510 out-ports { 3511 port { 3512 replicator_out: endpoint { 3513 remote-endpoint = <&etr_in>; 3514 }; 3515 }; 3516 }; 3517 3518 in-ports { 3519 port { 3520 replicator_in: endpoint { 3521 remote-endpoint = <&etf_out>; 3522 }; 3523 }; 3524 }; 3525 }; 3526 3527 etf@6047000 { 3528 compatible = "arm,coresight-tmc", "arm,primecell"; 3529 reg = <0 0x06047000 0 0x1000>; 3530 3531 clocks = <&aoss_qmp>; 3532 clock-names = "apb_pclk"; 3533 3534 out-ports { 3535 port { 3536 etf_out: endpoint { 3537 remote-endpoint = 3538 <&replicator_in>; 3539 }; 3540 }; 3541 }; 3542 3543 in-ports { 3544 #address-cells = <1>; 3545 #size-cells = <0>; 3546 3547 port@1 { 3548 reg = <1>; 3549 etf_in: endpoint { 3550 remote-endpoint = 3551 <&merge_funnel_out>; 3552 }; 3553 }; 3554 }; 3555 }; 3556 3557 etr@6048000 { 3558 compatible = "arm,coresight-tmc", "arm,primecell"; 3559 reg = <0 0x06048000 0 0x1000>; 3560 3561 clocks = <&aoss_qmp>; 3562 clock-names = "apb_pclk"; 3563 arm,scatter-gather; 3564 3565 in-ports { 3566 port { 3567 etr_in: endpoint { 3568 remote-endpoint = 3569 <&replicator_out>; 3570 }; 3571 }; 3572 }; 3573 }; 3574 3575 etm@7040000 { 3576 compatible = "arm,coresight-etm4x", "arm,primecell"; 3577 reg = <0 0x07040000 0 0x1000>; 3578 3579 cpu = <&CPU0>; 3580 3581 clocks = <&aoss_qmp>; 3582 clock-names = "apb_pclk"; 3583 arm,coresight-loses-context-with-cpu; 3584 3585 out-ports { 3586 port { 3587 etm0_out: endpoint { 3588 remote-endpoint = 3589 <&apss_funnel_in0>; 3590 }; 3591 }; 3592 }; 3593 }; 3594 3595 etm@7140000 { 3596 compatible = "arm,coresight-etm4x", "arm,primecell"; 3597 reg = <0 0x07140000 0 0x1000>; 3598 3599 cpu = <&CPU1>; 3600 3601 clocks = <&aoss_qmp>; 3602 clock-names = "apb_pclk"; 3603 arm,coresight-loses-context-with-cpu; 3604 3605 out-ports { 3606 port { 3607 etm1_out: endpoint { 3608 remote-endpoint = 3609 <&apss_funnel_in1>; 3610 }; 3611 }; 3612 }; 3613 }; 3614 3615 etm@7240000 { 3616 compatible = "arm,coresight-etm4x", "arm,primecell"; 3617 reg = <0 0x07240000 0 0x1000>; 3618 3619 cpu = <&CPU2>; 3620 3621 clocks = <&aoss_qmp>; 3622 clock-names = "apb_pclk"; 3623 arm,coresight-loses-context-with-cpu; 3624 3625 out-ports { 3626 port { 3627 etm2_out: endpoint { 3628 remote-endpoint = 3629 <&apss_funnel_in2>; 3630 }; 3631 }; 3632 }; 3633 }; 3634 3635 etm@7340000 { 3636 compatible = "arm,coresight-etm4x", "arm,primecell"; 3637 reg = <0 0x07340000 0 0x1000>; 3638 3639 cpu = <&CPU3>; 3640 3641 clocks = <&aoss_qmp>; 3642 clock-names = "apb_pclk"; 3643 arm,coresight-loses-context-with-cpu; 3644 3645 out-ports { 3646 port { 3647 etm3_out: endpoint { 3648 remote-endpoint = 3649 <&apss_funnel_in3>; 3650 }; 3651 }; 3652 }; 3653 }; 3654 3655 etm@7440000 { 3656 compatible = "arm,coresight-etm4x", "arm,primecell"; 3657 reg = <0 0x07440000 0 0x1000>; 3658 3659 cpu = <&CPU4>; 3660 3661 clocks = <&aoss_qmp>; 3662 clock-names = "apb_pclk"; 3663 arm,coresight-loses-context-with-cpu; 3664 3665 out-ports { 3666 port { 3667 etm4_out: endpoint { 3668 remote-endpoint = 3669 <&apss_funnel_in4>; 3670 }; 3671 }; 3672 }; 3673 }; 3674 3675 etm@7540000 { 3676 compatible = "arm,coresight-etm4x", "arm,primecell"; 3677 reg = <0 0x07540000 0 0x1000>; 3678 3679 cpu = <&CPU5>; 3680 3681 clocks = <&aoss_qmp>; 3682 clock-names = "apb_pclk"; 3683 arm,coresight-loses-context-with-cpu; 3684 3685 out-ports { 3686 port { 3687 etm5_out: endpoint { 3688 remote-endpoint = 3689 <&apss_funnel_in5>; 3690 }; 3691 }; 3692 }; 3693 }; 3694 3695 etm@7640000 { 3696 compatible = "arm,coresight-etm4x", "arm,primecell"; 3697 reg = <0 0x07640000 0 0x1000>; 3698 3699 cpu = <&CPU6>; 3700 3701 clocks = <&aoss_qmp>; 3702 clock-names = "apb_pclk"; 3703 arm,coresight-loses-context-with-cpu; 3704 3705 out-ports { 3706 port { 3707 etm6_out: endpoint { 3708 remote-endpoint = 3709 <&apss_funnel_in6>; 3710 }; 3711 }; 3712 }; 3713 }; 3714 3715 etm@7740000 { 3716 compatible = "arm,coresight-etm4x", "arm,primecell"; 3717 reg = <0 0x07740000 0 0x1000>; 3718 3719 cpu = <&CPU7>; 3720 3721 clocks = <&aoss_qmp>; 3722 clock-names = "apb_pclk"; 3723 arm,coresight-loses-context-with-cpu; 3724 3725 out-ports { 3726 port { 3727 etm7_out: endpoint { 3728 remote-endpoint = 3729 <&apss_funnel_in7>; 3730 }; 3731 }; 3732 }; 3733 }; 3734 3735 funnel@7800000 { /* APSS Funnel */ 3736 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3737 reg = <0 0x07800000 0 0x1000>; 3738 3739 clocks = <&aoss_qmp>; 3740 clock-names = "apb_pclk"; 3741 3742 out-ports { 3743 port { 3744 apss_funnel_out: endpoint { 3745 remote-endpoint = 3746 <&apss_merge_funnel_in>; 3747 }; 3748 }; 3749 }; 3750 3751 in-ports { 3752 #address-cells = <1>; 3753 #size-cells = <0>; 3754 3755 port@0 { 3756 reg = <0>; 3757 apss_funnel_in0: endpoint { 3758 remote-endpoint = 3759 <&etm0_out>; 3760 }; 3761 }; 3762 3763 port@1 { 3764 reg = <1>; 3765 apss_funnel_in1: endpoint { 3766 remote-endpoint = 3767 <&etm1_out>; 3768 }; 3769 }; 3770 3771 port@2 { 3772 reg = <2>; 3773 apss_funnel_in2: endpoint { 3774 remote-endpoint = 3775 <&etm2_out>; 3776 }; 3777 }; 3778 3779 port@3 { 3780 reg = <3>; 3781 apss_funnel_in3: endpoint { 3782 remote-endpoint = 3783 <&etm3_out>; 3784 }; 3785 }; 3786 3787 port@4 { 3788 reg = <4>; 3789 apss_funnel_in4: endpoint { 3790 remote-endpoint = 3791 <&etm4_out>; 3792 }; 3793 }; 3794 3795 port@5 { 3796 reg = <5>; 3797 apss_funnel_in5: endpoint { 3798 remote-endpoint = 3799 <&etm5_out>; 3800 }; 3801 }; 3802 3803 port@6 { 3804 reg = <6>; 3805 apss_funnel_in6: endpoint { 3806 remote-endpoint = 3807 <&etm6_out>; 3808 }; 3809 }; 3810 3811 port@7 { 3812 reg = <7>; 3813 apss_funnel_in7: endpoint { 3814 remote-endpoint = 3815 <&etm7_out>; 3816 }; 3817 }; 3818 }; 3819 }; 3820 3821 funnel@7810000 { 3822 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3823 reg = <0 0x07810000 0 0x1000>; 3824 3825 clocks = <&aoss_qmp>; 3826 clock-names = "apb_pclk"; 3827 3828 out-ports { 3829 port { 3830 apss_merge_funnel_out: endpoint { 3831 remote-endpoint = 3832 <&funnel2_in5>; 3833 }; 3834 }; 3835 }; 3836 3837 in-ports { 3838 port { 3839 apss_merge_funnel_in: endpoint { 3840 remote-endpoint = 3841 <&apss_funnel_out>; 3842 }; 3843 }; 3844 }; 3845 }; 3846 3847 sdhc_2: mmc@8804000 { 3848 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3849 reg = <0 0x08804000 0 0x1000>; 3850 3851 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3853 interrupt-names = "hc_irq", "pwr_irq"; 3854 3855 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3856 <&gcc GCC_SDCC2_APPS_CLK>, 3857 <&rpmhcc RPMH_CXO_CLK>; 3858 clock-names = "iface", "core", "xo"; 3859 iommus = <&apps_smmu 0xa0 0xf>; 3860 power-domains = <&rpmhpd SDM845_CX>; 3861 operating-points-v2 = <&sdhc2_opp_table>; 3862 3863 status = "disabled"; 3864 3865 sdhc2_opp_table: opp-table { 3866 compatible = "operating-points-v2"; 3867 3868 opp-9600000 { 3869 opp-hz = /bits/ 64 <9600000>; 3870 required-opps = <&rpmhpd_opp_min_svs>; 3871 }; 3872 3873 opp-19200000 { 3874 opp-hz = /bits/ 64 <19200000>; 3875 required-opps = <&rpmhpd_opp_low_svs>; 3876 }; 3877 3878 opp-100000000 { 3879 opp-hz = /bits/ 64 <100000000>; 3880 required-opps = <&rpmhpd_opp_svs>; 3881 }; 3882 3883 opp-201500000 { 3884 opp-hz = /bits/ 64 <201500000>; 3885 required-opps = <&rpmhpd_opp_svs_l1>; 3886 }; 3887 }; 3888 }; 3889 3890 qspi: spi@88df000 { 3891 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3892 reg = <0 0x088df000 0 0x600>; 3893 iommus = <&apps_smmu 0x160 0x0>; 3894 #address-cells = <1>; 3895 #size-cells = <0>; 3896 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3897 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3898 <&gcc GCC_QSPI_CORE_CLK>; 3899 clock-names = "iface", "core"; 3900 power-domains = <&rpmhpd SDM845_CX>; 3901 operating-points-v2 = <&qspi_opp_table>; 3902 status = "disabled"; 3903 }; 3904 3905 slim: slim-ngd@171c0000 { 3906 compatible = "qcom,slim-ngd-v2.1.0"; 3907 reg = <0 0x171c0000 0 0x2c000>; 3908 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3909 3910 dmas = <&slimbam 3>, <&slimbam 4>; 3911 dma-names = "rx", "tx"; 3912 3913 iommus = <&apps_smmu 0x1806 0x0>; 3914 #address-cells = <1>; 3915 #size-cells = <0>; 3916 status = "disabled"; 3917 }; 3918 3919 lmh_cluster1: lmh@17d70800 { 3920 compatible = "qcom,sdm845-lmh"; 3921 reg = <0 0x17d70800 0 0x400>; 3922 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3923 cpus = <&CPU4>; 3924 qcom,lmh-temp-arm-millicelsius = <65000>; 3925 qcom,lmh-temp-low-millicelsius = <94500>; 3926 qcom,lmh-temp-high-millicelsius = <95000>; 3927 interrupt-controller; 3928 #interrupt-cells = <1>; 3929 }; 3930 3931 lmh_cluster0: lmh@17d78800 { 3932 compatible = "qcom,sdm845-lmh"; 3933 reg = <0 0x17d78800 0 0x400>; 3934 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3935 cpus = <&CPU0>; 3936 qcom,lmh-temp-arm-millicelsius = <65000>; 3937 qcom,lmh-temp-low-millicelsius = <94500>; 3938 qcom,lmh-temp-high-millicelsius = <95000>; 3939 interrupt-controller; 3940 #interrupt-cells = <1>; 3941 }; 3942 3943 usb_1_hsphy: phy@88e2000 { 3944 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3945 reg = <0 0x088e2000 0 0x400>; 3946 status = "disabled"; 3947 #phy-cells = <0>; 3948 3949 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3950 <&rpmhcc RPMH_CXO_CLK>; 3951 clock-names = "cfg_ahb", "ref"; 3952 3953 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3954 3955 nvmem-cells = <&qusb2p_hstx_trim>; 3956 }; 3957 3958 usb_2_hsphy: phy@88e3000 { 3959 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3960 reg = <0 0x088e3000 0 0x400>; 3961 status = "disabled"; 3962 #phy-cells = <0>; 3963 3964 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3965 <&rpmhcc RPMH_CXO_CLK>; 3966 clock-names = "cfg_ahb", "ref"; 3967 3968 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3969 3970 nvmem-cells = <&qusb2s_hstx_trim>; 3971 }; 3972 3973 usb_1_qmpphy: phy@88e9000 { 3974 compatible = "qcom,sdm845-qmp-usb3-dp-phy"; 3975 reg = <0 0x088e9000 0 0x18c>, 3976 <0 0x088e8000 0 0x38>, 3977 <0 0x088ea000 0 0x40>; 3978 status = "disabled"; 3979 #address-cells = <2>; 3980 #size-cells = <2>; 3981 ranges; 3982 3983 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3984 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3985 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3986 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3987 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3988 3989 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3990 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 3991 reset-names = "phy", "common"; 3992 3993 usb_1_ssphy: usb3-phy@88e9200 { 3994 reg = <0 0x088e9200 0 0x128>, 3995 <0 0x088e9400 0 0x200>, 3996 <0 0x088e9c00 0 0x218>, 3997 <0 0x088e9600 0 0x128>, 3998 <0 0x088e9800 0 0x200>, 3999 <0 0x088e9a00 0 0x100>; 4000 #clock-cells = <0>; 4001 #phy-cells = <0>; 4002 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4003 clock-names = "pipe0"; 4004 clock-output-names = "usb3_phy_pipe_clk_src"; 4005 }; 4006 4007 dp_phy: dp-phy@88ea200 { 4008 reg = <0 0x088ea200 0 0x200>, 4009 <0 0x088ea400 0 0x200>, 4010 <0 0x088eaa00 0 0x200>, 4011 <0 0x088ea600 0 0x200>, 4012 <0 0x088ea800 0 0x200>; 4013 #clock-cells = <1>; 4014 #phy-cells = <0>; 4015 }; 4016 }; 4017 4018 usb_2_qmpphy: phy@88eb000 { 4019 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 4020 reg = <0 0x088eb000 0 0x18c>; 4021 status = "disabled"; 4022 #address-cells = <2>; 4023 #size-cells = <2>; 4024 ranges; 4025 4026 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 4027 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4028 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 4029 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 4030 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 4031 4032 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 4033 <&gcc GCC_USB3_PHY_SEC_BCR>; 4034 reset-names = "phy", "common"; 4035 4036 usb_2_ssphy: phy@88eb200 { 4037 reg = <0 0x088eb200 0 0x128>, 4038 <0 0x088eb400 0 0x1fc>, 4039 <0 0x088eb800 0 0x218>, 4040 <0 0x088eb600 0 0x70>; 4041 #clock-cells = <0>; 4042 #phy-cells = <0>; 4043 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 4044 clock-names = "pipe0"; 4045 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 4046 }; 4047 }; 4048 4049 usb_1: usb@a6f8800 { 4050 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4051 reg = <0 0x0a6f8800 0 0x400>; 4052 status = "disabled"; 4053 #address-cells = <2>; 4054 #size-cells = <2>; 4055 ranges; 4056 dma-ranges; 4057 4058 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4059 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4060 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4061 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4062 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4063 clock-names = "cfg_noc", 4064 "core", 4065 "iface", 4066 "sleep", 4067 "mock_utmi"; 4068 4069 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4070 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4071 assigned-clock-rates = <19200000>, <150000000>; 4072 4073 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 4077 interrupt-names = "hs_phy_irq", "ss_phy_irq", 4078 "dm_hs_phy_irq", "dp_hs_phy_irq"; 4079 4080 power-domains = <&gcc USB30_PRIM_GDSC>; 4081 4082 resets = <&gcc GCC_USB30_PRIM_BCR>; 4083 4084 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 4085 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4086 interconnect-names = "usb-ddr", "apps-usb"; 4087 4088 usb_1_dwc3: usb@a600000 { 4089 compatible = "snps,dwc3"; 4090 reg = <0 0x0a600000 0 0xcd00>; 4091 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4092 iommus = <&apps_smmu 0x740 0>; 4093 snps,dis_u2_susphy_quirk; 4094 snps,dis_enblslpm_quirk; 4095 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 4096 phy-names = "usb2-phy", "usb3-phy"; 4097 }; 4098 }; 4099 4100 usb_2: usb@a8f8800 { 4101 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4102 reg = <0 0x0a8f8800 0 0x400>; 4103 status = "disabled"; 4104 #address-cells = <2>; 4105 #size-cells = <2>; 4106 ranges; 4107 dma-ranges; 4108 4109 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4110 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4111 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4112 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4113 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4114 clock-names = "cfg_noc", 4115 "core", 4116 "iface", 4117 "sleep", 4118 "mock_utmi"; 4119 4120 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4121 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4122 assigned-clock-rates = <19200000>, <150000000>; 4123 4124 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 4128 interrupt-names = "hs_phy_irq", "ss_phy_irq", 4129 "dm_hs_phy_irq", "dp_hs_phy_irq"; 4130 4131 power-domains = <&gcc USB30_SEC_GDSC>; 4132 4133 resets = <&gcc GCC_USB30_SEC_BCR>; 4134 4135 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 4136 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4137 interconnect-names = "usb-ddr", "apps-usb"; 4138 4139 usb_2_dwc3: usb@a800000 { 4140 compatible = "snps,dwc3"; 4141 reg = <0 0x0a800000 0 0xcd00>; 4142 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4143 iommus = <&apps_smmu 0x760 0>; 4144 snps,dis_u2_susphy_quirk; 4145 snps,dis_enblslpm_quirk; 4146 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 4147 phy-names = "usb2-phy", "usb3-phy"; 4148 }; 4149 }; 4150 4151 venus: video-codec@aa00000 { 4152 compatible = "qcom,sdm845-venus-v2"; 4153 reg = <0 0x0aa00000 0 0xff000>; 4154 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4155 power-domains = <&videocc VENUS_GDSC>, 4156 <&videocc VCODEC0_GDSC>, 4157 <&videocc VCODEC1_GDSC>, 4158 <&rpmhpd SDM845_CX>; 4159 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 4160 operating-points-v2 = <&venus_opp_table>; 4161 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 4162 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4163 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 4164 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 4165 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 4166 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 4167 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 4168 clock-names = "core", "iface", "bus", 4169 "vcodec0_core", "vcodec0_bus", 4170 "vcodec1_core", "vcodec1_bus"; 4171 iommus = <&apps_smmu 0x10a0 0x8>, 4172 <&apps_smmu 0x10b0 0x0>; 4173 memory-region = <&venus_mem>; 4174 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, 4175 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 4176 interconnect-names = "video-mem", "cpu-cfg"; 4177 4178 status = "disabled"; 4179 4180 video-core0 { 4181 compatible = "venus-decoder"; 4182 }; 4183 4184 video-core1 { 4185 compatible = "venus-encoder"; 4186 }; 4187 4188 venus_opp_table: opp-table { 4189 compatible = "operating-points-v2"; 4190 4191 opp-100000000 { 4192 opp-hz = /bits/ 64 <100000000>; 4193 required-opps = <&rpmhpd_opp_min_svs>; 4194 }; 4195 4196 opp-200000000 { 4197 opp-hz = /bits/ 64 <200000000>; 4198 required-opps = <&rpmhpd_opp_low_svs>; 4199 }; 4200 4201 opp-320000000 { 4202 opp-hz = /bits/ 64 <320000000>; 4203 required-opps = <&rpmhpd_opp_svs>; 4204 }; 4205 4206 opp-380000000 { 4207 opp-hz = /bits/ 64 <380000000>; 4208 required-opps = <&rpmhpd_opp_svs_l1>; 4209 }; 4210 4211 opp-444000000 { 4212 opp-hz = /bits/ 64 <444000000>; 4213 required-opps = <&rpmhpd_opp_nom>; 4214 }; 4215 4216 opp-533000097 { 4217 opp-hz = /bits/ 64 <533000097>; 4218 required-opps = <&rpmhpd_opp_turbo>; 4219 }; 4220 }; 4221 }; 4222 4223 videocc: clock-controller@ab00000 { 4224 compatible = "qcom,sdm845-videocc"; 4225 reg = <0 0x0ab00000 0 0x10000>; 4226 clocks = <&rpmhcc RPMH_CXO_CLK>; 4227 clock-names = "bi_tcxo"; 4228 #clock-cells = <1>; 4229 #power-domain-cells = <1>; 4230 #reset-cells = <1>; 4231 }; 4232 4233 camss: camss@acb3000 { 4234 compatible = "qcom,sdm845-camss"; 4235 4236 reg = <0 0x0acb3000 0 0x1000>, 4237 <0 0x0acba000 0 0x1000>, 4238 <0 0x0acc8000 0 0x1000>, 4239 <0 0x0ac65000 0 0x1000>, 4240 <0 0x0ac66000 0 0x1000>, 4241 <0 0x0ac67000 0 0x1000>, 4242 <0 0x0ac68000 0 0x1000>, 4243 <0 0x0acaf000 0 0x4000>, 4244 <0 0x0acb6000 0 0x4000>, 4245 <0 0x0acc4000 0 0x4000>; 4246 reg-names = "csid0", 4247 "csid1", 4248 "csid2", 4249 "csiphy0", 4250 "csiphy1", 4251 "csiphy2", 4252 "csiphy3", 4253 "vfe0", 4254 "vfe1", 4255 "vfe_lite"; 4256 4257 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 4258 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 4259 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 4260 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 4261 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 4262 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 4263 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 4264 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 4265 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 4266 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 4267 interrupt-names = "csid0", 4268 "csid1", 4269 "csid2", 4270 "csiphy0", 4271 "csiphy1", 4272 "csiphy2", 4273 "csiphy3", 4274 "vfe0", 4275 "vfe1", 4276 "vfe_lite"; 4277 4278 power-domains = <&clock_camcc IFE_0_GDSC>, 4279 <&clock_camcc IFE_1_GDSC>, 4280 <&clock_camcc TITAN_TOP_GDSC>; 4281 4282 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4283 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4284 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, 4285 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, 4286 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, 4287 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, 4288 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, 4289 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, 4290 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, 4291 <&clock_camcc CAM_CC_CSIPHY0_CLK>, 4292 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, 4293 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, 4294 <&clock_camcc CAM_CC_CSIPHY1_CLK>, 4295 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, 4296 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, 4297 <&clock_camcc CAM_CC_CSIPHY2_CLK>, 4298 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, 4299 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, 4300 <&clock_camcc CAM_CC_CSIPHY3_CLK>, 4301 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, 4302 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, 4303 <&gcc GCC_CAMERA_AHB_CLK>, 4304 <&gcc GCC_CAMERA_AXI_CLK>, 4305 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4306 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4307 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, 4308 <&clock_camcc CAM_CC_IFE_0_CLK>, 4309 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4310 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, 4311 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, 4312 <&clock_camcc CAM_CC_IFE_1_CLK>, 4313 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4314 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, 4315 <&clock_camcc CAM_CC_IFE_LITE_CLK>, 4316 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4317 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; 4318 clock-names = "camnoc_axi", 4319 "cpas_ahb", 4320 "cphy_rx_src", 4321 "csi0", 4322 "csi0_src", 4323 "csi1", 4324 "csi1_src", 4325 "csi2", 4326 "csi2_src", 4327 "csiphy0", 4328 "csiphy0_timer", 4329 "csiphy0_timer_src", 4330 "csiphy1", 4331 "csiphy1_timer", 4332 "csiphy1_timer_src", 4333 "csiphy2", 4334 "csiphy2_timer", 4335 "csiphy2_timer_src", 4336 "csiphy3", 4337 "csiphy3_timer", 4338 "csiphy3_timer_src", 4339 "gcc_camera_ahb", 4340 "gcc_camera_axi", 4341 "slow_ahb_src", 4342 "soc_ahb", 4343 "vfe0_axi", 4344 "vfe0", 4345 "vfe0_cphy_rx", 4346 "vfe0_src", 4347 "vfe1_axi", 4348 "vfe1", 4349 "vfe1_cphy_rx", 4350 "vfe1_src", 4351 "vfe_lite", 4352 "vfe_lite_cphy_rx", 4353 "vfe_lite_src"; 4354 4355 iommus = <&apps_smmu 0x0808 0x0>, 4356 <&apps_smmu 0x0810 0x8>, 4357 <&apps_smmu 0x0c08 0x0>, 4358 <&apps_smmu 0x0c10 0x8>; 4359 4360 status = "disabled"; 4361 4362 ports { 4363 #address-cells = <1>; 4364 #size-cells = <0>; 4365 4366 port@0 { 4367 reg = <0>; 4368 }; 4369 4370 port@1 { 4371 reg = <1>; 4372 }; 4373 4374 port@2 { 4375 reg = <2>; 4376 }; 4377 4378 port@3 { 4379 reg = <3>; 4380 }; 4381 }; 4382 }; 4383 4384 cci: cci@ac4a000 { 4385 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; 4386 #address-cells = <1>; 4387 #size-cells = <0>; 4388 4389 reg = <0 0x0ac4a000 0 0x4000>; 4390 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4391 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 4392 4393 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4394 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4395 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4396 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4397 <&clock_camcc CAM_CC_CCI_CLK>, 4398 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 4399 clock-names = "camnoc_axi", 4400 "soc_ahb", 4401 "slow_ahb_src", 4402 "cpas_ahb", 4403 "cci", 4404 "cci_src"; 4405 4406 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4407 <&clock_camcc CAM_CC_CCI_CLK>; 4408 assigned-clock-rates = <80000000>, <37500000>; 4409 4410 pinctrl-names = "default", "sleep"; 4411 pinctrl-0 = <&cci0_default &cci1_default>; 4412 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4413 4414 status = "disabled"; 4415 4416 cci_i2c0: i2c-bus@0 { 4417 reg = <0>; 4418 clock-frequency = <1000000>; 4419 #address-cells = <1>; 4420 #size-cells = <0>; 4421 }; 4422 4423 cci_i2c1: i2c-bus@1 { 4424 reg = <1>; 4425 clock-frequency = <1000000>; 4426 #address-cells = <1>; 4427 #size-cells = <0>; 4428 }; 4429 }; 4430 4431 clock_camcc: clock-controller@ad00000 { 4432 compatible = "qcom,sdm845-camcc"; 4433 reg = <0 0x0ad00000 0 0x10000>; 4434 #clock-cells = <1>; 4435 #reset-cells = <1>; 4436 #power-domain-cells = <1>; 4437 clocks = <&rpmhcc RPMH_CXO_CLK>; 4438 clock-names = "bi_tcxo"; 4439 }; 4440 4441 mdss: display-subsystem@ae00000 { 4442 compatible = "qcom,sdm845-mdss"; 4443 reg = <0 0x0ae00000 0 0x1000>; 4444 reg-names = "mdss"; 4445 4446 power-domains = <&dispcc MDSS_GDSC>; 4447 4448 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4449 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4450 clock-names = "iface", "core"; 4451 4452 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4453 interrupt-controller; 4454 #interrupt-cells = <1>; 4455 4456 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 4457 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 4458 interconnect-names = "mdp0-mem", "mdp1-mem"; 4459 4460 iommus = <&apps_smmu 0x880 0x8>, 4461 <&apps_smmu 0xc80 0x8>; 4462 4463 status = "disabled"; 4464 4465 #address-cells = <2>; 4466 #size-cells = <2>; 4467 ranges; 4468 4469 mdss_mdp: display-controller@ae01000 { 4470 compatible = "qcom,sdm845-dpu"; 4471 reg = <0 0x0ae01000 0 0x8f000>, 4472 <0 0x0aeb0000 0 0x2008>; 4473 reg-names = "mdp", "vbif"; 4474 4475 clocks = <&gcc GCC_DISP_AXI_CLK>, 4476 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4477 <&dispcc DISP_CC_MDSS_AXI_CLK>, 4478 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4479 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4480 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 4481 4482 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4483 assigned-clock-rates = <19200000>; 4484 operating-points-v2 = <&mdp_opp_table>; 4485 power-domains = <&rpmhpd SDM845_CX>; 4486 4487 interrupt-parent = <&mdss>; 4488 interrupts = <0>; 4489 4490 ports { 4491 #address-cells = <1>; 4492 #size-cells = <0>; 4493 4494 port@0 { 4495 reg = <0>; 4496 dpu_intf0_out: endpoint { 4497 remote-endpoint = <&dp_in>; 4498 }; 4499 }; 4500 4501 port@1 { 4502 reg = <1>; 4503 dpu_intf1_out: endpoint { 4504 remote-endpoint = <&mdss_dsi0_in>; 4505 }; 4506 }; 4507 4508 port@2 { 4509 reg = <2>; 4510 dpu_intf2_out: endpoint { 4511 remote-endpoint = <&mdss_dsi1_in>; 4512 }; 4513 }; 4514 }; 4515 4516 mdp_opp_table: opp-table { 4517 compatible = "operating-points-v2"; 4518 4519 opp-19200000 { 4520 opp-hz = /bits/ 64 <19200000>; 4521 required-opps = <&rpmhpd_opp_min_svs>; 4522 }; 4523 4524 opp-171428571 { 4525 opp-hz = /bits/ 64 <171428571>; 4526 required-opps = <&rpmhpd_opp_low_svs>; 4527 }; 4528 4529 opp-344000000 { 4530 opp-hz = /bits/ 64 <344000000>; 4531 required-opps = <&rpmhpd_opp_svs_l1>; 4532 }; 4533 4534 opp-430000000 { 4535 opp-hz = /bits/ 64 <430000000>; 4536 required-opps = <&rpmhpd_opp_nom>; 4537 }; 4538 }; 4539 }; 4540 4541 mdss_dp: displayport-controller@ae90000 { 4542 status = "disabled"; 4543 compatible = "qcom,sdm845-dp"; 4544 4545 reg = <0 0x0ae90000 0 0x200>, 4546 <0 0x0ae90200 0 0x200>, 4547 <0 0x0ae90400 0 0x600>, 4548 <0 0x0ae90a00 0 0x600>, 4549 <0 0x0ae91000 0 0x600>; 4550 4551 interrupt-parent = <&mdss>; 4552 interrupts = <12>; 4553 4554 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4555 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4556 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4557 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4558 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4559 clock-names = "core_iface", "core_aux", "ctrl_link", 4560 "ctrl_link_iface", "stream_pixel"; 4561 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4562 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4563 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4564 phys = <&dp_phy>; 4565 phy-names = "dp"; 4566 4567 operating-points-v2 = <&dp_opp_table>; 4568 power-domains = <&rpmhpd SDM845_CX>; 4569 4570 ports { 4571 #address-cells = <1>; 4572 #size-cells = <0>; 4573 port@0 { 4574 reg = <0>; 4575 dp_in: endpoint { 4576 remote-endpoint = <&dpu_intf0_out>; 4577 }; 4578 }; 4579 4580 port@1 { 4581 reg = <1>; 4582 dp_out: endpoint { }; 4583 }; 4584 }; 4585 4586 dp_opp_table: opp-table { 4587 compatible = "operating-points-v2"; 4588 4589 opp-162000000 { 4590 opp-hz = /bits/ 64 <162000000>; 4591 required-opps = <&rpmhpd_opp_low_svs>; 4592 }; 4593 4594 opp-270000000 { 4595 opp-hz = /bits/ 64 <270000000>; 4596 required-opps = <&rpmhpd_opp_svs>; 4597 }; 4598 4599 opp-540000000 { 4600 opp-hz = /bits/ 64 <540000000>; 4601 required-opps = <&rpmhpd_opp_svs_l1>; 4602 }; 4603 4604 opp-810000000 { 4605 opp-hz = /bits/ 64 <810000000>; 4606 required-opps = <&rpmhpd_opp_nom>; 4607 }; 4608 }; 4609 }; 4610 4611 mdss_dsi0: dsi@ae94000 { 4612 compatible = "qcom,sdm845-dsi-ctrl", 4613 "qcom,mdss-dsi-ctrl"; 4614 reg = <0 0x0ae94000 0 0x400>; 4615 reg-names = "dsi_ctrl"; 4616 4617 interrupt-parent = <&mdss>; 4618 interrupts = <4>; 4619 4620 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4621 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4622 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4623 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4624 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4625 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4626 clock-names = "byte", 4627 "byte_intf", 4628 "pixel", 4629 "core", 4630 "iface", 4631 "bus"; 4632 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4633 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 4634 4635 operating-points-v2 = <&dsi_opp_table>; 4636 power-domains = <&rpmhpd SDM845_CX>; 4637 4638 phys = <&mdss_dsi0_phy>; 4639 4640 status = "disabled"; 4641 4642 #address-cells = <1>; 4643 #size-cells = <0>; 4644 4645 ports { 4646 #address-cells = <1>; 4647 #size-cells = <0>; 4648 4649 port@0 { 4650 reg = <0>; 4651 mdss_dsi0_in: endpoint { 4652 remote-endpoint = <&dpu_intf1_out>; 4653 }; 4654 }; 4655 4656 port@1 { 4657 reg = <1>; 4658 mdss_dsi0_out: endpoint { 4659 }; 4660 }; 4661 }; 4662 }; 4663 4664 mdss_dsi0_phy: phy@ae94400 { 4665 compatible = "qcom,dsi-phy-10nm"; 4666 reg = <0 0x0ae94400 0 0x200>, 4667 <0 0x0ae94600 0 0x280>, 4668 <0 0x0ae94a00 0 0x1e0>; 4669 reg-names = "dsi_phy", 4670 "dsi_phy_lane", 4671 "dsi_pll"; 4672 4673 #clock-cells = <1>; 4674 #phy-cells = <0>; 4675 4676 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4677 <&rpmhcc RPMH_CXO_CLK>; 4678 clock-names = "iface", "ref"; 4679 4680 status = "disabled"; 4681 }; 4682 4683 mdss_dsi1: dsi@ae96000 { 4684 compatible = "qcom,sdm845-dsi-ctrl", 4685 "qcom,mdss-dsi-ctrl"; 4686 reg = <0 0x0ae96000 0 0x400>; 4687 reg-names = "dsi_ctrl"; 4688 4689 interrupt-parent = <&mdss>; 4690 interrupts = <5>; 4691 4692 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4693 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4694 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4695 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4696 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4697 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4698 clock-names = "byte", 4699 "byte_intf", 4700 "pixel", 4701 "core", 4702 "iface", 4703 "bus"; 4704 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4705 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 4706 4707 operating-points-v2 = <&dsi_opp_table>; 4708 power-domains = <&rpmhpd SDM845_CX>; 4709 4710 phys = <&mdss_dsi1_phy>; 4711 4712 status = "disabled"; 4713 4714 #address-cells = <1>; 4715 #size-cells = <0>; 4716 4717 ports { 4718 #address-cells = <1>; 4719 #size-cells = <0>; 4720 4721 port@0 { 4722 reg = <0>; 4723 mdss_dsi1_in: endpoint { 4724 remote-endpoint = <&dpu_intf2_out>; 4725 }; 4726 }; 4727 4728 port@1 { 4729 reg = <1>; 4730 mdss_dsi1_out: endpoint { 4731 }; 4732 }; 4733 }; 4734 }; 4735 4736 mdss_dsi1_phy: phy@ae96400 { 4737 compatible = "qcom,dsi-phy-10nm"; 4738 reg = <0 0x0ae96400 0 0x200>, 4739 <0 0x0ae96600 0 0x280>, 4740 <0 0x0ae96a00 0 0x10e>; 4741 reg-names = "dsi_phy", 4742 "dsi_phy_lane", 4743 "dsi_pll"; 4744 4745 #clock-cells = <1>; 4746 #phy-cells = <0>; 4747 4748 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4749 <&rpmhcc RPMH_CXO_CLK>; 4750 clock-names = "iface", "ref"; 4751 4752 status = "disabled"; 4753 }; 4754 }; 4755 4756 gpu: gpu@5000000 { 4757 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4758 4759 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>; 4760 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4761 4762 /* 4763 * Look ma, no clocks! The GPU clocks and power are 4764 * controlled entirely by the GMU 4765 */ 4766 4767 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4768 4769 iommus = <&adreno_smmu 0>; 4770 4771 operating-points-v2 = <&gpu_opp_table>; 4772 4773 qcom,gmu = <&gmu>; 4774 4775 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4776 interconnect-names = "gfx-mem"; 4777 4778 status = "disabled"; 4779 4780 gpu_opp_table: opp-table { 4781 compatible = "operating-points-v2"; 4782 4783 opp-710000000 { 4784 opp-hz = /bits/ 64 <710000000>; 4785 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4786 opp-peak-kBps = <7216000>; 4787 }; 4788 4789 opp-675000000 { 4790 opp-hz = /bits/ 64 <675000000>; 4791 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4792 opp-peak-kBps = <7216000>; 4793 }; 4794 4795 opp-596000000 { 4796 opp-hz = /bits/ 64 <596000000>; 4797 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4798 opp-peak-kBps = <6220000>; 4799 }; 4800 4801 opp-520000000 { 4802 opp-hz = /bits/ 64 <520000000>; 4803 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4804 opp-peak-kBps = <6220000>; 4805 }; 4806 4807 opp-414000000 { 4808 opp-hz = /bits/ 64 <414000000>; 4809 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4810 opp-peak-kBps = <4068000>; 4811 }; 4812 4813 opp-342000000 { 4814 opp-hz = /bits/ 64 <342000000>; 4815 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4816 opp-peak-kBps = <2724000>; 4817 }; 4818 4819 opp-257000000 { 4820 opp-hz = /bits/ 64 <257000000>; 4821 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4822 opp-peak-kBps = <1648000>; 4823 }; 4824 }; 4825 }; 4826 4827 adreno_smmu: iommu@5040000 { 4828 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 4829 reg = <0 0x05040000 0 0x10000>; 4830 #iommu-cells = <1>; 4831 #global-interrupts = <2>; 4832 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4833 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4834 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4835 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4836 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4837 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4838 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4839 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4840 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4841 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4842 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4843 <&gcc GCC_GPU_CFG_AHB_CLK>; 4844 clock-names = "bus", "iface"; 4845 4846 power-domains = <&gpucc GPU_CX_GDSC>; 4847 }; 4848 4849 gmu: gmu@506a000 { 4850 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4851 4852 reg = <0 0x0506a000 0 0x30000>, 4853 <0 0x0b280000 0 0x10000>, 4854 <0 0x0b480000 0 0x10000>; 4855 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4856 4857 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4858 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4859 interrupt-names = "hfi", "gmu"; 4860 4861 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4862 <&gpucc GPU_CC_CXO_CLK>, 4863 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4864 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4865 clock-names = "gmu", "cxo", "axi", "memnoc"; 4866 4867 power-domains = <&gpucc GPU_CX_GDSC>, 4868 <&gpucc GPU_GX_GDSC>; 4869 power-domain-names = "cx", "gx"; 4870 4871 iommus = <&adreno_smmu 5>; 4872 4873 operating-points-v2 = <&gmu_opp_table>; 4874 4875 status = "disabled"; 4876 4877 gmu_opp_table: opp-table { 4878 compatible = "operating-points-v2"; 4879 4880 opp-400000000 { 4881 opp-hz = /bits/ 64 <400000000>; 4882 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4883 }; 4884 4885 opp-200000000 { 4886 opp-hz = /bits/ 64 <200000000>; 4887 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4888 }; 4889 }; 4890 }; 4891 4892 dispcc: clock-controller@af00000 { 4893 compatible = "qcom,sdm845-dispcc"; 4894 reg = <0 0x0af00000 0 0x10000>; 4895 clocks = <&rpmhcc RPMH_CXO_CLK>, 4896 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4897 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4898 <&mdss_dsi0_phy 0>, 4899 <&mdss_dsi0_phy 1>, 4900 <&mdss_dsi1_phy 0>, 4901 <&mdss_dsi1_phy 1>, 4902 <&dp_phy 0>, 4903 <&dp_phy 1>; 4904 clock-names = "bi_tcxo", 4905 "gcc_disp_gpll0_clk_src", 4906 "gcc_disp_gpll0_div_clk_src", 4907 "dsi0_phy_pll_out_byteclk", 4908 "dsi0_phy_pll_out_dsiclk", 4909 "dsi1_phy_pll_out_byteclk", 4910 "dsi1_phy_pll_out_dsiclk", 4911 "dp_link_clk_divsel_ten", 4912 "dp_vco_divided_clk_src_mux"; 4913 #clock-cells = <1>; 4914 #reset-cells = <1>; 4915 #power-domain-cells = <1>; 4916 }; 4917 4918 pdc_intc: interrupt-controller@b220000 { 4919 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 4920 reg = <0 0x0b220000 0 0x30000>; 4921 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 4922 #interrupt-cells = <2>; 4923 interrupt-parent = <&intc>; 4924 interrupt-controller; 4925 }; 4926 4927 pdc_reset: reset-controller@b2e0000 { 4928 compatible = "qcom,sdm845-pdc-global"; 4929 reg = <0 0x0b2e0000 0 0x20000>; 4930 #reset-cells = <1>; 4931 }; 4932 4933 tsens0: thermal-sensor@c263000 { 4934 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4935 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4936 <0 0x0c222000 0 0x1ff>; /* SROT */ 4937 #qcom,sensors = <13>; 4938 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4939 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4940 interrupt-names = "uplow", "critical"; 4941 #thermal-sensor-cells = <1>; 4942 }; 4943 4944 tsens1: thermal-sensor@c265000 { 4945 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4946 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4947 <0 0x0c223000 0 0x1ff>; /* SROT */ 4948 #qcom,sensors = <8>; 4949 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4950 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4951 interrupt-names = "uplow", "critical"; 4952 #thermal-sensor-cells = <1>; 4953 }; 4954 4955 aoss_reset: reset-controller@c2a0000 { 4956 compatible = "qcom,sdm845-aoss-cc"; 4957 reg = <0 0x0c2a0000 0 0x31000>; 4958 #reset-cells = <1>; 4959 }; 4960 4961 aoss_qmp: power-management@c300000 { 4962 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; 4963 reg = <0 0x0c300000 0 0x400>; 4964 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4965 mboxes = <&apss_shared 0>; 4966 4967 #clock-cells = <0>; 4968 4969 cx_cdev: cx { 4970 #cooling-cells = <2>; 4971 }; 4972 4973 ebi_cdev: ebi { 4974 #cooling-cells = <2>; 4975 }; 4976 }; 4977 4978 sram@c3f0000 { 4979 compatible = "qcom,sdm845-rpmh-stats"; 4980 reg = <0 0x0c3f0000 0 0x400>; 4981 }; 4982 4983 spmi_bus: spmi@c440000 { 4984 compatible = "qcom,spmi-pmic-arb"; 4985 reg = <0 0x0c440000 0 0x1100>, 4986 <0 0x0c600000 0 0x2000000>, 4987 <0 0x0e600000 0 0x100000>, 4988 <0 0x0e700000 0 0xa0000>, 4989 <0 0x0c40a000 0 0x26000>; 4990 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4991 interrupt-names = "periph_irq"; 4992 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4993 qcom,ee = <0>; 4994 qcom,channel = <0>; 4995 #address-cells = <2>; 4996 #size-cells = <0>; 4997 interrupt-controller; 4998 #interrupt-cells = <4>; 4999 }; 5000 5001 sram@146bf000 { 5002 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; 5003 reg = <0 0x146bf000 0 0x1000>; 5004 5005 #address-cells = <1>; 5006 #size-cells = <1>; 5007 5008 ranges = <0 0 0x146bf000 0x1000>; 5009 5010 pil-reloc@94c { 5011 compatible = "qcom,pil-reloc-info"; 5012 reg = <0x94c 0xc8>; 5013 }; 5014 }; 5015 5016 apps_smmu: iommu@15000000 { 5017 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 5018 reg = <0 0x15000000 0 0x80000>; 5019 #iommu-cells = <2>; 5020 #global-interrupts = <1>; 5021 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5022 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5023 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5024 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5025 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5026 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5027 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5028 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5029 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5030 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5031 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5032 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5033 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5034 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5035 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5036 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5037 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5038 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5039 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5040 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5041 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5042 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5043 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5044 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5045 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5046 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5047 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5048 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5049 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5050 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5051 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5052 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5053 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5055 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5056 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5057 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5058 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5061 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5069 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 5086 }; 5087 5088 lpasscc: clock-controller@17014000 { 5089 compatible = "qcom,sdm845-lpasscc"; 5090 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 5091 reg-names = "cc", "qdsp6ss"; 5092 #clock-cells = <1>; 5093 status = "disabled"; 5094 }; 5095 5096 gladiator_noc: interconnect@17900000 { 5097 compatible = "qcom,sdm845-gladiator-noc"; 5098 reg = <0 0x17900000 0 0xd080>; 5099 #interconnect-cells = <2>; 5100 qcom,bcm-voters = <&apps_bcm_voter>; 5101 }; 5102 5103 watchdog@17980000 { 5104 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 5105 reg = <0 0x17980000 0 0x1000>; 5106 clocks = <&sleep_clk>; 5107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5108 }; 5109 5110 apss_shared: mailbox@17990000 { 5111 compatible = "qcom,sdm845-apss-shared"; 5112 reg = <0 0x17990000 0 0x1000>; 5113 #mbox-cells = <1>; 5114 }; 5115 5116 apps_rsc: rsc@179c0000 { 5117 label = "apps_rsc"; 5118 compatible = "qcom,rpmh-rsc"; 5119 reg = <0 0x179c0000 0 0x10000>, 5120 <0 0x179d0000 0 0x10000>, 5121 <0 0x179e0000 0 0x10000>; 5122 reg-names = "drv-0", "drv-1", "drv-2"; 5123 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5126 qcom,tcs-offset = <0xd00>; 5127 qcom,drv-id = <2>; 5128 qcom,tcs-config = <ACTIVE_TCS 2>, 5129 <SLEEP_TCS 3>, 5130 <WAKE_TCS 3>, 5131 <CONTROL_TCS 1>; 5132 power-domains = <&CLUSTER_PD>; 5133 5134 apps_bcm_voter: bcm-voter { 5135 compatible = "qcom,bcm-voter"; 5136 }; 5137 5138 rpmhcc: clock-controller { 5139 compatible = "qcom,sdm845-rpmh-clk"; 5140 #clock-cells = <1>; 5141 clock-names = "xo"; 5142 clocks = <&xo_board>; 5143 }; 5144 5145 rpmhpd: power-controller { 5146 compatible = "qcom,sdm845-rpmhpd"; 5147 #power-domain-cells = <1>; 5148 operating-points-v2 = <&rpmhpd_opp_table>; 5149 5150 rpmhpd_opp_table: opp-table { 5151 compatible = "operating-points-v2"; 5152 5153 rpmhpd_opp_ret: opp1 { 5154 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5155 }; 5156 5157 rpmhpd_opp_min_svs: opp2 { 5158 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5159 }; 5160 5161 rpmhpd_opp_low_svs: opp3 { 5162 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5163 }; 5164 5165 rpmhpd_opp_svs: opp4 { 5166 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5167 }; 5168 5169 rpmhpd_opp_svs_l1: opp5 { 5170 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5171 }; 5172 5173 rpmhpd_opp_nom: opp6 { 5174 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5175 }; 5176 5177 rpmhpd_opp_nom_l1: opp7 { 5178 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5179 }; 5180 5181 rpmhpd_opp_nom_l2: opp8 { 5182 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5183 }; 5184 5185 rpmhpd_opp_turbo: opp9 { 5186 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5187 }; 5188 5189 rpmhpd_opp_turbo_l1: opp10 { 5190 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5191 }; 5192 }; 5193 }; 5194 }; 5195 5196 intc: interrupt-controller@17a00000 { 5197 compatible = "arm,gic-v3"; 5198 #address-cells = <2>; 5199 #size-cells = <2>; 5200 ranges; 5201 #interrupt-cells = <3>; 5202 interrupt-controller; 5203 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5204 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5205 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5206 5207 msi-controller@17a40000 { 5208 compatible = "arm,gic-v3-its"; 5209 msi-controller; 5210 #msi-cells = <1>; 5211 reg = <0 0x17a40000 0 0x20000>; 5212 status = "disabled"; 5213 }; 5214 }; 5215 5216 slimbam: dma-controller@17184000 { 5217 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 5218 qcom,controlled-remotely; 5219 reg = <0 0x17184000 0 0x2a000>; 5220 num-channels = <31>; 5221 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 5222 #dma-cells = <1>; 5223 qcom,ee = <1>; 5224 qcom,num-ees = <2>; 5225 iommus = <&apps_smmu 0x1806 0x0>; 5226 }; 5227 5228 timer@17c90000 { 5229 #address-cells = <1>; 5230 #size-cells = <1>; 5231 ranges = <0 0 0 0x20000000>; 5232 compatible = "arm,armv7-timer-mem"; 5233 reg = <0 0x17c90000 0 0x1000>; 5234 5235 frame@17ca0000 { 5236 frame-number = <0>; 5237 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 5238 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5239 reg = <0x17ca0000 0x1000>, 5240 <0x17cb0000 0x1000>; 5241 }; 5242 5243 frame@17cc0000 { 5244 frame-number = <1>; 5245 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 5246 reg = <0x17cc0000 0x1000>; 5247 status = "disabled"; 5248 }; 5249 5250 frame@17cd0000 { 5251 frame-number = <2>; 5252 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5253 reg = <0x17cd0000 0x1000>; 5254 status = "disabled"; 5255 }; 5256 5257 frame@17ce0000 { 5258 frame-number = <3>; 5259 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5260 reg = <0x17ce0000 0x1000>; 5261 status = "disabled"; 5262 }; 5263 5264 frame@17cf0000 { 5265 frame-number = <4>; 5266 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5267 reg = <0x17cf0000 0x1000>; 5268 status = "disabled"; 5269 }; 5270 5271 frame@17d00000 { 5272 frame-number = <5>; 5273 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5274 reg = <0x17d00000 0x1000>; 5275 status = "disabled"; 5276 }; 5277 5278 frame@17d10000 { 5279 frame-number = <6>; 5280 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5281 reg = <0x17d10000 0x1000>; 5282 status = "disabled"; 5283 }; 5284 }; 5285 5286 osm_l3: interconnect@17d41000 { 5287 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; 5288 reg = <0 0x17d41000 0 0x1400>; 5289 5290 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5291 clock-names = "xo", "alternate"; 5292 5293 #interconnect-cells = <1>; 5294 }; 5295 5296 cpufreq_hw: cpufreq@17d43000 { 5297 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw"; 5298 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 5299 reg-names = "freq-domain0", "freq-domain1"; 5300 5301 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; 5302 5303 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5304 clock-names = "xo", "alternate"; 5305 5306 #freq-domain-cells = <1>; 5307 #clock-cells = <1>; 5308 }; 5309 5310 wifi: wifi@18800000 { 5311 compatible = "qcom,wcn3990-wifi"; 5312 status = "disabled"; 5313 reg = <0 0x18800000 0 0x800000>; 5314 reg-names = "membase"; 5315 memory-region = <&wlan_msa_mem>; 5316 clock-names = "cxo_ref_clk_pin"; 5317 clocks = <&rpmhcc RPMH_RF_CLK2>; 5318 interrupts = 5319 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5320 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 5321 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 5322 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 5323 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5324 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5325 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5326 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5327 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5328 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5329 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5330 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 5331 iommus = <&apps_smmu 0x0040 0x1>; 5332 }; 5333 }; 5334 5335 sound: sound { 5336 }; 5337 5338 thermal-zones { 5339 cpu0-thermal { 5340 polling-delay-passive = <250>; 5341 polling-delay = <1000>; 5342 5343 thermal-sensors = <&tsens0 1>; 5344 5345 trips { 5346 cpu0_alert0: trip-point0 { 5347 temperature = <90000>; 5348 hysteresis = <2000>; 5349 type = "passive"; 5350 }; 5351 5352 cpu0_alert1: trip-point1 { 5353 temperature = <95000>; 5354 hysteresis = <2000>; 5355 type = "passive"; 5356 }; 5357 5358 cpu0_crit: cpu-crit { 5359 temperature = <110000>; 5360 hysteresis = <1000>; 5361 type = "critical"; 5362 }; 5363 }; 5364 }; 5365 5366 cpu1-thermal { 5367 polling-delay-passive = <250>; 5368 polling-delay = <1000>; 5369 5370 thermal-sensors = <&tsens0 2>; 5371 5372 trips { 5373 cpu1_alert0: trip-point0 { 5374 temperature = <90000>; 5375 hysteresis = <2000>; 5376 type = "passive"; 5377 }; 5378 5379 cpu1_alert1: trip-point1 { 5380 temperature = <95000>; 5381 hysteresis = <2000>; 5382 type = "passive"; 5383 }; 5384 5385 cpu1_crit: cpu-crit { 5386 temperature = <110000>; 5387 hysteresis = <1000>; 5388 type = "critical"; 5389 }; 5390 }; 5391 }; 5392 5393 cpu2-thermal { 5394 polling-delay-passive = <250>; 5395 polling-delay = <1000>; 5396 5397 thermal-sensors = <&tsens0 3>; 5398 5399 trips { 5400 cpu2_alert0: trip-point0 { 5401 temperature = <90000>; 5402 hysteresis = <2000>; 5403 type = "passive"; 5404 }; 5405 5406 cpu2_alert1: trip-point1 { 5407 temperature = <95000>; 5408 hysteresis = <2000>; 5409 type = "passive"; 5410 }; 5411 5412 cpu2_crit: cpu-crit { 5413 temperature = <110000>; 5414 hysteresis = <1000>; 5415 type = "critical"; 5416 }; 5417 }; 5418 }; 5419 5420 cpu3-thermal { 5421 polling-delay-passive = <250>; 5422 polling-delay = <1000>; 5423 5424 thermal-sensors = <&tsens0 4>; 5425 5426 trips { 5427 cpu3_alert0: trip-point0 { 5428 temperature = <90000>; 5429 hysteresis = <2000>; 5430 type = "passive"; 5431 }; 5432 5433 cpu3_alert1: trip-point1 { 5434 temperature = <95000>; 5435 hysteresis = <2000>; 5436 type = "passive"; 5437 }; 5438 5439 cpu3_crit: cpu-crit { 5440 temperature = <110000>; 5441 hysteresis = <1000>; 5442 type = "critical"; 5443 }; 5444 }; 5445 }; 5446 5447 cpu4-thermal { 5448 polling-delay-passive = <250>; 5449 polling-delay = <1000>; 5450 5451 thermal-sensors = <&tsens0 7>; 5452 5453 trips { 5454 cpu4_alert0: trip-point0 { 5455 temperature = <90000>; 5456 hysteresis = <2000>; 5457 type = "passive"; 5458 }; 5459 5460 cpu4_alert1: trip-point1 { 5461 temperature = <95000>; 5462 hysteresis = <2000>; 5463 type = "passive"; 5464 }; 5465 5466 cpu4_crit: cpu-crit { 5467 temperature = <110000>; 5468 hysteresis = <1000>; 5469 type = "critical"; 5470 }; 5471 }; 5472 }; 5473 5474 cpu5-thermal { 5475 polling-delay-passive = <250>; 5476 polling-delay = <1000>; 5477 5478 thermal-sensors = <&tsens0 8>; 5479 5480 trips { 5481 cpu5_alert0: trip-point0 { 5482 temperature = <90000>; 5483 hysteresis = <2000>; 5484 type = "passive"; 5485 }; 5486 5487 cpu5_alert1: trip-point1 { 5488 temperature = <95000>; 5489 hysteresis = <2000>; 5490 type = "passive"; 5491 }; 5492 5493 cpu5_crit: cpu-crit { 5494 temperature = <110000>; 5495 hysteresis = <1000>; 5496 type = "critical"; 5497 }; 5498 }; 5499 }; 5500 5501 cpu6-thermal { 5502 polling-delay-passive = <250>; 5503 polling-delay = <1000>; 5504 5505 thermal-sensors = <&tsens0 9>; 5506 5507 trips { 5508 cpu6_alert0: trip-point0 { 5509 temperature = <90000>; 5510 hysteresis = <2000>; 5511 type = "passive"; 5512 }; 5513 5514 cpu6_alert1: trip-point1 { 5515 temperature = <95000>; 5516 hysteresis = <2000>; 5517 type = "passive"; 5518 }; 5519 5520 cpu6_crit: cpu-crit { 5521 temperature = <110000>; 5522 hysteresis = <1000>; 5523 type = "critical"; 5524 }; 5525 }; 5526 }; 5527 5528 cpu7-thermal { 5529 polling-delay-passive = <250>; 5530 polling-delay = <1000>; 5531 5532 thermal-sensors = <&tsens0 10>; 5533 5534 trips { 5535 cpu7_alert0: trip-point0 { 5536 temperature = <90000>; 5537 hysteresis = <2000>; 5538 type = "passive"; 5539 }; 5540 5541 cpu7_alert1: trip-point1 { 5542 temperature = <95000>; 5543 hysteresis = <2000>; 5544 type = "passive"; 5545 }; 5546 5547 cpu7_crit: cpu-crit { 5548 temperature = <110000>; 5549 hysteresis = <1000>; 5550 type = "critical"; 5551 }; 5552 }; 5553 }; 5554 5555 aoss0-thermal { 5556 polling-delay-passive = <250>; 5557 polling-delay = <1000>; 5558 5559 thermal-sensors = <&tsens0 0>; 5560 5561 trips { 5562 aoss0_alert0: trip-point0 { 5563 temperature = <90000>; 5564 hysteresis = <2000>; 5565 type = "hot"; 5566 }; 5567 }; 5568 }; 5569 5570 cluster0-thermal { 5571 polling-delay-passive = <250>; 5572 polling-delay = <1000>; 5573 5574 thermal-sensors = <&tsens0 5>; 5575 5576 trips { 5577 cluster0_alert0: trip-point0 { 5578 temperature = <90000>; 5579 hysteresis = <2000>; 5580 type = "hot"; 5581 }; 5582 cluster0_crit: cluster0_crit { 5583 temperature = <110000>; 5584 hysteresis = <2000>; 5585 type = "critical"; 5586 }; 5587 }; 5588 }; 5589 5590 cluster1-thermal { 5591 polling-delay-passive = <250>; 5592 polling-delay = <1000>; 5593 5594 thermal-sensors = <&tsens0 6>; 5595 5596 trips { 5597 cluster1_alert0: trip-point0 { 5598 temperature = <90000>; 5599 hysteresis = <2000>; 5600 type = "hot"; 5601 }; 5602 cluster1_crit: cluster1_crit { 5603 temperature = <110000>; 5604 hysteresis = <2000>; 5605 type = "critical"; 5606 }; 5607 }; 5608 }; 5609 5610 gpu-top-thermal { 5611 polling-delay-passive = <250>; 5612 polling-delay = <1000>; 5613 5614 thermal-sensors = <&tsens0 11>; 5615 5616 trips { 5617 gpu1_alert0: trip-point0 { 5618 temperature = <90000>; 5619 hysteresis = <2000>; 5620 type = "hot"; 5621 }; 5622 }; 5623 }; 5624 5625 gpu-bottom-thermal { 5626 polling-delay-passive = <250>; 5627 polling-delay = <1000>; 5628 5629 thermal-sensors = <&tsens0 12>; 5630 5631 trips { 5632 gpu2_alert0: trip-point0 { 5633 temperature = <90000>; 5634 hysteresis = <2000>; 5635 type = "hot"; 5636 }; 5637 }; 5638 }; 5639 5640 aoss1-thermal { 5641 polling-delay-passive = <250>; 5642 polling-delay = <1000>; 5643 5644 thermal-sensors = <&tsens1 0>; 5645 5646 trips { 5647 aoss1_alert0: trip-point0 { 5648 temperature = <90000>; 5649 hysteresis = <2000>; 5650 type = "hot"; 5651 }; 5652 }; 5653 }; 5654 5655 q6-modem-thermal { 5656 polling-delay-passive = <250>; 5657 polling-delay = <1000>; 5658 5659 thermal-sensors = <&tsens1 1>; 5660 5661 trips { 5662 q6_modem_alert0: trip-point0 { 5663 temperature = <90000>; 5664 hysteresis = <2000>; 5665 type = "hot"; 5666 }; 5667 }; 5668 }; 5669 5670 mem-thermal { 5671 polling-delay-passive = <250>; 5672 polling-delay = <1000>; 5673 5674 thermal-sensors = <&tsens1 2>; 5675 5676 trips { 5677 mem_alert0: trip-point0 { 5678 temperature = <90000>; 5679 hysteresis = <2000>; 5680 type = "hot"; 5681 }; 5682 }; 5683 }; 5684 5685 wlan-thermal { 5686 polling-delay-passive = <250>; 5687 polling-delay = <1000>; 5688 5689 thermal-sensors = <&tsens1 3>; 5690 5691 trips { 5692 wlan_alert0: trip-point0 { 5693 temperature = <90000>; 5694 hysteresis = <2000>; 5695 type = "hot"; 5696 }; 5697 }; 5698 }; 5699 5700 q6-hvx-thermal { 5701 polling-delay-passive = <250>; 5702 polling-delay = <1000>; 5703 5704 thermal-sensors = <&tsens1 4>; 5705 5706 trips { 5707 q6_hvx_alert0: trip-point0 { 5708 temperature = <90000>; 5709 hysteresis = <2000>; 5710 type = "hot"; 5711 }; 5712 }; 5713 }; 5714 5715 camera-thermal { 5716 polling-delay-passive = <250>; 5717 polling-delay = <1000>; 5718 5719 thermal-sensors = <&tsens1 5>; 5720 5721 trips { 5722 camera_alert0: trip-point0 { 5723 temperature = <90000>; 5724 hysteresis = <2000>; 5725 type = "hot"; 5726 }; 5727 }; 5728 }; 5729 5730 video-thermal { 5731 polling-delay-passive = <250>; 5732 polling-delay = <1000>; 5733 5734 thermal-sensors = <&tsens1 6>; 5735 5736 trips { 5737 video_alert0: trip-point0 { 5738 temperature = <90000>; 5739 hysteresis = <2000>; 5740 type = "hot"; 5741 }; 5742 }; 5743 }; 5744 5745 modem-thermal { 5746 polling-delay-passive = <250>; 5747 polling-delay = <1000>; 5748 5749 thermal-sensors = <&tsens1 7>; 5750 5751 trips { 5752 modem_alert0: trip-point0 { 5753 temperature = <90000>; 5754 hysteresis = <2000>; 5755 type = "hot"; 5756 }; 5757 }; 5758 }; 5759 }; 5760 5761 timer { 5762 compatible = "arm,armv8-timer"; 5763 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 5764 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 5765 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 5766 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 5767 }; 5768}; 5769