1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ZynqMP Display Controller Driver 4 * 5 * Copyright (C) 2017 - 2020 Xilinx, Inc. 6 * 7 * Authors: 8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com> 9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 */ 11 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_crtc.h> 16 #include <drm/drm_device.h> 17 #include <drm/drm_fb_cma_helper.h> 18 #include <drm/drm_fourcc.h> 19 #include <drm/drm_framebuffer.h> 20 #include <drm/drm_managed.h> 21 #include <drm/drm_plane.h> 22 #include <drm/drm_plane_helper.h> 23 #include <drm/drm_vblank.h> 24 25 #include <linux/clk.h> 26 #include <linux/delay.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmaengine.h> 29 #include <linux/module.h> 30 #include <linux/of.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/spinlock.h> 34 35 #include "zynqmp_disp.h" 36 #include "zynqmp_disp_regs.h" 37 #include "zynqmp_dp.h" 38 #include "zynqmp_dpsub.h" 39 40 /* 41 * Overview 42 * -------- 43 * 44 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video 45 * Buffer Manager, the Video Rendering Pipeline (blender) and the Audio Mixer. 46 * 47 * +------------------------------------------------------------+ 48 * +--------+ | +----------------+ +-----------+ | 49 * | DPDMA | --->| | --> | Video | Video +-------------+ | 50 * | 4x vid | | | | | Rendering | -+--> | | | +------+ 51 * | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 | 52 * +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+ 53 * | | and STC | +-----------+ | | Controller | | +------+ 54 * Live Video --->| | --> | Audio | Audio | |---> | PHY1 | 55 * | | | | Mixer | --+-> | | | +------+ 56 * Live Audio --->| | --> | | || +-------------+ | 57 * | +----------------+ +-----------+ || | 58 * +---------------------------------------||-------------------+ 59 * vv 60 * Blended Video and 61 * Mixed Audio to PL 62 * 63 * Only non-live input from the DPDMA and output to the DisplayPort Source 64 * Controller are currently supported. Interface with the programmable logic 65 * for live streams is not implemented. 66 * 67 * The display controller code creates planes for the DPDMA video and graphics 68 * layers, and a CRTC for the Video Rendering Pipeline. 69 */ 70 71 #define ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS 4 72 #define ZYNQMP_DISP_AV_BUF_NUM_BUFFERS 6 73 74 #define ZYNQMP_DISP_NUM_LAYERS 2 75 #define ZYNQMP_DISP_MAX_NUM_SUB_PLANES 3 76 77 /** 78 * struct zynqmp_disp_format - Display subsystem format information 79 * @drm_fmt: DRM format (4CC) 80 * @buf_fmt: AV buffer format 81 * @bus_fmt: Media bus formats (live formats) 82 * @swap: Flag to swap R & B for RGB formats, and U & V for YUV formats 83 * @sf: Scaling factors for color components 84 */ 85 struct zynqmp_disp_format { 86 u32 drm_fmt; 87 u32 buf_fmt; 88 u32 bus_fmt; 89 bool swap; 90 const u32 *sf; 91 }; 92 93 /** 94 * enum zynqmp_disp_layer_id - Layer identifier 95 * @ZYNQMP_DISP_LAYER_VID: Video layer 96 * @ZYNQMP_DISP_LAYER_GFX: Graphics layer 97 */ 98 enum zynqmp_disp_layer_id { 99 ZYNQMP_DISP_LAYER_VID, 100 ZYNQMP_DISP_LAYER_GFX 101 }; 102 103 /** 104 * enum zynqmp_disp_layer_mode - Layer mode 105 * @ZYNQMP_DISP_LAYER_NONLIVE: non-live (memory) mode 106 * @ZYNQMP_DISP_LAYER_LIVE: live (stream) mode 107 */ 108 enum zynqmp_disp_layer_mode { 109 ZYNQMP_DISP_LAYER_NONLIVE, 110 ZYNQMP_DISP_LAYER_LIVE 111 }; 112 113 /** 114 * struct zynqmp_disp_layer_dma - DMA channel for one data plane of a layer 115 * @chan: DMA channel 116 * @xt: Interleaved DMA descriptor template 117 * @sgl: Data chunk for dma_interleaved_template 118 */ 119 struct zynqmp_disp_layer_dma { 120 struct dma_chan *chan; 121 struct dma_interleaved_template xt; 122 struct data_chunk sgl; 123 }; 124 125 /** 126 * struct zynqmp_disp_layer_info - Static layer information 127 * @formats: Array of supported formats 128 * @num_formats: Number of formats in @formats array 129 * @num_channels: Number of DMA channels 130 */ 131 struct zynqmp_disp_layer_info { 132 const struct zynqmp_disp_format *formats; 133 unsigned int num_formats; 134 unsigned int num_channels; 135 }; 136 137 /** 138 * struct zynqmp_disp_layer - Display layer (DRM plane) 139 * @plane: DRM plane 140 * @id: Layer ID 141 * @disp: Back pointer to struct zynqmp_disp 142 * @info: Static layer information 143 * @dmas: DMA channels 144 * @disp_fmt: Current format information 145 * @drm_fmt: Current DRM format information 146 * @mode: Current operation mode 147 */ 148 struct zynqmp_disp_layer { 149 struct drm_plane plane; 150 enum zynqmp_disp_layer_id id; 151 struct zynqmp_disp *disp; 152 const struct zynqmp_disp_layer_info *info; 153 154 struct zynqmp_disp_layer_dma dmas[ZYNQMP_DISP_MAX_NUM_SUB_PLANES]; 155 156 const struct zynqmp_disp_format *disp_fmt; 157 const struct drm_format_info *drm_fmt; 158 enum zynqmp_disp_layer_mode mode; 159 }; 160 161 /** 162 * struct zynqmp_disp - Display controller 163 * @dev: Device structure 164 * @drm: DRM core 165 * @dpsub: Display subsystem 166 * @crtc: DRM CRTC 167 * @blend.base: Register I/O base address for the blender 168 * @avbuf.base: Register I/O base address for the audio/video buffer manager 169 * @audio.base: Registers I/O base address for the audio mixer 170 * @audio.clk: Audio clock 171 * @audio.clk_from_ps: True of the audio clock comes from PS, false from PL 172 * @layers: Layers (planes) 173 * @event: Pending vblank event request 174 * @pclk: Pixel clock 175 * @pclk_from_ps: True of the video clock comes from PS, false from PL 176 */ 177 struct zynqmp_disp { 178 struct device *dev; 179 struct drm_device *drm; 180 struct zynqmp_dpsub *dpsub; 181 182 struct drm_crtc crtc; 183 184 struct { 185 void __iomem *base; 186 } blend; 187 struct { 188 void __iomem *base; 189 } avbuf; 190 struct { 191 void __iomem *base; 192 struct clk *clk; 193 bool clk_from_ps; 194 } audio; 195 196 struct zynqmp_disp_layer layers[ZYNQMP_DISP_NUM_LAYERS]; 197 198 struct drm_pending_vblank_event *event; 199 200 struct clk *pclk; 201 bool pclk_from_ps; 202 }; 203 204 /* ----------------------------------------------------------------------------- 205 * Audio/Video Buffer Manager 206 */ 207 208 static const u32 scaling_factors_444[] = { 209 ZYNQMP_DISP_AV_BUF_4BIT_SF, 210 ZYNQMP_DISP_AV_BUF_4BIT_SF, 211 ZYNQMP_DISP_AV_BUF_4BIT_SF, 212 }; 213 214 static const u32 scaling_factors_555[] = { 215 ZYNQMP_DISP_AV_BUF_5BIT_SF, 216 ZYNQMP_DISP_AV_BUF_5BIT_SF, 217 ZYNQMP_DISP_AV_BUF_5BIT_SF, 218 }; 219 220 static const u32 scaling_factors_565[] = { 221 ZYNQMP_DISP_AV_BUF_5BIT_SF, 222 ZYNQMP_DISP_AV_BUF_6BIT_SF, 223 ZYNQMP_DISP_AV_BUF_5BIT_SF, 224 }; 225 226 static const u32 scaling_factors_888[] = { 227 ZYNQMP_DISP_AV_BUF_8BIT_SF, 228 ZYNQMP_DISP_AV_BUF_8BIT_SF, 229 ZYNQMP_DISP_AV_BUF_8BIT_SF, 230 }; 231 232 static const u32 scaling_factors_101010[] = { 233 ZYNQMP_DISP_AV_BUF_10BIT_SF, 234 ZYNQMP_DISP_AV_BUF_10BIT_SF, 235 ZYNQMP_DISP_AV_BUF_10BIT_SF, 236 }; 237 238 /* List of video layer formats */ 239 static const struct zynqmp_disp_format avbuf_vid_fmts[] = { 240 { 241 .drm_fmt = DRM_FORMAT_VYUY, 242 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY, 243 .swap = true, 244 .sf = scaling_factors_888, 245 }, { 246 .drm_fmt = DRM_FORMAT_UYVY, 247 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY, 248 .swap = false, 249 .sf = scaling_factors_888, 250 }, { 251 .drm_fmt = DRM_FORMAT_YUYV, 252 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV, 253 .swap = false, 254 .sf = scaling_factors_888, 255 }, { 256 .drm_fmt = DRM_FORMAT_YVYU, 257 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV, 258 .swap = true, 259 .sf = scaling_factors_888, 260 }, { 261 .drm_fmt = DRM_FORMAT_YUV422, 262 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16, 263 .swap = false, 264 .sf = scaling_factors_888, 265 }, { 266 .drm_fmt = DRM_FORMAT_YVU422, 267 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16, 268 .swap = true, 269 .sf = scaling_factors_888, 270 }, { 271 .drm_fmt = DRM_FORMAT_YUV444, 272 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24, 273 .swap = false, 274 .sf = scaling_factors_888, 275 }, { 276 .drm_fmt = DRM_FORMAT_YVU444, 277 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24, 278 .swap = true, 279 .sf = scaling_factors_888, 280 }, { 281 .drm_fmt = DRM_FORMAT_NV16, 282 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI, 283 .swap = false, 284 .sf = scaling_factors_888, 285 }, { 286 .drm_fmt = DRM_FORMAT_NV61, 287 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI, 288 .swap = true, 289 .sf = scaling_factors_888, 290 }, { 291 .drm_fmt = DRM_FORMAT_BGR888, 292 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888, 293 .swap = false, 294 .sf = scaling_factors_888, 295 }, { 296 .drm_fmt = DRM_FORMAT_RGB888, 297 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888, 298 .swap = true, 299 .sf = scaling_factors_888, 300 }, { 301 .drm_fmt = DRM_FORMAT_XBGR8888, 302 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880, 303 .swap = false, 304 .sf = scaling_factors_888, 305 }, { 306 .drm_fmt = DRM_FORMAT_XRGB8888, 307 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880, 308 .swap = true, 309 .sf = scaling_factors_888, 310 }, { 311 .drm_fmt = DRM_FORMAT_XBGR2101010, 312 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10, 313 .swap = false, 314 .sf = scaling_factors_101010, 315 }, { 316 .drm_fmt = DRM_FORMAT_XRGB2101010, 317 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10, 318 .swap = true, 319 .sf = scaling_factors_101010, 320 }, { 321 .drm_fmt = DRM_FORMAT_YUV420, 322 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420, 323 .swap = false, 324 .sf = scaling_factors_888, 325 }, { 326 .drm_fmt = DRM_FORMAT_YVU420, 327 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420, 328 .swap = true, 329 .sf = scaling_factors_888, 330 }, { 331 .drm_fmt = DRM_FORMAT_NV12, 332 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420, 333 .swap = false, 334 .sf = scaling_factors_888, 335 }, { 336 .drm_fmt = DRM_FORMAT_NV21, 337 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420, 338 .swap = true, 339 .sf = scaling_factors_888, 340 }, 341 }; 342 343 /* List of graphics layer formats */ 344 static const struct zynqmp_disp_format avbuf_gfx_fmts[] = { 345 { 346 .drm_fmt = DRM_FORMAT_ABGR8888, 347 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888, 348 .swap = false, 349 .sf = scaling_factors_888, 350 }, { 351 .drm_fmt = DRM_FORMAT_ARGB8888, 352 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888, 353 .swap = true, 354 .sf = scaling_factors_888, 355 }, { 356 .drm_fmt = DRM_FORMAT_RGBA8888, 357 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888, 358 .swap = false, 359 .sf = scaling_factors_888, 360 }, { 361 .drm_fmt = DRM_FORMAT_BGRA8888, 362 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888, 363 .swap = true, 364 .sf = scaling_factors_888, 365 }, { 366 .drm_fmt = DRM_FORMAT_BGR888, 367 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888, 368 .swap = false, 369 .sf = scaling_factors_888, 370 }, { 371 .drm_fmt = DRM_FORMAT_RGB888, 372 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888, 373 .swap = false, 374 .sf = scaling_factors_888, 375 }, { 376 .drm_fmt = DRM_FORMAT_RGBA5551, 377 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551, 378 .swap = false, 379 .sf = scaling_factors_555, 380 }, { 381 .drm_fmt = DRM_FORMAT_BGRA5551, 382 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551, 383 .swap = true, 384 .sf = scaling_factors_555, 385 }, { 386 .drm_fmt = DRM_FORMAT_RGBA4444, 387 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444, 388 .swap = false, 389 .sf = scaling_factors_444, 390 }, { 391 .drm_fmt = DRM_FORMAT_BGRA4444, 392 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444, 393 .swap = true, 394 .sf = scaling_factors_444, 395 }, { 396 .drm_fmt = DRM_FORMAT_RGB565, 397 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565, 398 .swap = false, 399 .sf = scaling_factors_565, 400 }, { 401 .drm_fmt = DRM_FORMAT_BGR565, 402 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565, 403 .swap = true, 404 .sf = scaling_factors_565, 405 }, 406 }; 407 408 static u32 zynqmp_disp_avbuf_read(struct zynqmp_disp *disp, int reg) 409 { 410 return readl(disp->avbuf.base + reg); 411 } 412 413 static void zynqmp_disp_avbuf_write(struct zynqmp_disp *disp, int reg, u32 val) 414 { 415 writel(val, disp->avbuf.base + reg); 416 } 417 418 static bool zynqmp_disp_layer_is_gfx(const struct zynqmp_disp_layer *layer) 419 { 420 return layer->id == ZYNQMP_DISP_LAYER_GFX; 421 } 422 423 static bool zynqmp_disp_layer_is_video(const struct zynqmp_disp_layer *layer) 424 { 425 return layer->id == ZYNQMP_DISP_LAYER_VID; 426 } 427 428 /** 429 * zynqmp_disp_avbuf_set_format - Set the input format for a layer 430 * @disp: Display controller 431 * @layer: The layer 432 * @fmt: The format information 433 * 434 * Set the video buffer manager format for @layer to @fmt. 435 */ 436 static void zynqmp_disp_avbuf_set_format(struct zynqmp_disp *disp, 437 struct zynqmp_disp_layer *layer, 438 const struct zynqmp_disp_format *fmt) 439 { 440 unsigned int i; 441 u32 val; 442 443 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_FMT); 444 val &= zynqmp_disp_layer_is_video(layer) 445 ? ~ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK 446 : ~ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK; 447 val |= fmt->buf_fmt; 448 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_FMT, val); 449 450 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_SF; i++) { 451 unsigned int reg = zynqmp_disp_layer_is_video(layer) 452 ? ZYNQMP_DISP_AV_BUF_VID_COMP_SF(i) 453 : ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(i); 454 455 zynqmp_disp_avbuf_write(disp, reg, fmt->sf[i]); 456 } 457 } 458 459 /** 460 * zynqmp_disp_avbuf_set_clocks_sources - Set the clocks sources 461 * @disp: Display controller 462 * @video_from_ps: True if the video clock originates from the PS 463 * @audio_from_ps: True if the audio clock originates from the PS 464 * @timings_internal: True if video timings are generated internally 465 * 466 * Set the source for the video and audio clocks, as well as for the video 467 * timings. Clocks can originate from the PS or PL, and timings can be 468 * generated internally or externally. 469 */ 470 static void 471 zynqmp_disp_avbuf_set_clocks_sources(struct zynqmp_disp *disp, 472 bool video_from_ps, bool audio_from_ps, 473 bool timings_internal) 474 { 475 u32 val = 0; 476 477 if (video_from_ps) 478 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS; 479 if (audio_from_ps) 480 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS; 481 if (timings_internal) 482 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING; 483 484 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CLK_SRC, val); 485 } 486 487 /** 488 * zynqmp_disp_avbuf_enable_channels - Enable buffer channels 489 * @disp: Display controller 490 * 491 * Enable all (video and audio) buffer channels. 492 */ 493 static void zynqmp_disp_avbuf_enable_channels(struct zynqmp_disp *disp) 494 { 495 unsigned int i; 496 u32 val; 497 498 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN | 499 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX << 500 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT); 501 502 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS; i++) 503 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i), 504 val); 505 506 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN | 507 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX << 508 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT); 509 510 for (; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++) 511 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i), 512 val); 513 } 514 515 /** 516 * zynqmp_disp_avbuf_disable_channels - Disable buffer channels 517 * @disp: Display controller 518 * 519 * Disable all (video and audio) buffer channels. 520 */ 521 static void zynqmp_disp_avbuf_disable_channels(struct zynqmp_disp *disp) 522 { 523 unsigned int i; 524 525 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++) 526 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i), 527 ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH); 528 } 529 530 /** 531 * zynqmp_disp_avbuf_enable_audio - Enable audio 532 * @disp: Display controller 533 * 534 * Enable all audio buffers with a non-live (memory) source. 535 */ 536 static void zynqmp_disp_avbuf_enable_audio(struct zynqmp_disp *disp) 537 { 538 u32 val; 539 540 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT); 541 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK; 542 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM; 543 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN; 544 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 545 } 546 547 /** 548 * zynqmp_disp_avbuf_disable_audio - Disable audio 549 * @disp: Display controller 550 * 551 * Disable all audio buffers. 552 */ 553 static void zynqmp_disp_avbuf_disable_audio(struct zynqmp_disp *disp) 554 { 555 u32 val; 556 557 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT); 558 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK; 559 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE; 560 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN; 561 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 562 } 563 564 /** 565 * zynqmp_disp_avbuf_enable_video - Enable a video layer 566 * @disp: Display controller 567 * @layer: The layer 568 * @mode: Operating mode of layer 569 * 570 * Enable the video/graphics buffer for @layer. 571 */ 572 static void zynqmp_disp_avbuf_enable_video(struct zynqmp_disp *disp, 573 struct zynqmp_disp_layer *layer, 574 enum zynqmp_disp_layer_mode mode) 575 { 576 u32 val; 577 578 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT); 579 if (zynqmp_disp_layer_is_video(layer)) { 580 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK; 581 if (mode == ZYNQMP_DISP_LAYER_NONLIVE) 582 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM; 583 else 584 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE; 585 } else { 586 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK; 587 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM; 588 if (mode == ZYNQMP_DISP_LAYER_NONLIVE) 589 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM; 590 else 591 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE; 592 } 593 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 594 } 595 596 /** 597 * zynqmp_disp_avbuf_disable_video - Disable a video layer 598 * @disp: Display controller 599 * @layer: The layer 600 * 601 * Disable the video/graphics buffer for @layer. 602 */ 603 static void zynqmp_disp_avbuf_disable_video(struct zynqmp_disp *disp, 604 struct zynqmp_disp_layer *layer) 605 { 606 u32 val; 607 608 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT); 609 if (zynqmp_disp_layer_is_video(layer)) { 610 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK; 611 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE; 612 } else { 613 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK; 614 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE; 615 } 616 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 617 } 618 619 /** 620 * zynqmp_disp_avbuf_enable - Enable the video pipe 621 * @disp: Display controller 622 * 623 * De-assert the video pipe reset. 624 */ 625 static void zynqmp_disp_avbuf_enable(struct zynqmp_disp *disp) 626 { 627 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_SRST_REG, 0); 628 } 629 630 /** 631 * zynqmp_disp_avbuf_disable - Disable the video pipe 632 * @disp: Display controller 633 * 634 * Assert the video pipe reset. 635 */ 636 static void zynqmp_disp_avbuf_disable(struct zynqmp_disp *disp) 637 { 638 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_SRST_REG, 639 ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST); 640 } 641 642 /* ----------------------------------------------------------------------------- 643 * Blender (Video Pipeline) 644 */ 645 646 static void zynqmp_disp_blend_write(struct zynqmp_disp *disp, int reg, u32 val) 647 { 648 writel(val, disp->blend.base + reg); 649 } 650 651 /* 652 * Colorspace conversion matrices. 653 * 654 * Hardcode RGB <-> YUV conversion to full-range SDTV for now. 655 */ 656 static const u16 csc_zero_matrix[] = { 657 0x0, 0x0, 0x0, 658 0x0, 0x0, 0x0, 659 0x0, 0x0, 0x0 660 }; 661 662 static const u16 csc_identity_matrix[] = { 663 0x1000, 0x0, 0x0, 664 0x0, 0x1000, 0x0, 665 0x0, 0x0, 0x1000 666 }; 667 668 static const u32 csc_zero_offsets[] = { 669 0, 0, 0 670 }; 671 672 static const u16 csc_rgb_to_sdtv_matrix[] = { 673 0x4c9, 0x864, 0x1d3, 674 0x7d4d, 0x7ab3, 0x800, 675 0x800, 0x794d, 0x7eb3 676 }; 677 678 static const u32 csc_rgb_to_sdtv_offsets[] = { 679 0x0, 0x8000000, 0x8000000 680 }; 681 682 static const u16 csc_sdtv_to_rgb_matrix[] = { 683 0x1000, 0x166f, 0x0, 684 0x1000, 0x7483, 0x7a7f, 685 0x1000, 0x0, 0x1c5a 686 }; 687 688 static const u32 csc_sdtv_to_rgb_offsets[] = { 689 0x0, 0x1800, 0x1800 690 }; 691 692 /** 693 * zynqmp_disp_blend_set_output_format - Set the output format of the blender 694 * @disp: Display controller 695 * @format: Output format 696 * 697 * Set the output format of the blender to @format. 698 */ 699 static void zynqmp_disp_blend_set_output_format(struct zynqmp_disp *disp, 700 enum zynqmp_dpsub_format format) 701 { 702 static const unsigned int blend_output_fmts[] = { 703 [ZYNQMP_DPSUB_FORMAT_RGB] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB, 704 [ZYNQMP_DPSUB_FORMAT_YCRCB444] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444, 705 [ZYNQMP_DPSUB_FORMAT_YCRCB422] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422 706 | ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_EN_DOWNSAMPLE, 707 [ZYNQMP_DPSUB_FORMAT_YONLY] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY, 708 }; 709 710 u32 fmt = blend_output_fmts[format]; 711 const u16 *coeffs; 712 const u32 *offsets; 713 unsigned int i; 714 715 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT, fmt); 716 if (fmt == ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB) { 717 coeffs = csc_identity_matrix; 718 offsets = csc_zero_offsets; 719 } else { 720 coeffs = csc_rgb_to_sdtv_matrix; 721 offsets = csc_rgb_to_sdtv_offsets; 722 } 723 724 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i++) 725 zynqmp_disp_blend_write(disp, 726 ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF(i), 727 coeffs[i]); 728 729 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++) 730 zynqmp_disp_blend_write(disp, 731 ZYNQMP_DISP_V_BLEND_OUTCSC_OFFSET(i), 732 offsets[i]); 733 } 734 735 /** 736 * zynqmp_disp_blend_set_bg_color - Set the background color 737 * @disp: Display controller 738 * @rcr: Red/Cr color component 739 * @gy: Green/Y color component 740 * @bcb: Blue/Cb color component 741 * 742 * Set the background color to (@rcr, @gy, @bcb), corresponding to the R, G and 743 * B or Cr, Y and Cb components respectively depending on the selected output 744 * format. 745 */ 746 static void zynqmp_disp_blend_set_bg_color(struct zynqmp_disp *disp, 747 u32 rcr, u32 gy, u32 bcb) 748 { 749 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_0, rcr); 750 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_1, gy); 751 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_2, bcb); 752 } 753 754 /** 755 * zynqmp_disp_blend_set_global_alpha - Configure global alpha blending 756 * @disp: Display controller 757 * @enable: True to enable global alpha blending 758 * @alpha: Global alpha value (ignored if @enabled is false) 759 */ 760 static void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp, 761 bool enable, u32 alpha) 762 { 763 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA, 764 ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_VALUE(alpha) | 765 (enable ? ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN : 0)); 766 } 767 768 /** 769 * zynqmp_disp_blend_layer_set_csc - Configure colorspace conversion for layer 770 * @disp: Display controller 771 * @layer: The layer 772 * @coeffs: Colorspace conversion matrix 773 * @offsets: Colorspace conversion offsets 774 * 775 * Configure the input colorspace conversion matrix and offsets for the @layer. 776 * Columns of the matrix are automatically swapped based on the input format to 777 * handle RGB and YCrCb components permutations. 778 */ 779 static void zynqmp_disp_blend_layer_set_csc(struct zynqmp_disp *disp, 780 struct zynqmp_disp_layer *layer, 781 const u16 *coeffs, 782 const u32 *offsets) 783 { 784 unsigned int swap[3] = { 0, 1, 2 }; 785 unsigned int reg; 786 unsigned int i; 787 788 if (layer->disp_fmt->swap) { 789 if (layer->drm_fmt->is_yuv) { 790 /* Swap U and V. */ 791 swap[1] = 2; 792 swap[2] = 1; 793 } else { 794 /* Swap R and B. */ 795 swap[0] = 2; 796 swap[2] = 0; 797 } 798 } 799 800 if (zynqmp_disp_layer_is_video(layer)) 801 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(0); 802 else 803 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(0); 804 805 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i += 3, reg += 12) { 806 zynqmp_disp_blend_write(disp, reg + 0, coeffs[i + swap[0]]); 807 zynqmp_disp_blend_write(disp, reg + 4, coeffs[i + swap[1]]); 808 zynqmp_disp_blend_write(disp, reg + 8, coeffs[i + swap[2]]); 809 } 810 811 if (zynqmp_disp_layer_is_video(layer)) 812 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(0); 813 else 814 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(0); 815 816 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++) 817 zynqmp_disp_blend_write(disp, reg + i * 4, offsets[i]); 818 } 819 820 /** 821 * zynqmp_disp_blend_layer_enable - Enable a layer 822 * @disp: Display controller 823 * @layer: The layer 824 */ 825 static void zynqmp_disp_blend_layer_enable(struct zynqmp_disp *disp, 826 struct zynqmp_disp_layer *layer) 827 { 828 const u16 *coeffs; 829 const u32 *offsets; 830 u32 val; 831 832 val = (layer->drm_fmt->is_yuv ? 833 0 : ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB) | 834 (layer->drm_fmt->hsub > 1 ? 835 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US : 0); 836 837 zynqmp_disp_blend_write(disp, 838 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id), 839 val); 840 841 if (layer->drm_fmt->is_yuv) { 842 coeffs = csc_sdtv_to_rgb_matrix; 843 offsets = csc_sdtv_to_rgb_offsets; 844 } else { 845 coeffs = csc_identity_matrix; 846 offsets = csc_zero_offsets; 847 } 848 849 zynqmp_disp_blend_layer_set_csc(disp, layer, coeffs, offsets); 850 } 851 852 /** 853 * zynqmp_disp_blend_layer_disable - Disable a layer 854 * @disp: Display controller 855 * @layer: The layer 856 */ 857 static void zynqmp_disp_blend_layer_disable(struct zynqmp_disp *disp, 858 struct zynqmp_disp_layer *layer) 859 { 860 zynqmp_disp_blend_write(disp, 861 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id), 862 0); 863 864 zynqmp_disp_blend_layer_set_csc(disp, layer, csc_zero_matrix, 865 csc_zero_offsets); 866 } 867 868 /* ----------------------------------------------------------------------------- 869 * Audio Mixer 870 */ 871 872 static void zynqmp_disp_audio_write(struct zynqmp_disp *disp, int reg, u32 val) 873 { 874 writel(val, disp->audio.base + reg); 875 } 876 877 /** 878 * zynqmp_disp_audio_enable - Enable the audio mixer 879 * @disp: Display controller 880 * 881 * Enable the audio mixer by de-asserting the soft reset. The audio state is set to 882 * default values by the reset, set the default mixer volume explicitly. 883 */ 884 static void zynqmp_disp_audio_enable(struct zynqmp_disp *disp) 885 { 886 /* Clear the audio soft reset register as it's an non-reset flop. */ 887 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_SOFT_RESET, 0); 888 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_MIXER_VOLUME, 889 ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE); 890 } 891 892 /** 893 * zynqmp_disp_audio_disable - Disable the audio mixer 894 * @disp: Display controller 895 * 896 * Disable the audio mixer by asserting its soft reset. 897 */ 898 static void zynqmp_disp_audio_disable(struct zynqmp_disp *disp) 899 { 900 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_SOFT_RESET, 901 ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST); 902 } 903 904 static void zynqmp_disp_audio_init(struct zynqmp_disp *disp) 905 { 906 /* Try the live PL audio clock. */ 907 disp->audio.clk = devm_clk_get(disp->dev, "dp_live_audio_aclk"); 908 if (!IS_ERR(disp->audio.clk)) { 909 disp->audio.clk_from_ps = false; 910 return; 911 } 912 913 /* If the live PL audio clock is not valid, fall back to PS clock. */ 914 disp->audio.clk = devm_clk_get(disp->dev, "dp_aud_clk"); 915 if (!IS_ERR(disp->audio.clk)) { 916 disp->audio.clk_from_ps = true; 917 return; 918 } 919 920 dev_err(disp->dev, "audio disabled due to missing clock\n"); 921 } 922 923 /* ----------------------------------------------------------------------------- 924 * ZynqMP Display external functions for zynqmp_dp 925 */ 926 927 /** 928 * zynqmp_disp_handle_vblank - Handle the vblank event 929 * @disp: Display controller 930 * 931 * This function handles the vblank interrupt, and sends an event to 932 * CRTC object. This will be called by the DP vblank interrupt handler. 933 */ 934 void zynqmp_disp_handle_vblank(struct zynqmp_disp *disp) 935 { 936 struct drm_crtc *crtc = &disp->crtc; 937 938 drm_crtc_handle_vblank(crtc); 939 } 940 941 /** 942 * zynqmp_disp_audio_enabled - If the audio is enabled 943 * @disp: Display controller 944 * 945 * Return if the audio is enabled depending on the audio clock. 946 * 947 * Return: true if audio is enabled, or false. 948 */ 949 bool zynqmp_disp_audio_enabled(struct zynqmp_disp *disp) 950 { 951 return !!disp->audio.clk; 952 } 953 954 /** 955 * zynqmp_disp_get_audio_clk_rate - Get the current audio clock rate 956 * @disp: Display controller 957 * 958 * Return: the current audio clock rate. 959 */ 960 unsigned int zynqmp_disp_get_audio_clk_rate(struct zynqmp_disp *disp) 961 { 962 if (zynqmp_disp_audio_enabled(disp)) 963 return 0; 964 return clk_get_rate(disp->audio.clk); 965 } 966 967 /** 968 * zynqmp_disp_get_crtc_mask - Return the CRTC bit mask 969 * @disp: Display controller 970 * 971 * Return: the crtc mask of the zyqnmp_disp CRTC. 972 */ 973 uint32_t zynqmp_disp_get_crtc_mask(struct zynqmp_disp *disp) 974 { 975 return drm_crtc_mask(&disp->crtc); 976 } 977 978 /* ----------------------------------------------------------------------------- 979 * ZynqMP Display Layer & DRM Plane 980 */ 981 982 /** 983 * zynqmp_disp_layer_find_format - Find format information for a DRM format 984 * @layer: The layer 985 * @drm_fmt: DRM format to search 986 * 987 * Search display subsystem format information corresponding to the given DRM 988 * format @drm_fmt for the @layer, and return a pointer to the format 989 * descriptor. 990 * 991 * Return: A pointer to the format descriptor if found, NULL otherwise 992 */ 993 static const struct zynqmp_disp_format * 994 zynqmp_disp_layer_find_format(struct zynqmp_disp_layer *layer, 995 u32 drm_fmt) 996 { 997 unsigned int i; 998 999 for (i = 0; i < layer->info->num_formats; i++) { 1000 if (layer->info->formats[i].drm_fmt == drm_fmt) 1001 return &layer->info->formats[i]; 1002 } 1003 1004 return NULL; 1005 } 1006 1007 /** 1008 * zynqmp_disp_layer_enable - Enable a layer 1009 * @layer: The layer 1010 * 1011 * Enable the @layer in the audio/video buffer manager and the blender. DMA 1012 * channels are started separately by zynqmp_disp_layer_update(). 1013 */ 1014 static void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer) 1015 { 1016 zynqmp_disp_avbuf_enable_video(layer->disp, layer, 1017 ZYNQMP_DISP_LAYER_NONLIVE); 1018 zynqmp_disp_blend_layer_enable(layer->disp, layer); 1019 1020 layer->mode = ZYNQMP_DISP_LAYER_NONLIVE; 1021 } 1022 1023 /** 1024 * zynqmp_disp_layer_disable - Disable the layer 1025 * @layer: The layer 1026 * 1027 * Disable the layer by stopping its DMA channels and disabling it in the 1028 * audio/video buffer manager and the blender. 1029 */ 1030 static void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer) 1031 { 1032 unsigned int i; 1033 1034 for (i = 0; i < layer->drm_fmt->num_planes; i++) 1035 dmaengine_terminate_sync(layer->dmas[i].chan); 1036 1037 zynqmp_disp_avbuf_disable_video(layer->disp, layer); 1038 zynqmp_disp_blend_layer_disable(layer->disp, layer); 1039 } 1040 1041 /** 1042 * zynqmp_disp_layer_set_format - Set the layer format 1043 * @layer: The layer 1044 * @state: The plane state 1045 * 1046 * Set the format for @layer based on @state->fb->format. The layer must be 1047 * disabled. 1048 */ 1049 static void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, 1050 struct drm_plane_state *state) 1051 { 1052 const struct drm_format_info *info = state->fb->format; 1053 unsigned int i; 1054 1055 layer->disp_fmt = zynqmp_disp_layer_find_format(layer, info->format); 1056 layer->drm_fmt = info; 1057 1058 zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt); 1059 1060 /* 1061 * Set slave_id for each DMA channel to indicate they're part of a 1062 * video group. 1063 */ 1064 for (i = 0; i < info->num_planes; i++) { 1065 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1066 struct dma_slave_config config = { 1067 .direction = DMA_MEM_TO_DEV, 1068 .slave_id = 1, 1069 }; 1070 1071 dmaengine_slave_config(dma->chan, &config); 1072 } 1073 } 1074 1075 /** 1076 * zynqmp_disp_layer_update - Update the layer framebuffer 1077 * @layer: The layer 1078 * @state: The plane state 1079 * 1080 * Update the framebuffer for the layer by issuing a new DMA engine transaction 1081 * for the new framebuffer. 1082 * 1083 * Return: 0 on success, or the DMA descriptor failure error otherwise 1084 */ 1085 static int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer, 1086 struct drm_plane_state *state) 1087 { 1088 const struct drm_format_info *info = layer->drm_fmt; 1089 unsigned int i; 1090 1091 for (i = 0; i < layer->drm_fmt->num_planes; i++) { 1092 unsigned int width = state->crtc_w / (i ? info->hsub : 1); 1093 unsigned int height = state->crtc_h / (i ? info->vsub : 1); 1094 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1095 struct dma_async_tx_descriptor *desc; 1096 dma_addr_t paddr; 1097 1098 paddr = drm_fb_cma_get_gem_addr(state->fb, state, i); 1099 1100 dma->xt.numf = height; 1101 dma->sgl.size = width * info->cpp[i]; 1102 dma->sgl.icg = state->fb->pitches[i] - dma->sgl.size; 1103 dma->xt.src_start = paddr; 1104 dma->xt.frame_size = 1; 1105 dma->xt.dir = DMA_MEM_TO_DEV; 1106 dma->xt.src_sgl = true; 1107 dma->xt.dst_sgl = false; 1108 1109 desc = dmaengine_prep_interleaved_dma(dma->chan, &dma->xt, 1110 DMA_CTRL_ACK | 1111 DMA_PREP_REPEAT | 1112 DMA_PREP_LOAD_EOT); 1113 if (!desc) { 1114 dev_err(layer->disp->dev, 1115 "failed to prepare DMA descriptor\n"); 1116 return -ENOMEM; 1117 } 1118 1119 dmaengine_submit(desc); 1120 dma_async_issue_pending(dma->chan); 1121 } 1122 1123 return 0; 1124 } 1125 1126 static inline struct zynqmp_disp_layer *plane_to_layer(struct drm_plane *plane) 1127 { 1128 return container_of(plane, struct zynqmp_disp_layer, plane); 1129 } 1130 1131 static int 1132 zynqmp_disp_plane_atomic_check(struct drm_plane *plane, 1133 struct drm_atomic_state *state) 1134 { 1135 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1136 plane); 1137 struct drm_crtc_state *crtc_state; 1138 1139 if (!new_plane_state->crtc) 1140 return 0; 1141 1142 crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc); 1143 if (IS_ERR(crtc_state)) 1144 return PTR_ERR(crtc_state); 1145 1146 return drm_atomic_helper_check_plane_state(new_plane_state, 1147 crtc_state, 1148 DRM_PLANE_HELPER_NO_SCALING, 1149 DRM_PLANE_HELPER_NO_SCALING, 1150 false, false); 1151 } 1152 1153 static void 1154 zynqmp_disp_plane_atomic_disable(struct drm_plane *plane, 1155 struct drm_atomic_state *state) 1156 { 1157 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 1158 plane); 1159 struct zynqmp_disp_layer *layer = plane_to_layer(plane); 1160 1161 if (!old_state->fb) 1162 return; 1163 1164 zynqmp_disp_layer_disable(layer); 1165 1166 if (zynqmp_disp_layer_is_gfx(layer)) 1167 zynqmp_disp_blend_set_global_alpha(layer->disp, false, 1168 plane->state->alpha >> 8); 1169 } 1170 1171 static void 1172 zynqmp_disp_plane_atomic_update(struct drm_plane *plane, 1173 struct drm_atomic_state *state) 1174 { 1175 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); 1176 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); 1177 struct zynqmp_disp_layer *layer = plane_to_layer(plane); 1178 bool format_changed = false; 1179 1180 if (!old_state->fb || 1181 old_state->fb->format->format != new_state->fb->format->format) 1182 format_changed = true; 1183 1184 /* 1185 * If the format has changed (including going from a previously 1186 * disabled state to any format), reconfigure the format. Disable the 1187 * plane first if needed. 1188 */ 1189 if (format_changed) { 1190 if (old_state->fb) 1191 zynqmp_disp_layer_disable(layer); 1192 1193 zynqmp_disp_layer_set_format(layer, new_state); 1194 } 1195 1196 zynqmp_disp_layer_update(layer, new_state); 1197 1198 if (zynqmp_disp_layer_is_gfx(layer)) 1199 zynqmp_disp_blend_set_global_alpha(layer->disp, true, 1200 plane->state->alpha >> 8); 1201 1202 /* Enable or re-enable the plane is the format has changed. */ 1203 if (format_changed) 1204 zynqmp_disp_layer_enable(layer); 1205 } 1206 1207 static const struct drm_plane_helper_funcs zynqmp_disp_plane_helper_funcs = { 1208 .atomic_check = zynqmp_disp_plane_atomic_check, 1209 .atomic_update = zynqmp_disp_plane_atomic_update, 1210 .atomic_disable = zynqmp_disp_plane_atomic_disable, 1211 }; 1212 1213 static const struct drm_plane_funcs zynqmp_disp_plane_funcs = { 1214 .update_plane = drm_atomic_helper_update_plane, 1215 .disable_plane = drm_atomic_helper_disable_plane, 1216 .destroy = drm_plane_cleanup, 1217 .reset = drm_atomic_helper_plane_reset, 1218 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1219 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1220 }; 1221 1222 static int zynqmp_disp_create_planes(struct zynqmp_disp *disp) 1223 { 1224 unsigned int i, j; 1225 int ret; 1226 1227 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) { 1228 struct zynqmp_disp_layer *layer = &disp->layers[i]; 1229 enum drm_plane_type type; 1230 u32 *drm_formats; 1231 1232 drm_formats = drmm_kcalloc(disp->drm, sizeof(*drm_formats), 1233 layer->info->num_formats, 1234 GFP_KERNEL); 1235 if (!drm_formats) 1236 return -ENOMEM; 1237 1238 for (j = 0; j < layer->info->num_formats; ++j) 1239 drm_formats[j] = layer->info->formats[j].drm_fmt; 1240 1241 /* Graphics layer is primary, and video layer is overlay. */ 1242 type = zynqmp_disp_layer_is_video(layer) 1243 ? DRM_PLANE_TYPE_OVERLAY : DRM_PLANE_TYPE_PRIMARY; 1244 ret = drm_universal_plane_init(disp->drm, &layer->plane, 0, 1245 &zynqmp_disp_plane_funcs, 1246 drm_formats, 1247 layer->info->num_formats, 1248 NULL, type, NULL); 1249 if (ret) 1250 return ret; 1251 1252 drm_plane_helper_add(&layer->plane, 1253 &zynqmp_disp_plane_helper_funcs); 1254 1255 drm_plane_create_zpos_immutable_property(&layer->plane, i); 1256 if (zynqmp_disp_layer_is_gfx(layer)) 1257 drm_plane_create_alpha_property(&layer->plane); 1258 } 1259 1260 return 0; 1261 } 1262 1263 /** 1264 * zynqmp_disp_layer_release_dma - Release DMA channels for a layer 1265 * @disp: Display controller 1266 * @layer: The layer 1267 * 1268 * Release the DMA channels associated with @layer. 1269 */ 1270 static void zynqmp_disp_layer_release_dma(struct zynqmp_disp *disp, 1271 struct zynqmp_disp_layer *layer) 1272 { 1273 unsigned int i; 1274 1275 if (!layer->info) 1276 return; 1277 1278 for (i = 0; i < layer->info->num_channels; i++) { 1279 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1280 1281 if (!dma->chan) 1282 continue; 1283 1284 /* Make sure the channel is terminated before release. */ 1285 dmaengine_terminate_sync(dma->chan); 1286 dma_release_channel(dma->chan); 1287 } 1288 } 1289 1290 /** 1291 * zynqmp_disp_destroy_layers - Destroy all layers 1292 * @disp: Display controller 1293 */ 1294 static void zynqmp_disp_destroy_layers(struct zynqmp_disp *disp) 1295 { 1296 unsigned int i; 1297 1298 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) 1299 zynqmp_disp_layer_release_dma(disp, &disp->layers[i]); 1300 } 1301 1302 /** 1303 * zynqmp_disp_layer_request_dma - Request DMA channels for a layer 1304 * @disp: Display controller 1305 * @layer: The layer 1306 * 1307 * Request all DMA engine channels needed by @layer. 1308 * 1309 * Return: 0 on success, or the DMA channel request error otherwise 1310 */ 1311 static int zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp, 1312 struct zynqmp_disp_layer *layer) 1313 { 1314 static const char * const dma_names[] = { "vid", "gfx" }; 1315 unsigned int i; 1316 int ret; 1317 1318 for (i = 0; i < layer->info->num_channels; i++) { 1319 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1320 char dma_channel_name[16]; 1321 1322 snprintf(dma_channel_name, sizeof(dma_channel_name), 1323 "%s%u", dma_names[layer->id], i); 1324 dma->chan = dma_request_chan(disp->dev, dma_channel_name); 1325 if (IS_ERR(dma->chan)) { 1326 dev_err(disp->dev, "failed to request dma channel\n"); 1327 ret = PTR_ERR(dma->chan); 1328 dma->chan = NULL; 1329 return ret; 1330 } 1331 } 1332 1333 return 0; 1334 } 1335 1336 /** 1337 * zynqmp_disp_create_layers - Create and initialize all layers 1338 * @disp: Display controller 1339 * 1340 * Return: 0 on success, or the DMA channel request error otherwise 1341 */ 1342 static int zynqmp_disp_create_layers(struct zynqmp_disp *disp) 1343 { 1344 static const struct zynqmp_disp_layer_info layer_info[] = { 1345 [ZYNQMP_DISP_LAYER_VID] = { 1346 .formats = avbuf_vid_fmts, 1347 .num_formats = ARRAY_SIZE(avbuf_vid_fmts), 1348 .num_channels = 3, 1349 }, 1350 [ZYNQMP_DISP_LAYER_GFX] = { 1351 .formats = avbuf_gfx_fmts, 1352 .num_formats = ARRAY_SIZE(avbuf_gfx_fmts), 1353 .num_channels = 1, 1354 }, 1355 }; 1356 1357 unsigned int i; 1358 int ret; 1359 1360 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) { 1361 struct zynqmp_disp_layer *layer = &disp->layers[i]; 1362 1363 layer->id = i; 1364 layer->disp = disp; 1365 layer->info = &layer_info[i]; 1366 1367 ret = zynqmp_disp_layer_request_dma(disp, layer); 1368 if (ret) 1369 goto err; 1370 } 1371 1372 return 0; 1373 1374 err: 1375 zynqmp_disp_destroy_layers(disp); 1376 return ret; 1377 } 1378 1379 /* ----------------------------------------------------------------------------- 1380 * ZynqMP Display & DRM CRTC 1381 */ 1382 1383 /** 1384 * zynqmp_disp_enable - Enable the display controller 1385 * @disp: Display controller 1386 */ 1387 static void zynqmp_disp_enable(struct zynqmp_disp *disp) 1388 { 1389 zynqmp_disp_avbuf_enable(disp); 1390 /* Choose clock source based on the DT clock handle. */ 1391 zynqmp_disp_avbuf_set_clocks_sources(disp, disp->pclk_from_ps, 1392 disp->audio.clk_from_ps, true); 1393 zynqmp_disp_avbuf_enable_channels(disp); 1394 zynqmp_disp_avbuf_enable_audio(disp); 1395 1396 zynqmp_disp_audio_enable(disp); 1397 } 1398 1399 /** 1400 * zynqmp_disp_disable - Disable the display controller 1401 * @disp: Display controller 1402 */ 1403 static void zynqmp_disp_disable(struct zynqmp_disp *disp) 1404 { 1405 zynqmp_disp_audio_disable(disp); 1406 1407 zynqmp_disp_avbuf_disable_audio(disp); 1408 zynqmp_disp_avbuf_disable_channels(disp); 1409 zynqmp_disp_avbuf_disable(disp); 1410 } 1411 1412 static inline struct zynqmp_disp *crtc_to_disp(struct drm_crtc *crtc) 1413 { 1414 return container_of(crtc, struct zynqmp_disp, crtc); 1415 } 1416 1417 static int zynqmp_disp_crtc_setup_clock(struct drm_crtc *crtc, 1418 struct drm_display_mode *adjusted_mode) 1419 { 1420 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1421 unsigned long mode_clock = adjusted_mode->clock * 1000; 1422 unsigned long rate; 1423 long diff; 1424 int ret; 1425 1426 ret = clk_set_rate(disp->pclk, mode_clock); 1427 if (ret) { 1428 dev_err(disp->dev, "failed to set a pixel clock\n"); 1429 return ret; 1430 } 1431 1432 rate = clk_get_rate(disp->pclk); 1433 diff = rate - mode_clock; 1434 if (abs(diff) > mode_clock / 20) 1435 dev_info(disp->dev, 1436 "requested pixel rate: %lu actual rate: %lu\n", 1437 mode_clock, rate); 1438 else 1439 dev_dbg(disp->dev, 1440 "requested pixel rate: %lu actual rate: %lu\n", 1441 mode_clock, rate); 1442 1443 return 0; 1444 } 1445 1446 static void 1447 zynqmp_disp_crtc_atomic_enable(struct drm_crtc *crtc, 1448 struct drm_atomic_state *state) 1449 { 1450 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1451 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1452 int ret, vrefresh; 1453 1454 pm_runtime_get_sync(disp->dev); 1455 1456 zynqmp_disp_crtc_setup_clock(crtc, adjusted_mode); 1457 1458 ret = clk_prepare_enable(disp->pclk); 1459 if (ret) { 1460 dev_err(disp->dev, "failed to enable a pixel clock\n"); 1461 pm_runtime_put_sync(disp->dev); 1462 return; 1463 } 1464 1465 zynqmp_disp_blend_set_output_format(disp, ZYNQMP_DPSUB_FORMAT_RGB); 1466 zynqmp_disp_blend_set_bg_color(disp, 0, 0, 0); 1467 1468 zynqmp_disp_enable(disp); 1469 1470 /* Delay of 3 vblank intervals for timing gen to be stable */ 1471 vrefresh = (adjusted_mode->clock * 1000) / 1472 (adjusted_mode->vtotal * adjusted_mode->htotal); 1473 msleep(3 * 1000 / vrefresh); 1474 } 1475 1476 static void 1477 zynqmp_disp_crtc_atomic_disable(struct drm_crtc *crtc, 1478 struct drm_atomic_state *state) 1479 { 1480 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1481 struct drm_plane_state *old_plane_state; 1482 1483 /* 1484 * Disable the plane if active. The old plane state can be NULL in the 1485 * .shutdown() path if the plane is already disabled, skip 1486 * zynqmp_disp_plane_atomic_disable() in that case. 1487 */ 1488 old_plane_state = drm_atomic_get_old_plane_state(state, crtc->primary); 1489 if (old_plane_state) 1490 zynqmp_disp_plane_atomic_disable(crtc->primary, state); 1491 1492 zynqmp_disp_disable(disp); 1493 1494 drm_crtc_vblank_off(&disp->crtc); 1495 1496 spin_lock_irq(&crtc->dev->event_lock); 1497 if (crtc->state->event) { 1498 drm_crtc_send_vblank_event(crtc, crtc->state->event); 1499 crtc->state->event = NULL; 1500 } 1501 spin_unlock_irq(&crtc->dev->event_lock); 1502 1503 clk_disable_unprepare(disp->pclk); 1504 pm_runtime_put_sync(disp->dev); 1505 } 1506 1507 static int zynqmp_disp_crtc_atomic_check(struct drm_crtc *crtc, 1508 struct drm_atomic_state *state) 1509 { 1510 return drm_atomic_add_affected_planes(state, crtc); 1511 } 1512 1513 static void 1514 zynqmp_disp_crtc_atomic_begin(struct drm_crtc *crtc, 1515 struct drm_atomic_state *state) 1516 { 1517 drm_crtc_vblank_on(crtc); 1518 } 1519 1520 static void 1521 zynqmp_disp_crtc_atomic_flush(struct drm_crtc *crtc, 1522 struct drm_atomic_state *state) 1523 { 1524 if (crtc->state->event) { 1525 struct drm_pending_vblank_event *event; 1526 1527 /* Consume the flip_done event from atomic helper. */ 1528 event = crtc->state->event; 1529 crtc->state->event = NULL; 1530 1531 event->pipe = drm_crtc_index(crtc); 1532 1533 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1534 1535 spin_lock_irq(&crtc->dev->event_lock); 1536 drm_crtc_arm_vblank_event(crtc, event); 1537 spin_unlock_irq(&crtc->dev->event_lock); 1538 } 1539 } 1540 1541 static const struct drm_crtc_helper_funcs zynqmp_disp_crtc_helper_funcs = { 1542 .atomic_enable = zynqmp_disp_crtc_atomic_enable, 1543 .atomic_disable = zynqmp_disp_crtc_atomic_disable, 1544 .atomic_check = zynqmp_disp_crtc_atomic_check, 1545 .atomic_begin = zynqmp_disp_crtc_atomic_begin, 1546 .atomic_flush = zynqmp_disp_crtc_atomic_flush, 1547 }; 1548 1549 static int zynqmp_disp_crtc_enable_vblank(struct drm_crtc *crtc) 1550 { 1551 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1552 1553 zynqmp_dp_enable_vblank(disp->dpsub->dp); 1554 1555 return 0; 1556 } 1557 1558 static void zynqmp_disp_crtc_disable_vblank(struct drm_crtc *crtc) 1559 { 1560 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1561 1562 zynqmp_dp_disable_vblank(disp->dpsub->dp); 1563 } 1564 1565 static const struct drm_crtc_funcs zynqmp_disp_crtc_funcs = { 1566 .destroy = drm_crtc_cleanup, 1567 .set_config = drm_atomic_helper_set_config, 1568 .page_flip = drm_atomic_helper_page_flip, 1569 .reset = drm_atomic_helper_crtc_reset, 1570 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 1571 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 1572 .enable_vblank = zynqmp_disp_crtc_enable_vblank, 1573 .disable_vblank = zynqmp_disp_crtc_disable_vblank, 1574 }; 1575 1576 static int zynqmp_disp_create_crtc(struct zynqmp_disp *disp) 1577 { 1578 struct drm_plane *plane = &disp->layers[ZYNQMP_DISP_LAYER_GFX].plane; 1579 int ret; 1580 1581 ret = drm_crtc_init_with_planes(disp->drm, &disp->crtc, plane, 1582 NULL, &zynqmp_disp_crtc_funcs, NULL); 1583 if (ret < 0) 1584 return ret; 1585 1586 drm_crtc_helper_add(&disp->crtc, &zynqmp_disp_crtc_helper_funcs); 1587 1588 /* Start with vertical blanking interrupt reporting disabled. */ 1589 drm_crtc_vblank_off(&disp->crtc); 1590 1591 return 0; 1592 } 1593 1594 static void zynqmp_disp_map_crtc_to_plane(struct zynqmp_disp *disp) 1595 { 1596 u32 possible_crtcs = drm_crtc_mask(&disp->crtc); 1597 unsigned int i; 1598 1599 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) 1600 disp->layers[i].plane.possible_crtcs = possible_crtcs; 1601 } 1602 1603 /* ----------------------------------------------------------------------------- 1604 * Initialization & Cleanup 1605 */ 1606 1607 int zynqmp_disp_drm_init(struct zynqmp_dpsub *dpsub) 1608 { 1609 struct zynqmp_disp *disp = dpsub->disp; 1610 int ret; 1611 1612 ret = zynqmp_disp_create_planes(disp); 1613 if (ret) 1614 return ret; 1615 1616 ret = zynqmp_disp_create_crtc(disp); 1617 if (ret < 0) 1618 return ret; 1619 1620 zynqmp_disp_map_crtc_to_plane(disp); 1621 1622 return 0; 1623 } 1624 1625 int zynqmp_disp_probe(struct zynqmp_dpsub *dpsub, struct drm_device *drm) 1626 { 1627 struct platform_device *pdev = to_platform_device(dpsub->dev); 1628 struct zynqmp_disp *disp; 1629 struct zynqmp_disp_layer *layer; 1630 struct resource *res; 1631 int ret; 1632 1633 disp = drmm_kzalloc(drm, sizeof(*disp), GFP_KERNEL); 1634 if (!disp) 1635 return -ENOMEM; 1636 1637 disp->dev = &pdev->dev; 1638 disp->dpsub = dpsub; 1639 disp->drm = drm; 1640 1641 dpsub->disp = disp; 1642 1643 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "blend"); 1644 disp->blend.base = devm_ioremap_resource(disp->dev, res); 1645 if (IS_ERR(disp->blend.base)) 1646 return PTR_ERR(disp->blend.base); 1647 1648 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "av_buf"); 1649 disp->avbuf.base = devm_ioremap_resource(disp->dev, res); 1650 if (IS_ERR(disp->avbuf.base)) 1651 return PTR_ERR(disp->avbuf.base); 1652 1653 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aud"); 1654 disp->audio.base = devm_ioremap_resource(disp->dev, res); 1655 if (IS_ERR(disp->audio.base)) 1656 return PTR_ERR(disp->audio.base); 1657 1658 /* Try the live PL video clock */ 1659 disp->pclk = devm_clk_get(disp->dev, "dp_live_video_in_clk"); 1660 if (!IS_ERR(disp->pclk)) 1661 disp->pclk_from_ps = false; 1662 else if (PTR_ERR(disp->pclk) == -EPROBE_DEFER) 1663 return PTR_ERR(disp->pclk); 1664 1665 /* If the live PL video clock is not valid, fall back to PS clock */ 1666 if (IS_ERR_OR_NULL(disp->pclk)) { 1667 disp->pclk = devm_clk_get(disp->dev, "dp_vtc_pixel_clk_in"); 1668 if (IS_ERR(disp->pclk)) { 1669 dev_err(disp->dev, "failed to init any video clock\n"); 1670 return PTR_ERR(disp->pclk); 1671 } 1672 disp->pclk_from_ps = true; 1673 } 1674 1675 zynqmp_disp_audio_init(disp); 1676 1677 ret = zynqmp_disp_create_layers(disp); 1678 if (ret) 1679 return ret; 1680 1681 layer = &disp->layers[ZYNQMP_DISP_LAYER_VID]; 1682 dpsub->dma_align = 1 << layer->dmas[0].chan->device->copy_align; 1683 1684 return 0; 1685 } 1686 1687 void zynqmp_disp_remove(struct zynqmp_dpsub *dpsub) 1688 { 1689 struct zynqmp_disp *disp = dpsub->disp; 1690 1691 zynqmp_disp_destroy_layers(disp); 1692 } 1693