1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/sysfs.h> 71 #include <linux/types.h> 72 #include <linux/minmax.h> 73 #include <linux/mm.h> 74 #include <linux/cpu.h> 75 #include <linux/kasan.h> 76 #include <linux/percpu.h> 77 78 #include <asm/cpu.h> 79 #include <asm/cpufeature.h> 80 #include <asm/cpu_ops.h> 81 #include <asm/fpsimd.h> 82 #include <asm/hwcap.h> 83 #include <asm/insn.h> 84 #include <asm/kvm_host.h> 85 #include <asm/mmu_context.h> 86 #include <asm/mte.h> 87 #include <asm/processor.h> 88 #include <asm/smp.h> 89 #include <asm/sysreg.h> 90 #include <asm/traps.h> 91 #include <asm/vectors.h> 92 #include <asm/virt.h> 93 94 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 95 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 96 97 #ifdef CONFIG_COMPAT 98 #define COMPAT_ELF_HWCAP_DEFAULT \ 99 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 100 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 101 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 102 COMPAT_HWCAP_LPAE) 103 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 104 unsigned int compat_elf_hwcap2 __read_mostly; 105 #endif 106 107 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 108 EXPORT_SYMBOL(cpu_hwcaps); 109 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 110 111 /* Need also bit for ARM64_CB_PATCH */ 112 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 113 114 bool arm64_use_ng_mappings = false; 115 EXPORT_SYMBOL(arm64_use_ng_mappings); 116 117 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 118 119 /* 120 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 121 * support it? 122 */ 123 static bool __read_mostly allow_mismatched_32bit_el0; 124 125 /* 126 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 127 * seen at least one CPU capable of 32-bit EL0. 128 */ 129 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 130 131 /* 132 * Mask of CPUs supporting 32-bit EL0. 133 * Only valid if arm64_mismatched_32bit_el0 is enabled. 134 */ 135 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 136 137 /* 138 * Flag to indicate if we have computed the system wide 139 * capabilities based on the boot time active CPUs. This 140 * will be used to determine if a new booting CPU should 141 * go through the verification process to make sure that it 142 * supports the system capabilities, without using a hotplug 143 * notifier. This is also used to decide if we could use 144 * the fast path for checking constant CPU caps. 145 */ 146 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 147 EXPORT_SYMBOL(arm64_const_caps_ready); 148 static inline void finalize_system_capabilities(void) 149 { 150 static_branch_enable(&arm64_const_caps_ready); 151 } 152 153 void dump_cpu_features(void) 154 { 155 /* file-wide pr_fmt adds "CPU features: " prefix */ 156 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 157 } 158 159 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 160 EXPORT_SYMBOL(cpu_hwcap_keys); 161 162 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 163 { \ 164 .sign = SIGNED, \ 165 .visible = VISIBLE, \ 166 .strict = STRICT, \ 167 .type = TYPE, \ 168 .shift = SHIFT, \ 169 .width = WIDTH, \ 170 .safe_val = SAFE_VAL, \ 171 } 172 173 /* Define a feature with unsigned values */ 174 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 175 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 176 177 /* Define a feature with a signed value */ 178 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 179 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 180 181 #define ARM64_FTR_END \ 182 { \ 183 .width = 0, \ 184 } 185 186 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 187 188 static bool __system_matches_cap(unsigned int n); 189 190 /* 191 * NOTE: Any changes to the visibility of features should be kept in 192 * sync with the documentation of the CPU feature register ABI. 193 */ 194 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 208 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 209 ARM64_FTR_END, 210 }; 211 212 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 219 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 220 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 222 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 227 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 229 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 231 ARM64_FTR_END, 232 }; 233 234 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 237 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 239 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 242 ARM64_FTR_END, 243 }; 244 245 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 256 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 257 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY), 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY), 262 ARM64_FTR_END, 263 }; 264 265 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 266 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 267 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SME_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), 269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 271 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI), 272 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 273 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 274 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), 275 ARM64_FTR_END, 276 }; 277 278 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 279 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 280 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 282 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 284 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 285 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 286 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 288 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 290 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 292 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 293 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 294 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 296 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 297 ARM64_FTR_END, 298 }; 299 300 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 301 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 302 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 303 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 304 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 305 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 306 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 307 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 308 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 309 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 310 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 311 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 312 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 313 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 314 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 315 ARM64_FTR_END, 316 }; 317 318 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 319 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), 322 /* 323 * Page size not being supported at Stage-2 is not fatal. You 324 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 325 * your favourite nesting hypervisor. 326 * 327 * There is a small corner case where the hypervisor explicitly 328 * advertises a given granule size at Stage-2 (value 2) on some 329 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 330 * vCPUs. Although this is not forbidden by the architecture, it 331 * indicates that the hypervisor is being silly (or buggy). 332 * 333 * We make no effort to cope with this and pretend that if these 334 * fields are inconsistent across vCPUs, then it isn't worth 335 * trying to bring KVM up. 336 */ 337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1), 338 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1), 339 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1), 340 /* 341 * We already refuse to boot CPUs that don't support our configured 342 * page size, so we can only detect mismatches for a page size other 343 * than the one we're currently using. Unfortunately, SoCs like this 344 * exist in the wild so, even though we don't like it, we'll have to go 345 * along with it and treat them as non-strict. 346 */ 347 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 348 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 350 351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 352 /* Linux shouldn't care about secure memory */ 353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 356 /* 357 * Differing PARange is fine as long as all peripherals and memory are mapped 358 * within the minimum PARange of all CPUs 359 */ 360 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 361 ARM64_FTR_END, 362 }; 363 364 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TIDCP1_SHIFT, 4, 0), 366 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), 369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), 370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), 371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 377 ARM64_FTR_END, 378 }; 379 380 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 381 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0), 382 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0), 383 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0), 384 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0), 385 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0), 387 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0), 389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0), 390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0), 391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 394 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 395 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 396 ARM64_FTR_END, 397 }; 398 399 static const struct arm64_ftr_bits ftr_ctr[] = { 400 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 401 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 402 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 403 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 404 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 405 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 406 /* 407 * Linux can handle differing I-cache policies. Userspace JITs will 408 * make use of *minLine. 409 * If we have differing I-cache policies, report it as the weakest - VIPT. 410 */ 411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 412 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 413 ARM64_FTR_END, 414 }; 415 416 static struct arm64_ftr_override __ro_after_init no_override = { }; 417 418 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 419 .name = "SYS_CTR_EL0", 420 .ftr_bits = ftr_ctr, 421 .override = &no_override, 422 }; 423 424 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 425 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0), 427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0), 428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0), 429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0), 430 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf), 431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0), 432 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0), 433 ARM64_FTR_END, 434 }; 435 436 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 437 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0), 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 442 /* 443 * We can instantiate multiple PMU instances with different levels 444 * of support. 445 */ 446 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 448 ARM64_FTR_END, 449 }; 450 451 static const struct arm64_ftr_bits ftr_mvfr2[] = { 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), 453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), 454 ARM64_FTR_END, 455 }; 456 457 static const struct arm64_ftr_bits ftr_dczid[] = { 458 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 459 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 460 ARM64_FTR_END, 461 }; 462 463 static const struct arm64_ftr_bits ftr_gmid[] = { 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 465 ARM64_FTR_END, 466 }; 467 468 static const struct arm64_ftr_bits ftr_id_isar0[] = { 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 476 ARM64_FTR_END, 477 }; 478 479 static const struct arm64_ftr_bits ftr_id_isar5[] = { 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 486 ARM64_FTR_END, 487 }; 488 489 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0), 497 498 /* 499 * SpecSEI = 1 indicates that the PE might generate an SError on an 500 * external abort on speculative read. It is safe to assume that an 501 * SError might be generated than it will not be. Hence it has been 502 * classified as FTR_HIGHER_SAFE. 503 */ 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 505 ARM64_FTR_END, 506 }; 507 508 static const struct arm64_ftr_bits ftr_id_isar4[] = { 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 516 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 517 ARM64_FTR_END, 518 }; 519 520 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 522 ARM64_FTR_END, 523 }; 524 525 static const struct arm64_ftr_bits ftr_id_isar6[] = { 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 533 ARM64_FTR_END, 534 }; 535 536 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 537 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), 540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), 541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), 543 ARM64_FTR_END, 544 }; 545 546 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 551 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 552 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 554 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 555 ARM64_FTR_END, 556 }; 557 558 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 561 ARM64_FTR_END, 562 }; 563 564 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 565 /* [31:28] TraceFilt */ 566 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_PERFMON_SHIFT, 4, 0), 567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0), 568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0), 569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0), 570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0), 571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0), 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0), 573 ARM64_FTR_END, 574 }; 575 576 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 577 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 578 ARM64_FTR_END, 579 }; 580 581 static const struct arm64_ftr_bits ftr_zcr[] = { 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 583 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_WIDTH, 0), /* LEN */ 584 ARM64_FTR_END, 585 }; 586 587 static const struct arm64_ftr_bits ftr_smcr[] = { 588 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 589 SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0), /* LEN */ 590 ARM64_FTR_END, 591 }; 592 593 /* 594 * Common ftr bits for a 32bit register with all hidden, strict 595 * attributes, with 4bit feature fields and a default safe value of 596 * 0. Covers the following 32bit registers: 597 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 598 */ 599 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 604 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 605 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 607 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 608 ARM64_FTR_END, 609 }; 610 611 /* Table for a single 32bit feature value */ 612 static const struct arm64_ftr_bits ftr_single32[] = { 613 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 614 ARM64_FTR_END, 615 }; 616 617 static const struct arm64_ftr_bits ftr_raz[] = { 618 ARM64_FTR_END, 619 }; 620 621 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 622 .sys_id = id, \ 623 .reg = &(struct arm64_ftr_reg){ \ 624 .name = id_str, \ 625 .override = (ovr), \ 626 .ftr_bits = &((table)[0]), \ 627 }} 628 629 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 630 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 631 632 #define ARM64_FTR_REG(id, table) \ 633 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 634 635 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 636 struct arm64_ftr_override __ro_after_init id_aa64pfr0_override; 637 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 638 struct arm64_ftr_override __ro_after_init id_aa64zfr0_override; 639 struct arm64_ftr_override __ro_after_init id_aa64smfr0_override; 640 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 641 struct arm64_ftr_override __ro_after_init id_aa64isar2_override; 642 643 static const struct __ftr_reg_entry { 644 u32 sys_id; 645 struct arm64_ftr_reg *reg; 646 } arm64_ftr_regs[] = { 647 648 /* Op1 = 0, CRn = 0, CRm = 1 */ 649 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 650 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 651 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 652 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 653 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 654 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 655 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 656 657 /* Op1 = 0, CRn = 0, CRm = 2 */ 658 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 659 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 660 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 661 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 662 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 663 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 664 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 665 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 666 667 /* Op1 = 0, CRn = 0, CRm = 3 */ 668 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 669 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 670 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 671 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 672 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 673 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 674 675 /* Op1 = 0, CRn = 0, CRm = 4 */ 676 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 677 &id_aa64pfr0_override), 678 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 679 &id_aa64pfr1_override), 680 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 681 &id_aa64zfr0_override), 682 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 683 &id_aa64smfr0_override), 684 685 /* Op1 = 0, CRn = 0, CRm = 5 */ 686 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 687 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 688 689 /* Op1 = 0, CRn = 0, CRm = 6 */ 690 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 691 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 692 &id_aa64isar1_override), 693 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 694 &id_aa64isar2_override), 695 696 /* Op1 = 0, CRn = 0, CRm = 7 */ 697 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 698 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 699 &id_aa64mmfr1_override), 700 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 701 702 /* Op1 = 0, CRn = 1, CRm = 2 */ 703 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 704 ARM64_FTR_REG(SYS_SMCR_EL1, ftr_smcr), 705 706 /* Op1 = 1, CRn = 0, CRm = 0 */ 707 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 708 709 /* Op1 = 3, CRn = 0, CRm = 0 */ 710 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 711 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 712 713 /* Op1 = 3, CRn = 14, CRm = 0 */ 714 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 715 }; 716 717 static int search_cmp_ftr_reg(const void *id, const void *regp) 718 { 719 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 720 } 721 722 /* 723 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 724 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 725 * ascending order of sys_id, we use binary search to find a matching 726 * entry. 727 * 728 * returns - Upon success, matching ftr_reg entry for id. 729 * - NULL on failure. It is upto the caller to decide 730 * the impact of a failure. 731 */ 732 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 733 { 734 const struct __ftr_reg_entry *ret; 735 736 ret = bsearch((const void *)(unsigned long)sys_id, 737 arm64_ftr_regs, 738 ARRAY_SIZE(arm64_ftr_regs), 739 sizeof(arm64_ftr_regs[0]), 740 search_cmp_ftr_reg); 741 if (ret) 742 return ret->reg; 743 return NULL; 744 } 745 746 /* 747 * get_arm64_ftr_reg - Looks up a feature register entry using 748 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 749 * 750 * returns - Upon success, matching ftr_reg entry for id. 751 * - NULL on failure but with an WARN_ON(). 752 */ 753 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 754 { 755 struct arm64_ftr_reg *reg; 756 757 reg = get_arm64_ftr_reg_nowarn(sys_id); 758 759 /* 760 * Requesting a non-existent register search is an error. Warn 761 * and let the caller handle it. 762 */ 763 WARN_ON(!reg); 764 return reg; 765 } 766 767 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 768 s64 ftr_val) 769 { 770 u64 mask = arm64_ftr_mask(ftrp); 771 772 reg &= ~mask; 773 reg |= (ftr_val << ftrp->shift) & mask; 774 return reg; 775 } 776 777 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 778 s64 cur) 779 { 780 s64 ret = 0; 781 782 switch (ftrp->type) { 783 case FTR_EXACT: 784 ret = ftrp->safe_val; 785 break; 786 case FTR_LOWER_SAFE: 787 ret = min(new, cur); 788 break; 789 case FTR_HIGHER_OR_ZERO_SAFE: 790 if (!cur || !new) 791 break; 792 fallthrough; 793 case FTR_HIGHER_SAFE: 794 ret = max(new, cur); 795 break; 796 default: 797 BUG(); 798 } 799 800 return ret; 801 } 802 803 static void __init sort_ftr_regs(void) 804 { 805 unsigned int i; 806 807 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 808 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 809 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 810 unsigned int j = 0; 811 812 /* 813 * Features here must be sorted in descending order with respect 814 * to their shift values and should not overlap with each other. 815 */ 816 for (; ftr_bits->width != 0; ftr_bits++, j++) { 817 unsigned int width = ftr_reg->ftr_bits[j].width; 818 unsigned int shift = ftr_reg->ftr_bits[j].shift; 819 unsigned int prev_shift; 820 821 WARN((shift + width) > 64, 822 "%s has invalid feature at shift %d\n", 823 ftr_reg->name, shift); 824 825 /* 826 * Skip the first feature. There is nothing to 827 * compare against for now. 828 */ 829 if (j == 0) 830 continue; 831 832 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 833 WARN((shift + width) > prev_shift, 834 "%s has feature overlap at shift %d\n", 835 ftr_reg->name, shift); 836 } 837 838 /* 839 * Skip the first register. There is nothing to 840 * compare against for now. 841 */ 842 if (i == 0) 843 continue; 844 /* 845 * Registers here must be sorted in ascending order with respect 846 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 847 * to work correctly. 848 */ 849 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 850 } 851 } 852 853 /* 854 * Initialise the CPU feature register from Boot CPU values. 855 * Also initiliases the strict_mask for the register. 856 * Any bits that are not covered by an arm64_ftr_bits entry are considered 857 * RES0 for the system-wide value, and must strictly match. 858 */ 859 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 860 { 861 u64 val = 0; 862 u64 strict_mask = ~0x0ULL; 863 u64 user_mask = 0; 864 u64 valid_mask = 0; 865 866 const struct arm64_ftr_bits *ftrp; 867 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 868 869 if (!reg) 870 return; 871 872 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 873 u64 ftr_mask = arm64_ftr_mask(ftrp); 874 s64 ftr_new = arm64_ftr_value(ftrp, new); 875 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 876 877 if ((ftr_mask & reg->override->mask) == ftr_mask) { 878 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 879 char *str = NULL; 880 881 if (ftr_ovr != tmp) { 882 /* Unsafe, remove the override */ 883 reg->override->mask &= ~ftr_mask; 884 reg->override->val &= ~ftr_mask; 885 tmp = ftr_ovr; 886 str = "ignoring override"; 887 } else if (ftr_new != tmp) { 888 /* Override was valid */ 889 ftr_new = tmp; 890 str = "forced"; 891 } else if (ftr_ovr == tmp) { 892 /* Override was the safe value */ 893 str = "already set"; 894 } 895 896 if (str) 897 pr_warn("%s[%d:%d]: %s to %llx\n", 898 reg->name, 899 ftrp->shift + ftrp->width - 1, 900 ftrp->shift, str, tmp); 901 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 902 reg->override->val &= ~ftr_mask; 903 pr_warn("%s[%d:%d]: impossible override, ignored\n", 904 reg->name, 905 ftrp->shift + ftrp->width - 1, 906 ftrp->shift); 907 } 908 909 val = arm64_ftr_set_value(ftrp, val, ftr_new); 910 911 valid_mask |= ftr_mask; 912 if (!ftrp->strict) 913 strict_mask &= ~ftr_mask; 914 if (ftrp->visible) 915 user_mask |= ftr_mask; 916 else 917 reg->user_val = arm64_ftr_set_value(ftrp, 918 reg->user_val, 919 ftrp->safe_val); 920 } 921 922 val &= valid_mask; 923 924 reg->sys_val = val; 925 reg->strict_mask = strict_mask; 926 reg->user_mask = user_mask; 927 } 928 929 extern const struct arm64_cpu_capabilities arm64_errata[]; 930 static const struct arm64_cpu_capabilities arm64_features[]; 931 932 static void __init 933 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 934 { 935 for (; caps->matches; caps++) { 936 if (WARN(caps->capability >= ARM64_NCAPS, 937 "Invalid capability %d\n", caps->capability)) 938 continue; 939 if (WARN(cpu_hwcaps_ptrs[caps->capability], 940 "Duplicate entry for capability %d\n", 941 caps->capability)) 942 continue; 943 cpu_hwcaps_ptrs[caps->capability] = caps; 944 } 945 } 946 947 static void __init init_cpu_hwcaps_indirect_list(void) 948 { 949 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 950 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 951 } 952 953 static void __init setup_boot_cpu_capabilities(void); 954 955 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 956 { 957 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 958 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 959 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 960 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 961 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 962 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 963 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 964 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 965 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 966 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 967 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 968 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 969 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 970 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 971 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 972 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 973 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 974 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 975 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 976 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 977 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 978 } 979 980 void __init init_cpu_features(struct cpuinfo_arm64 *info) 981 { 982 /* Before we start using the tables, make sure it is sorted */ 983 sort_ftr_regs(); 984 985 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 986 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 987 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 988 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 989 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 990 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 991 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 992 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 993 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 994 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 995 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 996 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 997 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 998 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 999 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1000 1001 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1002 init_32bit_cpu_features(&info->aarch32); 1003 1004 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1005 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1006 info->reg_zcr = read_zcr_features(); 1007 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 1008 vec_init_vq_map(ARM64_VEC_SVE); 1009 } 1010 1011 if (IS_ENABLED(CONFIG_ARM64_SME) && 1012 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1013 info->reg_smcr = read_smcr_features(); 1014 /* 1015 * We mask out SMPS since even if the hardware 1016 * supports priorities the kernel does not at present 1017 * and we block access to them. 1018 */ 1019 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1020 init_cpu_ftr_reg(SYS_SMCR_EL1, info->reg_smcr); 1021 vec_init_vq_map(ARM64_VEC_SME); 1022 } 1023 1024 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1025 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1026 1027 /* 1028 * Initialize the indirect array of CPU hwcaps capabilities pointers 1029 * before we handle the boot CPU below. 1030 */ 1031 init_cpu_hwcaps_indirect_list(); 1032 1033 /* 1034 * Detect and enable early CPU capabilities based on the boot CPU, 1035 * after we have initialised the CPU feature infrastructure. 1036 */ 1037 setup_boot_cpu_capabilities(); 1038 } 1039 1040 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1041 { 1042 const struct arm64_ftr_bits *ftrp; 1043 1044 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1045 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1046 s64 ftr_new = arm64_ftr_value(ftrp, new); 1047 1048 if (ftr_cur == ftr_new) 1049 continue; 1050 /* Find a safe value */ 1051 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1052 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1053 } 1054 1055 } 1056 1057 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1058 { 1059 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1060 1061 if (!regp) 1062 return 0; 1063 1064 update_cpu_ftr_reg(regp, val); 1065 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1066 return 0; 1067 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1068 regp->name, boot, cpu, val); 1069 return 1; 1070 } 1071 1072 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1073 { 1074 const struct arm64_ftr_bits *ftrp; 1075 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1076 1077 if (!regp) 1078 return; 1079 1080 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1081 if (ftrp->shift == field) { 1082 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1083 break; 1084 } 1085 } 1086 1087 /* Bogus field? */ 1088 WARN_ON(!ftrp->width); 1089 } 1090 1091 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1092 struct cpuinfo_arm64 *boot) 1093 { 1094 static bool boot_cpu_32bit_regs_overridden = false; 1095 1096 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1097 return; 1098 1099 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1100 return; 1101 1102 boot->aarch32 = info->aarch32; 1103 init_32bit_cpu_features(&boot->aarch32); 1104 boot_cpu_32bit_regs_overridden = true; 1105 } 1106 1107 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1108 struct cpuinfo_32bit *boot) 1109 { 1110 int taint = 0; 1111 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1112 1113 /* 1114 * If we don't have AArch32 at EL1, then relax the strictness of 1115 * EL1-dependent register fields to avoid spurious sanity check fails. 1116 */ 1117 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1118 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 1119 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 1120 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 1121 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 1122 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 1123 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 1124 } 1125 1126 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1127 info->reg_id_dfr0, boot->reg_id_dfr0); 1128 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1129 info->reg_id_dfr1, boot->reg_id_dfr1); 1130 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1131 info->reg_id_isar0, boot->reg_id_isar0); 1132 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1133 info->reg_id_isar1, boot->reg_id_isar1); 1134 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1135 info->reg_id_isar2, boot->reg_id_isar2); 1136 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1137 info->reg_id_isar3, boot->reg_id_isar3); 1138 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1139 info->reg_id_isar4, boot->reg_id_isar4); 1140 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1141 info->reg_id_isar5, boot->reg_id_isar5); 1142 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1143 info->reg_id_isar6, boot->reg_id_isar6); 1144 1145 /* 1146 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1147 * ACTLR formats could differ across CPUs and therefore would have to 1148 * be trapped for virtualization anyway. 1149 */ 1150 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1151 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1152 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1153 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1154 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1155 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1156 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1157 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1158 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1159 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1160 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1161 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1162 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1163 info->reg_id_pfr0, boot->reg_id_pfr0); 1164 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1165 info->reg_id_pfr1, boot->reg_id_pfr1); 1166 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1167 info->reg_id_pfr2, boot->reg_id_pfr2); 1168 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1169 info->reg_mvfr0, boot->reg_mvfr0); 1170 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1171 info->reg_mvfr1, boot->reg_mvfr1); 1172 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1173 info->reg_mvfr2, boot->reg_mvfr2); 1174 1175 return taint; 1176 } 1177 1178 /* 1179 * Update system wide CPU feature registers with the values from a 1180 * non-boot CPU. Also performs SANITY checks to make sure that there 1181 * aren't any insane variations from that of the boot CPU. 1182 */ 1183 void update_cpu_features(int cpu, 1184 struct cpuinfo_arm64 *info, 1185 struct cpuinfo_arm64 *boot) 1186 { 1187 int taint = 0; 1188 1189 /* 1190 * The kernel can handle differing I-cache policies, but otherwise 1191 * caches should look identical. Userspace JITs will make use of 1192 * *minLine. 1193 */ 1194 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1195 info->reg_ctr, boot->reg_ctr); 1196 1197 /* 1198 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1199 * could result in too much or too little memory being zeroed if a 1200 * process is preempted and migrated between CPUs. 1201 */ 1202 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1203 info->reg_dczid, boot->reg_dczid); 1204 1205 /* If different, timekeeping will be broken (especially with KVM) */ 1206 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1207 info->reg_cntfrq, boot->reg_cntfrq); 1208 1209 /* 1210 * The kernel uses self-hosted debug features and expects CPUs to 1211 * support identical debug features. We presently need CTX_CMPs, WRPs, 1212 * and BRPs to be identical. 1213 * ID_AA64DFR1 is currently RES0. 1214 */ 1215 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1216 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1217 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1218 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1219 /* 1220 * Even in big.LITTLE, processors should be identical instruction-set 1221 * wise. 1222 */ 1223 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1224 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1225 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1226 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1227 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1228 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1229 1230 /* 1231 * Differing PARange support is fine as long as all peripherals and 1232 * memory are mapped within the minimum PARange of all CPUs. 1233 * Linux should not care about secure memory. 1234 */ 1235 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1236 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1237 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1238 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1239 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1240 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1241 1242 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1243 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1244 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1245 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1246 1247 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1248 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1249 1250 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1251 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1252 1253 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1254 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1255 info->reg_zcr = read_zcr_features(); 1256 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1257 info->reg_zcr, boot->reg_zcr); 1258 1259 /* Probe vector lengths */ 1260 if (!system_capabilities_finalized()) 1261 vec_update_vq_map(ARM64_VEC_SVE); 1262 } 1263 1264 if (IS_ENABLED(CONFIG_ARM64_SME) && 1265 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1266 info->reg_smcr = read_smcr_features(); 1267 /* 1268 * We mask out SMPS since even if the hardware 1269 * supports priorities the kernel does not at present 1270 * and we block access to them. 1271 */ 1272 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1273 taint |= check_update_ftr_reg(SYS_SMCR_EL1, cpu, 1274 info->reg_smcr, boot->reg_smcr); 1275 1276 /* Probe vector lengths */ 1277 if (!system_capabilities_finalized()) 1278 vec_update_vq_map(ARM64_VEC_SME); 1279 } 1280 1281 /* 1282 * The kernel uses the LDGM/STGM instructions and the number of tags 1283 * they read/write depends on the GMID_EL1.BS field. Check that the 1284 * value is the same on all CPUs. 1285 */ 1286 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1287 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1288 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1289 info->reg_gmid, boot->reg_gmid); 1290 } 1291 1292 /* 1293 * If we don't have AArch32 at all then skip the checks entirely 1294 * as the register values may be UNKNOWN and we're not going to be 1295 * using them for anything. 1296 * 1297 * This relies on a sanitised view of the AArch64 ID registers 1298 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1299 */ 1300 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1301 lazy_init_32bit_cpu_features(info, boot); 1302 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1303 &boot->aarch32); 1304 } 1305 1306 /* 1307 * Mismatched CPU features are a recipe for disaster. Don't even 1308 * pretend to support them. 1309 */ 1310 if (taint) { 1311 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1312 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1313 } 1314 } 1315 1316 u64 read_sanitised_ftr_reg(u32 id) 1317 { 1318 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1319 1320 if (!regp) 1321 return 0; 1322 return regp->sys_val; 1323 } 1324 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1325 1326 #define read_sysreg_case(r) \ 1327 case r: val = read_sysreg_s(r); break; 1328 1329 /* 1330 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1331 * Read the system register on the current CPU 1332 */ 1333 u64 __read_sysreg_by_encoding(u32 sys_id) 1334 { 1335 struct arm64_ftr_reg *regp; 1336 u64 val; 1337 1338 switch (sys_id) { 1339 read_sysreg_case(SYS_ID_PFR0_EL1); 1340 read_sysreg_case(SYS_ID_PFR1_EL1); 1341 read_sysreg_case(SYS_ID_PFR2_EL1); 1342 read_sysreg_case(SYS_ID_DFR0_EL1); 1343 read_sysreg_case(SYS_ID_DFR1_EL1); 1344 read_sysreg_case(SYS_ID_MMFR0_EL1); 1345 read_sysreg_case(SYS_ID_MMFR1_EL1); 1346 read_sysreg_case(SYS_ID_MMFR2_EL1); 1347 read_sysreg_case(SYS_ID_MMFR3_EL1); 1348 read_sysreg_case(SYS_ID_MMFR4_EL1); 1349 read_sysreg_case(SYS_ID_MMFR5_EL1); 1350 read_sysreg_case(SYS_ID_ISAR0_EL1); 1351 read_sysreg_case(SYS_ID_ISAR1_EL1); 1352 read_sysreg_case(SYS_ID_ISAR2_EL1); 1353 read_sysreg_case(SYS_ID_ISAR3_EL1); 1354 read_sysreg_case(SYS_ID_ISAR4_EL1); 1355 read_sysreg_case(SYS_ID_ISAR5_EL1); 1356 read_sysreg_case(SYS_ID_ISAR6_EL1); 1357 read_sysreg_case(SYS_MVFR0_EL1); 1358 read_sysreg_case(SYS_MVFR1_EL1); 1359 read_sysreg_case(SYS_MVFR2_EL1); 1360 1361 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1362 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1363 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1364 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1365 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1366 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1367 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1368 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1369 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1370 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1371 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1372 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1373 1374 read_sysreg_case(SYS_CNTFRQ_EL0); 1375 read_sysreg_case(SYS_CTR_EL0); 1376 read_sysreg_case(SYS_DCZID_EL0); 1377 1378 default: 1379 BUG(); 1380 return 0; 1381 } 1382 1383 regp = get_arm64_ftr_reg(sys_id); 1384 if (regp) { 1385 val &= ~regp->override->mask; 1386 val |= (regp->override->val & regp->override->mask); 1387 } 1388 1389 return val; 1390 } 1391 1392 #include <linux/irqchip/arm-gic-v3.h> 1393 1394 static bool 1395 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1396 { 1397 int val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1398 entry->field_width, 1399 entry->sign); 1400 1401 return val >= entry->min_field_value; 1402 } 1403 1404 static bool 1405 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1406 { 1407 u64 val; 1408 1409 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1410 if (scope == SCOPE_SYSTEM) 1411 val = read_sanitised_ftr_reg(entry->sys_reg); 1412 else 1413 val = __read_sysreg_by_encoding(entry->sys_reg); 1414 1415 return feature_matches(val, entry); 1416 } 1417 1418 const struct cpumask *system_32bit_el0_cpumask(void) 1419 { 1420 if (!system_supports_32bit_el0()) 1421 return cpu_none_mask; 1422 1423 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1424 return cpu_32bit_el0_mask; 1425 1426 return cpu_possible_mask; 1427 } 1428 1429 static int __init parse_32bit_el0_param(char *str) 1430 { 1431 allow_mismatched_32bit_el0 = true; 1432 return 0; 1433 } 1434 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1435 1436 static ssize_t aarch32_el0_show(struct device *dev, 1437 struct device_attribute *attr, char *buf) 1438 { 1439 const struct cpumask *mask = system_32bit_el0_cpumask(); 1440 1441 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1442 } 1443 static const DEVICE_ATTR_RO(aarch32_el0); 1444 1445 static int __init aarch32_el0_sysfs_init(void) 1446 { 1447 if (!allow_mismatched_32bit_el0) 1448 return 0; 1449 1450 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0); 1451 } 1452 device_initcall(aarch32_el0_sysfs_init); 1453 1454 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1455 { 1456 if (!has_cpuid_feature(entry, scope)) 1457 return allow_mismatched_32bit_el0; 1458 1459 if (scope == SCOPE_SYSTEM) 1460 pr_info("detected: 32-bit EL0 Support\n"); 1461 1462 return true; 1463 } 1464 1465 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1466 { 1467 bool has_sre; 1468 1469 if (!has_cpuid_feature(entry, scope)) 1470 return false; 1471 1472 has_sre = gic_enable_sre(); 1473 if (!has_sre) 1474 pr_warn_once("%s present but disabled by higher exception level\n", 1475 entry->desc); 1476 1477 return has_sre; 1478 } 1479 1480 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1481 { 1482 u32 midr = read_cpuid_id(); 1483 1484 /* Cavium ThunderX pass 1.x and 2.x */ 1485 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1486 MIDR_CPU_VAR_REV(0, 0), 1487 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1488 } 1489 1490 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1491 { 1492 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1493 1494 return cpuid_feature_extract_signed_field(pfr0, 1495 ID_AA64PFR0_FP_SHIFT) < 0; 1496 } 1497 1498 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1499 int scope) 1500 { 1501 u64 ctr; 1502 1503 if (scope == SCOPE_SYSTEM) 1504 ctr = arm64_ftr_reg_ctrel0.sys_val; 1505 else 1506 ctr = read_cpuid_effective_cachetype(); 1507 1508 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1509 } 1510 1511 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1512 { 1513 /* 1514 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1515 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1516 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1517 * value. 1518 */ 1519 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1520 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1521 } 1522 1523 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1524 int scope) 1525 { 1526 u64 ctr; 1527 1528 if (scope == SCOPE_SYSTEM) 1529 ctr = arm64_ftr_reg_ctrel0.sys_val; 1530 else 1531 ctr = read_cpuid_cachetype(); 1532 1533 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1534 } 1535 1536 static bool __maybe_unused 1537 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1538 { 1539 /* 1540 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1541 * may share TLB entries with a CPU stuck in the crashed 1542 * kernel. 1543 */ 1544 if (is_kdump_kernel()) 1545 return false; 1546 1547 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1548 return false; 1549 1550 return has_cpuid_feature(entry, scope); 1551 } 1552 1553 /* 1554 * This check is triggered during the early boot before the cpufeature 1555 * is initialised. Checking the status on the local CPU allows the boot 1556 * CPU to detect the need for non-global mappings and thus avoiding a 1557 * pagetable re-write after all the CPUs are booted. This check will be 1558 * anyway run on individual CPUs, allowing us to get the consistent 1559 * state once the SMP CPUs are up and thus make the switch to non-global 1560 * mappings if required. 1561 */ 1562 bool kaslr_requires_kpti(void) 1563 { 1564 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1565 return false; 1566 1567 /* 1568 * E0PD does a similar job to KPTI so can be used instead 1569 * where available. 1570 */ 1571 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1572 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1573 if (cpuid_feature_extract_unsigned_field(mmfr2, 1574 ID_AA64MMFR2_E0PD_SHIFT)) 1575 return false; 1576 } 1577 1578 /* 1579 * Systems affected by Cavium erratum 24756 are incompatible 1580 * with KPTI. 1581 */ 1582 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1583 extern const struct midr_range cavium_erratum_27456_cpus[]; 1584 1585 if (is_midr_in_range_list(read_cpuid_id(), 1586 cavium_erratum_27456_cpus)) 1587 return false; 1588 } 1589 1590 return kaslr_offset() > 0; 1591 } 1592 1593 static bool __meltdown_safe = true; 1594 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1595 1596 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1597 int scope) 1598 { 1599 /* List of CPUs that are not vulnerable and don't need KPTI */ 1600 static const struct midr_range kpti_safe_list[] = { 1601 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1602 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1603 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1604 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1605 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1606 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1607 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1608 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1609 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1610 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1611 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1612 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1613 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1614 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1615 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1616 { /* sentinel */ } 1617 }; 1618 char const *str = "kpti command line option"; 1619 bool meltdown_safe; 1620 1621 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1622 1623 /* Defer to CPU feature registers */ 1624 if (has_cpuid_feature(entry, scope)) 1625 meltdown_safe = true; 1626 1627 if (!meltdown_safe) 1628 __meltdown_safe = false; 1629 1630 /* 1631 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1632 * ThunderX leads to apparent I-cache corruption of kernel text, which 1633 * ends as well as you might imagine. Don't even try. We cannot rely 1634 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1635 * because cpucap detection order may change. However, since we know 1636 * affected CPUs are always in a homogeneous configuration, it is 1637 * safe to rely on this_cpu_has_cap() here. 1638 */ 1639 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1640 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1641 __kpti_forced = -1; 1642 } 1643 1644 /* Useful for KASLR robustness */ 1645 if (kaslr_requires_kpti()) { 1646 if (!__kpti_forced) { 1647 str = "KASLR"; 1648 __kpti_forced = 1; 1649 } 1650 } 1651 1652 if (cpu_mitigations_off() && !__kpti_forced) { 1653 str = "mitigations=off"; 1654 __kpti_forced = -1; 1655 } 1656 1657 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1658 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1659 return false; 1660 } 1661 1662 /* Forced? */ 1663 if (__kpti_forced) { 1664 pr_info_once("kernel page table isolation forced %s by %s\n", 1665 __kpti_forced > 0 ? "ON" : "OFF", str); 1666 return __kpti_forced > 0; 1667 } 1668 1669 return !meltdown_safe; 1670 } 1671 1672 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1673 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1674 1675 extern 1676 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1677 phys_addr_t size, pgprot_t prot, 1678 phys_addr_t (*pgtable_alloc)(int), int flags); 1679 1680 static phys_addr_t kpti_ng_temp_alloc; 1681 1682 static phys_addr_t kpti_ng_pgd_alloc(int shift) 1683 { 1684 kpti_ng_temp_alloc -= PAGE_SIZE; 1685 return kpti_ng_temp_alloc; 1686 } 1687 1688 static void __nocfi 1689 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1690 { 1691 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1692 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1693 kpti_remap_fn *remap_fn; 1694 1695 int cpu = smp_processor_id(); 1696 int levels = CONFIG_PGTABLE_LEVELS; 1697 int order = order_base_2(levels); 1698 u64 kpti_ng_temp_pgd_pa = 0; 1699 pgd_t *kpti_ng_temp_pgd; 1700 u64 alloc = 0; 1701 1702 if (__this_cpu_read(this_cpu_vector) == vectors) { 1703 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1704 1705 __this_cpu_write(this_cpu_vector, v); 1706 } 1707 1708 /* 1709 * We don't need to rewrite the page-tables if either we've done 1710 * it already or we have KASLR enabled and therefore have not 1711 * created any global mappings at all. 1712 */ 1713 if (arm64_use_ng_mappings) 1714 return; 1715 1716 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings)); 1717 1718 if (!cpu) { 1719 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1720 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1721 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1722 1723 // 1724 // Create a minimal page table hierarchy that permits us to map 1725 // the swapper page tables temporarily as we traverse them. 1726 // 1727 // The physical pages are laid out as follows: 1728 // 1729 // +--------+-/-------+-/------ +-\\--------+ 1730 // : PTE[] : | PMD[] : | PUD[] : || PGD[] : 1731 // +--------+-\-------+-\------ +-//--------+ 1732 // ^ 1733 // The first page is mapped into this hierarchy at a PMD_SHIFT 1734 // aligned virtual address, so that we can manipulate the PTE 1735 // level entries while the mapping is active. The first entry 1736 // covers the PTE[] page itself, the remaining entries are free 1737 // to be used as a ad-hoc fixmap. 1738 // 1739 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1740 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1741 kpti_ng_pgd_alloc, 0); 1742 } 1743 1744 cpu_install_idmap(); 1745 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1746 cpu_uninstall_idmap(); 1747 1748 if (!cpu) { 1749 free_pages(alloc, order); 1750 arm64_use_ng_mappings = true; 1751 } 1752 } 1753 #else 1754 static void 1755 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1756 { 1757 } 1758 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1759 1760 static int __init parse_kpti(char *str) 1761 { 1762 bool enabled; 1763 int ret = strtobool(str, &enabled); 1764 1765 if (ret) 1766 return ret; 1767 1768 __kpti_forced = enabled ? 1 : -1; 1769 return 0; 1770 } 1771 early_param("kpti", parse_kpti); 1772 1773 #ifdef CONFIG_ARM64_HW_AFDBM 1774 static inline void __cpu_enable_hw_dbm(void) 1775 { 1776 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1777 1778 write_sysreg(tcr, tcr_el1); 1779 isb(); 1780 local_flush_tlb_all(); 1781 } 1782 1783 static bool cpu_has_broken_dbm(void) 1784 { 1785 /* List of CPUs which have broken DBM support. */ 1786 static const struct midr_range cpus[] = { 1787 #ifdef CONFIG_ARM64_ERRATUM_1024718 1788 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1789 /* Kryo4xx Silver (rdpe => r1p0) */ 1790 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1791 #endif 1792 #ifdef CONFIG_ARM64_ERRATUM_2051678 1793 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1794 #endif 1795 {}, 1796 }; 1797 1798 return is_midr_in_range_list(read_cpuid_id(), cpus); 1799 } 1800 1801 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1802 { 1803 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1804 !cpu_has_broken_dbm(); 1805 } 1806 1807 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1808 { 1809 if (cpu_can_use_dbm(cap)) 1810 __cpu_enable_hw_dbm(); 1811 } 1812 1813 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1814 int __unused) 1815 { 1816 static bool detected = false; 1817 /* 1818 * DBM is a non-conflicting feature. i.e, the kernel can safely 1819 * run a mix of CPUs with and without the feature. So, we 1820 * unconditionally enable the capability to allow any late CPU 1821 * to use the feature. We only enable the control bits on the 1822 * CPU, if it actually supports. 1823 * 1824 * We have to make sure we print the "feature" detection only 1825 * when at least one CPU actually uses it. So check if this CPU 1826 * can actually use it and print the message exactly once. 1827 * 1828 * This is safe as all CPUs (including secondary CPUs - due to the 1829 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1830 * goes through the "matches" check exactly once. Also if a CPU 1831 * matches the criteria, it is guaranteed that the CPU will turn 1832 * the DBM on, as the capability is unconditionally enabled. 1833 */ 1834 if (!detected && cpu_can_use_dbm(cap)) { 1835 detected = true; 1836 pr_info("detected: Hardware dirty bit management\n"); 1837 } 1838 1839 return true; 1840 } 1841 1842 #endif 1843 1844 #ifdef CONFIG_ARM64_AMU_EXTN 1845 1846 /* 1847 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1848 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1849 * information regarding all the events that it supports. When a CPU bit is 1850 * set in the cpumask, the user of this feature can only rely on the presence 1851 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1852 * counters are enabled or access to these counters is enabled by code 1853 * executed at higher exception levels (firmware). 1854 */ 1855 static struct cpumask amu_cpus __read_mostly; 1856 1857 bool cpu_has_amu_feat(int cpu) 1858 { 1859 return cpumask_test_cpu(cpu, &amu_cpus); 1860 } 1861 1862 int get_cpu_with_amu_feat(void) 1863 { 1864 return cpumask_any(&amu_cpus); 1865 } 1866 1867 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1868 { 1869 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1870 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1871 smp_processor_id()); 1872 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1873 update_freq_counters_refs(); 1874 } 1875 } 1876 1877 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1878 int __unused) 1879 { 1880 /* 1881 * The AMU extension is a non-conflicting feature: the kernel can 1882 * safely run a mix of CPUs with and without support for the 1883 * activity monitors extension. Therefore, unconditionally enable 1884 * the capability to allow any late CPU to use the feature. 1885 * 1886 * With this feature unconditionally enabled, the cpu_enable 1887 * function will be called for all CPUs that match the criteria, 1888 * including secondary and hotplugged, marking this feature as 1889 * present on that respective CPU. The enable function will also 1890 * print a detection message. 1891 */ 1892 1893 return true; 1894 } 1895 #else 1896 int get_cpu_with_amu_feat(void) 1897 { 1898 return nr_cpu_ids; 1899 } 1900 #endif 1901 1902 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1903 { 1904 return is_kernel_in_hyp_mode(); 1905 } 1906 1907 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1908 { 1909 /* 1910 * Copy register values that aren't redirected by hardware. 1911 * 1912 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1913 * this value to tpidr_el2 before we patch the code. Once we've done 1914 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1915 * do anything here. 1916 */ 1917 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1918 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1919 } 1920 1921 #ifdef CONFIG_ARM64_PAN 1922 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1923 { 1924 /* 1925 * We modify PSTATE. This won't work from irq context as the PSTATE 1926 * is discarded once we return from the exception. 1927 */ 1928 WARN_ON_ONCE(in_interrupt()); 1929 1930 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1931 set_pstate_pan(1); 1932 } 1933 #endif /* CONFIG_ARM64_PAN */ 1934 1935 #ifdef CONFIG_ARM64_RAS_EXTN 1936 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1937 { 1938 /* Firmware may have left a deferred SError in this register. */ 1939 write_sysreg_s(0, SYS_DISR_EL1); 1940 } 1941 #endif /* CONFIG_ARM64_RAS_EXTN */ 1942 1943 #ifdef CONFIG_ARM64_PTR_AUTH 1944 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 1945 { 1946 int boot_val, sec_val; 1947 1948 /* We don't expect to be called with SCOPE_SYSTEM */ 1949 WARN_ON(scope == SCOPE_SYSTEM); 1950 /* 1951 * The ptr-auth feature levels are not intercompatible with lower 1952 * levels. Hence we must match ptr-auth feature level of the secondary 1953 * CPUs with that of the boot CPU. The level of boot cpu is fetched 1954 * from the sanitised register whereas direct register read is done for 1955 * the secondary CPUs. 1956 * The sanitised feature state is guaranteed to match that of the 1957 * boot CPU as a mismatched secondary CPU is parked before it gets 1958 * a chance to update the state, with the capability. 1959 */ 1960 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 1961 entry->field_pos, entry->sign); 1962 if (scope & SCOPE_BOOT_CPU) 1963 return boot_val >= entry->min_field_value; 1964 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 1965 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 1966 entry->field_pos, entry->sign); 1967 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 1968 } 1969 1970 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 1971 int scope) 1972 { 1973 bool api = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 1974 bool apa = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 1975 bool apa3 = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 1976 1977 return apa || apa3 || api; 1978 } 1979 1980 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1981 int __unused) 1982 { 1983 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1984 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 1985 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 1986 1987 return gpa || gpa3 || gpi; 1988 } 1989 #endif /* CONFIG_ARM64_PTR_AUTH */ 1990 1991 #ifdef CONFIG_ARM64_E0PD 1992 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 1993 { 1994 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 1995 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 1996 } 1997 #endif /* CONFIG_ARM64_E0PD */ 1998 1999 #ifdef CONFIG_ARM64_PSEUDO_NMI 2000 static bool enable_pseudo_nmi; 2001 2002 static int __init early_enable_pseudo_nmi(char *p) 2003 { 2004 return strtobool(p, &enable_pseudo_nmi); 2005 } 2006 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 2007 2008 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2009 int scope) 2010 { 2011 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 2012 } 2013 #endif 2014 2015 #ifdef CONFIG_ARM64_BTI 2016 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2017 { 2018 /* 2019 * Use of X16/X17 for tail-calls and trampolines that jump to 2020 * function entry points using BR is a requirement for 2021 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2022 * So, be strict and forbid other BRs using other registers to 2023 * jump onto a PACIxSP instruction: 2024 */ 2025 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2026 isb(); 2027 } 2028 #endif /* CONFIG_ARM64_BTI */ 2029 2030 #ifdef CONFIG_ARM64_MTE 2031 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2032 { 2033 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2034 isb(); 2035 2036 /* 2037 * Clear the tags in the zero page. This needs to be done via the 2038 * linear map which has the Tagged attribute. 2039 */ 2040 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags)) 2041 mte_clear_page_tags(lm_alias(empty_zero_page)); 2042 2043 kasan_init_hw_tags_cpu(); 2044 } 2045 #endif /* CONFIG_ARM64_MTE */ 2046 2047 static void elf_hwcap_fixup(void) 2048 { 2049 #ifdef CONFIG_ARM64_ERRATUM_1742098 2050 if (cpus_have_const_cap(ARM64_WORKAROUND_1742098)) 2051 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2052 #endif /* ARM64_ERRATUM_1742098 */ 2053 } 2054 2055 #ifdef CONFIG_KVM 2056 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2057 { 2058 return kvm_get_mode() == KVM_MODE_PROTECTED; 2059 } 2060 #endif /* CONFIG_KVM */ 2061 2062 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2063 { 2064 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2065 } 2066 2067 /* Internal helper functions to match cpu capability type */ 2068 static bool 2069 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2070 { 2071 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2072 } 2073 2074 static bool 2075 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2076 { 2077 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2078 } 2079 2080 static bool 2081 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2082 { 2083 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2084 } 2085 2086 static const struct arm64_cpu_capabilities arm64_features[] = { 2087 { 2088 .desc = "GIC system register CPU interface", 2089 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 2090 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2091 .matches = has_useable_gicv3_cpuif, 2092 .sys_reg = SYS_ID_AA64PFR0_EL1, 2093 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2094 .field_width = 4, 2095 .sign = FTR_UNSIGNED, 2096 .min_field_value = 1, 2097 }, 2098 { 2099 .desc = "Enhanced Counter Virtualization", 2100 .capability = ARM64_HAS_ECV, 2101 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2102 .matches = has_cpuid_feature, 2103 .sys_reg = SYS_ID_AA64MMFR0_EL1, 2104 .field_pos = ID_AA64MMFR0_ECV_SHIFT, 2105 .field_width = 4, 2106 .sign = FTR_UNSIGNED, 2107 .min_field_value = 1, 2108 }, 2109 #ifdef CONFIG_ARM64_PAN 2110 { 2111 .desc = "Privileged Access Never", 2112 .capability = ARM64_HAS_PAN, 2113 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2114 .matches = has_cpuid_feature, 2115 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2116 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 2117 .field_width = 4, 2118 .sign = FTR_UNSIGNED, 2119 .min_field_value = 1, 2120 .cpu_enable = cpu_enable_pan, 2121 }, 2122 #endif /* CONFIG_ARM64_PAN */ 2123 #ifdef CONFIG_ARM64_EPAN 2124 { 2125 .desc = "Enhanced Privileged Access Never", 2126 .capability = ARM64_HAS_EPAN, 2127 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2128 .matches = has_cpuid_feature, 2129 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2130 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 2131 .field_width = 4, 2132 .sign = FTR_UNSIGNED, 2133 .min_field_value = 3, 2134 }, 2135 #endif /* CONFIG_ARM64_EPAN */ 2136 #ifdef CONFIG_ARM64_LSE_ATOMICS 2137 { 2138 .desc = "LSE atomic instructions", 2139 .capability = ARM64_HAS_LSE_ATOMICS, 2140 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2141 .matches = has_cpuid_feature, 2142 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2143 .field_pos = ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 2144 .field_width = 4, 2145 .sign = FTR_UNSIGNED, 2146 .min_field_value = 2, 2147 }, 2148 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2149 { 2150 .desc = "Software prefetching using PRFM", 2151 .capability = ARM64_HAS_NO_HW_PREFETCH, 2152 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2153 .matches = has_no_hw_prefetch, 2154 }, 2155 { 2156 .desc = "Virtualization Host Extensions", 2157 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2158 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2159 .matches = runs_at_el2, 2160 .cpu_enable = cpu_copy_el2regs, 2161 }, 2162 { 2163 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2164 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2165 .matches = has_32bit_el0, 2166 .sys_reg = SYS_ID_AA64PFR0_EL1, 2167 .sign = FTR_UNSIGNED, 2168 .field_pos = ID_AA64PFR0_EL0_SHIFT, 2169 .field_width = 4, 2170 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT, 2171 }, 2172 #ifdef CONFIG_KVM 2173 { 2174 .desc = "32-bit EL1 Support", 2175 .capability = ARM64_HAS_32BIT_EL1, 2176 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2177 .matches = has_cpuid_feature, 2178 .sys_reg = SYS_ID_AA64PFR0_EL1, 2179 .sign = FTR_UNSIGNED, 2180 .field_pos = ID_AA64PFR0_EL1_SHIFT, 2181 .field_width = 4, 2182 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT, 2183 }, 2184 { 2185 .desc = "Protected KVM", 2186 .capability = ARM64_KVM_PROTECTED_MODE, 2187 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2188 .matches = is_kvm_protected_mode, 2189 }, 2190 #endif 2191 { 2192 .desc = "Kernel page table isolation (KPTI)", 2193 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2194 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2195 /* 2196 * The ID feature fields below are used to indicate that 2197 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2198 * more details. 2199 */ 2200 .sys_reg = SYS_ID_AA64PFR0_EL1, 2201 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 2202 .field_width = 4, 2203 .min_field_value = 1, 2204 .matches = unmap_kernel_at_el0, 2205 .cpu_enable = kpti_install_ng_mappings, 2206 }, 2207 { 2208 /* FP/SIMD is not implemented */ 2209 .capability = ARM64_HAS_NO_FPSIMD, 2210 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2211 .min_field_value = 0, 2212 .matches = has_no_fpsimd, 2213 }, 2214 #ifdef CONFIG_ARM64_PMEM 2215 { 2216 .desc = "Data cache clean to Point of Persistence", 2217 .capability = ARM64_HAS_DCPOP, 2218 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2219 .matches = has_cpuid_feature, 2220 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2221 .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT, 2222 .field_width = 4, 2223 .min_field_value = 1, 2224 }, 2225 { 2226 .desc = "Data cache clean to Point of Deep Persistence", 2227 .capability = ARM64_HAS_DCPODP, 2228 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2229 .matches = has_cpuid_feature, 2230 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2231 .sign = FTR_UNSIGNED, 2232 .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT, 2233 .field_width = 4, 2234 .min_field_value = 2, 2235 }, 2236 #endif 2237 #ifdef CONFIG_ARM64_SVE 2238 { 2239 .desc = "Scalable Vector Extension", 2240 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2241 .capability = ARM64_SVE, 2242 .sys_reg = SYS_ID_AA64PFR0_EL1, 2243 .sign = FTR_UNSIGNED, 2244 .field_pos = ID_AA64PFR0_SVE_SHIFT, 2245 .field_width = 4, 2246 .min_field_value = ID_AA64PFR0_SVE, 2247 .matches = has_cpuid_feature, 2248 .cpu_enable = sve_kernel_enable, 2249 }, 2250 #endif /* CONFIG_ARM64_SVE */ 2251 #ifdef CONFIG_ARM64_RAS_EXTN 2252 { 2253 .desc = "RAS Extension Support", 2254 .capability = ARM64_HAS_RAS_EXTN, 2255 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2256 .matches = has_cpuid_feature, 2257 .sys_reg = SYS_ID_AA64PFR0_EL1, 2258 .sign = FTR_UNSIGNED, 2259 .field_pos = ID_AA64PFR0_RAS_SHIFT, 2260 .field_width = 4, 2261 .min_field_value = ID_AA64PFR0_RAS_V1, 2262 .cpu_enable = cpu_clear_disr, 2263 }, 2264 #endif /* CONFIG_ARM64_RAS_EXTN */ 2265 #ifdef CONFIG_ARM64_AMU_EXTN 2266 { 2267 /* 2268 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 2269 * Therefore, don't provide .desc as we don't want the detection 2270 * message to be shown until at least one CPU is detected to 2271 * support the feature. 2272 */ 2273 .capability = ARM64_HAS_AMU_EXTN, 2274 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2275 .matches = has_amu, 2276 .sys_reg = SYS_ID_AA64PFR0_EL1, 2277 .sign = FTR_UNSIGNED, 2278 .field_pos = ID_AA64PFR0_AMU_SHIFT, 2279 .field_width = 4, 2280 .min_field_value = ID_AA64PFR0_AMU, 2281 .cpu_enable = cpu_amu_enable, 2282 }, 2283 #endif /* CONFIG_ARM64_AMU_EXTN */ 2284 { 2285 .desc = "Data cache clean to the PoU not required for I/D coherence", 2286 .capability = ARM64_HAS_CACHE_IDC, 2287 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2288 .matches = has_cache_idc, 2289 .cpu_enable = cpu_emulate_effective_ctr, 2290 }, 2291 { 2292 .desc = "Instruction cache invalidation not required for I/D coherence", 2293 .capability = ARM64_HAS_CACHE_DIC, 2294 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2295 .matches = has_cache_dic, 2296 }, 2297 { 2298 .desc = "Stage-2 Force Write-Back", 2299 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2300 .capability = ARM64_HAS_STAGE2_FWB, 2301 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2302 .sign = FTR_UNSIGNED, 2303 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 2304 .field_width = 4, 2305 .min_field_value = 1, 2306 .matches = has_cpuid_feature, 2307 }, 2308 { 2309 .desc = "ARMv8.4 Translation Table Level", 2310 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2311 .capability = ARM64_HAS_ARMv8_4_TTL, 2312 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2313 .sign = FTR_UNSIGNED, 2314 .field_pos = ID_AA64MMFR2_TTL_SHIFT, 2315 .field_width = 4, 2316 .min_field_value = 1, 2317 .matches = has_cpuid_feature, 2318 }, 2319 { 2320 .desc = "TLB range maintenance instructions", 2321 .capability = ARM64_HAS_TLB_RANGE, 2322 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2323 .matches = has_cpuid_feature, 2324 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2325 .field_pos = ID_AA64ISAR0_EL1_TLB_SHIFT, 2326 .field_width = 4, 2327 .sign = FTR_UNSIGNED, 2328 .min_field_value = ID_AA64ISAR0_EL1_TLB_RANGE, 2329 }, 2330 #ifdef CONFIG_ARM64_HW_AFDBM 2331 { 2332 /* 2333 * Since we turn this on always, we don't want the user to 2334 * think that the feature is available when it may not be. 2335 * So hide the description. 2336 * 2337 * .desc = "Hardware pagetable Dirty Bit Management", 2338 * 2339 */ 2340 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2341 .capability = ARM64_HW_DBM, 2342 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2343 .sign = FTR_UNSIGNED, 2344 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 2345 .field_width = 4, 2346 .min_field_value = 2, 2347 .matches = has_hw_dbm, 2348 .cpu_enable = cpu_enable_hw_dbm, 2349 }, 2350 #endif 2351 { 2352 .desc = "CRC32 instructions", 2353 .capability = ARM64_HAS_CRC32, 2354 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2355 .matches = has_cpuid_feature, 2356 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2357 .field_pos = ID_AA64ISAR0_EL1_CRC32_SHIFT, 2358 .field_width = 4, 2359 .min_field_value = 1, 2360 }, 2361 { 2362 .desc = "Speculative Store Bypassing Safe (SSBS)", 2363 .capability = ARM64_SSBS, 2364 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2365 .matches = has_cpuid_feature, 2366 .sys_reg = SYS_ID_AA64PFR1_EL1, 2367 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 2368 .field_width = 4, 2369 .sign = FTR_UNSIGNED, 2370 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 2371 }, 2372 #ifdef CONFIG_ARM64_CNP 2373 { 2374 .desc = "Common not Private translations", 2375 .capability = ARM64_HAS_CNP, 2376 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2377 .matches = has_useable_cnp, 2378 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2379 .sign = FTR_UNSIGNED, 2380 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 2381 .field_width = 4, 2382 .min_field_value = 1, 2383 .cpu_enable = cpu_enable_cnp, 2384 }, 2385 #endif 2386 { 2387 .desc = "Speculation barrier (SB)", 2388 .capability = ARM64_HAS_SB, 2389 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2390 .matches = has_cpuid_feature, 2391 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2392 .field_pos = ID_AA64ISAR1_EL1_SB_SHIFT, 2393 .field_width = 4, 2394 .sign = FTR_UNSIGNED, 2395 .min_field_value = 1, 2396 }, 2397 #ifdef CONFIG_ARM64_PTR_AUTH 2398 { 2399 .desc = "Address authentication (architected QARMA5 algorithm)", 2400 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2401 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2402 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2403 .sign = FTR_UNSIGNED, 2404 .field_pos = ID_AA64ISAR1_EL1_APA_SHIFT, 2405 .field_width = 4, 2406 .min_field_value = ID_AA64ISAR1_EL1_APA_PAuth, 2407 .matches = has_address_auth_cpucap, 2408 }, 2409 { 2410 .desc = "Address authentication (architected QARMA3 algorithm)", 2411 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2412 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2413 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2414 .sign = FTR_UNSIGNED, 2415 .field_pos = ID_AA64ISAR2_EL1_APA3_SHIFT, 2416 .field_width = 4, 2417 .min_field_value = ID_AA64ISAR2_EL1_APA3_PAuth, 2418 .matches = has_address_auth_cpucap, 2419 }, 2420 { 2421 .desc = "Address authentication (IMP DEF algorithm)", 2422 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2423 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2424 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2425 .sign = FTR_UNSIGNED, 2426 .field_pos = ID_AA64ISAR1_EL1_API_SHIFT, 2427 .field_width = 4, 2428 .min_field_value = ID_AA64ISAR1_EL1_API_PAuth, 2429 .matches = has_address_auth_cpucap, 2430 }, 2431 { 2432 .capability = ARM64_HAS_ADDRESS_AUTH, 2433 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2434 .matches = has_address_auth_metacap, 2435 }, 2436 { 2437 .desc = "Generic authentication (architected QARMA5 algorithm)", 2438 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2439 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2440 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2441 .sign = FTR_UNSIGNED, 2442 .field_pos = ID_AA64ISAR1_EL1_GPA_SHIFT, 2443 .field_width = 4, 2444 .min_field_value = ID_AA64ISAR1_EL1_GPA_IMP, 2445 .matches = has_cpuid_feature, 2446 }, 2447 { 2448 .desc = "Generic authentication (architected QARMA3 algorithm)", 2449 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2450 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2451 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2452 .sign = FTR_UNSIGNED, 2453 .field_pos = ID_AA64ISAR2_EL1_GPA3_SHIFT, 2454 .field_width = 4, 2455 .min_field_value = ID_AA64ISAR2_EL1_GPA3_IMP, 2456 .matches = has_cpuid_feature, 2457 }, 2458 { 2459 .desc = "Generic authentication (IMP DEF algorithm)", 2460 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2461 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2462 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2463 .sign = FTR_UNSIGNED, 2464 .field_pos = ID_AA64ISAR1_EL1_GPI_SHIFT, 2465 .field_width = 4, 2466 .min_field_value = ID_AA64ISAR1_EL1_GPI_IMP, 2467 .matches = has_cpuid_feature, 2468 }, 2469 { 2470 .capability = ARM64_HAS_GENERIC_AUTH, 2471 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2472 .matches = has_generic_auth, 2473 }, 2474 #endif /* CONFIG_ARM64_PTR_AUTH */ 2475 #ifdef CONFIG_ARM64_PSEUDO_NMI 2476 { 2477 /* 2478 * Depends on having GICv3 2479 */ 2480 .desc = "IRQ priority masking", 2481 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2482 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2483 .matches = can_use_gic_priorities, 2484 .sys_reg = SYS_ID_AA64PFR0_EL1, 2485 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2486 .field_width = 4, 2487 .sign = FTR_UNSIGNED, 2488 .min_field_value = 1, 2489 }, 2490 #endif 2491 #ifdef CONFIG_ARM64_E0PD 2492 { 2493 .desc = "E0PD", 2494 .capability = ARM64_HAS_E0PD, 2495 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2496 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2497 .sign = FTR_UNSIGNED, 2498 .field_width = 4, 2499 .field_pos = ID_AA64MMFR2_E0PD_SHIFT, 2500 .matches = has_cpuid_feature, 2501 .min_field_value = 1, 2502 .cpu_enable = cpu_enable_e0pd, 2503 }, 2504 #endif 2505 { 2506 .desc = "Random Number Generator", 2507 .capability = ARM64_HAS_RNG, 2508 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2509 .matches = has_cpuid_feature, 2510 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2511 .field_pos = ID_AA64ISAR0_EL1_RNDR_SHIFT, 2512 .field_width = 4, 2513 .sign = FTR_UNSIGNED, 2514 .min_field_value = 1, 2515 }, 2516 #ifdef CONFIG_ARM64_BTI 2517 { 2518 .desc = "Branch Target Identification", 2519 .capability = ARM64_BTI, 2520 #ifdef CONFIG_ARM64_BTI_KERNEL 2521 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2522 #else 2523 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2524 #endif 2525 .matches = has_cpuid_feature, 2526 .cpu_enable = bti_enable, 2527 .sys_reg = SYS_ID_AA64PFR1_EL1, 2528 .field_pos = ID_AA64PFR1_BT_SHIFT, 2529 .field_width = 4, 2530 .min_field_value = ID_AA64PFR1_BT_BTI, 2531 .sign = FTR_UNSIGNED, 2532 }, 2533 #endif 2534 #ifdef CONFIG_ARM64_MTE 2535 { 2536 .desc = "Memory Tagging Extension", 2537 .capability = ARM64_MTE, 2538 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2539 .matches = has_cpuid_feature, 2540 .sys_reg = SYS_ID_AA64PFR1_EL1, 2541 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2542 .field_width = 4, 2543 .min_field_value = ID_AA64PFR1_MTE, 2544 .sign = FTR_UNSIGNED, 2545 .cpu_enable = cpu_enable_mte, 2546 }, 2547 { 2548 .desc = "Asymmetric MTE Tag Check Fault", 2549 .capability = ARM64_MTE_ASYMM, 2550 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2551 .matches = has_cpuid_feature, 2552 .sys_reg = SYS_ID_AA64PFR1_EL1, 2553 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2554 .field_width = 4, 2555 .min_field_value = ID_AA64PFR1_MTE_ASYMM, 2556 .sign = FTR_UNSIGNED, 2557 }, 2558 #endif /* CONFIG_ARM64_MTE */ 2559 { 2560 .desc = "RCpc load-acquire (LDAPR)", 2561 .capability = ARM64_HAS_LDAPR, 2562 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2563 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2564 .sign = FTR_UNSIGNED, 2565 .field_pos = ID_AA64ISAR1_EL1_LRCPC_SHIFT, 2566 .field_width = 4, 2567 .matches = has_cpuid_feature, 2568 .min_field_value = 1, 2569 }, 2570 #ifdef CONFIG_ARM64_SME 2571 { 2572 .desc = "Scalable Matrix Extension", 2573 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2574 .capability = ARM64_SME, 2575 .sys_reg = SYS_ID_AA64PFR1_EL1, 2576 .sign = FTR_UNSIGNED, 2577 .field_pos = ID_AA64PFR1_SME_SHIFT, 2578 .field_width = 4, 2579 .min_field_value = ID_AA64PFR1_SME, 2580 .matches = has_cpuid_feature, 2581 .cpu_enable = sme_kernel_enable, 2582 }, 2583 /* FA64 should be sorted after the base SME capability */ 2584 { 2585 .desc = "FA64", 2586 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2587 .capability = ARM64_SME_FA64, 2588 .sys_reg = SYS_ID_AA64SMFR0_EL1, 2589 .sign = FTR_UNSIGNED, 2590 .field_pos = ID_AA64SMFR0_EL1_FA64_SHIFT, 2591 .field_width = 1, 2592 .min_field_value = ID_AA64SMFR0_EL1_FA64_IMP, 2593 .matches = has_cpuid_feature, 2594 .cpu_enable = fa64_kernel_enable, 2595 }, 2596 #endif /* CONFIG_ARM64_SME */ 2597 { 2598 .desc = "WFx with timeout", 2599 .capability = ARM64_HAS_WFXT, 2600 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2601 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2602 .sign = FTR_UNSIGNED, 2603 .field_pos = ID_AA64ISAR2_EL1_WFxT_SHIFT, 2604 .field_width = 4, 2605 .matches = has_cpuid_feature, 2606 .min_field_value = ID_AA64ISAR2_EL1_WFxT_IMP, 2607 }, 2608 { 2609 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2610 .capability = ARM64_HAS_TIDCP1, 2611 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2612 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2613 .sign = FTR_UNSIGNED, 2614 .field_pos = ID_AA64MMFR1_TIDCP1_SHIFT, 2615 .field_width = 4, 2616 .min_field_value = ID_AA64MMFR1_TIDCP1_IMP, 2617 .matches = has_cpuid_feature, 2618 .cpu_enable = cpu_trap_el0_impdef, 2619 }, 2620 {}, 2621 }; 2622 2623 #define HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ 2624 .matches = has_cpuid_feature, \ 2625 .sys_reg = reg, \ 2626 .field_pos = field, \ 2627 .field_width = width, \ 2628 .sign = s, \ 2629 .min_field_value = min_value, 2630 2631 #define __HWCAP_CAP(name, cap_type, cap) \ 2632 .desc = name, \ 2633 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2634 .hwcap_type = cap_type, \ 2635 .hwcap = cap, \ 2636 2637 #define HWCAP_CAP(reg, field, width, s, min_value, cap_type, cap) \ 2638 { \ 2639 __HWCAP_CAP(#cap, cap_type, cap) \ 2640 HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ 2641 } 2642 2643 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2644 { \ 2645 __HWCAP_CAP(#cap, cap_type, cap) \ 2646 .matches = cpucap_multi_entry_cap_matches, \ 2647 .match_list = list, \ 2648 } 2649 2650 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2651 { \ 2652 __HWCAP_CAP(#cap, cap_type, cap) \ 2653 .matches = match, \ 2654 } 2655 2656 #ifdef CONFIG_ARM64_PTR_AUTH 2657 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2658 { 2659 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_APA_SHIFT, 2660 4, FTR_UNSIGNED, 2661 ID_AA64ISAR1_EL1_APA_PAuth) 2662 }, 2663 { 2664 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_APA3_SHIFT, 2665 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_APA3_PAuth) 2666 }, 2667 { 2668 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT, 2669 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_API_PAuth) 2670 }, 2671 {}, 2672 }; 2673 2674 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2675 { 2676 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPA_SHIFT, 2677 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP) 2678 }, 2679 { 2680 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_GPA3_SHIFT, 2681 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_GPA3_IMP) 2682 }, 2683 { 2684 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT, 2685 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPI_IMP) 2686 }, 2687 {}, 2688 }; 2689 #endif 2690 2691 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2692 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2693 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2694 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2695 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2696 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2697 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2698 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2699 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2700 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2701 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2702 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2703 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2704 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2705 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2706 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2707 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2708 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2709 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2710 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2711 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2712 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2713 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2714 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2715 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2716 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2717 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2718 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2719 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2720 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2721 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2722 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_EBF16), 2723 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2724 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2725 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2726 #ifdef CONFIG_ARM64_SVE 2727 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 2728 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2729 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2730 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2731 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BitPerm_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2732 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BF16_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2733 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SHA3_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2734 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SM4_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2735 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_I8MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2736 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F32MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2737 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F64MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2738 #endif 2739 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2740 #ifdef CONFIG_ARM64_BTI 2741 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI), 2742 #endif 2743 #ifdef CONFIG_ARM64_PTR_AUTH 2744 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2745 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2746 #endif 2747 #ifdef CONFIG_ARM64_MTE 2748 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE), 2749 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3), 2750 #endif /* CONFIG_ARM64_MTE */ 2751 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), 2752 HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), 2753 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), 2754 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 2755 #ifdef CONFIG_ARM64_SME 2756 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME), 2757 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 2758 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I16I64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 2759 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F64F64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 2760 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I8I32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 2761 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 2762 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_B16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 2763 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F32F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 2764 #endif /* CONFIG_ARM64_SME */ 2765 {}, 2766 }; 2767 2768 #ifdef CONFIG_COMPAT 2769 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2770 { 2771 /* 2772 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2773 * in line with that of arm32 as in vfp_init(). We make sure that the 2774 * check is future proof, by making sure value is non-zero. 2775 */ 2776 u32 mvfr1; 2777 2778 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2779 if (scope == SCOPE_SYSTEM) 2780 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2781 else 2782 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2783 2784 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2785 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2786 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2787 } 2788 #endif 2789 2790 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2791 #ifdef CONFIG_COMPAT 2792 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2793 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2794 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2795 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2796 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2797 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2798 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2799 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2800 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2801 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2802 #endif 2803 {}, 2804 }; 2805 2806 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2807 { 2808 switch (cap->hwcap_type) { 2809 case CAP_HWCAP: 2810 cpu_set_feature(cap->hwcap); 2811 break; 2812 #ifdef CONFIG_COMPAT 2813 case CAP_COMPAT_HWCAP: 2814 compat_elf_hwcap |= (u32)cap->hwcap; 2815 break; 2816 case CAP_COMPAT_HWCAP2: 2817 compat_elf_hwcap2 |= (u32)cap->hwcap; 2818 break; 2819 #endif 2820 default: 2821 WARN_ON(1); 2822 break; 2823 } 2824 } 2825 2826 /* Check if we have a particular HWCAP enabled */ 2827 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2828 { 2829 bool rc; 2830 2831 switch (cap->hwcap_type) { 2832 case CAP_HWCAP: 2833 rc = cpu_have_feature(cap->hwcap); 2834 break; 2835 #ifdef CONFIG_COMPAT 2836 case CAP_COMPAT_HWCAP: 2837 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2838 break; 2839 case CAP_COMPAT_HWCAP2: 2840 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2841 break; 2842 #endif 2843 default: 2844 WARN_ON(1); 2845 rc = false; 2846 } 2847 2848 return rc; 2849 } 2850 2851 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2852 { 2853 /* We support emulation of accesses to CPU ID feature registers */ 2854 cpu_set_named_feature(CPUID); 2855 for (; hwcaps->matches; hwcaps++) 2856 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2857 cap_set_elf_hwcap(hwcaps); 2858 } 2859 2860 static void update_cpu_capabilities(u16 scope_mask) 2861 { 2862 int i; 2863 const struct arm64_cpu_capabilities *caps; 2864 2865 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2866 for (i = 0; i < ARM64_NCAPS; i++) { 2867 caps = cpu_hwcaps_ptrs[i]; 2868 if (!caps || !(caps->type & scope_mask) || 2869 cpus_have_cap(caps->capability) || 2870 !caps->matches(caps, cpucap_default_scope(caps))) 2871 continue; 2872 2873 if (caps->desc) 2874 pr_info("detected: %s\n", caps->desc); 2875 cpus_set_cap(caps->capability); 2876 2877 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2878 set_bit(caps->capability, boot_capabilities); 2879 } 2880 } 2881 2882 /* 2883 * Enable all the available capabilities on this CPU. The capabilities 2884 * with BOOT_CPU scope are handled separately and hence skipped here. 2885 */ 2886 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2887 { 2888 int i; 2889 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2890 2891 for_each_available_cap(i) { 2892 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2893 2894 if (WARN_ON(!cap)) 2895 continue; 2896 2897 if (!(cap->type & non_boot_scope)) 2898 continue; 2899 2900 if (cap->cpu_enable) 2901 cap->cpu_enable(cap); 2902 } 2903 return 0; 2904 } 2905 2906 /* 2907 * Run through the enabled capabilities and enable() it on all active 2908 * CPUs 2909 */ 2910 static void __init enable_cpu_capabilities(u16 scope_mask) 2911 { 2912 int i; 2913 const struct arm64_cpu_capabilities *caps; 2914 bool boot_scope; 2915 2916 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2917 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2918 2919 for (i = 0; i < ARM64_NCAPS; i++) { 2920 unsigned int num; 2921 2922 caps = cpu_hwcaps_ptrs[i]; 2923 if (!caps || !(caps->type & scope_mask)) 2924 continue; 2925 num = caps->capability; 2926 if (!cpus_have_cap(num)) 2927 continue; 2928 2929 /* Ensure cpus_have_const_cap(num) works */ 2930 static_branch_enable(&cpu_hwcap_keys[num]); 2931 2932 if (boot_scope && caps->cpu_enable) 2933 /* 2934 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2935 * before any secondary CPU boots. Thus, each secondary 2936 * will enable the capability as appropriate via 2937 * check_local_cpu_capabilities(). The only exception is 2938 * the boot CPU, for which the capability must be 2939 * enabled here. This approach avoids costly 2940 * stop_machine() calls for this case. 2941 */ 2942 caps->cpu_enable(caps); 2943 } 2944 2945 /* 2946 * For all non-boot scope capabilities, use stop_machine() 2947 * as it schedules the work allowing us to modify PSTATE, 2948 * instead of on_each_cpu() which uses an IPI, giving us a 2949 * PSTATE that disappears when we return. 2950 */ 2951 if (!boot_scope) 2952 stop_machine(cpu_enable_non_boot_scope_capabilities, 2953 NULL, cpu_online_mask); 2954 } 2955 2956 /* 2957 * Run through the list of capabilities to check for conflicts. 2958 * If the system has already detected a capability, take necessary 2959 * action on this CPU. 2960 */ 2961 static void verify_local_cpu_caps(u16 scope_mask) 2962 { 2963 int i; 2964 bool cpu_has_cap, system_has_cap; 2965 const struct arm64_cpu_capabilities *caps; 2966 2967 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2968 2969 for (i = 0; i < ARM64_NCAPS; i++) { 2970 caps = cpu_hwcaps_ptrs[i]; 2971 if (!caps || !(caps->type & scope_mask)) 2972 continue; 2973 2974 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2975 system_has_cap = cpus_have_cap(caps->capability); 2976 2977 if (system_has_cap) { 2978 /* 2979 * Check if the new CPU misses an advertised feature, 2980 * which is not safe to miss. 2981 */ 2982 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 2983 break; 2984 /* 2985 * We have to issue cpu_enable() irrespective of 2986 * whether the CPU has it or not, as it is enabeld 2987 * system wide. It is upto the call back to take 2988 * appropriate action on this CPU. 2989 */ 2990 if (caps->cpu_enable) 2991 caps->cpu_enable(caps); 2992 } else { 2993 /* 2994 * Check if the CPU has this capability if it isn't 2995 * safe to have when the system doesn't. 2996 */ 2997 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 2998 break; 2999 } 3000 } 3001 3002 if (i < ARM64_NCAPS) { 3003 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3004 smp_processor_id(), caps->capability, 3005 caps->desc, system_has_cap, cpu_has_cap); 3006 3007 if (cpucap_panic_on_conflict(caps)) 3008 cpu_panic_kernel(); 3009 else 3010 cpu_die_early(); 3011 } 3012 } 3013 3014 /* 3015 * Check for CPU features that are used in early boot 3016 * based on the Boot CPU value. 3017 */ 3018 static void check_early_cpu_features(void) 3019 { 3020 verify_cpu_asid_bits(); 3021 3022 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3023 } 3024 3025 static void 3026 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3027 { 3028 3029 for (; caps->matches; caps++) 3030 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3031 pr_crit("CPU%d: missing HWCAP: %s\n", 3032 smp_processor_id(), caps->desc); 3033 cpu_die_early(); 3034 } 3035 } 3036 3037 static void verify_local_elf_hwcaps(void) 3038 { 3039 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3040 3041 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3042 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3043 } 3044 3045 static void verify_sve_features(void) 3046 { 3047 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 3048 u64 zcr = read_zcr_features(); 3049 3050 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 3051 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 3052 3053 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) { 3054 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3055 smp_processor_id()); 3056 cpu_die_early(); 3057 } 3058 3059 /* Add checks on other ZCR bits here if necessary */ 3060 } 3061 3062 static void verify_sme_features(void) 3063 { 3064 u64 safe_smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1); 3065 u64 smcr = read_smcr_features(); 3066 3067 unsigned int safe_len = safe_smcr & SMCR_ELx_LEN_MASK; 3068 unsigned int len = smcr & SMCR_ELx_LEN_MASK; 3069 3070 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SME)) { 3071 pr_crit("CPU%d: SME: vector length support mismatch\n", 3072 smp_processor_id()); 3073 cpu_die_early(); 3074 } 3075 3076 /* Add checks on other SMCR bits here if necessary */ 3077 } 3078 3079 static void verify_hyp_capabilities(void) 3080 { 3081 u64 safe_mmfr1, mmfr0, mmfr1; 3082 int parange, ipa_max; 3083 unsigned int safe_vmid_bits, vmid_bits; 3084 3085 if (!IS_ENABLED(CONFIG_KVM)) 3086 return; 3087 3088 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3089 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 3090 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3091 3092 /* Verify VMID bits */ 3093 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3094 vmid_bits = get_vmid_bits(mmfr1); 3095 if (vmid_bits < safe_vmid_bits) { 3096 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3097 cpu_die_early(); 3098 } 3099 3100 /* Verify IPA range */ 3101 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3102 ID_AA64MMFR0_PARANGE_SHIFT); 3103 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3104 if (ipa_max < get_kvm_ipa_limit()) { 3105 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3106 cpu_die_early(); 3107 } 3108 } 3109 3110 /* 3111 * Run through the enabled system capabilities and enable() it on this CPU. 3112 * The capabilities were decided based on the available CPUs at the boot time. 3113 * Any new CPU should match the system wide status of the capability. If the 3114 * new CPU doesn't have a capability which the system now has enabled, we 3115 * cannot do anything to fix it up and could cause unexpected failures. So 3116 * we park the CPU. 3117 */ 3118 static void verify_local_cpu_capabilities(void) 3119 { 3120 /* 3121 * The capabilities with SCOPE_BOOT_CPU are checked from 3122 * check_early_cpu_features(), as they need to be verified 3123 * on all secondary CPUs. 3124 */ 3125 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3126 verify_local_elf_hwcaps(); 3127 3128 if (system_supports_sve()) 3129 verify_sve_features(); 3130 3131 if (system_supports_sme()) 3132 verify_sme_features(); 3133 3134 if (is_hyp_mode_available()) 3135 verify_hyp_capabilities(); 3136 } 3137 3138 void check_local_cpu_capabilities(void) 3139 { 3140 /* 3141 * All secondary CPUs should conform to the early CPU features 3142 * in use by the kernel based on boot CPU. 3143 */ 3144 check_early_cpu_features(); 3145 3146 /* 3147 * If we haven't finalised the system capabilities, this CPU gets 3148 * a chance to update the errata work arounds and local features. 3149 * Otherwise, this CPU should verify that it has all the system 3150 * advertised capabilities. 3151 */ 3152 if (!system_capabilities_finalized()) 3153 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3154 else 3155 verify_local_cpu_capabilities(); 3156 } 3157 3158 static void __init setup_boot_cpu_capabilities(void) 3159 { 3160 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 3161 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3162 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 3163 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3164 } 3165 3166 bool this_cpu_has_cap(unsigned int n) 3167 { 3168 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3169 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 3170 3171 if (cap) 3172 return cap->matches(cap, SCOPE_LOCAL_CPU); 3173 } 3174 3175 return false; 3176 } 3177 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3178 3179 /* 3180 * This helper function is used in a narrow window when, 3181 * - The system wide safe registers are set with all the SMP CPUs and, 3182 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 3183 * In all other cases cpus_have_{const_}cap() should be used. 3184 */ 3185 static bool __maybe_unused __system_matches_cap(unsigned int n) 3186 { 3187 if (n < ARM64_NCAPS) { 3188 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 3189 3190 if (cap) 3191 return cap->matches(cap, SCOPE_SYSTEM); 3192 } 3193 return false; 3194 } 3195 3196 void cpu_set_feature(unsigned int num) 3197 { 3198 set_bit(num, elf_hwcap); 3199 } 3200 3201 bool cpu_have_feature(unsigned int num) 3202 { 3203 return test_bit(num, elf_hwcap); 3204 } 3205 EXPORT_SYMBOL_GPL(cpu_have_feature); 3206 3207 unsigned long cpu_get_elf_hwcap(void) 3208 { 3209 /* 3210 * We currently only populate the first 32 bits of AT_HWCAP. Please 3211 * note that for userspace compatibility we guarantee that bits 62 3212 * and 63 will always be returned as 0. 3213 */ 3214 return elf_hwcap[0]; 3215 } 3216 3217 unsigned long cpu_get_elf_hwcap2(void) 3218 { 3219 return elf_hwcap[1]; 3220 } 3221 3222 static void __init setup_system_capabilities(void) 3223 { 3224 /* 3225 * We have finalised the system-wide safe feature 3226 * registers, finalise the capabilities that depend 3227 * on it. Also enable all the available capabilities, 3228 * that are not enabled already. 3229 */ 3230 update_cpu_capabilities(SCOPE_SYSTEM); 3231 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3232 } 3233 3234 void __init setup_cpu_features(void) 3235 { 3236 u32 cwg; 3237 3238 setup_system_capabilities(); 3239 setup_elf_hwcaps(arm64_elf_hwcaps); 3240 3241 if (system_supports_32bit_el0()) { 3242 setup_elf_hwcaps(compat_elf_hwcaps); 3243 elf_hwcap_fixup(); 3244 } 3245 3246 if (system_uses_ttbr0_pan()) 3247 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3248 3249 sve_setup(); 3250 sme_setup(); 3251 minsigstksz_setup(); 3252 3253 /* Advertise that we have computed the system capabilities */ 3254 finalize_system_capabilities(); 3255 3256 /* 3257 * Check for sane CTR_EL0.CWG value. 3258 */ 3259 cwg = cache_type_cwg(); 3260 if (!cwg) 3261 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3262 ARCH_DMA_MINALIGN); 3263 } 3264 3265 static int enable_mismatched_32bit_el0(unsigned int cpu) 3266 { 3267 /* 3268 * The first 32-bit-capable CPU we detected and so can no longer 3269 * be offlined by userspace. -1 indicates we haven't yet onlined 3270 * a 32-bit-capable CPU. 3271 */ 3272 static int lucky_winner = -1; 3273 3274 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3275 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3276 3277 if (cpu_32bit) { 3278 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3279 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3280 } 3281 3282 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3283 return 0; 3284 3285 if (lucky_winner >= 0) 3286 return 0; 3287 3288 /* 3289 * We've detected a mismatch. We need to keep one of our CPUs with 3290 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3291 * every CPU in the system for a 32-bit task. 3292 */ 3293 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3294 cpu_active_mask); 3295 get_cpu_device(lucky_winner)->offline_disabled = true; 3296 setup_elf_hwcaps(compat_elf_hwcaps); 3297 elf_hwcap_fixup(); 3298 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3299 cpu, lucky_winner); 3300 return 0; 3301 } 3302 3303 static int __init init_32bit_el0_mask(void) 3304 { 3305 if (!allow_mismatched_32bit_el0) 3306 return 0; 3307 3308 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3309 return -ENOMEM; 3310 3311 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3312 "arm64/mismatched_32bit_el0:online", 3313 enable_mismatched_32bit_el0, NULL); 3314 } 3315 subsys_initcall_sync(init_32bit_el0_mask); 3316 3317 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3318 { 3319 cpu_replace_ttbr1(lm_alias(swapper_pg_dir), idmap_pg_dir); 3320 } 3321 3322 /* 3323 * We emulate only the following system register space. 3324 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 3325 * See Table C5-6 System instruction encodings for System register accesses, 3326 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3327 */ 3328 static inline bool __attribute_const__ is_emulated(u32 id) 3329 { 3330 return (sys_reg_Op0(id) == 0x3 && 3331 sys_reg_CRn(id) == 0x0 && 3332 sys_reg_Op1(id) == 0x0 && 3333 (sys_reg_CRm(id) == 0 || 3334 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 3335 } 3336 3337 /* 3338 * With CRm == 0, reg should be one of : 3339 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3340 */ 3341 static inline int emulate_id_reg(u32 id, u64 *valp) 3342 { 3343 switch (id) { 3344 case SYS_MIDR_EL1: 3345 *valp = read_cpuid_id(); 3346 break; 3347 case SYS_MPIDR_EL1: 3348 *valp = SYS_MPIDR_SAFE_VAL; 3349 break; 3350 case SYS_REVIDR_EL1: 3351 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3352 *valp = 0; 3353 break; 3354 default: 3355 return -EINVAL; 3356 } 3357 3358 return 0; 3359 } 3360 3361 static int emulate_sys_reg(u32 id, u64 *valp) 3362 { 3363 struct arm64_ftr_reg *regp; 3364 3365 if (!is_emulated(id)) 3366 return -EINVAL; 3367 3368 if (sys_reg_CRm(id) == 0) 3369 return emulate_id_reg(id, valp); 3370 3371 regp = get_arm64_ftr_reg_nowarn(id); 3372 if (regp) 3373 *valp = arm64_ftr_reg_user_value(regp); 3374 else 3375 /* 3376 * The untracked registers are either IMPLEMENTATION DEFINED 3377 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3378 */ 3379 *valp = 0; 3380 return 0; 3381 } 3382 3383 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3384 { 3385 int rc; 3386 u64 val; 3387 3388 rc = emulate_sys_reg(sys_reg, &val); 3389 if (!rc) { 3390 pt_regs_write_reg(regs, rt, val); 3391 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3392 } 3393 return rc; 3394 } 3395 3396 static int emulate_mrs(struct pt_regs *regs, u32 insn) 3397 { 3398 u32 sys_reg, rt; 3399 3400 /* 3401 * sys_reg values are defined as used in mrs/msr instruction. 3402 * shift the imm value to get the encoding. 3403 */ 3404 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3405 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3406 return do_emulate_mrs(regs, sys_reg, rt); 3407 } 3408 3409 static struct undef_hook mrs_hook = { 3410 .instr_mask = 0xffff0000, 3411 .instr_val = 0xd5380000, 3412 .pstate_mask = PSR_AA32_MODE_MASK, 3413 .pstate_val = PSR_MODE_EL0t, 3414 .fn = emulate_mrs, 3415 }; 3416 3417 static int __init enable_mrs_emulation(void) 3418 { 3419 register_undef_hook(&mrs_hook); 3420 return 0; 3421 } 3422 3423 core_initcall(enable_mrs_emulation); 3424 3425 enum mitigation_state arm64_get_meltdown_state(void) 3426 { 3427 if (__meltdown_safe) 3428 return SPECTRE_UNAFFECTED; 3429 3430 if (arm64_kernel_unmapped_at_el0()) 3431 return SPECTRE_MITIGATED; 3432 3433 return SPECTRE_VULNERABLE; 3434 } 3435 3436 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3437 char *buf) 3438 { 3439 switch (arm64_get_meltdown_state()) { 3440 case SPECTRE_UNAFFECTED: 3441 return sprintf(buf, "Not affected\n"); 3442 3443 case SPECTRE_MITIGATED: 3444 return sprintf(buf, "Mitigation: PTI\n"); 3445 3446 default: 3447 return sprintf(buf, "Vulnerable\n"); 3448 } 3449 } 3450