1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Brad Volkin <bradley.d.volkin@intel.com> 25 * 26 */ 27 28 #include <drm/drm_cache.h> 29 30 #include "gt/intel_engine.h" 31 #include "gt/intel_engine_regs.h" 32 #include "gt/intel_gpu_commands.h" 33 #include "gt/intel_gt_regs.h" 34 35 #include "i915_cmd_parser.h" 36 #include "i915_drv.h" 37 #include "i915_memcpy.h" 38 #include "i915_reg.h" 39 40 /** 41 * DOC: batch buffer command parser 42 * 43 * Motivation: 44 * Certain OpenGL features (e.g. transform feedback, performance monitoring) 45 * require userspace code to submit batches containing commands such as 46 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some 47 * generations of the hardware will noop these commands in "unsecure" batches 48 * (which includes all userspace batches submitted via i915) even though the 49 * commands may be safe and represent the intended programming model of the 50 * device. 51 * 52 * The software command parser is similar in operation to the command parsing 53 * done in hardware for unsecure batches. However, the software parser allows 54 * some operations that would be noop'd by hardware, if the parser determines 55 * the operation is safe, and submits the batch as "secure" to prevent hardware 56 * parsing. 57 * 58 * Threats: 59 * At a high level, the hardware (and software) checks attempt to prevent 60 * granting userspace undue privileges. There are three categories of privilege. 61 * 62 * First, commands which are explicitly defined as privileged or which should 63 * only be used by the kernel driver. The parser rejects such commands 64 * 65 * Second, commands which access registers. To support correct/enhanced 66 * userspace functionality, particularly certain OpenGL extensions, the parser 67 * provides a whitelist of registers which userspace may safely access 68 * 69 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc). 70 * The parser always rejects such commands. 71 * 72 * The majority of the problematic commands fall in the MI_* range, with only a 73 * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW). 74 * 75 * Implementation: 76 * Each engine maintains tables of commands and registers which the parser 77 * uses in scanning batch buffers submitted to that engine. 78 * 79 * Since the set of commands that the parser must check for is significantly 80 * smaller than the number of commands supported, the parser tables contain only 81 * those commands required by the parser. This generally works because command 82 * opcode ranges have standard command length encodings. So for commands that 83 * the parser does not need to check, it can easily skip them. This is 84 * implemented via a per-engine length decoding vfunc. 85 * 86 * Unfortunately, there are a number of commands that do not follow the standard 87 * length encoding for their opcode range, primarily amongst the MI_* commands. 88 * To handle this, the parser provides a way to define explicit "skip" entries 89 * in the per-engine command tables. 90 * 91 * Other command table entries map fairly directly to high level categories 92 * mentioned above: rejected, register whitelist. The parser implements a number 93 * of checks, including the privileged memory checks, via a general bitmasking 94 * mechanism. 95 */ 96 97 /* 98 * A command that requires special handling by the command parser. 99 */ 100 struct drm_i915_cmd_descriptor { 101 /* 102 * Flags describing how the command parser processes the command. 103 * 104 * CMD_DESC_FIXED: The command has a fixed length if this is set, 105 * a length mask if not set 106 * CMD_DESC_SKIP: The command is allowed but does not follow the 107 * standard length encoding for the opcode range in 108 * which it falls 109 * CMD_DESC_REJECT: The command is never allowed 110 * CMD_DESC_REGISTER: The command should be checked against the 111 * register whitelist for the appropriate ring 112 */ 113 u32 flags; 114 #define CMD_DESC_FIXED (1<<0) 115 #define CMD_DESC_SKIP (1<<1) 116 #define CMD_DESC_REJECT (1<<2) 117 #define CMD_DESC_REGISTER (1<<3) 118 #define CMD_DESC_BITMASK (1<<4) 119 120 /* 121 * The command's unique identification bits and the bitmask to get them. 122 * This isn't strictly the opcode field as defined in the spec and may 123 * also include type, subtype, and/or subop fields. 124 */ 125 struct { 126 u32 value; 127 u32 mask; 128 } cmd; 129 130 /* 131 * The command's length. The command is either fixed length (i.e. does 132 * not include a length field) or has a length field mask. The flag 133 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has 134 * a length mask. All command entries in a command table must include 135 * length information. 136 */ 137 union { 138 u32 fixed; 139 u32 mask; 140 } length; 141 142 /* 143 * Describes where to find a register address in the command to check 144 * against the ring's register whitelist. Only valid if flags has the 145 * CMD_DESC_REGISTER bit set. 146 * 147 * A non-zero step value implies that the command may access multiple 148 * registers in sequence (e.g. LRI), in that case step gives the 149 * distance in dwords between individual offset fields. 150 */ 151 struct { 152 u32 offset; 153 u32 mask; 154 u32 step; 155 } reg; 156 157 #define MAX_CMD_DESC_BITMASKS 3 158 /* 159 * Describes command checks where a particular dword is masked and 160 * compared against an expected value. If the command does not match 161 * the expected value, the parser rejects it. Only valid if flags has 162 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero 163 * are valid. 164 * 165 * If the check specifies a non-zero condition_mask then the parser 166 * only performs the check when the bits specified by condition_mask 167 * are non-zero. 168 */ 169 struct { 170 u32 offset; 171 u32 mask; 172 u32 expected; 173 u32 condition_offset; 174 u32 condition_mask; 175 } bits[MAX_CMD_DESC_BITMASKS]; 176 }; 177 178 /* 179 * A table of commands requiring special handling by the command parser. 180 * 181 * Each engine has an array of tables. Each table consists of an array of 182 * command descriptors, which must be sorted with command opcodes in 183 * ascending order. 184 */ 185 struct drm_i915_cmd_table { 186 const struct drm_i915_cmd_descriptor *table; 187 int count; 188 }; 189 190 #define STD_MI_OPCODE_SHIFT (32 - 9) 191 #define STD_3D_OPCODE_SHIFT (32 - 16) 192 #define STD_2D_OPCODE_SHIFT (32 - 10) 193 #define STD_MFX_OPCODE_SHIFT (32 - 16) 194 #define MIN_OPCODE_SHIFT 16 195 196 #define CMD(op, opm, f, lm, fl, ...) \ 197 { \ 198 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \ 199 .cmd = { (op & ~0u << (opm)), ~0u << (opm) }, \ 200 .length = { (lm) }, \ 201 __VA_ARGS__ \ 202 } 203 204 /* Convenience macros to compress the tables */ 205 #define SMI STD_MI_OPCODE_SHIFT 206 #define S3D STD_3D_OPCODE_SHIFT 207 #define S2D STD_2D_OPCODE_SHIFT 208 #define SMFX STD_MFX_OPCODE_SHIFT 209 #define F true 210 #define S CMD_DESC_SKIP 211 #define R CMD_DESC_REJECT 212 #define W CMD_DESC_REGISTER 213 #define B CMD_DESC_BITMASK 214 215 /* Command Mask Fixed Len Action 216 ---------------------------------------------------------- */ 217 static const struct drm_i915_cmd_descriptor gen7_common_cmds[] = { 218 CMD( MI_NOOP, SMI, F, 1, S ), 219 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ), 220 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ), 221 CMD( MI_ARB_CHECK, SMI, F, 1, S ), 222 CMD( MI_REPORT_HEAD, SMI, F, 1, S ), 223 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), 224 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ), 225 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), 226 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, 227 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), 228 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B, 229 .reg = { .offset = 1, .mask = 0x007FFFFC }, 230 .bits = {{ 231 .offset = 0, 232 .mask = MI_GLOBAL_GTT, 233 .expected = 0, 234 }}, ), 235 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B, 236 .reg = { .offset = 1, .mask = 0x007FFFFC }, 237 .bits = {{ 238 .offset = 0, 239 .mask = MI_GLOBAL_GTT, 240 .expected = 0, 241 }}, ), 242 /* 243 * MI_BATCH_BUFFER_START requires some special handling. It's not 244 * really a 'skip' action but it doesn't seem like it's worth adding 245 * a new action. See intel_engine_cmd_parser(). 246 */ 247 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), 248 }; 249 250 static const struct drm_i915_cmd_descriptor gen7_render_cmds[] = { 251 CMD( MI_FLUSH, SMI, F, 1, S ), 252 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 253 CMD( MI_PREDICATE, SMI, F, 1, S ), 254 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), 255 CMD( MI_SET_APPID, SMI, F, 1, S ), 256 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 257 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ), 258 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), 259 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B, 260 .bits = {{ 261 .offset = 0, 262 .mask = MI_GLOBAL_GTT, 263 .expected = 0, 264 }}, ), 265 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ), 266 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B, 267 .bits = {{ 268 .offset = 0, 269 .mask = MI_GLOBAL_GTT, 270 .expected = 0, 271 }}, ), 272 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B, 273 .bits = {{ 274 .offset = 1, 275 .mask = MI_REPORT_PERF_COUNT_GGTT, 276 .expected = 0, 277 }}, ), 278 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 279 .bits = {{ 280 .offset = 0, 281 .mask = MI_GLOBAL_GTT, 282 .expected = 0, 283 }}, ), 284 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), 285 CMD( PIPELINE_SELECT, S3D, F, 1, S ), 286 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B, 287 .bits = {{ 288 .offset = 2, 289 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK, 290 .expected = 0, 291 }}, ), 292 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ), 293 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ), 294 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ), 295 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B, 296 .bits = {{ 297 .offset = 1, 298 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY), 299 .expected = 0, 300 }, 301 { 302 .offset = 1, 303 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB | 304 PIPE_CONTROL_STORE_DATA_INDEX), 305 .expected = 0, 306 .condition_offset = 1, 307 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK, 308 }}, ), 309 }; 310 311 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { 312 CMD( MI_SET_PREDICATE, SMI, F, 1, S ), 313 CMD( MI_RS_CONTROL, SMI, F, 1, S ), 314 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), 315 CMD( MI_SET_APPID, SMI, F, 1, S ), 316 CMD( MI_RS_CONTEXT, SMI, F, 1, S ), 317 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ), 318 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 319 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W, 320 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ), 321 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), 322 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), 323 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), 324 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ), 325 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ), 326 327 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ), 328 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ), 329 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ), 330 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ), 331 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ), 332 }; 333 334 static const struct drm_i915_cmd_descriptor gen7_video_cmds[] = { 335 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 336 CMD( MI_SET_APPID, SMI, F, 1, S ), 337 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 338 .bits = {{ 339 .offset = 0, 340 .mask = MI_GLOBAL_GTT, 341 .expected = 0, 342 }}, ), 343 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 344 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 345 .bits = {{ 346 .offset = 0, 347 .mask = MI_FLUSH_DW_NOTIFY, 348 .expected = 0, 349 }, 350 { 351 .offset = 1, 352 .mask = MI_FLUSH_DW_USE_GTT, 353 .expected = 0, 354 .condition_offset = 0, 355 .condition_mask = MI_FLUSH_DW_OP_MASK, 356 }, 357 { 358 .offset = 0, 359 .mask = MI_FLUSH_DW_STORE_INDEX, 360 .expected = 0, 361 .condition_offset = 0, 362 .condition_mask = MI_FLUSH_DW_OP_MASK, 363 }}, ), 364 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 365 .bits = {{ 366 .offset = 0, 367 .mask = MI_GLOBAL_GTT, 368 .expected = 0, 369 }}, ), 370 /* 371 * MFX_WAIT doesn't fit the way we handle length for most commands. 372 * It has a length field but it uses a non-standard length bias. 373 * It is always 1 dword though, so just treat it as fixed length. 374 */ 375 CMD( MFX_WAIT, SMFX, F, 1, S ), 376 }; 377 378 static const struct drm_i915_cmd_descriptor gen7_vecs_cmds[] = { 379 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 380 CMD( MI_SET_APPID, SMI, F, 1, S ), 381 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 382 .bits = {{ 383 .offset = 0, 384 .mask = MI_GLOBAL_GTT, 385 .expected = 0, 386 }}, ), 387 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 388 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 389 .bits = {{ 390 .offset = 0, 391 .mask = MI_FLUSH_DW_NOTIFY, 392 .expected = 0, 393 }, 394 { 395 .offset = 1, 396 .mask = MI_FLUSH_DW_USE_GTT, 397 .expected = 0, 398 .condition_offset = 0, 399 .condition_mask = MI_FLUSH_DW_OP_MASK, 400 }, 401 { 402 .offset = 0, 403 .mask = MI_FLUSH_DW_STORE_INDEX, 404 .expected = 0, 405 .condition_offset = 0, 406 .condition_mask = MI_FLUSH_DW_OP_MASK, 407 }}, ), 408 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 409 .bits = {{ 410 .offset = 0, 411 .mask = MI_GLOBAL_GTT, 412 .expected = 0, 413 }}, ), 414 }; 415 416 static const struct drm_i915_cmd_descriptor gen7_blt_cmds[] = { 417 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 418 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B, 419 .bits = {{ 420 .offset = 0, 421 .mask = MI_GLOBAL_GTT, 422 .expected = 0, 423 }}, ), 424 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 425 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 426 .bits = {{ 427 .offset = 0, 428 .mask = MI_FLUSH_DW_NOTIFY, 429 .expected = 0, 430 }, 431 { 432 .offset = 1, 433 .mask = MI_FLUSH_DW_USE_GTT, 434 .expected = 0, 435 .condition_offset = 0, 436 .condition_mask = MI_FLUSH_DW_OP_MASK, 437 }, 438 { 439 .offset = 0, 440 .mask = MI_FLUSH_DW_STORE_INDEX, 441 .expected = 0, 442 .condition_offset = 0, 443 .condition_mask = MI_FLUSH_DW_OP_MASK, 444 }}, ), 445 CMD( COLOR_BLT, S2D, !F, 0x3F, S ), 446 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), 447 }; 448 449 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = { 450 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ), 451 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 452 }; 453 454 /* 455 * For Gen9 we can still rely on the h/w to enforce cmd security, and only 456 * need to re-enforce the register access checks. We therefore only need to 457 * teach the cmdparser how to find the end of each command, and identify 458 * register accesses. The table doesn't need to reject any commands, and so 459 * the only commands listed here are: 460 * 1) Those that touch registers 461 * 2) Those that do not have the default 8-bit length 462 * 463 * Note that the default MI length mask chosen for this table is 0xFF, not 464 * the 0x3F used on older devices. This is because the vast majority of MI 465 * cmds on Gen9 use a standard 8-bit Length field. 466 * All the Gen9 blitter instructions are standard 0xFF length mask, and 467 * none allow access to non-general registers, so in fact no BLT cmds are 468 * included in the table at all. 469 * 470 */ 471 static const struct drm_i915_cmd_descriptor gen9_blt_cmds[] = { 472 CMD( MI_NOOP, SMI, F, 1, S ), 473 CMD( MI_USER_INTERRUPT, SMI, F, 1, S ), 474 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ), 475 CMD( MI_FLUSH, SMI, F, 1, S ), 476 CMD( MI_ARB_CHECK, SMI, F, 1, S ), 477 CMD( MI_REPORT_HEAD, SMI, F, 1, S ), 478 CMD( MI_ARB_ON_OFF, SMI, F, 1, S ), 479 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), 480 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, S ), 481 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, S ), 482 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ), 483 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, 484 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), 485 CMD( MI_UPDATE_GTT, SMI, !F, 0x3FF, S ), 486 CMD( MI_STORE_REGISTER_MEM_GEN8, SMI, F, 4, W, 487 .reg = { .offset = 1, .mask = 0x007FFFFC } ), 488 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, S ), 489 CMD( MI_LOAD_REGISTER_MEM_GEN8, SMI, F, 4, W, 490 .reg = { .offset = 1, .mask = 0x007FFFFC } ), 491 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W, 492 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ), 493 494 /* 495 * We allow BB_START but apply further checks. We just sanitize the 496 * basic fields here. 497 */ 498 #define MI_BB_START_OPERAND_MASK GENMASK(SMI-1, 0) 499 #define MI_BB_START_OPERAND_EXPECT (MI_BATCH_PPGTT_HSW | 1) 500 CMD( MI_BATCH_BUFFER_START_GEN8, SMI, !F, 0xFF, B, 501 .bits = {{ 502 .offset = 0, 503 .mask = MI_BB_START_OPERAND_MASK, 504 .expected = MI_BB_START_OPERAND_EXPECT, 505 }}, ), 506 }; 507 508 static const struct drm_i915_cmd_descriptor noop_desc = 509 CMD(MI_NOOP, SMI, F, 1, S); 510 511 #undef CMD 512 #undef SMI 513 #undef S3D 514 #undef S2D 515 #undef SMFX 516 #undef F 517 #undef S 518 #undef R 519 #undef W 520 #undef B 521 522 static const struct drm_i915_cmd_table gen7_render_cmd_table[] = { 523 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 524 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) }, 525 }; 526 527 static const struct drm_i915_cmd_table hsw_render_ring_cmd_table[] = { 528 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 529 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) }, 530 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) }, 531 }; 532 533 static const struct drm_i915_cmd_table gen7_video_cmd_table[] = { 534 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 535 { gen7_video_cmds, ARRAY_SIZE(gen7_video_cmds) }, 536 }; 537 538 static const struct drm_i915_cmd_table hsw_vebox_cmd_table[] = { 539 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 540 { gen7_vecs_cmds, ARRAY_SIZE(gen7_vecs_cmds) }, 541 }; 542 543 static const struct drm_i915_cmd_table gen7_blt_cmd_table[] = { 544 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 545 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) }, 546 }; 547 548 static const struct drm_i915_cmd_table hsw_blt_ring_cmd_table[] = { 549 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 550 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) }, 551 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) }, 552 }; 553 554 static const struct drm_i915_cmd_table gen9_blt_cmd_table[] = { 555 { gen9_blt_cmds, ARRAY_SIZE(gen9_blt_cmds) }, 556 }; 557 558 559 /* 560 * Register whitelists, sorted by increasing register offset. 561 */ 562 563 /* 564 * An individual whitelist entry granting access to register addr. If 565 * mask is non-zero the argument of immediate register writes will be 566 * AND-ed with mask, and the command will be rejected if the result 567 * doesn't match value. 568 * 569 * Registers with non-zero mask are only allowed to be written using 570 * LRI. 571 */ 572 struct drm_i915_reg_descriptor { 573 i915_reg_t addr; 574 u32 mask; 575 u32 value; 576 }; 577 578 /* Convenience macro for adding 32-bit registers. */ 579 #define REG32(_reg, ...) \ 580 { .addr = (_reg), __VA_ARGS__ } 581 582 #define REG32_IDX(_reg, idx) \ 583 { .addr = _reg(idx) } 584 585 /* 586 * Convenience macro for adding 64-bit registers. 587 * 588 * Some registers that userspace accesses are 64 bits. The register 589 * access commands only allow 32-bit accesses. Hence, we have to include 590 * entries for both halves of the 64-bit registers. 591 */ 592 #define REG64(_reg) \ 593 { .addr = _reg }, \ 594 { .addr = _reg ## _UDW } 595 596 #define REG64_IDX(_reg, idx) \ 597 { .addr = _reg(idx) }, \ 598 { .addr = _reg ## _UDW(idx) } 599 600 #define REG64_BASE_IDX(_reg, base, idx) \ 601 { .addr = _reg(base, idx) }, \ 602 { .addr = _reg ## _UDW(base, idx) } 603 604 static const struct drm_i915_reg_descriptor gen7_render_regs[] = { 605 REG64(GPGPU_THREADS_DISPATCHED), 606 REG64(HS_INVOCATION_COUNT), 607 REG64(DS_INVOCATION_COUNT), 608 REG64(IA_VERTICES_COUNT), 609 REG64(IA_PRIMITIVES_COUNT), 610 REG64(VS_INVOCATION_COUNT), 611 REG64(GS_INVOCATION_COUNT), 612 REG64(GS_PRIMITIVES_COUNT), 613 REG64(CL_INVOCATION_COUNT), 614 REG64(CL_PRIMITIVES_COUNT), 615 REG64(PS_INVOCATION_COUNT), 616 REG64(PS_DEPTH_COUNT), 617 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 618 REG64_IDX(MI_PREDICATE_SRC0, RENDER_RING_BASE), 619 REG64_IDX(MI_PREDICATE_SRC1, RENDER_RING_BASE), 620 REG32(GEN7_3DPRIM_END_OFFSET), 621 REG32(GEN7_3DPRIM_START_VERTEX), 622 REG32(GEN7_3DPRIM_VERTEX_COUNT), 623 REG32(GEN7_3DPRIM_INSTANCE_COUNT), 624 REG32(GEN7_3DPRIM_START_INSTANCE), 625 REG32(GEN7_3DPRIM_BASE_VERTEX), 626 REG32(GEN7_GPGPU_DISPATCHDIMX), 627 REG32(GEN7_GPGPU_DISPATCHDIMY), 628 REG32(GEN7_GPGPU_DISPATCHDIMZ), 629 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 630 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0), 631 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1), 632 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2), 633 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3), 634 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0), 635 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1), 636 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2), 637 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3), 638 REG32(GEN7_SO_WRITE_OFFSET(0)), 639 REG32(GEN7_SO_WRITE_OFFSET(1)), 640 REG32(GEN7_SO_WRITE_OFFSET(2)), 641 REG32(GEN7_SO_WRITE_OFFSET(3)), 642 REG32(GEN7_L3SQCREG1), 643 REG32(GEN7_L3CNTLREG2), 644 REG32(GEN7_L3CNTLREG3), 645 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 646 }; 647 648 static const struct drm_i915_reg_descriptor hsw_render_regs[] = { 649 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 0), 650 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 1), 651 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 2), 652 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 3), 653 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 4), 654 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 5), 655 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 6), 656 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 7), 657 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 8), 658 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 9), 659 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 10), 660 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 11), 661 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 12), 662 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 13), 663 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 14), 664 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 15), 665 REG32(HSW_SCRATCH1, 666 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE, 667 .value = 0), 668 REG32(HSW_ROW_CHICKEN3, 669 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 | 670 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 671 .value = 0), 672 }; 673 674 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = { 675 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 676 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 677 REG32(BCS_SWCTRL), 678 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 679 }; 680 681 static const struct drm_i915_reg_descriptor gen9_blt_regs[] = { 682 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 683 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 684 REG32(BCS_SWCTRL), 685 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 686 REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE), 687 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 0), 688 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 1), 689 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 2), 690 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 3), 691 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 4), 692 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 5), 693 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 6), 694 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 7), 695 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 8), 696 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 9), 697 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 10), 698 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 11), 699 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 12), 700 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 13), 701 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 14), 702 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 15), 703 }; 704 705 #undef REG64 706 #undef REG32 707 708 struct drm_i915_reg_table { 709 const struct drm_i915_reg_descriptor *regs; 710 int num_regs; 711 }; 712 713 static const struct drm_i915_reg_table ivb_render_reg_tables[] = { 714 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) }, 715 }; 716 717 static const struct drm_i915_reg_table ivb_blt_reg_tables[] = { 718 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) }, 719 }; 720 721 static const struct drm_i915_reg_table hsw_render_reg_tables[] = { 722 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) }, 723 { hsw_render_regs, ARRAY_SIZE(hsw_render_regs) }, 724 }; 725 726 static const struct drm_i915_reg_table hsw_blt_reg_tables[] = { 727 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) }, 728 }; 729 730 static const struct drm_i915_reg_table gen9_blt_reg_tables[] = { 731 { gen9_blt_regs, ARRAY_SIZE(gen9_blt_regs) }, 732 }; 733 734 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header) 735 { 736 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 737 u32 subclient = 738 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 739 740 if (client == INSTR_MI_CLIENT) 741 return 0x3F; 742 else if (client == INSTR_RC_CLIENT) { 743 if (subclient == INSTR_MEDIA_SUBCLIENT) 744 return 0xFFFF; 745 else 746 return 0xFF; 747 } 748 749 DRM_DEBUG("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header); 750 return 0; 751 } 752 753 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header) 754 { 755 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 756 u32 subclient = 757 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 758 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT; 759 760 if (client == INSTR_MI_CLIENT) 761 return 0x3F; 762 else if (client == INSTR_RC_CLIENT) { 763 if (subclient == INSTR_MEDIA_SUBCLIENT) { 764 if (op == 6) 765 return 0xFFFF; 766 else 767 return 0xFFF; 768 } else 769 return 0xFF; 770 } 771 772 DRM_DEBUG("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header); 773 return 0; 774 } 775 776 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header) 777 { 778 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 779 780 if (client == INSTR_MI_CLIENT) 781 return 0x3F; 782 else if (client == INSTR_BC_CLIENT) 783 return 0xFF; 784 785 DRM_DEBUG("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); 786 return 0; 787 } 788 789 static u32 gen9_blt_get_cmd_length_mask(u32 cmd_header) 790 { 791 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 792 793 if (client == INSTR_MI_CLIENT || client == INSTR_BC_CLIENT) 794 return 0xFF; 795 796 DRM_DEBUG("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); 797 return 0; 798 } 799 800 static bool validate_cmds_sorted(const struct intel_engine_cs *engine, 801 const struct drm_i915_cmd_table *cmd_tables, 802 int cmd_table_count) 803 { 804 int i; 805 bool ret = true; 806 807 if (!cmd_tables || cmd_table_count == 0) 808 return true; 809 810 for (i = 0; i < cmd_table_count; i++) { 811 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 812 u32 previous = 0; 813 int j; 814 815 for (j = 0; j < table->count; j++) { 816 const struct drm_i915_cmd_descriptor *desc = 817 &table->table[j]; 818 u32 curr = desc->cmd.value & desc->cmd.mask; 819 820 if (curr < previous) { 821 drm_err(&engine->i915->drm, 822 "CMD: %s [%d] command table not sorted: " 823 "table=%d entry=%d cmd=0x%08X prev=0x%08X\n", 824 engine->name, engine->id, 825 i, j, curr, previous); 826 ret = false; 827 } 828 829 previous = curr; 830 } 831 } 832 833 return ret; 834 } 835 836 static bool check_sorted(const struct intel_engine_cs *engine, 837 const struct drm_i915_reg_descriptor *reg_table, 838 int reg_count) 839 { 840 int i; 841 u32 previous = 0; 842 bool ret = true; 843 844 for (i = 0; i < reg_count; i++) { 845 u32 curr = i915_mmio_reg_offset(reg_table[i].addr); 846 847 if (curr < previous) { 848 drm_err(&engine->i915->drm, 849 "CMD: %s [%d] register table not sorted: " 850 "entry=%d reg=0x%08X prev=0x%08X\n", 851 engine->name, engine->id, 852 i, curr, previous); 853 ret = false; 854 } 855 856 previous = curr; 857 } 858 859 return ret; 860 } 861 862 static bool validate_regs_sorted(struct intel_engine_cs *engine) 863 { 864 int i; 865 const struct drm_i915_reg_table *table; 866 867 for (i = 0; i < engine->reg_table_count; i++) { 868 table = &engine->reg_tables[i]; 869 if (!check_sorted(engine, table->regs, table->num_regs)) 870 return false; 871 } 872 873 return true; 874 } 875 876 struct cmd_node { 877 const struct drm_i915_cmd_descriptor *desc; 878 struct hlist_node node; 879 }; 880 881 /* 882 * Different command ranges have different numbers of bits for the opcode. For 883 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The 884 * problem is that, for example, MI commands use bits 22:16 for other fields 885 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when 886 * we mask a command from a batch it could hash to the wrong bucket due to 887 * non-opcode bits being set. But if we don't include those bits, some 3D 888 * commands may hash to the same bucket due to not including opcode bits that 889 * make the command unique. For now, we will risk hashing to the same bucket. 890 */ 891 static inline u32 cmd_header_key(u32 x) 892 { 893 switch (x >> INSTR_CLIENT_SHIFT) { 894 default: 895 case INSTR_MI_CLIENT: 896 return x >> STD_MI_OPCODE_SHIFT; 897 case INSTR_RC_CLIENT: 898 return x >> STD_3D_OPCODE_SHIFT; 899 case INSTR_BC_CLIENT: 900 return x >> STD_2D_OPCODE_SHIFT; 901 } 902 } 903 904 static int init_hash_table(struct intel_engine_cs *engine, 905 const struct drm_i915_cmd_table *cmd_tables, 906 int cmd_table_count) 907 { 908 int i, j; 909 910 hash_init(engine->cmd_hash); 911 912 for (i = 0; i < cmd_table_count; i++) { 913 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 914 915 for (j = 0; j < table->count; j++) { 916 const struct drm_i915_cmd_descriptor *desc = 917 &table->table[j]; 918 struct cmd_node *desc_node = 919 kmalloc(sizeof(*desc_node), GFP_KERNEL); 920 921 if (!desc_node) 922 return -ENOMEM; 923 924 desc_node->desc = desc; 925 hash_add(engine->cmd_hash, &desc_node->node, 926 cmd_header_key(desc->cmd.value)); 927 } 928 } 929 930 return 0; 931 } 932 933 static void fini_hash_table(struct intel_engine_cs *engine) 934 { 935 struct hlist_node *tmp; 936 struct cmd_node *desc_node; 937 int i; 938 939 hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) { 940 hash_del(&desc_node->node); 941 kfree(desc_node); 942 } 943 } 944 945 /** 946 * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine 947 * @engine: the engine to initialize 948 * 949 * Optionally initializes fields related to batch buffer command parsing in the 950 * struct intel_engine_cs based on whether the platform requires software 951 * command parsing. 952 */ 953 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine) 954 { 955 const struct drm_i915_cmd_table *cmd_tables; 956 int cmd_table_count; 957 int ret; 958 959 if (GRAPHICS_VER(engine->i915) != 7 && !(GRAPHICS_VER(engine->i915) == 9 && 960 engine->class == COPY_ENGINE_CLASS)) 961 return 0; 962 963 switch (engine->class) { 964 case RENDER_CLASS: 965 if (IS_HASWELL(engine->i915)) { 966 cmd_tables = hsw_render_ring_cmd_table; 967 cmd_table_count = 968 ARRAY_SIZE(hsw_render_ring_cmd_table); 969 } else { 970 cmd_tables = gen7_render_cmd_table; 971 cmd_table_count = ARRAY_SIZE(gen7_render_cmd_table); 972 } 973 974 if (IS_HASWELL(engine->i915)) { 975 engine->reg_tables = hsw_render_reg_tables; 976 engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables); 977 } else { 978 engine->reg_tables = ivb_render_reg_tables; 979 engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables); 980 } 981 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask; 982 break; 983 case VIDEO_DECODE_CLASS: 984 cmd_tables = gen7_video_cmd_table; 985 cmd_table_count = ARRAY_SIZE(gen7_video_cmd_table); 986 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 987 break; 988 case COPY_ENGINE_CLASS: 989 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; 990 if (GRAPHICS_VER(engine->i915) == 9) { 991 cmd_tables = gen9_blt_cmd_table; 992 cmd_table_count = ARRAY_SIZE(gen9_blt_cmd_table); 993 engine->get_cmd_length_mask = 994 gen9_blt_get_cmd_length_mask; 995 996 /* BCS Engine unsafe without parser */ 997 engine->flags |= I915_ENGINE_REQUIRES_CMD_PARSER; 998 } else if (IS_HASWELL(engine->i915)) { 999 cmd_tables = hsw_blt_ring_cmd_table; 1000 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmd_table); 1001 } else { 1002 cmd_tables = gen7_blt_cmd_table; 1003 cmd_table_count = ARRAY_SIZE(gen7_blt_cmd_table); 1004 } 1005 1006 if (GRAPHICS_VER(engine->i915) == 9) { 1007 engine->reg_tables = gen9_blt_reg_tables; 1008 engine->reg_table_count = 1009 ARRAY_SIZE(gen9_blt_reg_tables); 1010 } else if (IS_HASWELL(engine->i915)) { 1011 engine->reg_tables = hsw_blt_reg_tables; 1012 engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables); 1013 } else { 1014 engine->reg_tables = ivb_blt_reg_tables; 1015 engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables); 1016 } 1017 break; 1018 case VIDEO_ENHANCEMENT_CLASS: 1019 cmd_tables = hsw_vebox_cmd_table; 1020 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmd_table); 1021 /* VECS can use the same length_mask function as VCS */ 1022 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 1023 break; 1024 default: 1025 MISSING_CASE(engine->class); 1026 goto out; 1027 } 1028 1029 if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) { 1030 drm_err(&engine->i915->drm, 1031 "%s: command descriptions are not sorted\n", 1032 engine->name); 1033 goto out; 1034 } 1035 if (!validate_regs_sorted(engine)) { 1036 drm_err(&engine->i915->drm, 1037 "%s: registers are not sorted\n", engine->name); 1038 goto out; 1039 } 1040 1041 ret = init_hash_table(engine, cmd_tables, cmd_table_count); 1042 if (ret) { 1043 drm_err(&engine->i915->drm, 1044 "%s: initialised failed!\n", engine->name); 1045 fini_hash_table(engine); 1046 goto out; 1047 } 1048 1049 engine->flags |= I915_ENGINE_USING_CMD_PARSER; 1050 1051 out: 1052 if (intel_engine_requires_cmd_parser(engine) && 1053 !intel_engine_using_cmd_parser(engine)) 1054 return -EINVAL; 1055 1056 return 0; 1057 } 1058 1059 /** 1060 * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields 1061 * @engine: the engine to clean up 1062 * 1063 * Releases any resources related to command parsing that may have been 1064 * initialized for the specified engine. 1065 */ 1066 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine) 1067 { 1068 if (!intel_engine_using_cmd_parser(engine)) 1069 return; 1070 1071 fini_hash_table(engine); 1072 } 1073 1074 static const struct drm_i915_cmd_descriptor* 1075 find_cmd_in_table(struct intel_engine_cs *engine, 1076 u32 cmd_header) 1077 { 1078 struct cmd_node *desc_node; 1079 1080 hash_for_each_possible(engine->cmd_hash, desc_node, node, 1081 cmd_header_key(cmd_header)) { 1082 const struct drm_i915_cmd_descriptor *desc = desc_node->desc; 1083 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) 1084 return desc; 1085 } 1086 1087 return NULL; 1088 } 1089 1090 /* 1091 * Returns a pointer to a descriptor for the command specified by cmd_header. 1092 * 1093 * The caller must supply space for a default descriptor via the default_desc 1094 * parameter. If no descriptor for the specified command exists in the engine's 1095 * command parser tables, this function fills in default_desc based on the 1096 * engine's default length encoding and returns default_desc. 1097 */ 1098 static const struct drm_i915_cmd_descriptor* 1099 find_cmd(struct intel_engine_cs *engine, 1100 u32 cmd_header, 1101 const struct drm_i915_cmd_descriptor *desc, 1102 struct drm_i915_cmd_descriptor *default_desc) 1103 { 1104 u32 mask; 1105 1106 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) 1107 return desc; 1108 1109 desc = find_cmd_in_table(engine, cmd_header); 1110 if (desc) 1111 return desc; 1112 1113 mask = engine->get_cmd_length_mask(cmd_header); 1114 if (!mask) 1115 return NULL; 1116 1117 default_desc->cmd.value = cmd_header; 1118 default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT; 1119 default_desc->length.mask = mask; 1120 default_desc->flags = CMD_DESC_SKIP; 1121 return default_desc; 1122 } 1123 1124 static const struct drm_i915_reg_descriptor * 1125 __find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr) 1126 { 1127 int start = 0, end = count; 1128 while (start < end) { 1129 int mid = start + (end - start) / 2; 1130 int ret = addr - i915_mmio_reg_offset(table[mid].addr); 1131 if (ret < 0) 1132 end = mid; 1133 else if (ret > 0) 1134 start = mid + 1; 1135 else 1136 return &table[mid]; 1137 } 1138 return NULL; 1139 } 1140 1141 static const struct drm_i915_reg_descriptor * 1142 find_reg(const struct intel_engine_cs *engine, u32 addr) 1143 { 1144 const struct drm_i915_reg_table *table = engine->reg_tables; 1145 const struct drm_i915_reg_descriptor *reg = NULL; 1146 int count = engine->reg_table_count; 1147 1148 for (; !reg && (count > 0); ++table, --count) 1149 reg = __find_reg(table->regs, table->num_regs, addr); 1150 1151 return reg; 1152 } 1153 1154 /* Returns a vmap'd pointer to dst_obj, which the caller must unmap */ 1155 static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, 1156 struct drm_i915_gem_object *src_obj, 1157 unsigned long offset, unsigned long length, 1158 bool *needs_clflush_after) 1159 { 1160 unsigned int src_needs_clflush; 1161 unsigned int dst_needs_clflush; 1162 void *dst, *src; 1163 int ret; 1164 1165 ret = i915_gem_object_prepare_write(dst_obj, &dst_needs_clflush); 1166 if (ret) 1167 return ERR_PTR(ret); 1168 1169 dst = i915_gem_object_pin_map(dst_obj, I915_MAP_WB); 1170 i915_gem_object_finish_access(dst_obj); 1171 if (IS_ERR(dst)) 1172 return dst; 1173 1174 ret = i915_gem_object_prepare_read(src_obj, &src_needs_clflush); 1175 if (ret) { 1176 i915_gem_object_unpin_map(dst_obj); 1177 return ERR_PTR(ret); 1178 } 1179 1180 src = ERR_PTR(-ENODEV); 1181 if (src_needs_clflush && i915_has_memcpy_from_wc()) { 1182 src = i915_gem_object_pin_map(src_obj, I915_MAP_WC); 1183 if (!IS_ERR(src)) { 1184 i915_unaligned_memcpy_from_wc(dst, 1185 src + offset, 1186 length); 1187 i915_gem_object_unpin_map(src_obj); 1188 } 1189 } 1190 if (IS_ERR(src)) { 1191 unsigned long x, n, remain; 1192 void *ptr; 1193 1194 /* 1195 * We can avoid clflushing partial cachelines before the write 1196 * if we only every write full cache-lines. Since we know that 1197 * both the source and destination are in multiples of 1198 * PAGE_SIZE, we can simply round up to the next cacheline. 1199 * We don't care about copying too much here as we only 1200 * validate up to the end of the batch. 1201 */ 1202 remain = length; 1203 if (dst_needs_clflush & CLFLUSH_BEFORE) 1204 remain = round_up(remain, 1205 boot_cpu_data.x86_clflush_size); 1206 1207 ptr = dst; 1208 x = offset_in_page(offset); 1209 for (n = offset >> PAGE_SHIFT; remain; n++) { 1210 int len = min(remain, PAGE_SIZE - x); 1211 1212 src = kmap_atomic(i915_gem_object_get_page(src_obj, n)); 1213 if (src_needs_clflush) 1214 drm_clflush_virt_range(src + x, len); 1215 memcpy(ptr, src + x, len); 1216 kunmap_atomic(src); 1217 1218 ptr += len; 1219 remain -= len; 1220 x = 0; 1221 } 1222 } 1223 1224 i915_gem_object_finish_access(src_obj); 1225 1226 memset32(dst + length, 0, (dst_obj->base.size - length) / sizeof(u32)); 1227 1228 /* dst_obj is returned with vmap pinned */ 1229 *needs_clflush_after = dst_needs_clflush & CLFLUSH_AFTER; 1230 1231 return dst; 1232 } 1233 1234 static inline bool cmd_desc_is(const struct drm_i915_cmd_descriptor * const desc, 1235 const u32 cmd) 1236 { 1237 return desc->cmd.value == (cmd & desc->cmd.mask); 1238 } 1239 1240 static bool check_cmd(const struct intel_engine_cs *engine, 1241 const struct drm_i915_cmd_descriptor *desc, 1242 const u32 *cmd, u32 length) 1243 { 1244 if (desc->flags & CMD_DESC_SKIP) 1245 return true; 1246 1247 if (desc->flags & CMD_DESC_REJECT) { 1248 DRM_DEBUG("CMD: Rejected command: 0x%08X\n", *cmd); 1249 return false; 1250 } 1251 1252 if (desc->flags & CMD_DESC_REGISTER) { 1253 /* 1254 * Get the distance between individual register offset 1255 * fields if the command can perform more than one 1256 * access at a time. 1257 */ 1258 const u32 step = desc->reg.step ? desc->reg.step : length; 1259 u32 offset; 1260 1261 for (offset = desc->reg.offset; offset < length; 1262 offset += step) { 1263 const u32 reg_addr = cmd[offset] & desc->reg.mask; 1264 const struct drm_i915_reg_descriptor *reg = 1265 find_reg(engine, reg_addr); 1266 1267 if (!reg) { 1268 DRM_DEBUG("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n", 1269 reg_addr, *cmd, engine->name); 1270 return false; 1271 } 1272 1273 /* 1274 * Check the value written to the register against the 1275 * allowed mask/value pair given in the whitelist entry. 1276 */ 1277 if (reg->mask) { 1278 if (cmd_desc_is(desc, MI_LOAD_REGISTER_MEM)) { 1279 DRM_DEBUG("CMD: Rejected LRM to masked register 0x%08X\n", 1280 reg_addr); 1281 return false; 1282 } 1283 1284 if (cmd_desc_is(desc, MI_LOAD_REGISTER_REG)) { 1285 DRM_DEBUG("CMD: Rejected LRR to masked register 0x%08X\n", 1286 reg_addr); 1287 return false; 1288 } 1289 1290 if (cmd_desc_is(desc, MI_LOAD_REGISTER_IMM(1)) && 1291 (offset + 2 > length || 1292 (cmd[offset + 1] & reg->mask) != reg->value)) { 1293 DRM_DEBUG("CMD: Rejected LRI to masked register 0x%08X\n", 1294 reg_addr); 1295 return false; 1296 } 1297 } 1298 } 1299 } 1300 1301 if (desc->flags & CMD_DESC_BITMASK) { 1302 int i; 1303 1304 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) { 1305 u32 dword; 1306 1307 if (desc->bits[i].mask == 0) 1308 break; 1309 1310 if (desc->bits[i].condition_mask != 0) { 1311 u32 offset = 1312 desc->bits[i].condition_offset; 1313 u32 condition = cmd[offset] & 1314 desc->bits[i].condition_mask; 1315 1316 if (condition == 0) 1317 continue; 1318 } 1319 1320 if (desc->bits[i].offset >= length) { 1321 DRM_DEBUG("CMD: Rejected command 0x%08X, too short to check bitmask (%s)\n", 1322 *cmd, engine->name); 1323 return false; 1324 } 1325 1326 dword = cmd[desc->bits[i].offset] & 1327 desc->bits[i].mask; 1328 1329 if (dword != desc->bits[i].expected) { 1330 DRM_DEBUG("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n", 1331 *cmd, 1332 desc->bits[i].mask, 1333 desc->bits[i].expected, 1334 dword, engine->name); 1335 return false; 1336 } 1337 } 1338 } 1339 1340 return true; 1341 } 1342 1343 static int check_bbstart(u32 *cmd, u32 offset, u32 length, 1344 u32 batch_length, 1345 u64 batch_addr, 1346 u64 shadow_addr, 1347 const unsigned long *jump_whitelist) 1348 { 1349 u64 jump_offset, jump_target; 1350 u32 target_cmd_offset, target_cmd_index; 1351 1352 /* For igt compatibility on older platforms */ 1353 if (!jump_whitelist) { 1354 DRM_DEBUG("CMD: Rejecting BB_START for ggtt based submission\n"); 1355 return -EACCES; 1356 } 1357 1358 if (length != 3) { 1359 DRM_DEBUG("CMD: Recursive BB_START with bad length(%u)\n", 1360 length); 1361 return -EINVAL; 1362 } 1363 1364 jump_target = *(u64 *)(cmd + 1); 1365 jump_offset = jump_target - batch_addr; 1366 1367 /* 1368 * Any underflow of jump_target is guaranteed to be outside the range 1369 * of a u32, so >= test catches both too large and too small 1370 */ 1371 if (jump_offset >= batch_length) { 1372 DRM_DEBUG("CMD: BB_START to 0x%llx jumps out of BB\n", 1373 jump_target); 1374 return -EINVAL; 1375 } 1376 1377 /* 1378 * This cannot overflow a u32 because we already checked jump_offset 1379 * is within the BB, and the batch_length is a u32 1380 */ 1381 target_cmd_offset = lower_32_bits(jump_offset); 1382 target_cmd_index = target_cmd_offset / sizeof(u32); 1383 1384 *(u64 *)(cmd + 1) = shadow_addr + target_cmd_offset; 1385 1386 if (target_cmd_index == offset) 1387 return 0; 1388 1389 if (IS_ERR(jump_whitelist)) 1390 return PTR_ERR(jump_whitelist); 1391 1392 if (!test_bit(target_cmd_index, jump_whitelist)) { 1393 DRM_DEBUG("CMD: BB_START to 0x%llx not a previously executed cmd\n", 1394 jump_target); 1395 return -EINVAL; 1396 } 1397 1398 return 0; 1399 } 1400 1401 static unsigned long *alloc_whitelist(u32 batch_length) 1402 { 1403 unsigned long *jmp; 1404 1405 /* 1406 * We expect batch_length to be less than 256KiB for known users, 1407 * i.e. we need at most an 8KiB bitmap allocation which should be 1408 * reasonably cheap due to kmalloc caches. 1409 */ 1410 1411 /* Prefer to report transient allocation failure rather than hit oom */ 1412 jmp = bitmap_zalloc(DIV_ROUND_UP(batch_length, sizeof(u32)), 1413 GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); 1414 if (!jmp) 1415 return ERR_PTR(-ENOMEM); 1416 1417 return jmp; 1418 } 1419 1420 #define LENGTH_BIAS 2 1421 1422 /** 1423 * intel_engine_cmd_parser() - parse a batch buffer for privilege violations 1424 * @engine: the engine on which the batch is to execute 1425 * @batch: the batch buffer in question 1426 * @batch_offset: byte offset in the batch at which execution starts 1427 * @batch_length: length of the commands in batch_obj 1428 * @shadow: validated copy of the batch buffer in question 1429 * @trampoline: true if we need to trampoline into privileged execution 1430 * 1431 * Parses the specified batch buffer looking for privilege violations as 1432 * described in the overview. 1433 * 1434 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES 1435 * if the batch appears legal but should use hardware parsing 1436 */ 1437 1438 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 1439 struct i915_vma *batch, 1440 unsigned long batch_offset, 1441 unsigned long batch_length, 1442 struct i915_vma *shadow, 1443 bool trampoline) 1444 { 1445 u32 *cmd, *batch_end, offset = 0; 1446 struct drm_i915_cmd_descriptor default_desc = noop_desc; 1447 const struct drm_i915_cmd_descriptor *desc = &default_desc; 1448 bool needs_clflush_after = false; 1449 unsigned long *jump_whitelist; 1450 u64 batch_addr, shadow_addr; 1451 int ret = 0; 1452 1453 GEM_BUG_ON(!IS_ALIGNED(batch_offset, sizeof(*cmd))); 1454 GEM_BUG_ON(!IS_ALIGNED(batch_length, sizeof(*cmd))); 1455 GEM_BUG_ON(range_overflows_t(u64, batch_offset, batch_length, 1456 batch->size)); 1457 GEM_BUG_ON(!batch_length); 1458 1459 cmd = copy_batch(shadow->obj, batch->obj, 1460 batch_offset, batch_length, 1461 &needs_clflush_after); 1462 if (IS_ERR(cmd)) { 1463 DRM_DEBUG("CMD: Failed to copy batch\n"); 1464 return PTR_ERR(cmd); 1465 } 1466 1467 jump_whitelist = NULL; 1468 if (!trampoline) 1469 /* Defer failure until attempted use */ 1470 jump_whitelist = alloc_whitelist(batch_length); 1471 1472 shadow_addr = gen8_canonical_addr(shadow->node.start); 1473 batch_addr = gen8_canonical_addr(batch->node.start + batch_offset); 1474 1475 /* 1476 * We use the batch length as size because the shadow object is as 1477 * large or larger and copy_batch() will write MI_NOPs to the extra 1478 * space. Parsing should be faster in some cases this way. 1479 */ 1480 batch_end = cmd + batch_length / sizeof(*batch_end); 1481 do { 1482 u32 length; 1483 1484 if (*cmd == MI_BATCH_BUFFER_END) 1485 break; 1486 1487 desc = find_cmd(engine, *cmd, desc, &default_desc); 1488 if (!desc) { 1489 DRM_DEBUG("CMD: Unrecognized command: 0x%08X\n", *cmd); 1490 ret = -EINVAL; 1491 break; 1492 } 1493 1494 if (desc->flags & CMD_DESC_FIXED) 1495 length = desc->length.fixed; 1496 else 1497 length = (*cmd & desc->length.mask) + LENGTH_BIAS; 1498 1499 if ((batch_end - cmd) < length) { 1500 DRM_DEBUG("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n", 1501 *cmd, 1502 length, 1503 batch_end - cmd); 1504 ret = -EINVAL; 1505 break; 1506 } 1507 1508 if (!check_cmd(engine, desc, cmd, length)) { 1509 ret = -EACCES; 1510 break; 1511 } 1512 1513 if (cmd_desc_is(desc, MI_BATCH_BUFFER_START)) { 1514 ret = check_bbstart(cmd, offset, length, batch_length, 1515 batch_addr, shadow_addr, 1516 jump_whitelist); 1517 break; 1518 } 1519 1520 if (!IS_ERR_OR_NULL(jump_whitelist)) 1521 __set_bit(offset, jump_whitelist); 1522 1523 cmd += length; 1524 offset += length; 1525 if (cmd >= batch_end) { 1526 DRM_DEBUG("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); 1527 ret = -EINVAL; 1528 break; 1529 } 1530 } while (1); 1531 1532 if (trampoline) { 1533 /* 1534 * With the trampoline, the shadow is executed twice. 1535 * 1536 * 1 - starting at offset 0, in privileged mode 1537 * 2 - starting at offset batch_len, as non-privileged 1538 * 1539 * Only if the batch is valid and safe to execute, do we 1540 * allow the first privileged execution to proceed. If not, 1541 * we terminate the first batch and use the second batchbuffer 1542 * entry to chain to the original unsafe non-privileged batch, 1543 * leaving it to the HW to validate. 1544 */ 1545 *batch_end = MI_BATCH_BUFFER_END; 1546 1547 if (ret) { 1548 /* Batch unsafe to execute with privileges, cancel! */ 1549 cmd = page_mask_bits(shadow->obj->mm.mapping); 1550 *cmd = MI_BATCH_BUFFER_END; 1551 1552 /* If batch is unsafe but valid, jump to the original */ 1553 if (ret == -EACCES) { 1554 unsigned int flags; 1555 1556 flags = MI_BATCH_NON_SECURE_I965; 1557 if (IS_HASWELL(engine->i915)) 1558 flags = MI_BATCH_NON_SECURE_HSW; 1559 1560 GEM_BUG_ON(!IS_GRAPHICS_VER(engine->i915, 6, 7)); 1561 __gen6_emit_bb_start(batch_end, 1562 batch_addr, 1563 flags); 1564 1565 ret = 0; /* allow execution */ 1566 } 1567 } 1568 } 1569 1570 i915_gem_object_flush_map(shadow->obj); 1571 1572 if (!IS_ERR_OR_NULL(jump_whitelist)) 1573 kfree(jump_whitelist); 1574 i915_gem_object_unpin_map(shadow->obj); 1575 return ret; 1576 } 1577 1578 /** 1579 * i915_cmd_parser_get_version() - get the cmd parser version number 1580 * @dev_priv: i915 device private 1581 * 1582 * The cmd parser maintains a simple increasing integer version number suitable 1583 * for passing to userspace clients to determine what operations are permitted. 1584 * 1585 * Return: the current version number of the cmd parser 1586 */ 1587 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv) 1588 { 1589 struct intel_engine_cs *engine; 1590 bool active = false; 1591 1592 /* If the command parser is not enabled, report 0 - unsupported */ 1593 for_each_uabi_engine(engine, dev_priv) { 1594 if (intel_engine_using_cmd_parser(engine)) { 1595 active = true; 1596 break; 1597 } 1598 } 1599 if (!active) 1600 return 0; 1601 1602 /* 1603 * Command parser version history 1604 * 1605 * 1. Initial version. Checks batches and reports violations, but leaves 1606 * hardware parsing enabled (so does not allow new use cases). 1607 * 2. Allow access to the MI_PREDICATE_SRC0 and 1608 * MI_PREDICATE_SRC1 registers. 1609 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register. 1610 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3. 1611 * 5. GPGPU dispatch compute indirect registers. 1612 * 6. TIMESTAMP register and Haswell CS GPR registers 1613 * 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers. 1614 * 8. Don't report cmd_check() failures as EINVAL errors to userspace; 1615 * rely on the HW to NOOP disallowed commands as it would without 1616 * the parser enabled. 1617 * 9. Don't whitelist or handle oacontrol specially, as ownership 1618 * for oacontrol state is moving to i915-perf. 1619 * 10. Support for Gen9 BCS Parsing 1620 */ 1621 return 10; 1622 } 1623