1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6350.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/mailbox/qcom-ipcc.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 clocks { 20 xo_board: xo-board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <76800000>; 24 clock-output-names = "xo_board"; 25 }; 26 27 sleep_clk: sleep-clk { 28 compatible = "fixed-clock"; 29 clock-frequency = <32764>; 30 #clock-cells = <0>; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 CPU0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "qcom,kryo560"; 41 reg = <0x0 0x0>; 42 enable-method = "psci"; 43 capacity-dmips-mhz = <1024>; 44 dynamic-power-coefficient = <100>; 45 next-level-cache = <&L2_0>; 46 qcom,freq-domain = <&cpufreq_hw 0>; 47 #cooling-cells = <2>; 48 L2_0: l2-cache { 49 compatible = "cache"; 50 next-level-cache = <&L3_0>; 51 L3_0: l3-cache { 52 compatible = "cache"; 53 }; 54 }; 55 }; 56 57 CPU1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "qcom,kryo560"; 60 reg = <0x0 0x100>; 61 enable-method = "psci"; 62 capacity-dmips-mhz = <1024>; 63 dynamic-power-coefficient = <100>; 64 next-level-cache = <&L2_100>; 65 qcom,freq-domain = <&cpufreq_hw 0>; 66 #cooling-cells = <2>; 67 L2_100: l2-cache { 68 compatible = "cache"; 69 next-level-cache = <&L3_0>; 70 }; 71 }; 72 73 CPU2: cpu@200 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo560"; 76 reg = <0x0 0x200>; 77 enable-method = "psci"; 78 capacity-dmips-mhz = <1024>; 79 dynamic-power-coefficient = <100>; 80 next-level-cache = <&L2_200>; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 #cooling-cells = <2>; 83 L2_200: l2-cache { 84 compatible = "cache"; 85 next-level-cache = <&L3_0>; 86 }; 87 }; 88 89 CPU3: cpu@300 { 90 device_type = "cpu"; 91 compatible = "qcom,kryo560"; 92 reg = <0x0 0x300>; 93 enable-method = "psci"; 94 capacity-dmips-mhz = <1024>; 95 dynamic-power-coefficient = <100>; 96 next-level-cache = <&L2_300>; 97 qcom,freq-domain = <&cpufreq_hw 0>; 98 #cooling-cells = <2>; 99 L2_300: l2-cache { 100 compatible = "cache"; 101 next-level-cache = <&L3_0>; 102 }; 103 }; 104 105 CPU4: cpu@400 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo560"; 108 reg = <0x0 0x400>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <1024>; 111 dynamic-power-coefficient = <100>; 112 next-level-cache = <&L2_400>; 113 qcom,freq-domain = <&cpufreq_hw 0>; 114 #cooling-cells = <2>; 115 L2_400: l2-cache { 116 compatible = "cache"; 117 next-level-cache = <&L3_0>; 118 }; 119 }; 120 121 CPU5: cpu@500 { 122 device_type = "cpu"; 123 compatible = "qcom,kryo560"; 124 reg = <0x0 0x500>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <1024>; 127 dynamic-power-coefficient = <100>; 128 next-level-cache = <&L2_500>; 129 qcom,freq-domain = <&cpufreq_hw 0>; 130 #cooling-cells = <2>; 131 L2_500: l2-cache { 132 compatible = "cache"; 133 next-level-cache = <&L3_0>; 134 }; 135 136 }; 137 138 CPU6: cpu@600 { 139 device_type = "cpu"; 140 compatible = "qcom,kryo560"; 141 reg = <0x0 0x600>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <1894>; 144 dynamic-power-coefficient = <703>; 145 next-level-cache = <&L2_600>; 146 qcom,freq-domain = <&cpufreq_hw 1>; 147 #cooling-cells = <2>; 148 L2_600: l2-cache { 149 compatible = "cache"; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU7: cpu@700 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo560"; 157 reg = <0x0 0x700>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1894>; 160 dynamic-power-coefficient = <703>; 161 next-level-cache = <&L2_700>; 162 qcom,freq-domain = <&cpufreq_hw 1>; 163 #cooling-cells = <2>; 164 L2_700: l2-cache { 165 compatible = "cache"; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 cpu-map { 171 cluster0 { 172 core0 { 173 cpu = <&CPU0>; 174 }; 175 176 core1 { 177 cpu = <&CPU1>; 178 }; 179 180 core2 { 181 cpu = <&CPU2>; 182 }; 183 184 core3 { 185 cpu = <&CPU3>; 186 }; 187 188 core4 { 189 cpu = <&CPU4>; 190 }; 191 192 core5 { 193 cpu = <&CPU5>; 194 }; 195 196 core6 { 197 cpu = <&CPU6>; 198 }; 199 200 core7 { 201 cpu = <&CPU7>; 202 }; 203 }; 204 }; 205 }; 206 207 firmware { 208 scm: scm { 209 compatible = "qcom,scm-sm6350", "qcom,scm"; 210 #reset-cells = <1>; 211 }; 212 }; 213 214 memory@80000000 { 215 device_type = "memory"; 216 /* We expect the bootloader to fill in the size */ 217 reg = <0x0 0x80000000 0x0 0x0>; 218 }; 219 220 pmu { 221 compatible = "arm,armv8-pmuv3"; 222 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 223 }; 224 225 psci { 226 compatible = "arm,psci-1.0"; 227 method = "smc"; 228 }; 229 230 reserved_memory: reserved-memory { 231 #address-cells = <2>; 232 #size-cells = <2>; 233 ranges; 234 235 hyp_mem: memory@80000000 { 236 reg = <0 0x80000000 0 0x600000>; 237 no-map; 238 }; 239 240 xbl_aop_mem: memory@80700000 { 241 reg = <0 0x80700000 0 0x160000>; 242 no-map; 243 }; 244 245 cmd_db: memory@80860000 { 246 compatible = "qcom,cmd-db"; 247 reg = <0 0x80860000 0 0x20000>; 248 no-map; 249 }; 250 251 sec_apps_mem: memory@808ff000 { 252 reg = <0 0x808ff000 0 0x1000>; 253 no-map; 254 }; 255 256 smem_mem: memory@80900000 { 257 reg = <0 0x80900000 0 0x200000>; 258 no-map; 259 }; 260 261 cdsp_sec_mem: memory@80b00000 { 262 reg = <0 0x80b00000 0 0x1e00000>; 263 no-map; 264 }; 265 266 pil_camera_mem: memory@86000000 { 267 reg = <0 0x86000000 0 0x500000>; 268 no-map; 269 }; 270 271 pil_npu_mem: memory@86500000 { 272 reg = <0 0x86500000 0 0x500000>; 273 no-map; 274 }; 275 276 pil_video_mem: memory@86a00000 { 277 reg = <0 0x86a00000 0 0x500000>; 278 no-map; 279 }; 280 281 pil_cdsp_mem: memory@86f00000 { 282 reg = <0 0x86f00000 0 0x1e00000>; 283 no-map; 284 }; 285 286 pil_adsp_mem: memory@88d00000 { 287 reg = <0 0x88d00000 0 0x2800000>; 288 no-map; 289 }; 290 291 wlan_fw_mem: memory@8b500000 { 292 reg = <0 0x8b500000 0 0x200000>; 293 no-map; 294 }; 295 296 pil_ipa_fw_mem: memory@8b700000 { 297 reg = <0 0x8b700000 0 0x10000>; 298 no-map; 299 }; 300 301 pil_ipa_gsi_mem: memory@8b710000 { 302 reg = <0 0x8b710000 0 0x5400>; 303 no-map; 304 }; 305 306 pil_gpu_mem: memory@8b715400 { 307 reg = <0 0x8b715400 0 0x2000>; 308 no-map; 309 }; 310 311 pil_modem_mem: memory@8b800000 { 312 reg = <0 0x8b800000 0 0xf800000>; 313 no-map; 314 }; 315 316 cont_splash_memory: memory@a0000000 { 317 reg = <0 0xa0000000 0 0x2300000>; 318 no-map; 319 }; 320 321 dfps_data_memory: memory@a2300000 { 322 reg = <0 0xa2300000 0 0x100000>; 323 no-map; 324 }; 325 326 removed_region: memory@c0000000 { 327 reg = <0 0xc0000000 0 0x3900000>; 328 no-map; 329 }; 330 331 debug_region: memory@ffb00000 { 332 reg = <0 0xffb00000 0 0xc0000>; 333 no-map; 334 }; 335 336 last_log_region: memory@ffbc0000 { 337 reg = <0 0xffbc0000 0 0x40000>; 338 no-map; 339 }; 340 341 ramoops: ramoops@ffc00000 { 342 compatible = "removed-dma-pool", "ramoops"; 343 reg = <0 0xffc00000 0 0x00100000>; 344 record-size = <0x1000>; 345 console-size = <0x40000>; 346 ftrace-size = <0x0>; 347 msg-size = <0x20000 0x20000>; 348 cc-size = <0x0>; 349 no-map; 350 }; 351 352 cmdline_region: memory@ffd00000 { 353 reg = <0 0xffd00000 0 0x1000>; 354 no-map; 355 }; 356 }; 357 358 smem { 359 compatible = "qcom,smem"; 360 memory-region = <&smem_mem>; 361 hwlocks = <&tcsr_mutex 3>; 362 }; 363 364 soc: soc@0 { 365 #address-cells = <2>; 366 #size-cells = <2>; 367 ranges = <0 0 0 0 0x10 0>; 368 dma-ranges = <0 0 0 0 0x10 0>; 369 compatible = "simple-bus"; 370 371 gcc: clock-controller@100000 { 372 compatible = "qcom,gcc-sm6350"; 373 reg = <0 0x00100000 0 0x1f0000>; 374 #clock-cells = <1>; 375 #reset-cells = <1>; 376 #power-domain-cells = <1>; 377 clock-names = "bi_tcxo", 378 "bi_tcxo_ao", 379 "sleep_clk"; 380 clocks = <&rpmhcc RPMH_CXO_CLK>, 381 <&rpmhcc RPMH_CXO_CLK_A>, 382 <&sleep_clk>; 383 }; 384 385 ipcc: mailbox@408000 { 386 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 387 reg = <0 0x00408000 0 0x1000>; 388 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 389 interrupt-controller; 390 #interrupt-cells = <3>; 391 #mbox-cells = <2>; 392 }; 393 394 rng: rng@793000 { 395 compatible = "qcom,prng-ee"; 396 reg = <0 0x00793000 0 0x1000>; 397 clocks = <&gcc GCC_PRNG_AHB_CLK>; 398 clock-names = "core"; 399 }; 400 401 sdhc_1: sdhci@7c4000 { 402 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 403 reg = <0 0x007c4000 0 0x1000>, 404 <0 0x007c5000 0 0x1000>, 405 <0 0x007c8000 0 0x8000>; 406 reg-names = "hc", "cqhci", "ice"; 407 408 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 410 interrupt-names = "hc_irq", "pwr_irq"; 411 412 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 413 <&gcc GCC_SDCC1_APPS_CLK>, 414 <&rpmhcc RPMH_CXO_CLK>; 415 clock-names = "iface", "core", "xo"; 416 qcom,dll-config = <0x000f642c>; 417 qcom,ddr-config = <0x80040868>; 418 power-domains = <&rpmhpd 0>; 419 operating-points-v2 = <&sdhc1_opp_table>; 420 bus-width = <8>; 421 non-removable; 422 supports-cqe; 423 424 status = "disabled"; 425 426 sdhc1_opp_table: sdhc1-opp-table { 427 compatible = "operating-points-v2"; 428 429 opp-19200000 { 430 opp-hz = /bits/ 64 <19200000>; 431 required-opps = <&rpmhpd_opp_min_svs>; 432 }; 433 434 opp-100000000 { 435 opp-hz = /bits/ 64 <100000000>; 436 required-opps = <&rpmhpd_opp_low_svs>; 437 }; 438 439 opp-384000000 { 440 opp-hz = /bits/ 64 <384000000>; 441 required-opps = <&rpmhpd_opp_svs_l1>; 442 }; 443 }; 444 }; 445 446 tcsr_mutex: hwlock@1f40000 { 447 compatible = "qcom,tcsr-mutex"; 448 reg = <0x0 0x01f40000 0x0 0x40000>; 449 #hwlock-cells = <1>; 450 }; 451 452 sdhc_2: sdhci@8804000 { 453 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 454 reg = <0 0x08804000 0 0x1000>; 455 456 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 458 interrupt-names = "hc_irq", "pwr_irq"; 459 460 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 461 <&gcc GCC_SDCC2_APPS_CLK>, 462 <&rpmhcc RPMH_CXO_CLK>; 463 clock-names = "iface", "core", "xo"; 464 qcom,dll-config = <0x0007642c>; 465 qcom,ddr-config = <0x80040868>; 466 power-domains = <&rpmhpd 0>; 467 operating-points-v2 = <&sdhc2_opp_table>; 468 bus-width = <4>; 469 470 status = "disabled"; 471 472 sdhc2_opp_table: sdhc2-opp-table { 473 compatible = "operating-points-v2"; 474 475 opp-100000000 { 476 opp-hz = /bits/ 64 <100000000>; 477 required-opps = <&rpmhpd_opp_svs_l1>; 478 }; 479 480 opp-202000000 { 481 opp-hz = /bits/ 64 <202000000>; 482 required-opps = <&rpmhpd_opp_nom>; 483 }; 484 }; 485 }; 486 487 usb_1_hsphy: phy@88e3000 { 488 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 489 reg = <0 0x088e3000 0 0x400>; 490 status = "disabled"; 491 #phy-cells = <0>; 492 493 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 494 clock-names = "cfg_ahb", "ref"; 495 496 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 497 }; 498 499 usb_1_qmpphy: phy@88e9000 { 500 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 501 reg = <0 0x088e9000 0 0x200>, 502 <0 0x088e8000 0 0x40>, 503 <0 0x088ea000 0 0x200>; 504 status = "disabled"; 505 #address-cells = <2>; 506 #size-cells = <2>; 507 ranges; 508 509 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 510 <&rpmhcc RPMH_QLINK_CLK>, 511 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 512 <&xo_board>; 513 clock-names = "aux", "ref", "com_aux", "cfg_ahb"; 514 515 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 516 <&gcc GCC_USB3_PHY_PRIM_BCR>; 517 reset-names = "phy", "common"; 518 519 usb_1_ssphy: usb3-phy@88e9200 { 520 reg = <0 0x088e9200 0 0x200>, 521 <0 0x088e9400 0 0x200>, 522 <0 0x088e9c00 0 0x400>, 523 <0 0x088e9600 0 0x200>, 524 <0 0x088e9800 0 0x200>, 525 <0 0x088e9a00 0 0x100>; 526 #clock-cells = <0>; 527 #phy-cells = <0>; 528 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 529 clock-names = "pipe0"; 530 clock-output-names = "usb3_phy_pipe_clk_src"; 531 }; 532 533 dp_phy: dp-phy@88ea200 { 534 reg = <0 0x088ea200 0 0x200>, 535 <0 0x088ea400 0 0x200>, 536 <0 0x088eac00 0 0x400>, 537 <0 0x088ea600 0 0x200>, 538 <0 0x088ea800 0 0x200>, 539 <0 0x088eaa00 0 0x100>; 540 #phy-cells = <0>; 541 #clock-cells = <1>; 542 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 543 clock-names = "pipe0"; 544 clock-output-names = "usb3_phy_pipe_clk_src"; 545 }; 546 }; 547 548 system-cache-controller@9200000 { 549 compatible = "qcom,sm6350-llcc"; 550 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 551 reg-names = "llcc_base", "llcc_broadcast_base"; 552 }; 553 554 usb_1: usb@a6f8800 { 555 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 556 reg = <0 0x0a6f8800 0 0x400>; 557 status = "disabled"; 558 #address-cells = <2>; 559 #size-cells = <2>; 560 ranges; 561 562 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 563 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 564 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 565 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 566 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 567 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 568 "sleep"; 569 570 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 571 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 572 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 573 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 574 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 575 "dm_hs_phy_irq", "ss_phy_irq"; 576 577 power-domains = <&gcc USB30_PRIM_GDSC>; 578 579 resets = <&gcc GCC_USB30_PRIM_BCR>; 580 581 usb_1_dwc3: usb@a600000 { 582 compatible = "snps,dwc3"; 583 reg = <0 0x0a600000 0 0xcd00>; 584 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 585 iommus = <&apps_smmu 0x540 0x0>; 586 snps,dis_u2_susphy_quirk; 587 snps,dis_enblslpm_quirk; 588 snps,has-lpm-erratum; 589 snps,hird-threshold = /bits/ 8 <0x10>; 590 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 591 phy-names = "usb2-phy", "usb3-phy"; 592 }; 593 }; 594 595 pdc: interrupt-controller@b220000 { 596 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 597 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 598 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 599 <125 63 1>, <126 655 12>, <138 139 15>; 600 #interrupt-cells = <2>; 601 interrupt-parent = <&intc>; 602 interrupt-controller; 603 }; 604 605 tsens0: thermal-sensor@c263000 { 606 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 607 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 608 <0 0x0c222000 0 0x8>; /* SROT */ 609 #qcom,sensors = <16>; 610 interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 611 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 612 interrupt-names = "uplow", "critical"; 613 #thermal-sensor-cells = <1>; 614 }; 615 616 tsens1: thermal-sensor@c265000 { 617 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 618 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 619 <0 0x0c223000 0 0x8>; /* SROT */ 620 #qcom,sensors = <16>; 621 interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 622 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 623 interrupt-names = "uplow", "critical"; 624 #thermal-sensor-cells = <1>; 625 }; 626 627 aoss_qmp: power-controller@c300000 { 628 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 629 reg = <0 0x0c300000 0 0x1000>; 630 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 631 IRQ_TYPE_EDGE_RISING>; 632 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 633 634 #clock-cells = <0>; 635 #power-domain-cells = <1>; 636 }; 637 638 spmi_bus: spmi@c440000 { 639 compatible = "qcom,spmi-pmic-arb"; 640 reg = <0 0xc440000 0 0x1100>, 641 <0 0xc600000 0 0x2000000>, 642 <0 0xe600000 0 0x100000>, 643 <0 0xe700000 0 0xa0000>, 644 <0 0xc40a000 0 0x26000>; 645 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 646 interrupt-names = "periph_irq"; 647 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 648 qcom,ee = <0>; 649 qcom,channel = <0>; 650 #address-cells = <2>; 651 #size-cells = <0>; 652 interrupt-controller; 653 #interrupt-cells = <4>; 654 }; 655 656 tlmm: pinctrl@f100000 { 657 compatible = "qcom,sm6350-tlmm"; 658 reg = <0 0x0f100000 0 0x300000>; 659 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 668 gpio-controller; 669 #gpio-cells = <2>; 670 interrupt-controller; 671 #interrupt-cells = <2>; 672 gpio-ranges = <&tlmm 0 0 157>; 673 }; 674 675 apps_smmu: iommu@15000000 { 676 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 677 reg = <0 0x15000000 0 0x100000>; 678 #iommu-cells = <2>; 679 #global-interrupts = <1>; 680 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 761 }; 762 763 intc: interrupt-controller@17a00000 { 764 compatible = "arm,gic-v3"; 765 #interrupt-cells = <3>; 766 interrupt-controller; 767 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 768 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 769 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 770 }; 771 772 watchdog@17c10000 { 773 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 774 reg = <0 0x17c10000 0 0x1000>; 775 clocks = <&sleep_clk>; 776 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 777 }; 778 779 timer@17c20000 { 780 compatible = "arm,armv7-timer-mem"; 781 reg = <0x0 0x17c20000 0x0 0x1000>; 782 clock-frequency = <19200000>; 783 #address-cells = <2>; 784 #size-cells = <2>; 785 ranges; 786 787 frame@17c21000 { 788 frame-number = <0>; 789 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 791 reg = <0x0 0x17c21000 0x0 0x1000>, 792 <0x0 0x17c22000 0x0 0x1000>; 793 }; 794 795 frame@17c23000 { 796 frame-number = <1>; 797 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 798 reg = <0x0 0x17c23000 0x0 0x1000>; 799 status = "disabled"; 800 }; 801 802 frame@17c25000 { 803 frame-number = <2>; 804 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 805 reg = <0x0 0x17c25000 0x0 0x1000>; 806 status = "disabled"; 807 }; 808 809 frame@17c27000 { 810 frame-number = <3>; 811 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 812 reg = <0x0 0x17c27000 0x0 0x1000>; 813 status = "disabled"; 814 }; 815 816 frame@17c29000 { 817 frame-number = <4>; 818 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 819 reg = <0x0 0x17c29000 0x0 0x1000>; 820 status = "disabled"; 821 }; 822 823 frame@17c2b000 { 824 frame-number = <5>; 825 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 826 reg = <0x0 0x17c2b000 0x0 0x1000>; 827 status = "disabled"; 828 }; 829 830 frame@17c2d000 { 831 frame-number = <6>; 832 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 833 reg = <0x0 0x17c2d000 0x0 0x1000>; 834 status = "disabled"; 835 }; 836 }; 837 838 apps_rsc: rsc@18200000 { 839 compatible = "qcom,rpmh-rsc"; 840 label = "apps_rsc"; 841 reg = <0x0 0x18200000 0x0 0x10000>, 842 <0x0 0x18210000 0x0 0x10000>, 843 <0x0 0x18220000 0x0 0x10000>; 844 reg-names = "drv-0", "drv-1", "drv-2"; 845 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 848 qcom,tcs-offset = <0xd00>; 849 qcom,drv-id = <2>; 850 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 851 <WAKE_TCS 3>, <CONTROL_TCS 1>; 852 853 rpmhcc: clock-controller { 854 compatible = "qcom,sm6350-rpmh-clk"; 855 #clock-cells = <1>; 856 clock-names = "xo"; 857 clocks = <&xo_board>; 858 }; 859 860 rpmhpd: power-controller { 861 compatible = "qcom,sm6350-rpmhpd"; 862 #power-domain-cells = <1>; 863 operating-points-v2 = <&rpmhpd_opp_table>; 864 865 rpmhpd_opp_table: opp-table { 866 compatible = "operating-points-v2"; 867 868 rpmhpd_opp_ret: opp1 { 869 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 870 }; 871 872 rpmhpd_opp_min_svs: opp2 { 873 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 874 }; 875 876 rpmhpd_opp_low_svs: opp3 { 877 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 878 }; 879 880 rpmhpd_opp_svs: opp4 { 881 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 882 }; 883 884 rpmhpd_opp_svs_l1: opp5 { 885 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 886 }; 887 888 rpmhpd_opp_nom: opp6 { 889 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 890 }; 891 892 rpmhpd_opp_nom_l1: opp7 { 893 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 894 }; 895 896 rpmhpd_opp_nom_l2: opp8 { 897 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 898 }; 899 900 rpmhpd_opp_turbo: opp9 { 901 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 902 }; 903 904 rpmhpd_opp_turbo_l1: opp10 { 905 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 906 }; 907 }; 908 }; 909 910 apps_bcm_voter: bcm_voter { 911 compatible = "qcom,bcm-voter"; 912 }; 913 }; 914 915 cpufreq_hw: cpufreq@18323000 { 916 compatible = "qcom,cpufreq-hw"; 917 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 918 reg-names = "freq-domain0", "freq-domain1"; 919 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 920 clock-names = "xo", "alternate"; 921 922 #freq-domain-cells = <1>; 923 }; 924 }; 925 926 timer { 927 compatible = "arm,armv8-timer"; 928 clock-frequency = <19200000>; 929 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 930 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 931 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 932 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 933 }; 934}; 935