1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 static bool enable_acomp = true; 42 module_param(enable_acomp, bool, 0444); 43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)"); 44 45 static bool enable_silent_stream = 46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM); 47 module_param(enable_silent_stream, bool, 0644); 48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices"); 49 50 static bool enable_all_pins; 51 module_param(enable_all_pins, bool, 0444); 52 MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins"); 53 54 struct hdmi_spec_per_cvt { 55 hda_nid_t cvt_nid; 56 int assigned; 57 unsigned int channels_min; 58 unsigned int channels_max; 59 u32 rates; 60 u64 formats; 61 unsigned int maxbps; 62 }; 63 64 /* max. connections to a widget */ 65 #define HDA_MAX_CONNECTIONS 32 66 67 struct hdmi_spec_per_pin { 68 hda_nid_t pin_nid; 69 int dev_id; 70 /* pin idx, different device entries on the same pin use the same idx */ 71 int pin_nid_idx; 72 int num_mux_nids; 73 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 74 int mux_idx; 75 hda_nid_t cvt_nid; 76 77 struct hda_codec *codec; 78 struct hdmi_eld sink_eld; 79 struct mutex lock; 80 struct delayed_work work; 81 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 82 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 83 int repoll_count; 84 bool setup; /* the stream has been set up by prepare callback */ 85 bool silent_stream; 86 int channels; /* current number of channels */ 87 bool non_pcm; 88 bool chmap_set; /* channel-map override by ALSA API? */ 89 unsigned char chmap[8]; /* ALSA API channel-map */ 90 #ifdef CONFIG_SND_PROC_FS 91 struct snd_info_entry *proc_entry; 92 #endif 93 }; 94 95 /* operations used by generic code that can be overridden by patches */ 96 struct hdmi_ops { 97 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 98 int dev_id, unsigned char *buf, int *eld_size); 99 100 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 101 int dev_id, 102 int ca, int active_channels, int conn_type); 103 104 /* enable/disable HBR (HD passthrough) */ 105 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 106 int dev_id, bool hbr); 107 108 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 109 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 110 int format); 111 112 void (*pin_cvt_fixup)(struct hda_codec *codec, 113 struct hdmi_spec_per_pin *per_pin, 114 hda_nid_t cvt_nid); 115 }; 116 117 struct hdmi_pcm { 118 struct hda_pcm *pcm; 119 struct snd_jack *jack; 120 struct snd_kcontrol *eld_ctl; 121 }; 122 123 struct hdmi_spec { 124 struct hda_codec *codec; 125 int num_cvts; 126 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 127 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 128 129 /* 130 * num_pins is the number of virtual pins 131 * for example, there are 3 pins, and each pin 132 * has 4 device entries, then the num_pins is 12 133 */ 134 int num_pins; 135 /* 136 * num_nids is the number of real pins 137 * In the above example, num_nids is 3 138 */ 139 int num_nids; 140 /* 141 * dev_num is the number of device entries 142 * on each pin. 143 * In the above example, dev_num is 4 144 */ 145 int dev_num; 146 struct snd_array pins; /* struct hdmi_spec_per_pin */ 147 struct hdmi_pcm pcm_rec[16]; 148 struct mutex pcm_lock; 149 struct mutex bind_lock; /* for audio component binding */ 150 /* pcm_bitmap means which pcms have been assigned to pins*/ 151 unsigned long pcm_bitmap; 152 int pcm_used; /* counter of pcm_rec[] */ 153 /* bitmap shows whether the pcm is opened in user space 154 * bit 0 means the first playback PCM (PCM3); 155 * bit 1 means the second playback PCM, and so on. 156 */ 157 unsigned long pcm_in_use; 158 159 struct hdmi_eld temp_eld; 160 struct hdmi_ops ops; 161 162 bool dyn_pin_out; 163 bool dyn_pcm_assign; 164 bool dyn_pcm_no_legacy; 165 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 166 /* 167 * Non-generic VIA/NVIDIA specific 168 */ 169 struct hda_multi_out multiout; 170 struct hda_pcm_stream pcm_playback; 171 172 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 173 bool acomp_registered; /* audio component registered in this driver */ 174 bool force_connect; /* force connectivity */ 175 struct drm_audio_component_audio_ops drm_audio_ops; 176 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 177 178 struct hdac_chmap chmap; 179 hda_nid_t vendor_nid; 180 const int *port_map; 181 int port_num; 182 bool send_silent_stream; /* Flag to enable silent stream feature */ 183 }; 184 185 #ifdef CONFIG_SND_HDA_COMPONENT 186 static inline bool codec_has_acomp(struct hda_codec *codec) 187 { 188 struct hdmi_spec *spec = codec->spec; 189 return spec->use_acomp_notifier; 190 } 191 #else 192 #define codec_has_acomp(codec) false 193 #endif 194 195 struct hdmi_audio_infoframe { 196 u8 type; /* 0x84 */ 197 u8 ver; /* 0x01 */ 198 u8 len; /* 0x0a */ 199 200 u8 checksum; 201 202 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 203 u8 SS01_SF24; 204 u8 CXT04; 205 u8 CA; 206 u8 LFEPBL01_LSV36_DM_INH7; 207 }; 208 209 struct dp_audio_infoframe { 210 u8 type; /* 0x84 */ 211 u8 len; /* 0x1b */ 212 u8 ver; /* 0x11 << 2 */ 213 214 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 215 u8 SS01_SF24; 216 u8 CXT04; 217 u8 CA; 218 u8 LFEPBL01_LSV36_DM_INH7; 219 }; 220 221 union audio_infoframe { 222 struct hdmi_audio_infoframe hdmi; 223 struct dp_audio_infoframe dp; 224 u8 bytes[0]; 225 }; 226 227 /* 228 * HDMI routines 229 */ 230 231 #define get_pin(spec, idx) \ 232 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 233 #define get_cvt(spec, idx) \ 234 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 235 /* obtain hdmi_pcm object assigned to idx */ 236 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 237 /* obtain hda_pcm object assigned to idx */ 238 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 239 240 static int pin_id_to_pin_index(struct hda_codec *codec, 241 hda_nid_t pin_nid, int dev_id) 242 { 243 struct hdmi_spec *spec = codec->spec; 244 int pin_idx; 245 struct hdmi_spec_per_pin *per_pin; 246 247 /* 248 * (dev_id == -1) means it is NON-MST pin 249 * return the first virtual pin on this port 250 */ 251 if (dev_id == -1) 252 dev_id = 0; 253 254 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 255 per_pin = get_pin(spec, pin_idx); 256 if ((per_pin->pin_nid == pin_nid) && 257 (per_pin->dev_id == dev_id)) 258 return pin_idx; 259 } 260 261 codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid); 262 return -EINVAL; 263 } 264 265 static int hinfo_to_pcm_index(struct hda_codec *codec, 266 struct hda_pcm_stream *hinfo) 267 { 268 struct hdmi_spec *spec = codec->spec; 269 int pcm_idx; 270 271 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 272 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 273 return pcm_idx; 274 275 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo); 276 return -EINVAL; 277 } 278 279 static int hinfo_to_pin_index(struct hda_codec *codec, 280 struct hda_pcm_stream *hinfo) 281 { 282 struct hdmi_spec *spec = codec->spec; 283 struct hdmi_spec_per_pin *per_pin; 284 int pin_idx; 285 286 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 287 per_pin = get_pin(spec, pin_idx); 288 if (per_pin->pcm && 289 per_pin->pcm->pcm->stream == hinfo) 290 return pin_idx; 291 } 292 293 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo, 294 hinfo_to_pcm_index(codec, hinfo)); 295 return -EINVAL; 296 } 297 298 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 299 int pcm_idx) 300 { 301 int i; 302 struct hdmi_spec_per_pin *per_pin; 303 304 for (i = 0; i < spec->num_pins; i++) { 305 per_pin = get_pin(spec, i); 306 if (per_pin->pcm_idx == pcm_idx) 307 return per_pin; 308 } 309 return NULL; 310 } 311 312 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 313 { 314 struct hdmi_spec *spec = codec->spec; 315 int cvt_idx; 316 317 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 318 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 319 return cvt_idx; 320 321 codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid); 322 return -EINVAL; 323 } 324 325 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 326 struct snd_ctl_elem_info *uinfo) 327 { 328 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 329 struct hdmi_spec *spec = codec->spec; 330 struct hdmi_spec_per_pin *per_pin; 331 struct hdmi_eld *eld; 332 int pcm_idx; 333 334 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 335 336 pcm_idx = kcontrol->private_value; 337 mutex_lock(&spec->pcm_lock); 338 per_pin = pcm_idx_to_pin(spec, pcm_idx); 339 if (!per_pin) { 340 /* no pin is bound to the pcm */ 341 uinfo->count = 0; 342 goto unlock; 343 } 344 eld = &per_pin->sink_eld; 345 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 346 347 unlock: 348 mutex_unlock(&spec->pcm_lock); 349 return 0; 350 } 351 352 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 353 struct snd_ctl_elem_value *ucontrol) 354 { 355 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 356 struct hdmi_spec *spec = codec->spec; 357 struct hdmi_spec_per_pin *per_pin; 358 struct hdmi_eld *eld; 359 int pcm_idx; 360 int err = 0; 361 362 pcm_idx = kcontrol->private_value; 363 mutex_lock(&spec->pcm_lock); 364 per_pin = pcm_idx_to_pin(spec, pcm_idx); 365 if (!per_pin) { 366 /* no pin is bound to the pcm */ 367 memset(ucontrol->value.bytes.data, 0, 368 ARRAY_SIZE(ucontrol->value.bytes.data)); 369 goto unlock; 370 } 371 372 eld = &per_pin->sink_eld; 373 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 374 eld->eld_size > ELD_MAX_SIZE) { 375 snd_BUG(); 376 err = -EINVAL; 377 goto unlock; 378 } 379 380 memset(ucontrol->value.bytes.data, 0, 381 ARRAY_SIZE(ucontrol->value.bytes.data)); 382 if (eld->eld_valid) 383 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 384 eld->eld_size); 385 386 unlock: 387 mutex_unlock(&spec->pcm_lock); 388 return err; 389 } 390 391 static const struct snd_kcontrol_new eld_bytes_ctl = { 392 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | 393 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, 394 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 395 .name = "ELD", 396 .info = hdmi_eld_ctl_info, 397 .get = hdmi_eld_ctl_get, 398 }; 399 400 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 401 int device) 402 { 403 struct snd_kcontrol *kctl; 404 struct hdmi_spec *spec = codec->spec; 405 int err; 406 407 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 408 if (!kctl) 409 return -ENOMEM; 410 kctl->private_value = pcm_idx; 411 kctl->id.device = device; 412 413 /* no pin nid is associated with the kctl now 414 * tbd: associate pin nid to eld ctl later 415 */ 416 err = snd_hda_ctl_add(codec, 0, kctl); 417 if (err < 0) 418 return err; 419 420 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 421 return 0; 422 } 423 424 #ifdef BE_PARANOID 425 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 426 int *packet_index, int *byte_index) 427 { 428 int val; 429 430 val = snd_hda_codec_read(codec, pin_nid, 0, 431 AC_VERB_GET_HDMI_DIP_INDEX, 0); 432 433 *packet_index = val >> 5; 434 *byte_index = val & 0x1f; 435 } 436 #endif 437 438 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 439 int packet_index, int byte_index) 440 { 441 int val; 442 443 val = (packet_index << 5) | (byte_index & 0x1f); 444 445 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 446 } 447 448 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 449 unsigned char val) 450 { 451 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 452 } 453 454 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 455 { 456 struct hdmi_spec *spec = codec->spec; 457 int pin_out; 458 459 /* Unmute */ 460 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 461 snd_hda_codec_write(codec, pin_nid, 0, 462 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 463 464 if (spec->dyn_pin_out) 465 /* Disable pin out until stream is active */ 466 pin_out = 0; 467 else 468 /* Enable pin out: some machines with GM965 gets broken output 469 * when the pin is disabled or changed while using with HDMI 470 */ 471 pin_out = PIN_OUT; 472 473 snd_hda_codec_write(codec, pin_nid, 0, 474 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 475 } 476 477 /* 478 * ELD proc files 479 */ 480 481 #ifdef CONFIG_SND_PROC_FS 482 static void print_eld_info(struct snd_info_entry *entry, 483 struct snd_info_buffer *buffer) 484 { 485 struct hdmi_spec_per_pin *per_pin = entry->private_data; 486 487 mutex_lock(&per_pin->lock); 488 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 489 mutex_unlock(&per_pin->lock); 490 } 491 492 static void write_eld_info(struct snd_info_entry *entry, 493 struct snd_info_buffer *buffer) 494 { 495 struct hdmi_spec_per_pin *per_pin = entry->private_data; 496 497 mutex_lock(&per_pin->lock); 498 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 499 mutex_unlock(&per_pin->lock); 500 } 501 502 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 503 { 504 char name[32]; 505 struct hda_codec *codec = per_pin->codec; 506 struct snd_info_entry *entry; 507 int err; 508 509 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 510 err = snd_card_proc_new(codec->card, name, &entry); 511 if (err < 0) 512 return err; 513 514 snd_info_set_text_ops(entry, per_pin, print_eld_info); 515 entry->c.text.write = write_eld_info; 516 entry->mode |= 0200; 517 per_pin->proc_entry = entry; 518 519 return 0; 520 } 521 522 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 523 { 524 if (!per_pin->codec->bus->shutdown) { 525 snd_info_free_entry(per_pin->proc_entry); 526 per_pin->proc_entry = NULL; 527 } 528 } 529 #else 530 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 531 int index) 532 { 533 return 0; 534 } 535 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 536 { 537 } 538 #endif 539 540 /* 541 * Audio InfoFrame routines 542 */ 543 544 /* 545 * Enable Audio InfoFrame Transmission 546 */ 547 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 548 hda_nid_t pin_nid) 549 { 550 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 551 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 552 AC_DIPXMIT_BEST); 553 } 554 555 /* 556 * Disable Audio InfoFrame Transmission 557 */ 558 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 559 hda_nid_t pin_nid) 560 { 561 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 562 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 563 AC_DIPXMIT_DISABLE); 564 } 565 566 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 567 { 568 #ifdef CONFIG_SND_DEBUG_VERBOSE 569 int i; 570 int size; 571 572 size = snd_hdmi_get_eld_size(codec, pin_nid); 573 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 574 575 for (i = 0; i < 8; i++) { 576 size = snd_hda_codec_read(codec, pin_nid, 0, 577 AC_VERB_GET_HDMI_DIP_SIZE, i); 578 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 579 } 580 #endif 581 } 582 583 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 584 { 585 #ifdef BE_PARANOID 586 int i, j; 587 int size; 588 int pi, bi; 589 for (i = 0; i < 8; i++) { 590 size = snd_hda_codec_read(codec, pin_nid, 0, 591 AC_VERB_GET_HDMI_DIP_SIZE, i); 592 if (size == 0) 593 continue; 594 595 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 596 for (j = 1; j < 1000; j++) { 597 hdmi_write_dip_byte(codec, pin_nid, 0x0); 598 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 599 if (pi != i) 600 codec_dbg(codec, "dip index %d: %d != %d\n", 601 bi, pi, i); 602 if (bi == 0) /* byte index wrapped around */ 603 break; 604 } 605 codec_dbg(codec, 606 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 607 i, size, j); 608 } 609 #endif 610 } 611 612 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 613 { 614 u8 *bytes = (u8 *)hdmi_ai; 615 u8 sum = 0; 616 int i; 617 618 hdmi_ai->checksum = 0; 619 620 for (i = 0; i < sizeof(*hdmi_ai); i++) 621 sum += bytes[i]; 622 623 hdmi_ai->checksum = -sum; 624 } 625 626 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 627 hda_nid_t pin_nid, 628 u8 *dip, int size) 629 { 630 int i; 631 632 hdmi_debug_dip_size(codec, pin_nid); 633 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 634 635 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 636 for (i = 0; i < size; i++) 637 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 638 } 639 640 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 641 u8 *dip, int size) 642 { 643 u8 val; 644 int i; 645 646 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 647 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 648 != AC_DIPXMIT_BEST) 649 return false; 650 651 for (i = 0; i < size; i++) { 652 val = snd_hda_codec_read(codec, pin_nid, 0, 653 AC_VERB_GET_HDMI_DIP_DATA, 0); 654 if (val != dip[i]) 655 return false; 656 } 657 658 return true; 659 } 660 661 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 662 int dev_id, unsigned char *buf, int *eld_size) 663 { 664 snd_hda_set_dev_select(codec, nid, dev_id); 665 666 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 667 } 668 669 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 670 hda_nid_t pin_nid, int dev_id, 671 int ca, int active_channels, 672 int conn_type) 673 { 674 union audio_infoframe ai; 675 676 memset(&ai, 0, sizeof(ai)); 677 if (conn_type == 0) { /* HDMI */ 678 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 679 680 hdmi_ai->type = 0x84; 681 hdmi_ai->ver = 0x01; 682 hdmi_ai->len = 0x0a; 683 hdmi_ai->CC02_CT47 = active_channels - 1; 684 hdmi_ai->CA = ca; 685 hdmi_checksum_audio_infoframe(hdmi_ai); 686 } else if (conn_type == 1) { /* DisplayPort */ 687 struct dp_audio_infoframe *dp_ai = &ai.dp; 688 689 dp_ai->type = 0x84; 690 dp_ai->len = 0x1b; 691 dp_ai->ver = 0x11 << 2; 692 dp_ai->CC02_CT47 = active_channels - 1; 693 dp_ai->CA = ca; 694 } else { 695 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid); 696 return; 697 } 698 699 snd_hda_set_dev_select(codec, pin_nid, dev_id); 700 701 /* 702 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 703 * sizeof(*dp_ai) to avoid partial match/update problems when 704 * the user switches between HDMI/DP monitors. 705 */ 706 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 707 sizeof(ai))) { 708 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n", 709 __func__, pin_nid, active_channels, ca); 710 hdmi_stop_infoframe_trans(codec, pin_nid); 711 hdmi_fill_audio_infoframe(codec, pin_nid, 712 ai.bytes, sizeof(ai)); 713 hdmi_start_infoframe_trans(codec, pin_nid); 714 } 715 } 716 717 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 718 struct hdmi_spec_per_pin *per_pin, 719 bool non_pcm) 720 { 721 struct hdmi_spec *spec = codec->spec; 722 struct hdac_chmap *chmap = &spec->chmap; 723 hda_nid_t pin_nid = per_pin->pin_nid; 724 int dev_id = per_pin->dev_id; 725 int channels = per_pin->channels; 726 int active_channels; 727 struct hdmi_eld *eld; 728 int ca; 729 730 if (!channels) 731 return; 732 733 snd_hda_set_dev_select(codec, pin_nid, dev_id); 734 735 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 736 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 737 snd_hda_codec_write(codec, pin_nid, 0, 738 AC_VERB_SET_AMP_GAIN_MUTE, 739 AMP_OUT_UNMUTE); 740 741 eld = &per_pin->sink_eld; 742 743 ca = snd_hdac_channel_allocation(&codec->core, 744 eld->info.spk_alloc, channels, 745 per_pin->chmap_set, non_pcm, per_pin->chmap); 746 747 active_channels = snd_hdac_get_active_channels(ca); 748 749 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 750 active_channels); 751 752 /* 753 * always configure channel mapping, it may have been changed by the 754 * user in the meantime 755 */ 756 snd_hdac_setup_channel_mapping(&spec->chmap, 757 pin_nid, non_pcm, ca, channels, 758 per_pin->chmap, per_pin->chmap_set); 759 760 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 761 ca, active_channels, eld->info.conn_type); 762 763 per_pin->non_pcm = non_pcm; 764 } 765 766 /* 767 * Unsolicited events 768 */ 769 770 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 771 772 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 773 int dev_id) 774 { 775 struct hdmi_spec *spec = codec->spec; 776 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 777 778 if (pin_idx < 0) 779 return; 780 mutex_lock(&spec->pcm_lock); 781 hdmi_present_sense(get_pin(spec, pin_idx), 1); 782 mutex_unlock(&spec->pcm_lock); 783 } 784 785 static void jack_callback(struct hda_codec *codec, 786 struct hda_jack_callback *jack) 787 { 788 /* stop polling when notification is enabled */ 789 if (codec_has_acomp(codec)) 790 return; 791 792 check_presence_and_report(codec, jack->nid, jack->dev_id); 793 } 794 795 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res, 796 struct hda_jack_tbl *jack) 797 { 798 jack->jack_dirty = 1; 799 800 codec_dbg(codec, 801 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 802 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 803 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 804 805 check_presence_and_report(codec, jack->nid, jack->dev_id); 806 } 807 808 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 809 { 810 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 811 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 812 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 813 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 814 815 codec_info(codec, 816 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 817 codec->addr, 818 tag, 819 subtag, 820 cp_state, 821 cp_ready); 822 823 /* TODO */ 824 if (cp_state) { 825 ; 826 } 827 if (cp_ready) { 828 ; 829 } 830 } 831 832 833 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 834 { 835 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 836 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 837 struct hda_jack_tbl *jack; 838 839 if (codec_has_acomp(codec)) 840 return; 841 842 if (codec->dp_mst) { 843 int dev_entry = 844 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 845 846 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 847 } else { 848 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 849 } 850 851 if (!jack) { 852 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 853 return; 854 } 855 856 if (subtag == 0) 857 hdmi_intrinsic_event(codec, res, jack); 858 else 859 hdmi_non_intrinsic_event(codec, res); 860 } 861 862 static void haswell_verify_D0(struct hda_codec *codec, 863 hda_nid_t cvt_nid, hda_nid_t nid) 864 { 865 int pwr; 866 867 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 868 * thus pins could only choose converter 0 for use. Make sure the 869 * converters are in correct power state */ 870 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 871 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 872 873 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 874 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 875 AC_PWRST_D0); 876 msleep(40); 877 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 878 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 879 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr); 880 } 881 } 882 883 /* 884 * Callbacks 885 */ 886 887 /* HBR should be Non-PCM, 8 channels */ 888 #define is_hbr_format(format) \ 889 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 890 891 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 892 int dev_id, bool hbr) 893 { 894 int pinctl, new_pinctl; 895 896 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 897 snd_hda_set_dev_select(codec, pin_nid, dev_id); 898 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 899 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 900 901 if (pinctl < 0) 902 return hbr ? -EINVAL : 0; 903 904 new_pinctl = pinctl & ~AC_PINCTL_EPT; 905 if (hbr) 906 new_pinctl |= AC_PINCTL_EPT_HBR; 907 else 908 new_pinctl |= AC_PINCTL_EPT_NATIVE; 909 910 codec_dbg(codec, 911 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 912 pin_nid, 913 pinctl == new_pinctl ? "" : "new-", 914 new_pinctl); 915 916 if (pinctl != new_pinctl) 917 snd_hda_codec_write(codec, pin_nid, 0, 918 AC_VERB_SET_PIN_WIDGET_CONTROL, 919 new_pinctl); 920 } else if (hbr) 921 return -EINVAL; 922 923 return 0; 924 } 925 926 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 927 hda_nid_t pin_nid, int dev_id, 928 u32 stream_tag, int format) 929 { 930 struct hdmi_spec *spec = codec->spec; 931 unsigned int param; 932 int err; 933 934 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 935 is_hbr_format(format)); 936 937 if (err) { 938 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 939 return err; 940 } 941 942 if (spec->intel_hsw_fixup) { 943 944 /* 945 * on recent platforms IEC Coding Type is required for HBR 946 * support, read current Digital Converter settings and set 947 * ICT bitfield if needed. 948 */ 949 param = snd_hda_codec_read(codec, cvt_nid, 0, 950 AC_VERB_GET_DIGI_CONVERT_1, 0); 951 952 param = (param >> 16) & ~(AC_DIG3_ICT); 953 954 /* on recent platforms ICT mode is required for HBR support */ 955 if (is_hbr_format(format)) 956 param |= 0x1; 957 958 snd_hda_codec_write(codec, cvt_nid, 0, 959 AC_VERB_SET_DIGI_CONVERT_3, param); 960 } 961 962 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 963 return 0; 964 } 965 966 /* Try to find an available converter 967 * If pin_idx is less then zero, just try to find an available converter. 968 * Otherwise, try to find an available converter and get the cvt mux index 969 * of the pin. 970 */ 971 static int hdmi_choose_cvt(struct hda_codec *codec, 972 int pin_idx, int *cvt_id) 973 { 974 struct hdmi_spec *spec = codec->spec; 975 struct hdmi_spec_per_pin *per_pin; 976 struct hdmi_spec_per_cvt *per_cvt = NULL; 977 int cvt_idx, mux_idx = 0; 978 979 /* pin_idx < 0 means no pin will be bound to the converter */ 980 if (pin_idx < 0) 981 per_pin = NULL; 982 else 983 per_pin = get_pin(spec, pin_idx); 984 985 if (per_pin && per_pin->silent_stream) { 986 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 987 if (cvt_id) 988 *cvt_id = cvt_idx; 989 return 0; 990 } 991 992 /* Dynamically assign converter to stream */ 993 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 994 per_cvt = get_cvt(spec, cvt_idx); 995 996 /* Must not already be assigned */ 997 if (per_cvt->assigned) 998 continue; 999 if (per_pin == NULL) 1000 break; 1001 /* Must be in pin's mux's list of converters */ 1002 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1003 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 1004 break; 1005 /* Not in mux list */ 1006 if (mux_idx == per_pin->num_mux_nids) 1007 continue; 1008 break; 1009 } 1010 1011 /* No free converters */ 1012 if (cvt_idx == spec->num_cvts) 1013 return -EBUSY; 1014 1015 if (per_pin != NULL) 1016 per_pin->mux_idx = mux_idx; 1017 1018 if (cvt_id) 1019 *cvt_id = cvt_idx; 1020 1021 return 0; 1022 } 1023 1024 /* Assure the pin select the right convetor */ 1025 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1026 struct hdmi_spec_per_pin *per_pin) 1027 { 1028 hda_nid_t pin_nid = per_pin->pin_nid; 1029 int mux_idx, curr; 1030 1031 mux_idx = per_pin->mux_idx; 1032 curr = snd_hda_codec_read(codec, pin_nid, 0, 1033 AC_VERB_GET_CONNECT_SEL, 0); 1034 if (curr != mux_idx) 1035 snd_hda_codec_write_cache(codec, pin_nid, 0, 1036 AC_VERB_SET_CONNECT_SEL, 1037 mux_idx); 1038 } 1039 1040 /* get the mux index for the converter of the pins 1041 * converter's mux index is the same for all pins on Intel platform 1042 */ 1043 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1044 hda_nid_t cvt_nid) 1045 { 1046 int i; 1047 1048 for (i = 0; i < spec->num_cvts; i++) 1049 if (spec->cvt_nids[i] == cvt_nid) 1050 return i; 1051 return -EINVAL; 1052 } 1053 1054 /* Intel HDMI workaround to fix audio routing issue: 1055 * For some Intel display codecs, pins share the same connection list. 1056 * So a conveter can be selected by multiple pins and playback on any of these 1057 * pins will generate sound on the external display, because audio flows from 1058 * the same converter to the display pipeline. Also muting one pin may make 1059 * other pins have no sound output. 1060 * So this function assures that an assigned converter for a pin is not selected 1061 * by any other pins. 1062 */ 1063 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1064 hda_nid_t pin_nid, 1065 int dev_id, int mux_idx) 1066 { 1067 struct hdmi_spec *spec = codec->spec; 1068 hda_nid_t nid; 1069 int cvt_idx, curr; 1070 struct hdmi_spec_per_cvt *per_cvt; 1071 struct hdmi_spec_per_pin *per_pin; 1072 int pin_idx; 1073 1074 /* configure the pins connections */ 1075 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1076 int dev_id_saved; 1077 int dev_num; 1078 1079 per_pin = get_pin(spec, pin_idx); 1080 /* 1081 * pin not connected to monitor 1082 * no need to operate on it 1083 */ 1084 if (!per_pin->pcm) 1085 continue; 1086 1087 if ((per_pin->pin_nid == pin_nid) && 1088 (per_pin->dev_id == dev_id)) 1089 continue; 1090 1091 /* 1092 * if per_pin->dev_id >= dev_num, 1093 * snd_hda_get_dev_select() will fail, 1094 * and the following operation is unpredictable. 1095 * So skip this situation. 1096 */ 1097 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1098 if (per_pin->dev_id >= dev_num) 1099 continue; 1100 1101 nid = per_pin->pin_nid; 1102 1103 /* 1104 * Calling this function should not impact 1105 * on the device entry selection 1106 * So let's save the dev id for each pin, 1107 * and restore it when return 1108 */ 1109 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1110 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1111 curr = snd_hda_codec_read(codec, nid, 0, 1112 AC_VERB_GET_CONNECT_SEL, 0); 1113 if (curr != mux_idx) { 1114 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1115 continue; 1116 } 1117 1118 1119 /* choose an unassigned converter. The conveters in the 1120 * connection list are in the same order as in the codec. 1121 */ 1122 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1123 per_cvt = get_cvt(spec, cvt_idx); 1124 if (!per_cvt->assigned) { 1125 codec_dbg(codec, 1126 "choose cvt %d for pin NID 0x%x\n", 1127 cvt_idx, nid); 1128 snd_hda_codec_write_cache(codec, nid, 0, 1129 AC_VERB_SET_CONNECT_SEL, 1130 cvt_idx); 1131 break; 1132 } 1133 } 1134 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1135 } 1136 } 1137 1138 /* A wrapper of intel_not_share_asigned_cvt() */ 1139 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1140 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1141 { 1142 int mux_idx; 1143 struct hdmi_spec *spec = codec->spec; 1144 1145 /* On Intel platform, the mapping of converter nid to 1146 * mux index of the pins are always the same. 1147 * The pin nid may be 0, this means all pins will not 1148 * share the converter. 1149 */ 1150 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1151 if (mux_idx >= 0) 1152 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1153 } 1154 1155 /* skeleton caller of pin_cvt_fixup ops */ 1156 static void pin_cvt_fixup(struct hda_codec *codec, 1157 struct hdmi_spec_per_pin *per_pin, 1158 hda_nid_t cvt_nid) 1159 { 1160 struct hdmi_spec *spec = codec->spec; 1161 1162 if (spec->ops.pin_cvt_fixup) 1163 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1164 } 1165 1166 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1167 * in dyn_pcm_assign mode. 1168 */ 1169 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1170 struct hda_codec *codec, 1171 struct snd_pcm_substream *substream) 1172 { 1173 struct hdmi_spec *spec = codec->spec; 1174 struct snd_pcm_runtime *runtime = substream->runtime; 1175 int cvt_idx, pcm_idx; 1176 struct hdmi_spec_per_cvt *per_cvt = NULL; 1177 int err; 1178 1179 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1180 if (pcm_idx < 0) 1181 return -EINVAL; 1182 1183 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1184 if (err) 1185 return err; 1186 1187 per_cvt = get_cvt(spec, cvt_idx); 1188 per_cvt->assigned = 1; 1189 hinfo->nid = per_cvt->cvt_nid; 1190 1191 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1192 1193 set_bit(pcm_idx, &spec->pcm_in_use); 1194 /* todo: setup spdif ctls assign */ 1195 1196 /* Initially set the converter's capabilities */ 1197 hinfo->channels_min = per_cvt->channels_min; 1198 hinfo->channels_max = per_cvt->channels_max; 1199 hinfo->rates = per_cvt->rates; 1200 hinfo->formats = per_cvt->formats; 1201 hinfo->maxbps = per_cvt->maxbps; 1202 1203 /* Store the updated parameters */ 1204 runtime->hw.channels_min = hinfo->channels_min; 1205 runtime->hw.channels_max = hinfo->channels_max; 1206 runtime->hw.formats = hinfo->formats; 1207 runtime->hw.rates = hinfo->rates; 1208 1209 snd_pcm_hw_constraint_step(substream->runtime, 0, 1210 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1211 return 0; 1212 } 1213 1214 /* 1215 * HDA PCM callbacks 1216 */ 1217 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1218 struct hda_codec *codec, 1219 struct snd_pcm_substream *substream) 1220 { 1221 struct hdmi_spec *spec = codec->spec; 1222 struct snd_pcm_runtime *runtime = substream->runtime; 1223 int pin_idx, cvt_idx, pcm_idx; 1224 struct hdmi_spec_per_pin *per_pin; 1225 struct hdmi_eld *eld; 1226 struct hdmi_spec_per_cvt *per_cvt = NULL; 1227 int err; 1228 1229 /* Validate hinfo */ 1230 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1231 if (pcm_idx < 0) 1232 return -EINVAL; 1233 1234 mutex_lock(&spec->pcm_lock); 1235 pin_idx = hinfo_to_pin_index(codec, hinfo); 1236 if (!spec->dyn_pcm_assign) { 1237 if (snd_BUG_ON(pin_idx < 0)) { 1238 err = -EINVAL; 1239 goto unlock; 1240 } 1241 } else { 1242 /* no pin is assigned to the PCM 1243 * PA need pcm open successfully when probe 1244 */ 1245 if (pin_idx < 0) { 1246 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1247 goto unlock; 1248 } 1249 } 1250 1251 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1252 if (err < 0) 1253 goto unlock; 1254 1255 per_cvt = get_cvt(spec, cvt_idx); 1256 /* Claim converter */ 1257 per_cvt->assigned = 1; 1258 1259 set_bit(pcm_idx, &spec->pcm_in_use); 1260 per_pin = get_pin(spec, pin_idx); 1261 per_pin->cvt_nid = per_cvt->cvt_nid; 1262 hinfo->nid = per_cvt->cvt_nid; 1263 1264 /* flip stripe flag for the assigned stream if supported */ 1265 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1266 azx_stream(get_azx_dev(substream))->stripe = 1; 1267 1268 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1269 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1270 AC_VERB_SET_CONNECT_SEL, 1271 per_pin->mux_idx); 1272 1273 /* configure unused pins to choose other converters */ 1274 pin_cvt_fixup(codec, per_pin, 0); 1275 1276 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1277 1278 /* Initially set the converter's capabilities */ 1279 hinfo->channels_min = per_cvt->channels_min; 1280 hinfo->channels_max = per_cvt->channels_max; 1281 hinfo->rates = per_cvt->rates; 1282 hinfo->formats = per_cvt->formats; 1283 hinfo->maxbps = per_cvt->maxbps; 1284 1285 eld = &per_pin->sink_eld; 1286 /* Restrict capabilities by ELD if this isn't disabled */ 1287 if (!static_hdmi_pcm && eld->eld_valid) { 1288 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1289 if (hinfo->channels_min > hinfo->channels_max || 1290 !hinfo->rates || !hinfo->formats) { 1291 per_cvt->assigned = 0; 1292 hinfo->nid = 0; 1293 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1294 err = -ENODEV; 1295 goto unlock; 1296 } 1297 } 1298 1299 /* Store the updated parameters */ 1300 runtime->hw.channels_min = hinfo->channels_min; 1301 runtime->hw.channels_max = hinfo->channels_max; 1302 runtime->hw.formats = hinfo->formats; 1303 runtime->hw.rates = hinfo->rates; 1304 1305 snd_pcm_hw_constraint_step(substream->runtime, 0, 1306 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1307 unlock: 1308 mutex_unlock(&spec->pcm_lock); 1309 return err; 1310 } 1311 1312 /* 1313 * HDA/HDMI auto parsing 1314 */ 1315 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1316 { 1317 struct hdmi_spec *spec = codec->spec; 1318 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1319 hda_nid_t pin_nid = per_pin->pin_nid; 1320 int dev_id = per_pin->dev_id; 1321 int conns; 1322 1323 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1324 codec_warn(codec, 1325 "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n", 1326 pin_nid, get_wcaps(codec, pin_nid)); 1327 return -EINVAL; 1328 } 1329 1330 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1331 1332 if (spec->intel_hsw_fixup) { 1333 conns = spec->num_cvts; 1334 memcpy(per_pin->mux_nids, spec->cvt_nids, 1335 sizeof(hda_nid_t) * conns); 1336 } else { 1337 conns = snd_hda_get_raw_connections(codec, pin_nid, 1338 per_pin->mux_nids, 1339 HDA_MAX_CONNECTIONS); 1340 } 1341 1342 /* all the device entries on the same pin have the same conn list */ 1343 per_pin->num_mux_nids = conns; 1344 1345 return 0; 1346 } 1347 1348 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1349 struct hdmi_spec_per_pin *per_pin) 1350 { 1351 int i; 1352 1353 /* on the new machines, try to assign the pcm slot dynamically, 1354 * not use the preferred fixed map (legacy way) anymore. 1355 */ 1356 if (spec->dyn_pcm_no_legacy) 1357 goto last_try; 1358 1359 /* 1360 * generic_hdmi_build_pcms() may allocate extra PCMs on some 1361 * platforms (with maximum of 'num_nids + dev_num - 1') 1362 * 1363 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n 1364 * if m==0. This guarantees that dynamic pcm assignments are compatible 1365 * with the legacy static per_pin-pcm assignment that existed in the 1366 * days before DP-MST. 1367 * 1368 * Intel DP-MST prefers this legacy behavior for compatibility, too. 1369 * 1370 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)). 1371 */ 1372 1373 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) { 1374 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1375 return per_pin->pin_nid_idx; 1376 } else { 1377 i = spec->num_nids + (per_pin->dev_id - 1); 1378 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap))) 1379 return i; 1380 } 1381 1382 /* have a second try; check the area over num_nids */ 1383 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1384 if (!test_bit(i, &spec->pcm_bitmap)) 1385 return i; 1386 } 1387 1388 last_try: 1389 /* the last try; check the empty slots in pins */ 1390 for (i = 0; i < spec->num_nids; i++) { 1391 if (!test_bit(i, &spec->pcm_bitmap)) 1392 return i; 1393 } 1394 return -EBUSY; 1395 } 1396 1397 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1398 struct hdmi_spec_per_pin *per_pin) 1399 { 1400 int idx; 1401 1402 /* pcm already be attached to the pin */ 1403 if (per_pin->pcm) 1404 return; 1405 idx = hdmi_find_pcm_slot(spec, per_pin); 1406 if (idx == -EBUSY) 1407 return; 1408 per_pin->pcm_idx = idx; 1409 per_pin->pcm = get_hdmi_pcm(spec, idx); 1410 set_bit(idx, &spec->pcm_bitmap); 1411 } 1412 1413 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1414 struct hdmi_spec_per_pin *per_pin) 1415 { 1416 int idx; 1417 1418 /* pcm already be detached from the pin */ 1419 if (!per_pin->pcm) 1420 return; 1421 idx = per_pin->pcm_idx; 1422 per_pin->pcm_idx = -1; 1423 per_pin->pcm = NULL; 1424 if (idx >= 0 && idx < spec->pcm_used) 1425 clear_bit(idx, &spec->pcm_bitmap); 1426 } 1427 1428 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1429 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1430 { 1431 int mux_idx; 1432 1433 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1434 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1435 break; 1436 return mux_idx; 1437 } 1438 1439 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1440 1441 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1442 struct hdmi_spec_per_pin *per_pin) 1443 { 1444 struct hda_codec *codec = per_pin->codec; 1445 struct hda_pcm *pcm; 1446 struct hda_pcm_stream *hinfo; 1447 struct snd_pcm_substream *substream; 1448 int mux_idx; 1449 bool non_pcm; 1450 1451 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1452 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1453 else 1454 return; 1455 if (!pcm->pcm) 1456 return; 1457 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1458 return; 1459 1460 /* hdmi audio only uses playback and one substream */ 1461 hinfo = pcm->stream; 1462 substream = pcm->pcm->streams[0].substream; 1463 1464 per_pin->cvt_nid = hinfo->nid; 1465 1466 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1467 if (mux_idx < per_pin->num_mux_nids) { 1468 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1469 per_pin->dev_id); 1470 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1471 AC_VERB_SET_CONNECT_SEL, 1472 mux_idx); 1473 } 1474 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1475 1476 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1477 if (substream->runtime) 1478 per_pin->channels = substream->runtime->channels; 1479 per_pin->setup = true; 1480 per_pin->mux_idx = mux_idx; 1481 1482 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1483 } 1484 1485 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1486 struct hdmi_spec_per_pin *per_pin) 1487 { 1488 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1489 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1490 1491 per_pin->chmap_set = false; 1492 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1493 1494 per_pin->setup = false; 1495 per_pin->channels = 0; 1496 } 1497 1498 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec, 1499 struct hdmi_spec_per_pin *per_pin) 1500 { 1501 struct hdmi_spec *spec = codec->spec; 1502 1503 if (per_pin->pcm_idx >= 0) 1504 return spec->pcm_rec[per_pin->pcm_idx].jack; 1505 else 1506 return NULL; 1507 } 1508 1509 /* update per_pin ELD from the given new ELD; 1510 * setup info frame and notification accordingly 1511 * also notify ELD kctl and report jack status changes 1512 */ 1513 static void update_eld(struct hda_codec *codec, 1514 struct hdmi_spec_per_pin *per_pin, 1515 struct hdmi_eld *eld, 1516 int repoll) 1517 { 1518 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1519 struct hdmi_spec *spec = codec->spec; 1520 struct snd_jack *pcm_jack; 1521 bool old_eld_valid = pin_eld->eld_valid; 1522 bool eld_changed; 1523 int pcm_idx; 1524 1525 if (eld->eld_valid) { 1526 if (eld->eld_size <= 0 || 1527 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1528 eld->eld_size) < 0) { 1529 eld->eld_valid = false; 1530 if (repoll) { 1531 schedule_delayed_work(&per_pin->work, 1532 msecs_to_jiffies(300)); 1533 return; 1534 } 1535 } 1536 } 1537 1538 if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) { 1539 eld->eld_valid = false; 1540 eld->eld_size = 0; 1541 } 1542 1543 /* for monitor disconnection, save pcm_idx firstly */ 1544 pcm_idx = per_pin->pcm_idx; 1545 1546 /* 1547 * pcm_idx >=0 before update_eld() means it is in monitor 1548 * disconnected event. Jack must be fetched before update_eld(). 1549 */ 1550 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1551 1552 if (spec->dyn_pcm_assign) { 1553 if (eld->eld_valid) { 1554 hdmi_attach_hda_pcm(spec, per_pin); 1555 hdmi_pcm_setup_pin(spec, per_pin); 1556 } else { 1557 hdmi_pcm_reset_pin(spec, per_pin); 1558 hdmi_detach_hda_pcm(spec, per_pin); 1559 } 1560 } 1561 /* if pcm_idx == -1, it means this is in monitor connection event 1562 * we can get the correct pcm_idx now. 1563 */ 1564 if (pcm_idx == -1) 1565 pcm_idx = per_pin->pcm_idx; 1566 if (!pcm_jack) 1567 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1568 1569 if (eld->eld_valid) 1570 snd_hdmi_show_eld(codec, &eld->info); 1571 1572 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1573 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1574 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1575 if (pin_eld->eld_size != eld->eld_size || 1576 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1577 eld->eld_size) != 0) 1578 eld_changed = true; 1579 1580 if (eld_changed) { 1581 pin_eld->monitor_present = eld->monitor_present; 1582 pin_eld->eld_valid = eld->eld_valid; 1583 pin_eld->eld_size = eld->eld_size; 1584 if (eld->eld_valid) 1585 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1586 eld->eld_size); 1587 pin_eld->info = eld->info; 1588 } 1589 1590 /* 1591 * Re-setup pin and infoframe. This is needed e.g. when 1592 * - sink is first plugged-in 1593 * - transcoder can change during stream playback on Haswell 1594 * and this can make HW reset converter selection on a pin. 1595 */ 1596 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1597 pin_cvt_fixup(codec, per_pin, 0); 1598 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1599 } 1600 1601 if (eld_changed && pcm_idx >= 0) 1602 snd_ctl_notify(codec->card, 1603 SNDRV_CTL_EVENT_MASK_VALUE | 1604 SNDRV_CTL_EVENT_MASK_INFO, 1605 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1606 1607 if (eld_changed && pcm_jack) 1608 snd_jack_report(pcm_jack, 1609 (eld->monitor_present && eld->eld_valid) ? 1610 SND_JACK_AVOUT : 0); 1611 } 1612 1613 /* update ELD and jack state via HD-audio verbs */ 1614 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1615 int repoll) 1616 { 1617 struct hda_codec *codec = per_pin->codec; 1618 struct hdmi_spec *spec = codec->spec; 1619 struct hdmi_eld *eld = &spec->temp_eld; 1620 hda_nid_t pin_nid = per_pin->pin_nid; 1621 int dev_id = per_pin->dev_id; 1622 /* 1623 * Always execute a GetPinSense verb here, even when called from 1624 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1625 * response's PD bit is not the real PD value, but indicates that 1626 * the real PD value changed. An older version of the HD-audio 1627 * specification worked this way. Hence, we just ignore the data in 1628 * the unsolicited response to avoid custom WARs. 1629 */ 1630 int present; 1631 int ret; 1632 1633 ret = snd_hda_power_up_pm(codec); 1634 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) 1635 goto out; 1636 1637 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1638 1639 mutex_lock(&per_pin->lock); 1640 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1641 if (eld->monitor_present) 1642 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1643 else 1644 eld->eld_valid = false; 1645 1646 codec_dbg(codec, 1647 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n", 1648 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1649 1650 if (eld->eld_valid) { 1651 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1652 eld->eld_buffer, &eld->eld_size) < 0) 1653 eld->eld_valid = false; 1654 } 1655 1656 update_eld(codec, per_pin, eld, repoll); 1657 mutex_unlock(&per_pin->lock); 1658 out: 1659 snd_hda_power_down_pm(codec); 1660 } 1661 1662 #define I915_SILENT_RATE 48000 1663 #define I915_SILENT_CHANNELS 2 1664 #define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE 1665 #define I915_SILENT_FORMAT_BITS 16 1666 #define I915_SILENT_FMT_MASK 0xf 1667 1668 static void silent_stream_enable(struct hda_codec *codec, 1669 struct hdmi_spec_per_pin *per_pin) 1670 { 1671 struct hdmi_spec *spec = codec->spec; 1672 struct hdmi_spec_per_cvt *per_cvt; 1673 int cvt_idx, pin_idx, err; 1674 unsigned int format; 1675 1676 mutex_lock(&per_pin->lock); 1677 1678 if (per_pin->setup) { 1679 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n"); 1680 goto unlock_out; 1681 } 1682 1683 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id); 1684 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1685 if (err) { 1686 codec_err(codec, "hdmi: no free converter to enable silent mode\n"); 1687 goto unlock_out; 1688 } 1689 1690 per_cvt = get_cvt(spec, cvt_idx); 1691 per_cvt->assigned = 1; 1692 per_pin->cvt_nid = per_cvt->cvt_nid; 1693 per_pin->silent_stream = true; 1694 1695 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n", 1696 per_pin->pin_nid, per_cvt->cvt_nid); 1697 1698 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1699 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1700 AC_VERB_SET_CONNECT_SEL, 1701 per_pin->mux_idx); 1702 1703 /* configure unused pins to choose other converters */ 1704 pin_cvt_fixup(codec, per_pin, 0); 1705 1706 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1707 per_pin->dev_id, I915_SILENT_RATE); 1708 1709 /* trigger silent stream generation in hw */ 1710 format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS, 1711 I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0); 1712 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, 1713 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format); 1714 usleep_range(100, 200); 1715 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format); 1716 1717 per_pin->channels = I915_SILENT_CHANNELS; 1718 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1719 1720 unlock_out: 1721 mutex_unlock(&per_pin->lock); 1722 } 1723 1724 static void silent_stream_disable(struct hda_codec *codec, 1725 struct hdmi_spec_per_pin *per_pin) 1726 { 1727 struct hdmi_spec *spec = codec->spec; 1728 struct hdmi_spec_per_cvt *per_cvt; 1729 int cvt_idx; 1730 1731 mutex_lock(&per_pin->lock); 1732 if (!per_pin->silent_stream) 1733 goto unlock_out; 1734 1735 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n", 1736 per_pin->pin_nid, per_pin->cvt_nid); 1737 1738 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 1739 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) { 1740 per_cvt = get_cvt(spec, cvt_idx); 1741 per_cvt->assigned = 0; 1742 } 1743 1744 per_pin->cvt_nid = 0; 1745 per_pin->silent_stream = false; 1746 1747 unlock_out: 1748 mutex_unlock(&per_pin->lock); 1749 } 1750 1751 /* update ELD and jack state via audio component */ 1752 static void sync_eld_via_acomp(struct hda_codec *codec, 1753 struct hdmi_spec_per_pin *per_pin) 1754 { 1755 struct hdmi_spec *spec = codec->spec; 1756 struct hdmi_eld *eld = &spec->temp_eld; 1757 bool monitor_prev, monitor_next; 1758 1759 mutex_lock(&per_pin->lock); 1760 eld->monitor_present = false; 1761 monitor_prev = per_pin->sink_eld.monitor_present; 1762 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1763 per_pin->dev_id, &eld->monitor_present, 1764 eld->eld_buffer, ELD_MAX_SIZE); 1765 eld->eld_valid = (eld->eld_size > 0); 1766 update_eld(codec, per_pin, eld, 0); 1767 monitor_next = per_pin->sink_eld.monitor_present; 1768 mutex_unlock(&per_pin->lock); 1769 1770 /* 1771 * Power-up will call hdmi_present_sense, so the PM calls 1772 * have to be done without mutex held. 1773 */ 1774 1775 if (spec->send_silent_stream) { 1776 int pm_ret; 1777 1778 if (!monitor_prev && monitor_next) { 1779 pm_ret = snd_hda_power_up_pm(codec); 1780 if (pm_ret < 0) 1781 codec_err(codec, 1782 "Monitor plugged-in, Failed to power up codec ret=[%d]\n", 1783 pm_ret); 1784 silent_stream_enable(codec, per_pin); 1785 } else if (monitor_prev && !monitor_next) { 1786 silent_stream_disable(codec, per_pin); 1787 pm_ret = snd_hda_power_down_pm(codec); 1788 if (pm_ret < 0) 1789 codec_err(codec, 1790 "Monitor plugged-out, Failed to power down codec ret=[%d]\n", 1791 pm_ret); 1792 } 1793 } 1794 } 1795 1796 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1797 { 1798 struct hda_codec *codec = per_pin->codec; 1799 1800 if (!codec_has_acomp(codec)) 1801 hdmi_present_sense_via_verbs(per_pin, repoll); 1802 else 1803 sync_eld_via_acomp(codec, per_pin); 1804 } 1805 1806 static void hdmi_repoll_eld(struct work_struct *work) 1807 { 1808 struct hdmi_spec_per_pin *per_pin = 1809 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1810 struct hda_codec *codec = per_pin->codec; 1811 struct hdmi_spec *spec = codec->spec; 1812 struct hda_jack_tbl *jack; 1813 1814 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1815 per_pin->dev_id); 1816 if (jack) 1817 jack->jack_dirty = 1; 1818 1819 if (per_pin->repoll_count++ > 6) 1820 per_pin->repoll_count = 0; 1821 1822 mutex_lock(&spec->pcm_lock); 1823 hdmi_present_sense(per_pin, per_pin->repoll_count); 1824 mutex_unlock(&spec->pcm_lock); 1825 } 1826 1827 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1828 { 1829 struct hdmi_spec *spec = codec->spec; 1830 unsigned int caps, config; 1831 int pin_idx; 1832 struct hdmi_spec_per_pin *per_pin; 1833 int err; 1834 int dev_num, i; 1835 1836 caps = snd_hda_query_pin_caps(codec, pin_nid); 1837 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1838 return 0; 1839 1840 /* 1841 * For DP MST audio, Configuration Default is the same for 1842 * all device entries on the same pin 1843 */ 1844 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1845 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE && 1846 !spec->force_connect) 1847 return 0; 1848 1849 /* 1850 * To simplify the implementation, malloc all 1851 * the virtual pins in the initialization statically 1852 */ 1853 if (spec->intel_hsw_fixup) { 1854 /* 1855 * On Intel platforms, device entries count returned 1856 * by AC_PAR_DEVLIST_LEN is dynamic, and depends on 1857 * the type of receiver that is connected. Allocate pin 1858 * structures based on worst case. 1859 */ 1860 dev_num = spec->dev_num; 1861 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1862 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1863 /* 1864 * spec->dev_num is the maxinum number of device entries 1865 * among all the pins 1866 */ 1867 spec->dev_num = (spec->dev_num > dev_num) ? 1868 spec->dev_num : dev_num; 1869 } else { 1870 /* 1871 * If the platform doesn't support DP MST, 1872 * manually set dev_num to 1. This means 1873 * the pin has only one device entry. 1874 */ 1875 dev_num = 1; 1876 spec->dev_num = 1; 1877 } 1878 1879 for (i = 0; i < dev_num; i++) { 1880 pin_idx = spec->num_pins; 1881 per_pin = snd_array_new(&spec->pins); 1882 1883 if (!per_pin) 1884 return -ENOMEM; 1885 1886 if (spec->dyn_pcm_assign) { 1887 per_pin->pcm = NULL; 1888 per_pin->pcm_idx = -1; 1889 } else { 1890 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1891 per_pin->pcm_idx = pin_idx; 1892 } 1893 per_pin->pin_nid = pin_nid; 1894 per_pin->pin_nid_idx = spec->num_nids; 1895 per_pin->dev_id = i; 1896 per_pin->non_pcm = false; 1897 snd_hda_set_dev_select(codec, pin_nid, i); 1898 err = hdmi_read_pin_conn(codec, pin_idx); 1899 if (err < 0) 1900 return err; 1901 spec->num_pins++; 1902 } 1903 spec->num_nids++; 1904 1905 return 0; 1906 } 1907 1908 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1909 { 1910 struct hdmi_spec *spec = codec->spec; 1911 struct hdmi_spec_per_cvt *per_cvt; 1912 unsigned int chans; 1913 int err; 1914 1915 chans = get_wcaps(codec, cvt_nid); 1916 chans = get_wcaps_channels(chans); 1917 1918 per_cvt = snd_array_new(&spec->cvts); 1919 if (!per_cvt) 1920 return -ENOMEM; 1921 1922 per_cvt->cvt_nid = cvt_nid; 1923 per_cvt->channels_min = 2; 1924 if (chans <= 16) { 1925 per_cvt->channels_max = chans; 1926 if (chans > spec->chmap.channels_max) 1927 spec->chmap.channels_max = chans; 1928 } 1929 1930 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1931 &per_cvt->rates, 1932 &per_cvt->formats, 1933 &per_cvt->maxbps); 1934 if (err < 0) 1935 return err; 1936 1937 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1938 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1939 spec->num_cvts++; 1940 1941 return 0; 1942 } 1943 1944 static const struct snd_pci_quirk force_connect_list[] = { 1945 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1), 1946 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1), 1947 SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1), 1948 SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1), 1949 {} 1950 }; 1951 1952 static int hdmi_parse_codec(struct hda_codec *codec) 1953 { 1954 struct hdmi_spec *spec = codec->spec; 1955 hda_nid_t start_nid; 1956 unsigned int caps; 1957 int i, nodes; 1958 const struct snd_pci_quirk *q; 1959 1960 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid); 1961 if (!start_nid || nodes < 0) { 1962 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1963 return -EINVAL; 1964 } 1965 1966 if (enable_all_pins) 1967 spec->force_connect = true; 1968 1969 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list); 1970 1971 if (q && q->value) 1972 spec->force_connect = true; 1973 1974 /* 1975 * hdmi_add_pin() assumes total amount of converters to 1976 * be known, so first discover all converters 1977 */ 1978 for (i = 0; i < nodes; i++) { 1979 hda_nid_t nid = start_nid + i; 1980 1981 caps = get_wcaps(codec, nid); 1982 1983 if (!(caps & AC_WCAP_DIGITAL)) 1984 continue; 1985 1986 if (get_wcaps_type(caps) == AC_WID_AUD_OUT) 1987 hdmi_add_cvt(codec, nid); 1988 } 1989 1990 /* discover audio pins */ 1991 for (i = 0; i < nodes; i++) { 1992 hda_nid_t nid = start_nid + i; 1993 1994 caps = get_wcaps(codec, nid); 1995 1996 if (!(caps & AC_WCAP_DIGITAL)) 1997 continue; 1998 1999 if (get_wcaps_type(caps) == AC_WID_PIN) 2000 hdmi_add_pin(codec, nid); 2001 } 2002 2003 return 0; 2004 } 2005 2006 /* 2007 */ 2008 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 2009 { 2010 struct hda_spdif_out *spdif; 2011 bool non_pcm; 2012 2013 mutex_lock(&codec->spdif_mutex); 2014 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 2015 /* Add sanity check to pass klockwork check. 2016 * This should never happen. 2017 */ 2018 if (WARN_ON(spdif == NULL)) { 2019 mutex_unlock(&codec->spdif_mutex); 2020 return true; 2021 } 2022 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 2023 mutex_unlock(&codec->spdif_mutex); 2024 return non_pcm; 2025 } 2026 2027 /* 2028 * HDMI callbacks 2029 */ 2030 2031 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2032 struct hda_codec *codec, 2033 unsigned int stream_tag, 2034 unsigned int format, 2035 struct snd_pcm_substream *substream) 2036 { 2037 hda_nid_t cvt_nid = hinfo->nid; 2038 struct hdmi_spec *spec = codec->spec; 2039 int pin_idx; 2040 struct hdmi_spec_per_pin *per_pin; 2041 struct snd_pcm_runtime *runtime = substream->runtime; 2042 bool non_pcm; 2043 int pinctl, stripe; 2044 int err = 0; 2045 2046 mutex_lock(&spec->pcm_lock); 2047 pin_idx = hinfo_to_pin_index(codec, hinfo); 2048 if (spec->dyn_pcm_assign && pin_idx < 0) { 2049 /* when dyn_pcm_assign and pcm is not bound to a pin 2050 * skip pin setup and return 0 to make audio playback 2051 * be ongoing 2052 */ 2053 pin_cvt_fixup(codec, NULL, cvt_nid); 2054 snd_hda_codec_setup_stream(codec, cvt_nid, 2055 stream_tag, 0, format); 2056 goto unlock; 2057 } 2058 2059 if (snd_BUG_ON(pin_idx < 0)) { 2060 err = -EINVAL; 2061 goto unlock; 2062 } 2063 per_pin = get_pin(spec, pin_idx); 2064 2065 /* Verify pin:cvt selections to avoid silent audio after S3. 2066 * After S3, the audio driver restores pin:cvt selections 2067 * but this can happen before gfx is ready and such selection 2068 * is overlooked by HW. Thus multiple pins can share a same 2069 * default convertor and mute control will affect each other, 2070 * which can cause a resumed audio playback become silent 2071 * after S3. 2072 */ 2073 pin_cvt_fixup(codec, per_pin, 0); 2074 2075 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 2076 /* Todo: add DP1.2 MST audio support later */ 2077 if (codec_has_acomp(codec)) 2078 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 2079 per_pin->dev_id, runtime->rate); 2080 2081 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 2082 mutex_lock(&per_pin->lock); 2083 per_pin->channels = substream->runtime->channels; 2084 per_pin->setup = true; 2085 2086 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 2087 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 2088 substream); 2089 snd_hda_codec_write(codec, cvt_nid, 0, 2090 AC_VERB_SET_STRIPE_CONTROL, 2091 stripe); 2092 } 2093 2094 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 2095 mutex_unlock(&per_pin->lock); 2096 if (spec->dyn_pin_out) { 2097 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2098 per_pin->dev_id); 2099 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2100 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2101 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2102 AC_VERB_SET_PIN_WIDGET_CONTROL, 2103 pinctl | PIN_OUT); 2104 } 2105 2106 /* snd_hda_set_dev_select() has been called before */ 2107 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 2108 per_pin->dev_id, stream_tag, format); 2109 unlock: 2110 mutex_unlock(&spec->pcm_lock); 2111 return err; 2112 } 2113 2114 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2115 struct hda_codec *codec, 2116 struct snd_pcm_substream *substream) 2117 { 2118 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 2119 return 0; 2120 } 2121 2122 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 2123 struct hda_codec *codec, 2124 struct snd_pcm_substream *substream) 2125 { 2126 struct hdmi_spec *spec = codec->spec; 2127 int cvt_idx, pin_idx, pcm_idx; 2128 struct hdmi_spec_per_cvt *per_cvt; 2129 struct hdmi_spec_per_pin *per_pin; 2130 int pinctl; 2131 int err = 0; 2132 2133 mutex_lock(&spec->pcm_lock); 2134 if (hinfo->nid) { 2135 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 2136 if (snd_BUG_ON(pcm_idx < 0)) { 2137 err = -EINVAL; 2138 goto unlock; 2139 } 2140 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 2141 if (snd_BUG_ON(cvt_idx < 0)) { 2142 err = -EINVAL; 2143 goto unlock; 2144 } 2145 per_cvt = get_cvt(spec, cvt_idx); 2146 per_cvt->assigned = 0; 2147 hinfo->nid = 0; 2148 2149 azx_stream(get_azx_dev(substream))->stripe = 0; 2150 2151 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2152 clear_bit(pcm_idx, &spec->pcm_in_use); 2153 pin_idx = hinfo_to_pin_index(codec, hinfo); 2154 if (spec->dyn_pcm_assign && pin_idx < 0) 2155 goto unlock; 2156 2157 if (snd_BUG_ON(pin_idx < 0)) { 2158 err = -EINVAL; 2159 goto unlock; 2160 } 2161 per_pin = get_pin(spec, pin_idx); 2162 2163 if (spec->dyn_pin_out) { 2164 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2165 per_pin->dev_id); 2166 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2167 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2168 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2169 AC_VERB_SET_PIN_WIDGET_CONTROL, 2170 pinctl & ~PIN_OUT); 2171 } 2172 2173 mutex_lock(&per_pin->lock); 2174 per_pin->chmap_set = false; 2175 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2176 2177 per_pin->setup = false; 2178 per_pin->channels = 0; 2179 mutex_unlock(&per_pin->lock); 2180 } 2181 2182 unlock: 2183 mutex_unlock(&spec->pcm_lock); 2184 2185 return err; 2186 } 2187 2188 static const struct hda_pcm_ops generic_ops = { 2189 .open = hdmi_pcm_open, 2190 .close = hdmi_pcm_close, 2191 .prepare = generic_hdmi_playback_pcm_prepare, 2192 .cleanup = generic_hdmi_playback_pcm_cleanup, 2193 }; 2194 2195 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2196 { 2197 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2198 struct hdmi_spec *spec = codec->spec; 2199 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2200 2201 if (!per_pin) 2202 return 0; 2203 2204 return per_pin->sink_eld.info.spk_alloc; 2205 } 2206 2207 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2208 unsigned char *chmap) 2209 { 2210 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2211 struct hdmi_spec *spec = codec->spec; 2212 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2213 2214 /* chmap is already set to 0 in caller */ 2215 if (!per_pin) 2216 return; 2217 2218 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2219 } 2220 2221 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2222 unsigned char *chmap, int prepared) 2223 { 2224 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2225 struct hdmi_spec *spec = codec->spec; 2226 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2227 2228 if (!per_pin) 2229 return; 2230 mutex_lock(&per_pin->lock); 2231 per_pin->chmap_set = true; 2232 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2233 if (prepared) 2234 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2235 mutex_unlock(&per_pin->lock); 2236 } 2237 2238 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2239 { 2240 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2241 struct hdmi_spec *spec = codec->spec; 2242 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2243 2244 return per_pin ? true:false; 2245 } 2246 2247 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2248 { 2249 struct hdmi_spec *spec = codec->spec; 2250 int idx, pcm_num; 2251 2252 /* 2253 * for non-mst mode, pcm number is the same as before 2254 * for DP MST mode without extra PCM, pcm number is same 2255 * for DP MST mode with extra PCMs, pcm number is 2256 * (nid number + dev_num - 1) 2257 * dev_num is the device entry number in a pin 2258 */ 2259 2260 if (codec->mst_no_extra_pcms) 2261 pcm_num = spec->num_nids; 2262 else 2263 pcm_num = spec->num_nids + spec->dev_num - 1; 2264 2265 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2266 2267 for (idx = 0; idx < pcm_num; idx++) { 2268 struct hda_pcm *info; 2269 struct hda_pcm_stream *pstr; 2270 2271 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2272 if (!info) 2273 return -ENOMEM; 2274 2275 spec->pcm_rec[idx].pcm = info; 2276 spec->pcm_used++; 2277 info->pcm_type = HDA_PCM_TYPE_HDMI; 2278 info->own_chmap = true; 2279 2280 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2281 pstr->substreams = 1; 2282 pstr->ops = generic_ops; 2283 /* pcm number is less than 16 */ 2284 if (spec->pcm_used >= 16) 2285 break; 2286 /* other pstr fields are set in open */ 2287 } 2288 2289 return 0; 2290 } 2291 2292 static void free_hdmi_jack_priv(struct snd_jack *jack) 2293 { 2294 struct hdmi_pcm *pcm = jack->private_data; 2295 2296 pcm->jack = NULL; 2297 } 2298 2299 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2300 { 2301 char hdmi_str[32] = "HDMI/DP"; 2302 struct hdmi_spec *spec = codec->spec; 2303 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx); 2304 struct snd_jack *jack; 2305 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2306 int err; 2307 2308 if (pcmdev > 0) 2309 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2310 if (!spec->dyn_pcm_assign && 2311 !is_jack_detectable(codec, per_pin->pin_nid)) 2312 strncat(hdmi_str, " Phantom", 2313 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2314 2315 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack, 2316 true, false); 2317 if (err < 0) 2318 return err; 2319 2320 spec->pcm_rec[pcm_idx].jack = jack; 2321 jack->private_data = &spec->pcm_rec[pcm_idx]; 2322 jack->private_free = free_hdmi_jack_priv; 2323 return 0; 2324 } 2325 2326 static int generic_hdmi_build_controls(struct hda_codec *codec) 2327 { 2328 struct hdmi_spec *spec = codec->spec; 2329 int dev, err; 2330 int pin_idx, pcm_idx; 2331 2332 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2333 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2334 /* no PCM: mark this for skipping permanently */ 2335 set_bit(pcm_idx, &spec->pcm_bitmap); 2336 continue; 2337 } 2338 2339 err = generic_hdmi_build_jack(codec, pcm_idx); 2340 if (err < 0) 2341 return err; 2342 2343 /* create the spdif for each pcm 2344 * pin will be bound when monitor is connected 2345 */ 2346 if (spec->dyn_pcm_assign) 2347 err = snd_hda_create_dig_out_ctls(codec, 2348 0, spec->cvt_nids[0], 2349 HDA_PCM_TYPE_HDMI); 2350 else { 2351 struct hdmi_spec_per_pin *per_pin = 2352 get_pin(spec, pcm_idx); 2353 err = snd_hda_create_dig_out_ctls(codec, 2354 per_pin->pin_nid, 2355 per_pin->mux_nids[0], 2356 HDA_PCM_TYPE_HDMI); 2357 } 2358 if (err < 0) 2359 return err; 2360 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2361 2362 dev = get_pcm_rec(spec, pcm_idx)->device; 2363 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2364 /* add control for ELD Bytes */ 2365 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2366 if (err < 0) 2367 return err; 2368 } 2369 } 2370 2371 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2372 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2373 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 2374 2375 pin_eld->eld_valid = false; 2376 hdmi_present_sense(per_pin, 0); 2377 } 2378 2379 /* add channel maps */ 2380 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2381 struct hda_pcm *pcm; 2382 2383 pcm = get_pcm_rec(spec, pcm_idx); 2384 if (!pcm || !pcm->pcm) 2385 break; 2386 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2387 if (err < 0) 2388 return err; 2389 } 2390 2391 return 0; 2392 } 2393 2394 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2395 { 2396 struct hdmi_spec *spec = codec->spec; 2397 int pin_idx; 2398 2399 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2400 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2401 2402 per_pin->codec = codec; 2403 mutex_init(&per_pin->lock); 2404 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2405 eld_proc_new(per_pin, pin_idx); 2406 } 2407 return 0; 2408 } 2409 2410 static int generic_hdmi_init(struct hda_codec *codec) 2411 { 2412 struct hdmi_spec *spec = codec->spec; 2413 int pin_idx; 2414 2415 mutex_lock(&spec->bind_lock); 2416 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2417 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2418 hda_nid_t pin_nid = per_pin->pin_nid; 2419 int dev_id = per_pin->dev_id; 2420 2421 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2422 hdmi_init_pin(codec, pin_nid); 2423 if (codec_has_acomp(codec)) 2424 continue; 2425 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id, 2426 jack_callback); 2427 } 2428 mutex_unlock(&spec->bind_lock); 2429 return 0; 2430 } 2431 2432 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2433 { 2434 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2435 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2436 } 2437 2438 static void hdmi_array_free(struct hdmi_spec *spec) 2439 { 2440 snd_array_free(&spec->pins); 2441 snd_array_free(&spec->cvts); 2442 } 2443 2444 static void generic_spec_free(struct hda_codec *codec) 2445 { 2446 struct hdmi_spec *spec = codec->spec; 2447 2448 if (spec) { 2449 hdmi_array_free(spec); 2450 kfree(spec); 2451 codec->spec = NULL; 2452 } 2453 codec->dp_mst = false; 2454 } 2455 2456 static void generic_hdmi_free(struct hda_codec *codec) 2457 { 2458 struct hdmi_spec *spec = codec->spec; 2459 int pin_idx, pcm_idx; 2460 2461 if (spec->acomp_registered) { 2462 snd_hdac_acomp_exit(&codec->bus->core); 2463 } else if (codec_has_acomp(codec)) { 2464 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2465 } 2466 codec->relaxed_resume = 0; 2467 2468 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2469 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2470 cancel_delayed_work_sync(&per_pin->work); 2471 eld_proc_free(per_pin); 2472 } 2473 2474 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2475 if (spec->pcm_rec[pcm_idx].jack == NULL) 2476 continue; 2477 if (spec->dyn_pcm_assign) 2478 snd_device_free(codec->card, 2479 spec->pcm_rec[pcm_idx].jack); 2480 else 2481 spec->pcm_rec[pcm_idx].jack = NULL; 2482 } 2483 2484 generic_spec_free(codec); 2485 } 2486 2487 #ifdef CONFIG_PM 2488 static int generic_hdmi_suspend(struct hda_codec *codec) 2489 { 2490 struct hdmi_spec *spec = codec->spec; 2491 int pin_idx; 2492 2493 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2494 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2495 cancel_delayed_work_sync(&per_pin->work); 2496 } 2497 return 0; 2498 } 2499 2500 static int generic_hdmi_resume(struct hda_codec *codec) 2501 { 2502 struct hdmi_spec *spec = codec->spec; 2503 int pin_idx; 2504 2505 codec->patch_ops.init(codec); 2506 snd_hda_regmap_sync(codec); 2507 2508 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2509 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2510 hdmi_present_sense(per_pin, 1); 2511 } 2512 return 0; 2513 } 2514 #endif 2515 2516 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2517 .init = generic_hdmi_init, 2518 .free = generic_hdmi_free, 2519 .build_pcms = generic_hdmi_build_pcms, 2520 .build_controls = generic_hdmi_build_controls, 2521 .unsol_event = hdmi_unsol_event, 2522 #ifdef CONFIG_PM 2523 .suspend = generic_hdmi_suspend, 2524 .resume = generic_hdmi_resume, 2525 #endif 2526 }; 2527 2528 static const struct hdmi_ops generic_standard_hdmi_ops = { 2529 .pin_get_eld = hdmi_pin_get_eld, 2530 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2531 .pin_hbr_setup = hdmi_pin_hbr_setup, 2532 .setup_stream = hdmi_setup_stream, 2533 }; 2534 2535 /* allocate codec->spec and assign/initialize generic parser ops */ 2536 static int alloc_generic_hdmi(struct hda_codec *codec) 2537 { 2538 struct hdmi_spec *spec; 2539 2540 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2541 if (!spec) 2542 return -ENOMEM; 2543 2544 spec->codec = codec; 2545 spec->ops = generic_standard_hdmi_ops; 2546 spec->dev_num = 1; /* initialize to 1 */ 2547 mutex_init(&spec->pcm_lock); 2548 mutex_init(&spec->bind_lock); 2549 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2550 2551 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2552 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2553 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2554 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc; 2555 2556 codec->spec = spec; 2557 hdmi_array_init(spec, 4); 2558 2559 codec->patch_ops = generic_hdmi_patch_ops; 2560 2561 return 0; 2562 } 2563 2564 /* generic HDMI parser */ 2565 static int patch_generic_hdmi(struct hda_codec *codec) 2566 { 2567 int err; 2568 2569 err = alloc_generic_hdmi(codec); 2570 if (err < 0) 2571 return err; 2572 2573 err = hdmi_parse_codec(codec); 2574 if (err < 0) { 2575 generic_spec_free(codec); 2576 return err; 2577 } 2578 2579 generic_hdmi_init_per_pins(codec); 2580 return 0; 2581 } 2582 2583 /* 2584 * generic audio component binding 2585 */ 2586 2587 /* turn on / off the unsol event jack detection dynamically */ 2588 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2589 int dev_id, bool use_acomp) 2590 { 2591 struct hda_jack_tbl *tbl; 2592 2593 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2594 if (tbl) { 2595 /* clear unsol even if component notifier is used, or re-enable 2596 * if notifier is cleared 2597 */ 2598 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2599 snd_hda_codec_write_cache(codec, nid, 0, 2600 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2601 } 2602 } 2603 2604 /* set up / clear component notifier dynamically */ 2605 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2606 bool use_acomp) 2607 { 2608 struct hdmi_spec *spec; 2609 int i; 2610 2611 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2612 mutex_lock(&spec->bind_lock); 2613 spec->use_acomp_notifier = use_acomp; 2614 spec->codec->relaxed_resume = use_acomp; 2615 spec->codec->bus->keep_power = 0; 2616 /* reprogram each jack detection logic depending on the notifier */ 2617 for (i = 0; i < spec->num_pins; i++) 2618 reprogram_jack_detect(spec->codec, 2619 get_pin(spec, i)->pin_nid, 2620 get_pin(spec, i)->dev_id, 2621 use_acomp); 2622 mutex_unlock(&spec->bind_lock); 2623 } 2624 2625 /* enable / disable the notifier via master bind / unbind */ 2626 static int generic_acomp_master_bind(struct device *dev, 2627 struct drm_audio_component *acomp) 2628 { 2629 generic_acomp_notifier_set(acomp, true); 2630 return 0; 2631 } 2632 2633 static void generic_acomp_master_unbind(struct device *dev, 2634 struct drm_audio_component *acomp) 2635 { 2636 generic_acomp_notifier_set(acomp, false); 2637 } 2638 2639 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2640 static int match_bound_vga(struct device *dev, int subtype, void *data) 2641 { 2642 struct hdac_bus *bus = data; 2643 struct pci_dev *pci, *master; 2644 2645 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2646 return 0; 2647 master = to_pci_dev(bus->dev); 2648 pci = to_pci_dev(dev); 2649 return master->bus == pci->bus; 2650 } 2651 2652 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2653 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2654 { 2655 struct hda_codec *codec = audio_ptr; 2656 struct hdmi_spec *spec = codec->spec; 2657 hda_nid_t pin_nid = spec->port2pin(codec, port); 2658 2659 if (!pin_nid) 2660 return; 2661 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2662 return; 2663 /* skip notification during system suspend (but not in runtime PM); 2664 * the state will be updated at resume 2665 */ 2666 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2667 return; 2668 /* ditto during suspend/resume process itself */ 2669 if (snd_hdac_is_in_pm(&codec->core)) 2670 return; 2671 2672 check_presence_and_report(codec, pin_nid, dev_id); 2673 } 2674 2675 /* set up the private drm_audio_ops from the template */ 2676 static void setup_drm_audio_ops(struct hda_codec *codec, 2677 const struct drm_audio_component_audio_ops *ops) 2678 { 2679 struct hdmi_spec *spec = codec->spec; 2680 2681 spec->drm_audio_ops.audio_ptr = codec; 2682 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2683 * will call pin_eld_notify with using audio_ptr pointer 2684 * We need make sure audio_ptr is really setup 2685 */ 2686 wmb(); 2687 spec->drm_audio_ops.pin2port = ops->pin2port; 2688 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2689 spec->drm_audio_ops.master_bind = ops->master_bind; 2690 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2691 } 2692 2693 /* initialize the generic HDMI audio component */ 2694 static void generic_acomp_init(struct hda_codec *codec, 2695 const struct drm_audio_component_audio_ops *ops, 2696 int (*port2pin)(struct hda_codec *, int)) 2697 { 2698 struct hdmi_spec *spec = codec->spec; 2699 2700 if (!enable_acomp) { 2701 codec_info(codec, "audio component disabled by module option\n"); 2702 return; 2703 } 2704 2705 spec->port2pin = port2pin; 2706 setup_drm_audio_ops(codec, ops); 2707 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2708 match_bound_vga, 0)) { 2709 spec->acomp_registered = true; 2710 } 2711 } 2712 2713 /* 2714 * Intel codec parsers and helpers 2715 */ 2716 2717 #define INTEL_GET_VENDOR_VERB 0xf81 2718 #define INTEL_SET_VENDOR_VERB 0x781 2719 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2720 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2721 2722 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2723 bool update_tree) 2724 { 2725 unsigned int vendor_param; 2726 struct hdmi_spec *spec = codec->spec; 2727 2728 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2729 INTEL_GET_VENDOR_VERB, 0); 2730 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2731 return; 2732 2733 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2734 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2735 INTEL_SET_VENDOR_VERB, vendor_param); 2736 if (vendor_param == -1) 2737 return; 2738 2739 if (update_tree) 2740 snd_hda_codec_update_widgets(codec); 2741 } 2742 2743 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2744 { 2745 unsigned int vendor_param; 2746 struct hdmi_spec *spec = codec->spec; 2747 2748 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2749 INTEL_GET_VENDOR_VERB, 0); 2750 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2751 return; 2752 2753 /* enable DP1.2 mode */ 2754 vendor_param |= INTEL_EN_DP12; 2755 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2756 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2757 INTEL_SET_VENDOR_VERB, vendor_param); 2758 } 2759 2760 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2761 * Otherwise you may get severe h/w communication errors. 2762 */ 2763 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2764 unsigned int power_state) 2765 { 2766 if (power_state == AC_PWRST_D0) { 2767 intel_haswell_enable_all_pins(codec, false); 2768 intel_haswell_fixup_enable_dp12(codec); 2769 } 2770 2771 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2772 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2773 } 2774 2775 /* There is a fixed mapping between audio pin node and display port. 2776 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2777 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2778 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2779 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2780 * 2781 * on VLV, ILK: 2782 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2783 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2784 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2785 */ 2786 static int intel_base_nid(struct hda_codec *codec) 2787 { 2788 switch (codec->core.vendor_id) { 2789 case 0x80860054: /* ILK */ 2790 case 0x80862804: /* ILK */ 2791 case 0x80862882: /* VLV */ 2792 return 4; 2793 default: 2794 return 5; 2795 } 2796 } 2797 2798 static int intel_pin2port(void *audio_ptr, int pin_nid) 2799 { 2800 struct hda_codec *codec = audio_ptr; 2801 struct hdmi_spec *spec = codec->spec; 2802 int base_nid, i; 2803 2804 if (!spec->port_num) { 2805 base_nid = intel_base_nid(codec); 2806 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2807 return -1; 2808 return pin_nid - base_nid + 1; 2809 } 2810 2811 /* 2812 * looking for the pin number in the mapping table and return 2813 * the index which indicate the port number 2814 */ 2815 for (i = 0; i < spec->port_num; i++) { 2816 if (pin_nid == spec->port_map[i]) 2817 return i; 2818 } 2819 2820 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid); 2821 return -1; 2822 } 2823 2824 static int intel_port2pin(struct hda_codec *codec, int port) 2825 { 2826 struct hdmi_spec *spec = codec->spec; 2827 2828 if (!spec->port_num) { 2829 /* we assume only from port-B to port-D */ 2830 if (port < 1 || port > 3) 2831 return 0; 2832 return port + intel_base_nid(codec) - 1; 2833 } 2834 2835 if (port < 0 || port >= spec->port_num) 2836 return 0; 2837 return spec->port_map[port]; 2838 } 2839 2840 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2841 { 2842 struct hda_codec *codec = audio_ptr; 2843 int pin_nid; 2844 int dev_id = pipe; 2845 2846 pin_nid = intel_port2pin(codec, port); 2847 if (!pin_nid) 2848 return; 2849 /* skip notification during system suspend (but not in runtime PM); 2850 * the state will be updated at resume 2851 */ 2852 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2853 return; 2854 /* ditto during suspend/resume process itself */ 2855 if (snd_hdac_is_in_pm(&codec->core)) 2856 return; 2857 2858 snd_hdac_i915_set_bclk(&codec->bus->core); 2859 check_presence_and_report(codec, pin_nid, dev_id); 2860 } 2861 2862 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2863 .pin2port = intel_pin2port, 2864 .pin_eld_notify = intel_pin_eld_notify, 2865 }; 2866 2867 /* register i915 component pin_eld_notify callback */ 2868 static void register_i915_notifier(struct hda_codec *codec) 2869 { 2870 struct hdmi_spec *spec = codec->spec; 2871 2872 spec->use_acomp_notifier = true; 2873 spec->port2pin = intel_port2pin; 2874 setup_drm_audio_ops(codec, &intel_audio_ops); 2875 snd_hdac_acomp_register_notifier(&codec->bus->core, 2876 &spec->drm_audio_ops); 2877 /* no need for forcible resume for jack check thanks to notifier */ 2878 codec->relaxed_resume = 1; 2879 } 2880 2881 /* setup_stream ops override for HSW+ */ 2882 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2883 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2884 int format) 2885 { 2886 haswell_verify_D0(codec, cvt_nid, pin_nid); 2887 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2888 stream_tag, format); 2889 } 2890 2891 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2892 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2893 struct hdmi_spec_per_pin *per_pin, 2894 hda_nid_t cvt_nid) 2895 { 2896 if (per_pin) { 2897 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid); 2898 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2899 per_pin->dev_id); 2900 intel_verify_pin_cvt_connect(codec, per_pin); 2901 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2902 per_pin->dev_id, per_pin->mux_idx); 2903 } else { 2904 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2905 } 2906 } 2907 2908 /* precondition and allocation for Intel codecs */ 2909 static int alloc_intel_hdmi(struct hda_codec *codec) 2910 { 2911 int err; 2912 2913 /* requires i915 binding */ 2914 if (!codec->bus->core.audio_component) { 2915 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2916 /* set probe_id here to prevent generic fallback binding */ 2917 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 2918 return -ENODEV; 2919 } 2920 2921 err = alloc_generic_hdmi(codec); 2922 if (err < 0) 2923 return err; 2924 /* no need to handle unsol events */ 2925 codec->patch_ops.unsol_event = NULL; 2926 return 0; 2927 } 2928 2929 /* parse and post-process for Intel codecs */ 2930 static int parse_intel_hdmi(struct hda_codec *codec) 2931 { 2932 int err, retries = 3; 2933 2934 do { 2935 err = hdmi_parse_codec(codec); 2936 } while (err < 0 && retries--); 2937 2938 if (err < 0) { 2939 generic_spec_free(codec); 2940 return err; 2941 } 2942 2943 generic_hdmi_init_per_pins(codec); 2944 register_i915_notifier(codec); 2945 return 0; 2946 } 2947 2948 /* Intel Haswell and onwards; audio component with eld notifier */ 2949 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 2950 const int *port_map, int port_num, int dev_num, 2951 bool send_silent_stream) 2952 { 2953 struct hdmi_spec *spec; 2954 int err; 2955 2956 err = alloc_intel_hdmi(codec); 2957 if (err < 0) 2958 return err; 2959 spec = codec->spec; 2960 codec->dp_mst = true; 2961 spec->dyn_pcm_assign = true; 2962 spec->vendor_nid = vendor_nid; 2963 spec->port_map = port_map; 2964 spec->port_num = port_num; 2965 spec->intel_hsw_fixup = true; 2966 spec->dev_num = dev_num; 2967 2968 intel_haswell_enable_all_pins(codec, true); 2969 intel_haswell_fixup_enable_dp12(codec); 2970 2971 codec->display_power_control = 1; 2972 2973 codec->patch_ops.set_power_state = haswell_set_power_state; 2974 codec->depop_delay = 0; 2975 codec->auto_runtime_pm = 1; 2976 2977 spec->ops.setup_stream = i915_hsw_setup_stream; 2978 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2979 2980 /* 2981 * Enable silent stream feature, if it is enabled via 2982 * module param or Kconfig option 2983 */ 2984 if (send_silent_stream) 2985 spec->send_silent_stream = true; 2986 2987 return parse_intel_hdmi(codec); 2988 } 2989 2990 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2991 { 2992 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3, 2993 enable_silent_stream); 2994 } 2995 2996 static int patch_i915_glk_hdmi(struct hda_codec *codec) 2997 { 2998 /* 2999 * Silent stream calls audio component .get_power() from 3000 * .pin_eld_notify(). On GLK this will deadlock in i915 due 3001 * to the audio vs. CDCLK workaround. 3002 */ 3003 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false); 3004 } 3005 3006 static int patch_i915_icl_hdmi(struct hda_codec *codec) 3007 { 3008 /* 3009 * pin to port mapping table where the value indicate the pin number and 3010 * the index indicate the port number. 3011 */ 3012 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 3013 3014 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3, 3015 enable_silent_stream); 3016 } 3017 3018 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 3019 { 3020 /* 3021 * pin to port mapping table where the value indicate the pin number and 3022 * the index indicate the port number. 3023 */ 3024 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 3025 int ret; 3026 3027 ret = intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4, 3028 enable_silent_stream); 3029 if (!ret) { 3030 struct hdmi_spec *spec = codec->spec; 3031 3032 spec->dyn_pcm_no_legacy = true; 3033 } 3034 3035 return ret; 3036 } 3037 3038 /* Intel Baytrail and Braswell; with eld notifier */ 3039 static int patch_i915_byt_hdmi(struct hda_codec *codec) 3040 { 3041 struct hdmi_spec *spec; 3042 int err; 3043 3044 err = alloc_intel_hdmi(codec); 3045 if (err < 0) 3046 return err; 3047 spec = codec->spec; 3048 3049 /* For Valleyview/Cherryview, only the display codec is in the display 3050 * power well and can use link_power ops to request/release the power. 3051 */ 3052 codec->display_power_control = 1; 3053 3054 codec->depop_delay = 0; 3055 codec->auto_runtime_pm = 1; 3056 3057 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 3058 3059 return parse_intel_hdmi(codec); 3060 } 3061 3062 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 3063 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 3064 { 3065 int err; 3066 3067 err = alloc_intel_hdmi(codec); 3068 if (err < 0) 3069 return err; 3070 return parse_intel_hdmi(codec); 3071 } 3072 3073 /* 3074 * Shared non-generic implementations 3075 */ 3076 3077 static int simple_playback_build_pcms(struct hda_codec *codec) 3078 { 3079 struct hdmi_spec *spec = codec->spec; 3080 struct hda_pcm *info; 3081 unsigned int chans; 3082 struct hda_pcm_stream *pstr; 3083 struct hdmi_spec_per_cvt *per_cvt; 3084 3085 per_cvt = get_cvt(spec, 0); 3086 chans = get_wcaps(codec, per_cvt->cvt_nid); 3087 chans = get_wcaps_channels(chans); 3088 3089 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 3090 if (!info) 3091 return -ENOMEM; 3092 spec->pcm_rec[0].pcm = info; 3093 info->pcm_type = HDA_PCM_TYPE_HDMI; 3094 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3095 *pstr = spec->pcm_playback; 3096 pstr->nid = per_cvt->cvt_nid; 3097 if (pstr->channels_max <= 2 && chans && chans <= 16) 3098 pstr->channels_max = chans; 3099 3100 return 0; 3101 } 3102 3103 /* unsolicited event for jack sensing */ 3104 static void simple_hdmi_unsol_event(struct hda_codec *codec, 3105 unsigned int res) 3106 { 3107 snd_hda_jack_set_dirty_all(codec); 3108 snd_hda_jack_report_sync(codec); 3109 } 3110 3111 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 3112 * as long as spec->pins[] is set correctly 3113 */ 3114 #define simple_hdmi_build_jack generic_hdmi_build_jack 3115 3116 static int simple_playback_build_controls(struct hda_codec *codec) 3117 { 3118 struct hdmi_spec *spec = codec->spec; 3119 struct hdmi_spec_per_cvt *per_cvt; 3120 int err; 3121 3122 per_cvt = get_cvt(spec, 0); 3123 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 3124 per_cvt->cvt_nid, 3125 HDA_PCM_TYPE_HDMI); 3126 if (err < 0) 3127 return err; 3128 return simple_hdmi_build_jack(codec, 0); 3129 } 3130 3131 static int simple_playback_init(struct hda_codec *codec) 3132 { 3133 struct hdmi_spec *spec = codec->spec; 3134 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 3135 hda_nid_t pin = per_pin->pin_nid; 3136 3137 snd_hda_codec_write(codec, pin, 0, 3138 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 3139 /* some codecs require to unmute the pin */ 3140 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 3141 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 3142 AMP_OUT_UNMUTE); 3143 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 3144 return 0; 3145 } 3146 3147 static void simple_playback_free(struct hda_codec *codec) 3148 { 3149 struct hdmi_spec *spec = codec->spec; 3150 3151 hdmi_array_free(spec); 3152 kfree(spec); 3153 } 3154 3155 /* 3156 * Nvidia specific implementations 3157 */ 3158 3159 #define Nv_VERB_SET_Channel_Allocation 0xF79 3160 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 3161 #define Nv_VERB_SET_Audio_Protection_On 0xF98 3162 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 3163 3164 #define nvhdmi_master_con_nid_7x 0x04 3165 #define nvhdmi_master_pin_nid_7x 0x05 3166 3167 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 3168 /*front, rear, clfe, rear_surr */ 3169 0x6, 0x8, 0xa, 0xc, 3170 }; 3171 3172 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3173 /* set audio protect on */ 3174 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3175 /* enable digital output on pin widget */ 3176 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3177 {} /* terminator */ 3178 }; 3179 3180 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3181 /* set audio protect on */ 3182 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3183 /* enable digital output on pin widget */ 3184 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3185 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3186 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3187 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3188 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3189 {} /* terminator */ 3190 }; 3191 3192 #ifdef LIMITED_RATE_FMT_SUPPORT 3193 /* support only the safe format and rate */ 3194 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3195 #define SUPPORTED_MAXBPS 16 3196 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3197 #else 3198 /* support all rates and formats */ 3199 #define SUPPORTED_RATES \ 3200 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3201 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3202 SNDRV_PCM_RATE_192000) 3203 #define SUPPORTED_MAXBPS 24 3204 #define SUPPORTED_FORMATS \ 3205 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3206 #endif 3207 3208 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3209 { 3210 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3211 return 0; 3212 } 3213 3214 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3215 { 3216 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3217 return 0; 3218 } 3219 3220 static const unsigned int channels_2_6_8[] = { 3221 2, 6, 8 3222 }; 3223 3224 static const unsigned int channels_2_8[] = { 3225 2, 8 3226 }; 3227 3228 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3229 .count = ARRAY_SIZE(channels_2_6_8), 3230 .list = channels_2_6_8, 3231 .mask = 0, 3232 }; 3233 3234 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3235 .count = ARRAY_SIZE(channels_2_8), 3236 .list = channels_2_8, 3237 .mask = 0, 3238 }; 3239 3240 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3241 struct hda_codec *codec, 3242 struct snd_pcm_substream *substream) 3243 { 3244 struct hdmi_spec *spec = codec->spec; 3245 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3246 3247 switch (codec->preset->vendor_id) { 3248 case 0x10de0002: 3249 case 0x10de0003: 3250 case 0x10de0005: 3251 case 0x10de0006: 3252 hw_constraints_channels = &hw_constraints_2_8_channels; 3253 break; 3254 case 0x10de0007: 3255 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3256 break; 3257 default: 3258 break; 3259 } 3260 3261 if (hw_constraints_channels != NULL) { 3262 snd_pcm_hw_constraint_list(substream->runtime, 0, 3263 SNDRV_PCM_HW_PARAM_CHANNELS, 3264 hw_constraints_channels); 3265 } else { 3266 snd_pcm_hw_constraint_step(substream->runtime, 0, 3267 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3268 } 3269 3270 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3271 } 3272 3273 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3274 struct hda_codec *codec, 3275 struct snd_pcm_substream *substream) 3276 { 3277 struct hdmi_spec *spec = codec->spec; 3278 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3279 } 3280 3281 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3282 struct hda_codec *codec, 3283 unsigned int stream_tag, 3284 unsigned int format, 3285 struct snd_pcm_substream *substream) 3286 { 3287 struct hdmi_spec *spec = codec->spec; 3288 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3289 stream_tag, format, substream); 3290 } 3291 3292 static const struct hda_pcm_stream simple_pcm_playback = { 3293 .substreams = 1, 3294 .channels_min = 2, 3295 .channels_max = 2, 3296 .ops = { 3297 .open = simple_playback_pcm_open, 3298 .close = simple_playback_pcm_close, 3299 .prepare = simple_playback_pcm_prepare 3300 }, 3301 }; 3302 3303 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3304 .build_controls = simple_playback_build_controls, 3305 .build_pcms = simple_playback_build_pcms, 3306 .init = simple_playback_init, 3307 .free = simple_playback_free, 3308 .unsol_event = simple_hdmi_unsol_event, 3309 }; 3310 3311 static int patch_simple_hdmi(struct hda_codec *codec, 3312 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3313 { 3314 struct hdmi_spec *spec; 3315 struct hdmi_spec_per_cvt *per_cvt; 3316 struct hdmi_spec_per_pin *per_pin; 3317 3318 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3319 if (!spec) 3320 return -ENOMEM; 3321 3322 spec->codec = codec; 3323 codec->spec = spec; 3324 hdmi_array_init(spec, 1); 3325 3326 spec->multiout.num_dacs = 0; /* no analog */ 3327 spec->multiout.max_channels = 2; 3328 spec->multiout.dig_out_nid = cvt_nid; 3329 spec->num_cvts = 1; 3330 spec->num_pins = 1; 3331 per_pin = snd_array_new(&spec->pins); 3332 per_cvt = snd_array_new(&spec->cvts); 3333 if (!per_pin || !per_cvt) { 3334 simple_playback_free(codec); 3335 return -ENOMEM; 3336 } 3337 per_cvt->cvt_nid = cvt_nid; 3338 per_pin->pin_nid = pin_nid; 3339 spec->pcm_playback = simple_pcm_playback; 3340 3341 codec->patch_ops = simple_hdmi_patch_ops; 3342 3343 return 0; 3344 } 3345 3346 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3347 int channels) 3348 { 3349 unsigned int chanmask; 3350 int chan = channels ? (channels - 1) : 1; 3351 3352 switch (channels) { 3353 default: 3354 case 0: 3355 case 2: 3356 chanmask = 0x00; 3357 break; 3358 case 4: 3359 chanmask = 0x08; 3360 break; 3361 case 6: 3362 chanmask = 0x0b; 3363 break; 3364 case 8: 3365 chanmask = 0x13; 3366 break; 3367 } 3368 3369 /* Set the audio infoframe channel allocation and checksum fields. The 3370 * channel count is computed implicitly by the hardware. */ 3371 snd_hda_codec_write(codec, 0x1, 0, 3372 Nv_VERB_SET_Channel_Allocation, chanmask); 3373 3374 snd_hda_codec_write(codec, 0x1, 0, 3375 Nv_VERB_SET_Info_Frame_Checksum, 3376 (0x71 - chan - chanmask)); 3377 } 3378 3379 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3380 struct hda_codec *codec, 3381 struct snd_pcm_substream *substream) 3382 { 3383 struct hdmi_spec *spec = codec->spec; 3384 int i; 3385 3386 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3387 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3388 for (i = 0; i < 4; i++) { 3389 /* set the stream id */ 3390 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3391 AC_VERB_SET_CHANNEL_STREAMID, 0); 3392 /* set the stream format */ 3393 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3394 AC_VERB_SET_STREAM_FORMAT, 0); 3395 } 3396 3397 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3398 * streams are disabled. */ 3399 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3400 3401 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3402 } 3403 3404 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3405 struct hda_codec *codec, 3406 unsigned int stream_tag, 3407 unsigned int format, 3408 struct snd_pcm_substream *substream) 3409 { 3410 int chs; 3411 unsigned int dataDCC2, channel_id; 3412 int i; 3413 struct hdmi_spec *spec = codec->spec; 3414 struct hda_spdif_out *spdif; 3415 struct hdmi_spec_per_cvt *per_cvt; 3416 3417 mutex_lock(&codec->spdif_mutex); 3418 per_cvt = get_cvt(spec, 0); 3419 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3420 3421 chs = substream->runtime->channels; 3422 3423 dataDCC2 = 0x2; 3424 3425 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3426 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3427 snd_hda_codec_write(codec, 3428 nvhdmi_master_con_nid_7x, 3429 0, 3430 AC_VERB_SET_DIGI_CONVERT_1, 3431 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3432 3433 /* set the stream id */ 3434 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3435 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3436 3437 /* set the stream format */ 3438 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3439 AC_VERB_SET_STREAM_FORMAT, format); 3440 3441 /* turn on again (if needed) */ 3442 /* enable and set the channel status audio/data flag */ 3443 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3444 snd_hda_codec_write(codec, 3445 nvhdmi_master_con_nid_7x, 3446 0, 3447 AC_VERB_SET_DIGI_CONVERT_1, 3448 spdif->ctls & 0xff); 3449 snd_hda_codec_write(codec, 3450 nvhdmi_master_con_nid_7x, 3451 0, 3452 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3453 } 3454 3455 for (i = 0; i < 4; i++) { 3456 if (chs == 2) 3457 channel_id = 0; 3458 else 3459 channel_id = i * 2; 3460 3461 /* turn off SPDIF once; 3462 *otherwise the IEC958 bits won't be updated 3463 */ 3464 if (codec->spdif_status_reset && 3465 (spdif->ctls & AC_DIG1_ENABLE)) 3466 snd_hda_codec_write(codec, 3467 nvhdmi_con_nids_7x[i], 3468 0, 3469 AC_VERB_SET_DIGI_CONVERT_1, 3470 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3471 /* set the stream id */ 3472 snd_hda_codec_write(codec, 3473 nvhdmi_con_nids_7x[i], 3474 0, 3475 AC_VERB_SET_CHANNEL_STREAMID, 3476 (stream_tag << 4) | channel_id); 3477 /* set the stream format */ 3478 snd_hda_codec_write(codec, 3479 nvhdmi_con_nids_7x[i], 3480 0, 3481 AC_VERB_SET_STREAM_FORMAT, 3482 format); 3483 /* turn on again (if needed) */ 3484 /* enable and set the channel status audio/data flag */ 3485 if (codec->spdif_status_reset && 3486 (spdif->ctls & AC_DIG1_ENABLE)) { 3487 snd_hda_codec_write(codec, 3488 nvhdmi_con_nids_7x[i], 3489 0, 3490 AC_VERB_SET_DIGI_CONVERT_1, 3491 spdif->ctls & 0xff); 3492 snd_hda_codec_write(codec, 3493 nvhdmi_con_nids_7x[i], 3494 0, 3495 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3496 } 3497 } 3498 3499 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3500 3501 mutex_unlock(&codec->spdif_mutex); 3502 return 0; 3503 } 3504 3505 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3506 .substreams = 1, 3507 .channels_min = 2, 3508 .channels_max = 8, 3509 .nid = nvhdmi_master_con_nid_7x, 3510 .rates = SUPPORTED_RATES, 3511 .maxbps = SUPPORTED_MAXBPS, 3512 .formats = SUPPORTED_FORMATS, 3513 .ops = { 3514 .open = simple_playback_pcm_open, 3515 .close = nvhdmi_8ch_7x_pcm_close, 3516 .prepare = nvhdmi_8ch_7x_pcm_prepare 3517 }, 3518 }; 3519 3520 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3521 { 3522 struct hdmi_spec *spec; 3523 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3524 nvhdmi_master_pin_nid_7x); 3525 if (err < 0) 3526 return err; 3527 3528 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3529 /* override the PCM rates, etc, as the codec doesn't give full list */ 3530 spec = codec->spec; 3531 spec->pcm_playback.rates = SUPPORTED_RATES; 3532 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3533 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3534 return 0; 3535 } 3536 3537 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3538 { 3539 struct hdmi_spec *spec = codec->spec; 3540 int err = simple_playback_build_pcms(codec); 3541 if (!err) { 3542 struct hda_pcm *info = get_pcm_rec(spec, 0); 3543 info->own_chmap = true; 3544 } 3545 return err; 3546 } 3547 3548 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3549 { 3550 struct hdmi_spec *spec = codec->spec; 3551 struct hda_pcm *info; 3552 struct snd_pcm_chmap *chmap; 3553 int err; 3554 3555 err = simple_playback_build_controls(codec); 3556 if (err < 0) 3557 return err; 3558 3559 /* add channel maps */ 3560 info = get_pcm_rec(spec, 0); 3561 err = snd_pcm_add_chmap_ctls(info->pcm, 3562 SNDRV_PCM_STREAM_PLAYBACK, 3563 snd_pcm_alt_chmaps, 8, 0, &chmap); 3564 if (err < 0) 3565 return err; 3566 switch (codec->preset->vendor_id) { 3567 case 0x10de0002: 3568 case 0x10de0003: 3569 case 0x10de0005: 3570 case 0x10de0006: 3571 chmap->channel_mask = (1U << 2) | (1U << 8); 3572 break; 3573 case 0x10de0007: 3574 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3575 } 3576 return 0; 3577 } 3578 3579 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3580 { 3581 struct hdmi_spec *spec; 3582 int err = patch_nvhdmi_2ch(codec); 3583 if (err < 0) 3584 return err; 3585 spec = codec->spec; 3586 spec->multiout.max_channels = 8; 3587 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3588 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3589 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3590 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3591 3592 /* Initialize the audio infoframe channel mask and checksum to something 3593 * valid */ 3594 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3595 3596 return 0; 3597 } 3598 3599 /* 3600 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3601 * - 0x10de0015 3602 * - 0x10de0040 3603 */ 3604 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3605 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3606 { 3607 if (cap->ca_index == 0x00 && channels == 2) 3608 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3609 3610 /* If the speaker allocation matches the channel count, it is OK. */ 3611 if (cap->channels != channels) 3612 return -1; 3613 3614 /* all channels are remappable freely */ 3615 return SNDRV_CTL_TLVT_CHMAP_VAR; 3616 } 3617 3618 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3619 int ca, int chs, unsigned char *map) 3620 { 3621 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3622 return -EINVAL; 3623 3624 return 0; 3625 } 3626 3627 /* map from pin NID to port; port is 0-based */ 3628 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3629 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3630 { 3631 return pin_nid - 4; 3632 } 3633 3634 /* reverse-map from port to pin NID: see above */ 3635 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3636 { 3637 return port + 4; 3638 } 3639 3640 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3641 .pin2port = nvhdmi_pin2port, 3642 .pin_eld_notify = generic_acomp_pin_eld_notify, 3643 .master_bind = generic_acomp_master_bind, 3644 .master_unbind = generic_acomp_master_unbind, 3645 }; 3646 3647 static int patch_nvhdmi(struct hda_codec *codec) 3648 { 3649 struct hdmi_spec *spec; 3650 int err; 3651 3652 err = alloc_generic_hdmi(codec); 3653 if (err < 0) 3654 return err; 3655 codec->dp_mst = true; 3656 3657 spec = codec->spec; 3658 spec->dyn_pcm_assign = true; 3659 3660 err = hdmi_parse_codec(codec); 3661 if (err < 0) { 3662 generic_spec_free(codec); 3663 return err; 3664 } 3665 3666 generic_hdmi_init_per_pins(codec); 3667 3668 spec->dyn_pin_out = true; 3669 3670 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3671 nvhdmi_chmap_cea_alloc_validate_get_type; 3672 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3673 3674 codec->link_down_at_suspend = 1; 3675 3676 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3677 3678 return 0; 3679 } 3680 3681 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3682 { 3683 struct hdmi_spec *spec; 3684 int err; 3685 3686 err = patch_generic_hdmi(codec); 3687 if (err) 3688 return err; 3689 3690 spec = codec->spec; 3691 spec->dyn_pin_out = true; 3692 3693 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3694 nvhdmi_chmap_cea_alloc_validate_get_type; 3695 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3696 3697 codec->link_down_at_suspend = 1; 3698 3699 return 0; 3700 } 3701 3702 /* 3703 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3704 * accessed using vendor-defined verbs. These registers can be used for 3705 * interoperability between the HDA and HDMI drivers. 3706 */ 3707 3708 /* Audio Function Group node */ 3709 #define NVIDIA_AFG_NID 0x01 3710 3711 /* 3712 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3713 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3714 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3715 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3716 * additional bit (at position 30) to signal the validity of the format. 3717 * 3718 * | 31 | 30 | 29 16 | 15 0 | 3719 * +---------+-------+--------+--------+ 3720 * | TRIGGER | VALID | UNUSED | FORMAT | 3721 * +-----------------------------------| 3722 * 3723 * Note that for the trigger bit to take effect it needs to change value 3724 * (i.e. it needs to be toggled). 3725 */ 3726 #define NVIDIA_GET_SCRATCH0 0xfa6 3727 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3728 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3729 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3730 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3731 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3732 #define NVIDIA_SCRATCH_VALID (1 << 6) 3733 3734 #define NVIDIA_GET_SCRATCH1 0xfab 3735 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3736 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3737 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3738 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3739 3740 /* 3741 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3742 * the format is invalidated so that the HDMI codec can be disabled. 3743 */ 3744 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3745 { 3746 unsigned int value; 3747 3748 /* bits [31:30] contain the trigger and valid bits */ 3749 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3750 NVIDIA_GET_SCRATCH0, 0); 3751 value = (value >> 24) & 0xff; 3752 3753 /* bits [15:0] are used to store the HDA format */ 3754 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3755 NVIDIA_SET_SCRATCH0_BYTE0, 3756 (format >> 0) & 0xff); 3757 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3758 NVIDIA_SET_SCRATCH0_BYTE1, 3759 (format >> 8) & 0xff); 3760 3761 /* bits [16:24] are unused */ 3762 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3763 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3764 3765 /* 3766 * Bit 30 signals that the data is valid and hence that HDMI audio can 3767 * be enabled. 3768 */ 3769 if (format == 0) 3770 value &= ~NVIDIA_SCRATCH_VALID; 3771 else 3772 value |= NVIDIA_SCRATCH_VALID; 3773 3774 /* 3775 * Whenever the trigger bit is toggled, an interrupt is raised in the 3776 * HDMI codec. The HDMI driver will use that as trigger to update its 3777 * configuration. 3778 */ 3779 value ^= NVIDIA_SCRATCH_TRIGGER; 3780 3781 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3782 NVIDIA_SET_SCRATCH0_BYTE3, value); 3783 } 3784 3785 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3786 struct hda_codec *codec, 3787 unsigned int stream_tag, 3788 unsigned int format, 3789 struct snd_pcm_substream *substream) 3790 { 3791 int err; 3792 3793 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3794 format, substream); 3795 if (err < 0) 3796 return err; 3797 3798 /* notify the HDMI codec of the format change */ 3799 tegra_hdmi_set_format(codec, format); 3800 3801 return 0; 3802 } 3803 3804 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3805 struct hda_codec *codec, 3806 struct snd_pcm_substream *substream) 3807 { 3808 /* invalidate the format in the HDMI codec */ 3809 tegra_hdmi_set_format(codec, 0); 3810 3811 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3812 } 3813 3814 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3815 { 3816 struct hdmi_spec *spec = codec->spec; 3817 unsigned int i; 3818 3819 for (i = 0; i < spec->num_pins; i++) { 3820 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3821 3822 if (pcm->pcm_type == type) 3823 return pcm; 3824 } 3825 3826 return NULL; 3827 } 3828 3829 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3830 { 3831 struct hda_pcm_stream *stream; 3832 struct hda_pcm *pcm; 3833 int err; 3834 3835 err = generic_hdmi_build_pcms(codec); 3836 if (err < 0) 3837 return err; 3838 3839 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3840 if (!pcm) 3841 return -ENODEV; 3842 3843 /* 3844 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3845 * codec about format changes. 3846 */ 3847 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3848 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3849 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3850 3851 return 0; 3852 } 3853 3854 static int patch_tegra_hdmi(struct hda_codec *codec) 3855 { 3856 struct hdmi_spec *spec; 3857 int err; 3858 3859 err = patch_generic_hdmi(codec); 3860 if (err) 3861 return err; 3862 3863 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3864 spec = codec->spec; 3865 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3866 nvhdmi_chmap_cea_alloc_validate_get_type; 3867 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3868 3869 return 0; 3870 } 3871 3872 /* 3873 * ATI/AMD-specific implementations 3874 */ 3875 3876 #define is_amdhdmi_rev3_or_later(codec) \ 3877 ((codec)->core.vendor_id == 0x1002aa01 && \ 3878 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3879 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3880 3881 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3882 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3883 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3884 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3885 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3886 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3887 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3888 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3889 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3890 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3891 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3892 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3893 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3894 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3895 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3896 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3897 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3898 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3899 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3900 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3901 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3902 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3903 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3904 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3905 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3906 3907 /* AMD specific HDA cvt verbs */ 3908 #define ATI_VERB_SET_RAMP_RATE 0x770 3909 #define ATI_VERB_GET_RAMP_RATE 0xf70 3910 3911 #define ATI_OUT_ENABLE 0x1 3912 3913 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3914 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3915 3916 #define ATI_HBR_CAPABLE 0x01 3917 #define ATI_HBR_ENABLE 0x10 3918 3919 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3920 int dev_id, unsigned char *buf, int *eld_size) 3921 { 3922 WARN_ON(dev_id != 0); 3923 /* call hda_eld.c ATI/AMD-specific function */ 3924 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3925 is_amdhdmi_rev3_or_later(codec)); 3926 } 3927 3928 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 3929 hda_nid_t pin_nid, int dev_id, int ca, 3930 int active_channels, int conn_type) 3931 { 3932 WARN_ON(dev_id != 0); 3933 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3934 } 3935 3936 static int atihdmi_paired_swap_fc_lfe(int pos) 3937 { 3938 /* 3939 * ATI/AMD have automatic FC/LFE swap built-in 3940 * when in pairwise mapping mode. 3941 */ 3942 3943 switch (pos) { 3944 /* see channel_allocations[].speakers[] */ 3945 case 2: return 3; 3946 case 3: return 2; 3947 default: break; 3948 } 3949 3950 return pos; 3951 } 3952 3953 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 3954 int ca, int chs, unsigned char *map) 3955 { 3956 struct hdac_cea_channel_speaker_allocation *cap; 3957 int i, j; 3958 3959 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3960 3961 cap = snd_hdac_get_ch_alloc_from_ca(ca); 3962 for (i = 0; i < chs; ++i) { 3963 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 3964 bool ok = false; 3965 bool companion_ok = false; 3966 3967 if (!mask) 3968 continue; 3969 3970 for (j = 0 + i % 2; j < 8; j += 2) { 3971 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3972 if (cap->speakers[chan_idx] == mask) { 3973 /* channel is in a supported position */ 3974 ok = true; 3975 3976 if (i % 2 == 0 && i + 1 < chs) { 3977 /* even channel, check the odd companion */ 3978 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3979 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 3980 int comp_mask_act = cap->speakers[comp_chan_idx]; 3981 3982 if (comp_mask_req == comp_mask_act) 3983 companion_ok = true; 3984 else 3985 return -EINVAL; 3986 } 3987 break; 3988 } 3989 } 3990 3991 if (!ok) 3992 return -EINVAL; 3993 3994 if (companion_ok) 3995 i++; /* companion channel already checked */ 3996 } 3997 3998 return 0; 3999 } 4000 4001 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 4002 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 4003 { 4004 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4005 int verb; 4006 int ati_channel_setup = 0; 4007 4008 if (hdmi_slot > 7) 4009 return -EINVAL; 4010 4011 if (!has_amd_full_remap_support(codec)) { 4012 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 4013 4014 /* In case this is an odd slot but without stream channel, do not 4015 * disable the slot since the corresponding even slot could have a 4016 * channel. In case neither have a channel, the slot pair will be 4017 * disabled when this function is called for the even slot. */ 4018 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 4019 return 0; 4020 4021 hdmi_slot -= hdmi_slot % 2; 4022 4023 if (stream_channel != 0xf) 4024 stream_channel -= stream_channel % 2; 4025 } 4026 4027 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 4028 4029 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 4030 4031 if (stream_channel != 0xf) 4032 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 4033 4034 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 4035 } 4036 4037 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 4038 hda_nid_t pin_nid, int asp_slot) 4039 { 4040 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4041 bool was_odd = false; 4042 int ati_asp_slot = asp_slot; 4043 int verb; 4044 int ati_channel_setup; 4045 4046 if (asp_slot > 7) 4047 return -EINVAL; 4048 4049 if (!has_amd_full_remap_support(codec)) { 4050 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 4051 if (ati_asp_slot % 2 != 0) { 4052 ati_asp_slot -= 1; 4053 was_odd = true; 4054 } 4055 } 4056 4057 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 4058 4059 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 4060 4061 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 4062 return 0xf; 4063 4064 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 4065 } 4066 4067 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 4068 struct hdac_chmap *chmap, 4069 struct hdac_cea_channel_speaker_allocation *cap, 4070 int channels) 4071 { 4072 int c; 4073 4074 /* 4075 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 4076 * we need to take that into account (a single channel may take 2 4077 * channel slots if we need to carry a silent channel next to it). 4078 * On Rev3+ AMD codecs this function is not used. 4079 */ 4080 int chanpairs = 0; 4081 4082 /* We only produce even-numbered channel count TLVs */ 4083 if ((channels % 2) != 0) 4084 return -1; 4085 4086 for (c = 0; c < 7; c += 2) { 4087 if (cap->speakers[c] || cap->speakers[c+1]) 4088 chanpairs++; 4089 } 4090 4091 if (chanpairs * 2 != channels) 4092 return -1; 4093 4094 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 4095 } 4096 4097 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 4098 struct hdac_cea_channel_speaker_allocation *cap, 4099 unsigned int *chmap, int channels) 4100 { 4101 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 4102 int count = 0; 4103 int c; 4104 4105 for (c = 7; c >= 0; c--) { 4106 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 4107 int spk = cap->speakers[chan]; 4108 if (!spk) { 4109 /* add N/A channel if the companion channel is occupied */ 4110 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 4111 chmap[count++] = SNDRV_CHMAP_NA; 4112 4113 continue; 4114 } 4115 4116 chmap[count++] = snd_hdac_spk_to_chmap(spk); 4117 } 4118 4119 WARN_ON(count != channels); 4120 } 4121 4122 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 4123 int dev_id, bool hbr) 4124 { 4125 int hbr_ctl, hbr_ctl_new; 4126 4127 WARN_ON(dev_id != 0); 4128 4129 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 4130 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 4131 if (hbr) 4132 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 4133 else 4134 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 4135 4136 codec_dbg(codec, 4137 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 4138 pin_nid, 4139 hbr_ctl == hbr_ctl_new ? "" : "new-", 4140 hbr_ctl_new); 4141 4142 if (hbr_ctl != hbr_ctl_new) 4143 snd_hda_codec_write(codec, pin_nid, 0, 4144 ATI_VERB_SET_HBR_CONTROL, 4145 hbr_ctl_new); 4146 4147 } else if (hbr) 4148 return -EINVAL; 4149 4150 return 0; 4151 } 4152 4153 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 4154 hda_nid_t pin_nid, int dev_id, 4155 u32 stream_tag, int format) 4156 { 4157 if (is_amdhdmi_rev3_or_later(codec)) { 4158 int ramp_rate = 180; /* default as per AMD spec */ 4159 /* disable ramp-up/down for non-pcm as per AMD spec */ 4160 if (format & AC_FMT_TYPE_NON_PCM) 4161 ramp_rate = 0; 4162 4163 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 4164 } 4165 4166 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 4167 stream_tag, format); 4168 } 4169 4170 4171 static int atihdmi_init(struct hda_codec *codec) 4172 { 4173 struct hdmi_spec *spec = codec->spec; 4174 int pin_idx, err; 4175 4176 err = generic_hdmi_init(codec); 4177 4178 if (err) 4179 return err; 4180 4181 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 4182 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 4183 4184 /* make sure downmix information in infoframe is zero */ 4185 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 4186 4187 /* enable channel-wise remap mode if supported */ 4188 if (has_amd_full_remap_support(codec)) 4189 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 4190 ATI_VERB_SET_MULTICHANNEL_MODE, 4191 ATI_MULTICHANNEL_MODE_SINGLE); 4192 } 4193 codec->auto_runtime_pm = 1; 4194 4195 return 0; 4196 } 4197 4198 /* map from pin NID to port; port is 0-based */ 4199 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 4200 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 4201 { 4202 return pin_nid / 2 - 1; 4203 } 4204 4205 /* reverse-map from port to pin NID: see above */ 4206 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4207 { 4208 return port * 2 + 3; 4209 } 4210 4211 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4212 .pin2port = atihdmi_pin2port, 4213 .pin_eld_notify = generic_acomp_pin_eld_notify, 4214 .master_bind = generic_acomp_master_bind, 4215 .master_unbind = generic_acomp_master_unbind, 4216 }; 4217 4218 static int patch_atihdmi(struct hda_codec *codec) 4219 { 4220 struct hdmi_spec *spec; 4221 struct hdmi_spec_per_cvt *per_cvt; 4222 int err, cvt_idx; 4223 4224 err = patch_generic_hdmi(codec); 4225 4226 if (err) 4227 return err; 4228 4229 codec->patch_ops.init = atihdmi_init; 4230 4231 spec = codec->spec; 4232 4233 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4234 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4235 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4236 spec->ops.setup_stream = atihdmi_setup_stream; 4237 4238 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4239 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4240 4241 if (!has_amd_full_remap_support(codec)) { 4242 /* override to ATI/AMD-specific versions with pairwise mapping */ 4243 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4244 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4245 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4246 atihdmi_paired_cea_alloc_to_tlv_chmap; 4247 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4248 } 4249 4250 /* ATI/AMD converters do not advertise all of their capabilities */ 4251 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4252 per_cvt = get_cvt(spec, cvt_idx); 4253 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4254 per_cvt->rates |= SUPPORTED_RATES; 4255 per_cvt->formats |= SUPPORTED_FORMATS; 4256 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4257 } 4258 4259 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4260 4261 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4262 * the link-down as is. Tell the core to allow it. 4263 */ 4264 codec->link_down_at_suspend = 1; 4265 4266 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4267 4268 return 0; 4269 } 4270 4271 /* VIA HDMI Implementation */ 4272 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4273 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4274 4275 static int patch_via_hdmi(struct hda_codec *codec) 4276 { 4277 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4278 } 4279 4280 /* 4281 * patch entries 4282 */ 4283 static const struct hda_device_id snd_hda_id_hdmi[] = { 4284 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4285 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4286 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4287 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4288 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4289 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4290 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4291 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4292 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4293 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4294 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4295 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4296 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4297 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4298 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4299 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4300 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4301 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4302 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4303 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4304 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4305 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4306 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4307 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4308 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4309 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4310 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4311 /* 17 is known to be absent */ 4312 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4313 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4314 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4315 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4316 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4317 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4318 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4319 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4320 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4321 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4322 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4323 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4324 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4325 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4326 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4327 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4328 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4329 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4330 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4331 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4332 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4333 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4334 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4335 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4336 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4337 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4338 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4339 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4340 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4341 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4342 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4343 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4344 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4345 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4346 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4347 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4348 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4349 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4350 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4351 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4352 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4353 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4354 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4355 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4356 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4357 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4358 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4359 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4360 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4361 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4362 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi), 4363 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), 4364 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), 4365 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), 4366 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), 4367 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4368 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4369 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4370 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4371 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4372 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4373 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4374 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4375 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4376 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4377 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4378 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4379 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4380 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4381 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4382 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4383 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4384 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4385 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4386 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4387 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4388 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4389 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4390 HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi), 4391 HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi), 4392 HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi), 4393 HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_tgl_hdmi), 4394 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi), 4395 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi), 4396 HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_tgl_hdmi), 4397 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4398 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4399 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4400 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4401 /* special ID for generic HDMI */ 4402 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4403 {} /* terminator */ 4404 }; 4405 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4406 4407 MODULE_LICENSE("GPL"); 4408 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4409 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4410 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4411 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4412 4413 static struct hda_codec_driver hdmi_driver = { 4414 .id = snd_hda_id_hdmi, 4415 }; 4416 4417 module_hda_codec_driver(hdmi_driver); 4418