1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * VGICv3 MMIO handling functions 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/irqchip/arm-gic-v3.h> 8 #include <linux/kvm.h> 9 #include <linux/kvm_host.h> 10 #include <linux/interrupt.h> 11 #include <kvm/iodev.h> 12 #include <kvm/arm_vgic.h> 13 14 #include <asm/kvm_emulate.h> 15 #include <asm/kvm_arm.h> 16 #include <asm/kvm_mmu.h> 17 18 #include "vgic.h" 19 #include "vgic-mmio.h" 20 21 /* extract @num bytes at @offset bytes offset in data */ 22 unsigned long extract_bytes(u64 data, unsigned int offset, 23 unsigned int num) 24 { 25 return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0); 26 } 27 28 /* allows updates of any half of a 64-bit register (or the whole thing) */ 29 u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len, 30 unsigned long val) 31 { 32 int lower = (offset & 4) * 8; 33 int upper = lower + 8 * len - 1; 34 35 reg &= ~GENMASK_ULL(upper, lower); 36 val &= GENMASK_ULL(len * 8 - 1, 0); 37 38 return reg | ((u64)val << lower); 39 } 40 41 bool vgic_has_its(struct kvm *kvm) 42 { 43 struct vgic_dist *dist = &kvm->arch.vgic; 44 45 if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3) 46 return false; 47 48 return dist->has_its; 49 } 50 51 bool vgic_supports_direct_msis(struct kvm *kvm) 52 { 53 return (kvm_vgic_global_state.has_gicv4_1 || 54 (kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm))); 55 } 56 57 /* 58 * The Revision field in the IIDR have the following meanings: 59 * 60 * Revision 2: Interrupt groups are guest-configurable and signaled using 61 * their configured groups. 62 */ 63 64 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu, 65 gpa_t addr, unsigned int len) 66 { 67 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic; 68 u32 value = 0; 69 70 switch (addr & 0x0c) { 71 case GICD_CTLR: 72 if (vgic->enabled) 73 value |= GICD_CTLR_ENABLE_SS_G1; 74 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS; 75 if (vgic->nassgireq) 76 value |= GICD_CTLR_nASSGIreq; 77 break; 78 case GICD_TYPER: 79 value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS; 80 value = (value >> 5) - 1; 81 if (vgic_has_its(vcpu->kvm)) { 82 value |= (INTERRUPT_ID_BITS_ITS - 1) << 19; 83 value |= GICD_TYPER_LPIS; 84 } else { 85 value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19; 86 } 87 break; 88 case GICD_TYPER2: 89 if (kvm_vgic_global_state.has_gicv4_1 && gic_cpuif_has_vsgi()) 90 value = GICD_TYPER2_nASSGIcap; 91 break; 92 case GICD_IIDR: 93 value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) | 94 (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) | 95 (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT); 96 break; 97 default: 98 return 0; 99 } 100 101 return value; 102 } 103 104 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu, 105 gpa_t addr, unsigned int len, 106 unsigned long val) 107 { 108 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 109 110 switch (addr & 0x0c) { 111 case GICD_CTLR: { 112 bool was_enabled, is_hwsgi; 113 114 mutex_lock(&vcpu->kvm->lock); 115 116 was_enabled = dist->enabled; 117 is_hwsgi = dist->nassgireq; 118 119 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1; 120 121 /* Not a GICv4.1? No HW SGIs */ 122 if (!kvm_vgic_global_state.has_gicv4_1 || !gic_cpuif_has_vsgi()) 123 val &= ~GICD_CTLR_nASSGIreq; 124 125 /* Dist stays enabled? nASSGIreq is RO */ 126 if (was_enabled && dist->enabled) { 127 val &= ~GICD_CTLR_nASSGIreq; 128 val |= FIELD_PREP(GICD_CTLR_nASSGIreq, is_hwsgi); 129 } 130 131 /* Switching HW SGIs? */ 132 dist->nassgireq = val & GICD_CTLR_nASSGIreq; 133 if (is_hwsgi != dist->nassgireq) 134 vgic_v4_configure_vsgis(vcpu->kvm); 135 136 if (kvm_vgic_global_state.has_gicv4_1 && 137 was_enabled != dist->enabled) 138 kvm_make_all_cpus_request(vcpu->kvm, KVM_REQ_RELOAD_GICv4); 139 else if (!was_enabled && dist->enabled) 140 vgic_kick_vcpus(vcpu->kvm); 141 142 mutex_unlock(&vcpu->kvm->lock); 143 break; 144 } 145 case GICD_TYPER: 146 case GICD_TYPER2: 147 case GICD_IIDR: 148 /* This is at best for documentation purposes... */ 149 return; 150 } 151 } 152 153 static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu, 154 gpa_t addr, unsigned int len, 155 unsigned long val) 156 { 157 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 158 159 switch (addr & 0x0c) { 160 case GICD_TYPER2: 161 case GICD_IIDR: 162 if (val != vgic_mmio_read_v3_misc(vcpu, addr, len)) 163 return -EINVAL; 164 return 0; 165 case GICD_CTLR: 166 /* Not a GICv4.1? No HW SGIs */ 167 if (!kvm_vgic_global_state.has_gicv4_1) 168 val &= ~GICD_CTLR_nASSGIreq; 169 170 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1; 171 dist->nassgireq = val & GICD_CTLR_nASSGIreq; 172 return 0; 173 } 174 175 vgic_mmio_write_v3_misc(vcpu, addr, len, val); 176 return 0; 177 } 178 179 static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu, 180 gpa_t addr, unsigned int len) 181 { 182 int intid = VGIC_ADDR_TO_INTID(addr, 64); 183 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid); 184 unsigned long ret = 0; 185 186 if (!irq) 187 return 0; 188 189 /* The upper word is RAZ for us. */ 190 if (!(addr & 4)) 191 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len); 192 193 vgic_put_irq(vcpu->kvm, irq); 194 return ret; 195 } 196 197 static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu, 198 gpa_t addr, unsigned int len, 199 unsigned long val) 200 { 201 int intid = VGIC_ADDR_TO_INTID(addr, 64); 202 struct vgic_irq *irq; 203 unsigned long flags; 204 205 /* The upper word is WI for us since we don't implement Aff3. */ 206 if (addr & 4) 207 return; 208 209 irq = vgic_get_irq(vcpu->kvm, NULL, intid); 210 211 if (!irq) 212 return; 213 214 raw_spin_lock_irqsave(&irq->irq_lock, flags); 215 216 /* We only care about and preserve Aff0, Aff1 and Aff2. */ 217 irq->mpidr = val & GENMASK(23, 0); 218 irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr); 219 220 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 221 vgic_put_irq(vcpu->kvm, irq); 222 } 223 224 static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu, 225 gpa_t addr, unsigned int len) 226 { 227 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 228 229 return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0; 230 } 231 232 233 static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu, 234 gpa_t addr, unsigned int len, 235 unsigned long val) 236 { 237 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 238 bool was_enabled = vgic_cpu->lpis_enabled; 239 240 if (!vgic_has_its(vcpu->kvm)) 241 return; 242 243 vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS; 244 245 if (was_enabled && !vgic_cpu->lpis_enabled) { 246 vgic_flush_pending_lpis(vcpu); 247 vgic_its_invalidate_cache(vcpu->kvm); 248 } 249 250 if (!was_enabled && vgic_cpu->lpis_enabled) 251 vgic_enable_lpis(vcpu); 252 } 253 254 static bool vgic_mmio_vcpu_rdist_is_last(struct kvm_vcpu *vcpu) 255 { 256 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic; 257 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 258 struct vgic_redist_region *iter, *rdreg = vgic_cpu->rdreg; 259 260 if (!rdreg) 261 return false; 262 263 if (vgic_cpu->rdreg_index < rdreg->free_index - 1) { 264 return false; 265 } else if (rdreg->count && vgic_cpu->rdreg_index == (rdreg->count - 1)) { 266 struct list_head *rd_regions = &vgic->rd_regions; 267 gpa_t end = rdreg->base + rdreg->count * KVM_VGIC_V3_REDIST_SIZE; 268 269 /* 270 * the rdist is the last one of the redist region, 271 * check whether there is no other contiguous rdist region 272 */ 273 list_for_each_entry(iter, rd_regions, list) { 274 if (iter->base == end && iter->free_index > 0) 275 return false; 276 } 277 } 278 return true; 279 } 280 281 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu, 282 gpa_t addr, unsigned int len) 283 { 284 unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu); 285 int target_vcpu_id = vcpu->vcpu_id; 286 u64 value; 287 288 value = (u64)(mpidr & GENMASK(23, 0)) << 32; 289 value |= ((target_vcpu_id & 0xffff) << 8); 290 291 if (vgic_has_its(vcpu->kvm)) 292 value |= GICR_TYPER_PLPIS; 293 294 if (vgic_mmio_vcpu_rdist_is_last(vcpu)) 295 value |= GICR_TYPER_LAST; 296 297 return extract_bytes(value, addr & 7, len); 298 } 299 300 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu, 301 gpa_t addr, unsigned int len) 302 { 303 return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); 304 } 305 306 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu, 307 gpa_t addr, unsigned int len) 308 { 309 switch (addr & 0xffff) { 310 case GICD_PIDR2: 311 /* report a GICv3 compliant implementation */ 312 return 0x3b; 313 } 314 315 return 0; 316 } 317 318 static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu, 319 gpa_t addr, unsigned int len) 320 { 321 u32 intid = VGIC_ADDR_TO_INTID(addr, 1); 322 u32 value = 0; 323 int i; 324 325 /* 326 * pending state of interrupt is latched in pending_latch variable. 327 * Userspace will save and restore pending state and line_level 328 * separately. 329 * Refer to Documentation/virt/kvm/devices/arm-vgic-v3.rst 330 * for handling of ISPENDR and ICPENDR. 331 */ 332 for (i = 0; i < len * 8; i++) { 333 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); 334 bool state = irq->pending_latch; 335 336 if (irq->hw && vgic_irq_is_sgi(irq->intid)) { 337 int err; 338 339 err = irq_get_irqchip_state(irq->host_irq, 340 IRQCHIP_STATE_PENDING, 341 &state); 342 WARN_ON(err); 343 } 344 345 if (state) 346 value |= (1U << i); 347 348 vgic_put_irq(vcpu->kvm, irq); 349 } 350 351 return value; 352 } 353 354 static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu, 355 gpa_t addr, unsigned int len, 356 unsigned long val) 357 { 358 u32 intid = VGIC_ADDR_TO_INTID(addr, 1); 359 int i; 360 unsigned long flags; 361 362 for (i = 0; i < len * 8; i++) { 363 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); 364 365 raw_spin_lock_irqsave(&irq->irq_lock, flags); 366 if (test_bit(i, &val)) { 367 /* 368 * pending_latch is set irrespective of irq type 369 * (level or edge) to avoid dependency that VM should 370 * restore irq config before pending info. 371 */ 372 irq->pending_latch = true; 373 vgic_queue_irq_unlock(vcpu->kvm, irq, flags); 374 } else { 375 irq->pending_latch = false; 376 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 377 } 378 379 vgic_put_irq(vcpu->kvm, irq); 380 } 381 382 return 0; 383 } 384 385 /* We want to avoid outer shareable. */ 386 u64 vgic_sanitise_shareability(u64 field) 387 { 388 switch (field) { 389 case GIC_BASER_OuterShareable: 390 return GIC_BASER_InnerShareable; 391 default: 392 return field; 393 } 394 } 395 396 /* Avoid any inner non-cacheable mapping. */ 397 u64 vgic_sanitise_inner_cacheability(u64 field) 398 { 399 switch (field) { 400 case GIC_BASER_CACHE_nCnB: 401 case GIC_BASER_CACHE_nC: 402 return GIC_BASER_CACHE_RaWb; 403 default: 404 return field; 405 } 406 } 407 408 /* Non-cacheable or same-as-inner are OK. */ 409 u64 vgic_sanitise_outer_cacheability(u64 field) 410 { 411 switch (field) { 412 case GIC_BASER_CACHE_SameAsInner: 413 case GIC_BASER_CACHE_nC: 414 return field; 415 default: 416 return GIC_BASER_CACHE_SameAsInner; 417 } 418 } 419 420 u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift, 421 u64 (*sanitise_fn)(u64)) 422 { 423 u64 field = (reg & field_mask) >> field_shift; 424 425 field = sanitise_fn(field) << field_shift; 426 return (reg & ~field_mask) | field; 427 } 428 429 #define PROPBASER_RES0_MASK \ 430 (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5)) 431 #define PENDBASER_RES0_MASK \ 432 (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \ 433 GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0)) 434 435 static u64 vgic_sanitise_pendbaser(u64 reg) 436 { 437 reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK, 438 GICR_PENDBASER_SHAREABILITY_SHIFT, 439 vgic_sanitise_shareability); 440 reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK, 441 GICR_PENDBASER_INNER_CACHEABILITY_SHIFT, 442 vgic_sanitise_inner_cacheability); 443 reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK, 444 GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT, 445 vgic_sanitise_outer_cacheability); 446 447 reg &= ~PENDBASER_RES0_MASK; 448 449 return reg; 450 } 451 452 static u64 vgic_sanitise_propbaser(u64 reg) 453 { 454 reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK, 455 GICR_PROPBASER_SHAREABILITY_SHIFT, 456 vgic_sanitise_shareability); 457 reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK, 458 GICR_PROPBASER_INNER_CACHEABILITY_SHIFT, 459 vgic_sanitise_inner_cacheability); 460 reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK, 461 GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT, 462 vgic_sanitise_outer_cacheability); 463 464 reg &= ~PROPBASER_RES0_MASK; 465 return reg; 466 } 467 468 static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu, 469 gpa_t addr, unsigned int len) 470 { 471 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 472 473 return extract_bytes(dist->propbaser, addr & 7, len); 474 } 475 476 static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu, 477 gpa_t addr, unsigned int len, 478 unsigned long val) 479 { 480 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 481 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 482 u64 old_propbaser, propbaser; 483 484 /* Storing a value with LPIs already enabled is undefined */ 485 if (vgic_cpu->lpis_enabled) 486 return; 487 488 do { 489 old_propbaser = READ_ONCE(dist->propbaser); 490 propbaser = old_propbaser; 491 propbaser = update_64bit_reg(propbaser, addr & 4, len, val); 492 propbaser = vgic_sanitise_propbaser(propbaser); 493 } while (cmpxchg64(&dist->propbaser, old_propbaser, 494 propbaser) != old_propbaser); 495 } 496 497 static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu, 498 gpa_t addr, unsigned int len) 499 { 500 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 501 u64 value = vgic_cpu->pendbaser; 502 503 value &= ~GICR_PENDBASER_PTZ; 504 505 return extract_bytes(value, addr & 7, len); 506 } 507 508 static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu, 509 gpa_t addr, unsigned int len, 510 unsigned long val) 511 { 512 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 513 u64 old_pendbaser, pendbaser; 514 515 /* Storing a value with LPIs already enabled is undefined */ 516 if (vgic_cpu->lpis_enabled) 517 return; 518 519 do { 520 old_pendbaser = READ_ONCE(vgic_cpu->pendbaser); 521 pendbaser = old_pendbaser; 522 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val); 523 pendbaser = vgic_sanitise_pendbaser(pendbaser); 524 } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser, 525 pendbaser) != old_pendbaser); 526 } 527 528 /* 529 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the 530 * redistributors, while SPIs are covered by registers in the distributor 531 * block. Trying to set private IRQs in this block gets ignored. 532 * We take some special care here to fix the calculation of the register 533 * offset. 534 */ 535 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \ 536 { \ 537 .reg_offset = off, \ 538 .bits_per_irq = bpi, \ 539 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \ 540 .access_flags = acc, \ 541 .read = vgic_mmio_read_raz, \ 542 .write = vgic_mmio_write_wi, \ 543 }, { \ 544 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \ 545 .bits_per_irq = bpi, \ 546 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \ 547 .access_flags = acc, \ 548 .read = rd, \ 549 .write = wr, \ 550 .uaccess_read = ur, \ 551 .uaccess_write = uw, \ 552 } 553 554 static const struct vgic_register_region vgic_v3_dist_registers[] = { 555 REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR, 556 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 557 NULL, vgic_mmio_uaccess_write_v3_misc, 558 16, VGIC_ACCESS_32bit), 559 REGISTER_DESC_WITH_LENGTH(GICD_STATUSR, 560 vgic_mmio_read_rao, vgic_mmio_write_wi, 4, 561 VGIC_ACCESS_32bit), 562 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR, 563 vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1, 564 VGIC_ACCESS_32bit), 565 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER, 566 vgic_mmio_read_enable, vgic_mmio_write_senable, 567 NULL, vgic_uaccess_write_senable, 1, 568 VGIC_ACCESS_32bit), 569 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER, 570 vgic_mmio_read_enable, vgic_mmio_write_cenable, 571 NULL, vgic_uaccess_write_cenable, 1, 572 VGIC_ACCESS_32bit), 573 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR, 574 vgic_mmio_read_pending, vgic_mmio_write_spending, 575 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1, 576 VGIC_ACCESS_32bit), 577 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR, 578 vgic_mmio_read_pending, vgic_mmio_write_cpending, 579 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1, 580 VGIC_ACCESS_32bit), 581 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER, 582 vgic_mmio_read_active, vgic_mmio_write_sactive, 583 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 1, 584 VGIC_ACCESS_32bit), 585 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER, 586 vgic_mmio_read_active, vgic_mmio_write_cactive, 587 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 588 1, VGIC_ACCESS_32bit), 589 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR, 590 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL, 591 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), 592 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR, 593 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8, 594 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), 595 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR, 596 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2, 597 VGIC_ACCESS_32bit), 598 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR, 599 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, 600 VGIC_ACCESS_32bit), 601 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER, 602 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64, 603 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 604 REGISTER_DESC_WITH_LENGTH(GICD_IDREGS, 605 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, 606 VGIC_ACCESS_32bit), 607 }; 608 609 static const struct vgic_register_region vgic_v3_rd_registers[] = { 610 /* RD_base registers */ 611 REGISTER_DESC_WITH_LENGTH(GICR_CTLR, 612 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4, 613 VGIC_ACCESS_32bit), 614 REGISTER_DESC_WITH_LENGTH(GICR_STATUSR, 615 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 616 VGIC_ACCESS_32bit), 617 REGISTER_DESC_WITH_LENGTH(GICR_IIDR, 618 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4, 619 VGIC_ACCESS_32bit), 620 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_TYPER, 621 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 622 NULL, vgic_mmio_uaccess_write_wi, 8, 623 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 624 REGISTER_DESC_WITH_LENGTH(GICR_WAKER, 625 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 626 VGIC_ACCESS_32bit), 627 REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER, 628 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8, 629 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 630 REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER, 631 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8, 632 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 633 REGISTER_DESC_WITH_LENGTH(GICR_IDREGS, 634 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, 635 VGIC_ACCESS_32bit), 636 /* SGI_base registers */ 637 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0, 638 vgic_mmio_read_group, vgic_mmio_write_group, 4, 639 VGIC_ACCESS_32bit), 640 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISENABLER0, 641 vgic_mmio_read_enable, vgic_mmio_write_senable, 642 NULL, vgic_uaccess_write_senable, 4, 643 VGIC_ACCESS_32bit), 644 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICENABLER0, 645 vgic_mmio_read_enable, vgic_mmio_write_cenable, 646 NULL, vgic_uaccess_write_cenable, 4, 647 VGIC_ACCESS_32bit), 648 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0, 649 vgic_mmio_read_pending, vgic_mmio_write_spending, 650 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4, 651 VGIC_ACCESS_32bit), 652 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICPENDR0, 653 vgic_mmio_read_pending, vgic_mmio_write_cpending, 654 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4, 655 VGIC_ACCESS_32bit), 656 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISACTIVER0, 657 vgic_mmio_read_active, vgic_mmio_write_sactive, 658 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 4, 659 VGIC_ACCESS_32bit), 660 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICACTIVER0, 661 vgic_mmio_read_active, vgic_mmio_write_cactive, 662 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 4, 663 VGIC_ACCESS_32bit), 664 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IPRIORITYR0, 665 vgic_mmio_read_priority, vgic_mmio_write_priority, 32, 666 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), 667 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICFGR0, 668 vgic_mmio_read_config, vgic_mmio_write_config, 8, 669 VGIC_ACCESS_32bit), 670 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGRPMODR0, 671 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 672 VGIC_ACCESS_32bit), 673 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_NSACR, 674 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 675 VGIC_ACCESS_32bit), 676 }; 677 678 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev) 679 { 680 dev->regions = vgic_v3_dist_registers; 681 dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers); 682 683 kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops); 684 685 return SZ_64K; 686 } 687 688 /** 689 * vgic_register_redist_iodev - register a single redist iodev 690 * @vcpu: The VCPU to which the redistributor belongs 691 * 692 * Register a KVM iodev for this VCPU's redistributor using the address 693 * provided. 694 * 695 * Return 0 on success, -ERRNO otherwise. 696 */ 697 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu) 698 { 699 struct kvm *kvm = vcpu->kvm; 700 struct vgic_dist *vgic = &kvm->arch.vgic; 701 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 702 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev; 703 struct vgic_redist_region *rdreg; 704 gpa_t rd_base; 705 int ret; 706 707 if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) 708 return 0; 709 710 /* 711 * We may be creating VCPUs before having set the base address for the 712 * redistributor region, in which case we will come back to this 713 * function for all VCPUs when the base address is set. Just return 714 * without doing any work for now. 715 */ 716 rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions); 717 if (!rdreg) 718 return 0; 719 720 if (!vgic_v3_check_base(kvm)) 721 return -EINVAL; 722 723 vgic_cpu->rdreg = rdreg; 724 vgic_cpu->rdreg_index = rdreg->free_index; 725 726 rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE; 727 728 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops); 729 rd_dev->base_addr = rd_base; 730 rd_dev->iodev_type = IODEV_REDIST; 731 rd_dev->regions = vgic_v3_rd_registers; 732 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rd_registers); 733 rd_dev->redist_vcpu = vcpu; 734 735 mutex_lock(&kvm->slots_lock); 736 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base, 737 2 * SZ_64K, &rd_dev->dev); 738 mutex_unlock(&kvm->slots_lock); 739 740 if (ret) 741 return ret; 742 743 rdreg->free_index++; 744 return 0; 745 } 746 747 static void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu) 748 { 749 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev; 750 751 kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev); 752 } 753 754 static int vgic_register_all_redist_iodevs(struct kvm *kvm) 755 { 756 struct kvm_vcpu *vcpu; 757 unsigned long c; 758 int ret = 0; 759 760 kvm_for_each_vcpu(c, vcpu, kvm) { 761 ret = vgic_register_redist_iodev(vcpu); 762 if (ret) 763 break; 764 } 765 766 if (ret) { 767 /* The current c failed, so iterate over the previous ones. */ 768 int i; 769 770 mutex_lock(&kvm->slots_lock); 771 for (i = 0; i < c; i++) { 772 vcpu = kvm_get_vcpu(kvm, i); 773 vgic_unregister_redist_iodev(vcpu); 774 } 775 mutex_unlock(&kvm->slots_lock); 776 } 777 778 return ret; 779 } 780 781 /** 782 * vgic_v3_alloc_redist_region - Allocate a new redistributor region 783 * 784 * Performs various checks before inserting the rdist region in the list. 785 * Those tests depend on whether the size of the rdist region is known 786 * (ie. count != 0). The list is sorted by rdist region index. 787 * 788 * @kvm: kvm handle 789 * @index: redist region index 790 * @base: base of the new rdist region 791 * @count: number of redistributors the region is made of (0 in the old style 792 * single region, whose size is induced from the number of vcpus) 793 * 794 * Return 0 on success, < 0 otherwise 795 */ 796 static int vgic_v3_alloc_redist_region(struct kvm *kvm, uint32_t index, 797 gpa_t base, uint32_t count) 798 { 799 struct vgic_dist *d = &kvm->arch.vgic; 800 struct vgic_redist_region *rdreg; 801 struct list_head *rd_regions = &d->rd_regions; 802 int nr_vcpus = atomic_read(&kvm->online_vcpus); 803 size_t size = count ? count * KVM_VGIC_V3_REDIST_SIZE 804 : nr_vcpus * KVM_VGIC_V3_REDIST_SIZE; 805 int ret; 806 807 /* cross the end of memory ? */ 808 if (base + size < base) 809 return -EINVAL; 810 811 if (list_empty(rd_regions)) { 812 if (index != 0) 813 return -EINVAL; 814 } else { 815 rdreg = list_last_entry(rd_regions, 816 struct vgic_redist_region, list); 817 818 /* Don't mix single region and discrete redist regions */ 819 if (!count && rdreg->count) 820 return -EINVAL; 821 822 if (!count) 823 return -EEXIST; 824 825 if (index != rdreg->index + 1) 826 return -EINVAL; 827 } 828 829 /* 830 * For legacy single-region redistributor regions (!count), 831 * check that the redistributor region does not overlap with the 832 * distributor's address space. 833 */ 834 if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) && 835 vgic_dist_overlap(kvm, base, size)) 836 return -EINVAL; 837 838 /* collision with any other rdist region? */ 839 if (vgic_v3_rdist_overlap(kvm, base, size)) 840 return -EINVAL; 841 842 rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL_ACCOUNT); 843 if (!rdreg) 844 return -ENOMEM; 845 846 rdreg->base = VGIC_ADDR_UNDEF; 847 848 ret = vgic_check_iorange(kvm, rdreg->base, base, SZ_64K, size); 849 if (ret) 850 goto free; 851 852 rdreg->base = base; 853 rdreg->count = count; 854 rdreg->free_index = 0; 855 rdreg->index = index; 856 857 list_add_tail(&rdreg->list, rd_regions); 858 return 0; 859 free: 860 kfree(rdreg); 861 return ret; 862 } 863 864 void vgic_v3_free_redist_region(struct vgic_redist_region *rdreg) 865 { 866 list_del(&rdreg->list); 867 kfree(rdreg); 868 } 869 870 int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count) 871 { 872 int ret; 873 874 ret = vgic_v3_alloc_redist_region(kvm, index, addr, count); 875 if (ret) 876 return ret; 877 878 /* 879 * Register iodevs for each existing VCPU. Adding more VCPUs 880 * afterwards will register the iodevs when needed. 881 */ 882 ret = vgic_register_all_redist_iodevs(kvm); 883 if (ret) { 884 struct vgic_redist_region *rdreg; 885 886 rdreg = vgic_v3_rdist_region_from_index(kvm, index); 887 vgic_v3_free_redist_region(rdreg); 888 return ret; 889 } 890 891 return 0; 892 } 893 894 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr) 895 { 896 const struct vgic_register_region *region; 897 struct vgic_io_device iodev; 898 struct vgic_reg_attr reg_attr; 899 struct kvm_vcpu *vcpu; 900 gpa_t addr; 901 int ret; 902 903 ret = vgic_v3_parse_attr(dev, attr, ®_attr); 904 if (ret) 905 return ret; 906 907 vcpu = reg_attr.vcpu; 908 addr = reg_attr.addr; 909 910 switch (attr->group) { 911 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: 912 iodev.regions = vgic_v3_dist_registers; 913 iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers); 914 iodev.base_addr = 0; 915 break; 916 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{ 917 iodev.regions = vgic_v3_rd_registers; 918 iodev.nr_regions = ARRAY_SIZE(vgic_v3_rd_registers); 919 iodev.base_addr = 0; 920 break; 921 } 922 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: { 923 u64 reg, id; 924 925 id = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK); 926 return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, ®); 927 } 928 default: 929 return -ENXIO; 930 } 931 932 /* We only support aligned 32-bit accesses. */ 933 if (addr & 3) 934 return -ENXIO; 935 936 region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32)); 937 if (!region) 938 return -ENXIO; 939 940 return 0; 941 } 942 /* 943 * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI 944 * generation register ICC_SGI1R_EL1) with a given VCPU. 945 * If the VCPU's MPIDR matches, return the level0 affinity, otherwise 946 * return -1. 947 */ 948 static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu) 949 { 950 unsigned long affinity; 951 int level0; 952 953 /* 954 * Split the current VCPU's MPIDR into affinity level 0 and the 955 * rest as this is what we have to compare against. 956 */ 957 affinity = kvm_vcpu_get_mpidr_aff(vcpu); 958 level0 = MPIDR_AFFINITY_LEVEL(affinity, 0); 959 affinity &= ~MPIDR_LEVEL_MASK; 960 961 /* bail out if the upper three levels don't match */ 962 if (sgi_aff != affinity) 963 return -1; 964 965 /* Is this VCPU's bit set in the mask ? */ 966 if (!(sgi_cpu_mask & BIT(level0))) 967 return -1; 968 969 return level0; 970 } 971 972 /* 973 * The ICC_SGI* registers encode the affinity differently from the MPIDR, 974 * so provide a wrapper to use the existing defines to isolate a certain 975 * affinity level. 976 */ 977 #define SGI_AFFINITY_LEVEL(reg, level) \ 978 ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \ 979 >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level)) 980 981 /** 982 * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs 983 * @vcpu: The VCPU requesting a SGI 984 * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU 985 * @allow_group1: Does the sysreg access allow generation of G1 SGIs 986 * 987 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register. 988 * This will trap in sys_regs.c and call this function. 989 * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the 990 * target processors as well as a bitmask of 16 Aff0 CPUs. 991 * If the interrupt routing mode bit is not set, we iterate over all VCPUs to 992 * check for matching ones. If this bit is set, we signal all, but not the 993 * calling VCPU. 994 */ 995 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1) 996 { 997 struct kvm *kvm = vcpu->kvm; 998 struct kvm_vcpu *c_vcpu; 999 u16 target_cpus; 1000 u64 mpidr; 1001 int sgi; 1002 int vcpu_id = vcpu->vcpu_id; 1003 bool broadcast; 1004 unsigned long c, flags; 1005 1006 sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT; 1007 broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT); 1008 target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT; 1009 mpidr = SGI_AFFINITY_LEVEL(reg, 3); 1010 mpidr |= SGI_AFFINITY_LEVEL(reg, 2); 1011 mpidr |= SGI_AFFINITY_LEVEL(reg, 1); 1012 1013 /* 1014 * We iterate over all VCPUs to find the MPIDRs matching the request. 1015 * If we have handled one CPU, we clear its bit to detect early 1016 * if we are already finished. This avoids iterating through all 1017 * VCPUs when most of the times we just signal a single VCPU. 1018 */ 1019 kvm_for_each_vcpu(c, c_vcpu, kvm) { 1020 struct vgic_irq *irq; 1021 1022 /* Exit early if we have dealt with all requested CPUs */ 1023 if (!broadcast && target_cpus == 0) 1024 break; 1025 1026 /* Don't signal the calling VCPU */ 1027 if (broadcast && c == vcpu_id) 1028 continue; 1029 1030 if (!broadcast) { 1031 int level0; 1032 1033 level0 = match_mpidr(mpidr, target_cpus, c_vcpu); 1034 if (level0 == -1) 1035 continue; 1036 1037 /* remove this matching VCPU from the mask */ 1038 target_cpus &= ~BIT(level0); 1039 } 1040 1041 irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi); 1042 1043 raw_spin_lock_irqsave(&irq->irq_lock, flags); 1044 1045 /* 1046 * An access targeting Group0 SGIs can only generate 1047 * those, while an access targeting Group1 SGIs can 1048 * generate interrupts of either group. 1049 */ 1050 if (!irq->group || allow_group1) { 1051 if (!irq->hw) { 1052 irq->pending_latch = true; 1053 vgic_queue_irq_unlock(vcpu->kvm, irq, flags); 1054 } else { 1055 /* HW SGI? Ask the GIC to inject it */ 1056 int err; 1057 err = irq_set_irqchip_state(irq->host_irq, 1058 IRQCHIP_STATE_PENDING, 1059 true); 1060 WARN_RATELIMIT(err, "IRQ %d", irq->host_irq); 1061 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 1062 } 1063 } else { 1064 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 1065 } 1066 1067 vgic_put_irq(vcpu->kvm, irq); 1068 } 1069 } 1070 1071 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, 1072 int offset, u32 *val) 1073 { 1074 struct vgic_io_device dev = { 1075 .regions = vgic_v3_dist_registers, 1076 .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers), 1077 }; 1078 1079 return vgic_uaccess(vcpu, &dev, is_write, offset, val); 1080 } 1081 1082 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write, 1083 int offset, u32 *val) 1084 { 1085 struct vgic_io_device rd_dev = { 1086 .regions = vgic_v3_rd_registers, 1087 .nr_regions = ARRAY_SIZE(vgic_v3_rd_registers), 1088 }; 1089 1090 return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val); 1091 } 1092 1093 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write, 1094 u32 intid, u64 *val) 1095 { 1096 if (intid % 32) 1097 return -EINVAL; 1098 1099 if (is_write) 1100 vgic_write_irq_line_level_info(vcpu, intid, *val); 1101 else 1102 *val = vgic_read_irq_line_level_info(vcpu, intid); 1103 1104 return 0; 1105 } 1106