1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mfd/qcom-rpm.h> 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/clock/qcom,gcc-ipq806x.h> 8#include <dt-bindings/clock/qcom,lcc-ipq806x.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/reset/qcom,gcc-ipq806x.h> 11#include <dt-bindings/soc/qcom,gsbi.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Qualcomm IPQ8064"; 18 compatible = "qcom,ipq8064"; 19 interrupt-parent = <&intc>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 compatible = "qcom,krait"; 27 enable-method = "qcom,kpss-acc-v1"; 28 device_type = "cpu"; 29 reg = <0>; 30 next-level-cache = <&L2>; 31 qcom,acc = <&acc0>; 32 qcom,saw = <&saw0>; 33 }; 34 35 cpu1: cpu@1 { 36 compatible = "qcom,krait"; 37 enable-method = "qcom,kpss-acc-v1"; 38 device_type = "cpu"; 39 reg = <1>; 40 next-level-cache = <&L2>; 41 qcom,acc = <&acc1>; 42 qcom,saw = <&saw1>; 43 }; 44 45 L2: l2-cache { 46 compatible = "cache"; 47 cache-level = <2>; 48 }; 49 }; 50 51 thermal-zones { 52 sensor0-thermal { 53 polling-delay-passive = <0>; 54 polling-delay = <0>; 55 thermal-sensors = <&tsens 0>; 56 57 trips { 58 cpu-critical { 59 temperature = <105000>; 60 hysteresis = <2000>; 61 type = "critical"; 62 }; 63 64 cpu-hot { 65 temperature = <95000>; 66 hysteresis = <2000>; 67 type = "hot"; 68 }; 69 }; 70 }; 71 72 sensor1-thermal { 73 polling-delay-passive = <0>; 74 polling-delay = <0>; 75 thermal-sensors = <&tsens 1>; 76 77 trips { 78 cpu-critical { 79 temperature = <105000>; 80 hysteresis = <2000>; 81 type = "critical"; 82 }; 83 84 cpu-hot { 85 temperature = <95000>; 86 hysteresis = <2000>; 87 type = "hot"; 88 }; 89 }; 90 }; 91 92 sensor2-thermal { 93 polling-delay-passive = <0>; 94 polling-delay = <0>; 95 thermal-sensors = <&tsens 2>; 96 97 trips { 98 cpu-critical { 99 temperature = <105000>; 100 hysteresis = <2000>; 101 type = "critical"; 102 }; 103 104 cpu-hot { 105 temperature = <95000>; 106 hysteresis = <2000>; 107 type = "hot"; 108 }; 109 }; 110 }; 111 112 sensor3-thermal { 113 polling-delay-passive = <0>; 114 polling-delay = <0>; 115 thermal-sensors = <&tsens 3>; 116 117 trips { 118 cpu-critical { 119 temperature = <105000>; 120 hysteresis = <2000>; 121 type = "critical"; 122 }; 123 124 cpu-hot { 125 temperature = <95000>; 126 hysteresis = <2000>; 127 type = "hot"; 128 }; 129 }; 130 }; 131 132 sensor4-thermal { 133 polling-delay-passive = <0>; 134 polling-delay = <0>; 135 thermal-sensors = <&tsens 4>; 136 137 trips { 138 cpu-critical { 139 temperature = <105000>; 140 hysteresis = <2000>; 141 type = "critical"; 142 }; 143 144 cpu-hot { 145 temperature = <95000>; 146 hysteresis = <2000>; 147 type = "hot"; 148 }; 149 }; 150 }; 151 152 sensor5-thermal { 153 polling-delay-passive = <0>; 154 polling-delay = <0>; 155 thermal-sensors = <&tsens 5>; 156 157 trips { 158 cpu-critical { 159 temperature = <105000>; 160 hysteresis = <2000>; 161 type = "critical"; 162 }; 163 164 cpu-hot { 165 temperature = <95000>; 166 hysteresis = <2000>; 167 type = "hot"; 168 }; 169 }; 170 }; 171 172 sensor6-thermal { 173 polling-delay-passive = <0>; 174 polling-delay = <0>; 175 thermal-sensors = <&tsens 6>; 176 177 trips { 178 cpu-critical { 179 temperature = <105000>; 180 hysteresis = <2000>; 181 type = "critical"; 182 }; 183 184 cpu-hot { 185 temperature = <95000>; 186 hysteresis = <2000>; 187 type = "hot"; 188 }; 189 }; 190 }; 191 192 sensor7-thermal { 193 polling-delay-passive = <0>; 194 polling-delay = <0>; 195 thermal-sensors = <&tsens 7>; 196 197 trips { 198 cpu-critical { 199 temperature = <105000>; 200 hysteresis = <2000>; 201 type = "critical"; 202 }; 203 204 cpu-hot { 205 temperature = <95000>; 206 hysteresis = <2000>; 207 type = "hot"; 208 }; 209 }; 210 }; 211 212 sensor8-thermal { 213 polling-delay-passive = <0>; 214 polling-delay = <0>; 215 thermal-sensors = <&tsens 8>; 216 217 trips { 218 cpu-critical { 219 temperature = <105000>; 220 hysteresis = <2000>; 221 type = "critical"; 222 }; 223 224 cpu-hot { 225 temperature = <95000>; 226 hysteresis = <2000>; 227 type = "hot"; 228 }; 229 }; 230 }; 231 232 sensor9-thermal { 233 polling-delay-passive = <0>; 234 polling-delay = <0>; 235 thermal-sensors = <&tsens 9>; 236 237 trips { 238 cpu-critical { 239 temperature = <105000>; 240 hysteresis = <2000>; 241 type = "critical"; 242 }; 243 244 cpu-hot { 245 temperature = <95000>; 246 hysteresis = <2000>; 247 type = "hot"; 248 }; 249 }; 250 }; 251 252 sensor10-thermal { 253 polling-delay-passive = <0>; 254 polling-delay = <0>; 255 thermal-sensors = <&tsens 10>; 256 257 trips { 258 cpu-critical { 259 temperature = <105000>; 260 hysteresis = <2000>; 261 type = "critical"; 262 }; 263 264 cpu-hot { 265 temperature = <95000>; 266 hysteresis = <2000>; 267 type = "hot"; 268 }; 269 }; 270 }; 271 }; 272 273 memory { 274 device_type = "memory"; 275 reg = <0x0 0x0>; 276 }; 277 278 cpu-pmu { 279 compatible = "qcom,krait-pmu"; 280 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 281 IRQ_TYPE_LEVEL_HIGH)>; 282 }; 283 284 reserved-memory { 285 #address-cells = <1>; 286 #size-cells = <1>; 287 ranges; 288 289 nss@40000000 { 290 reg = <0x40000000 0x1000000>; 291 no-map; 292 }; 293 294 smem: smem@41000000 { 295 compatible = "qcom,smem"; 296 reg = <0x41000000 0x200000>; 297 no-map; 298 299 hwlocks = <&sfpb_mutex 3>; 300 }; 301 }; 302 303 clocks { 304 cxo_board: cxo_board { 305 compatible = "fixed-clock"; 306 #clock-cells = <0>; 307 clock-frequency = <25000000>; 308 }; 309 310 pxo_board: pxo_board { 311 compatible = "fixed-clock"; 312 #clock-cells = <0>; 313 clock-frequency = <25000000>; 314 }; 315 316 sleep_clk: sleep_clk { 317 compatible = "fixed-clock"; 318 clock-frequency = <32768>; 319 #clock-cells = <0>; 320 }; 321 }; 322 323 firmware { 324 scm { 325 compatible = "qcom,scm-ipq806x", "qcom,scm"; 326 }; 327 }; 328 329 stmmac_axi_setup: stmmac-axi-config { 330 snps,wr_osr_lmt = <7>; 331 snps,rd_osr_lmt = <7>; 332 snps,blen = <16 0 0 0 0 0 0>; 333 }; 334 335 vsdcc_fixed: vsdcc-regulator { 336 compatible = "regulator-fixed"; 337 regulator-name = "SDCC Power"; 338 regulator-min-microvolt = <3300000>; 339 regulator-max-microvolt = <3300000>; 340 regulator-always-on; 341 }; 342 343 soc: soc { 344 #address-cells = <1>; 345 #size-cells = <1>; 346 ranges; 347 compatible = "simple-bus"; 348 349 rpm: rpm@108000 { 350 compatible = "qcom,rpm-ipq8064"; 351 reg = <0x00108000 0x1000>; 352 qcom,ipc = <&l2cc 0x8 2>; 353 354 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 357 interrupt-names = "ack", "err", "wakeup"; 358 359 clocks = <&gcc RPM_MSG_RAM_H_CLK>; 360 clock-names = "ram"; 361 362 rpmcc: clock-controller { 363 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; 364 #clock-cells = <1>; 365 }; 366 }; 367 368 qcom,ssbi@500000 { 369 compatible = "qcom,ssbi"; 370 reg = <0x00500000 0x1000>; 371 qcom,controller-type = "pmic-arbiter"; 372 }; 373 374 qfprom: qfprom@700000 { 375 compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; 376 reg = <0x00700000 0x1000>; 377 #address-cells = <1>; 378 #size-cells = <1>; 379 speedbin_efuse: speedbin@c0 { 380 reg = <0xc0 0x4>; 381 }; 382 tsens_calib: calib@400 { 383 reg = <0x400 0xb>; 384 }; 385 tsens_calib_backup: calib_backup@410 { 386 reg = <0x410 0xb>; 387 }; 388 }; 389 390 qcom_pinmux: pinmux@800000 { 391 compatible = "qcom,ipq8064-pinctrl"; 392 reg = <0x00800000 0x4000>; 393 394 gpio-controller; 395 gpio-ranges = <&qcom_pinmux 0 0 69>; 396 #gpio-cells = <2>; 397 interrupt-controller; 398 #interrupt-cells = <2>; 399 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 400 401 pcie0_pins: pcie0_pinmux { 402 mux { 403 pins = "gpio3"; 404 function = "pcie1_rst"; 405 drive-strength = <12>; 406 bias-disable; 407 }; 408 }; 409 410 pcie1_pins: pcie1_pinmux { 411 mux { 412 pins = "gpio48"; 413 function = "pcie2_rst"; 414 drive-strength = <12>; 415 bias-disable; 416 }; 417 }; 418 419 pcie2_pins: pcie2_pinmux { 420 mux { 421 pins = "gpio63"; 422 function = "pcie3_rst"; 423 drive-strength = <12>; 424 bias-disable; 425 }; 426 }; 427 428 i2c4_pins: i2c4-default { 429 pins = "gpio12", "gpio13"; 430 function = "gsbi4"; 431 drive-strength = <12>; 432 bias-disable; 433 }; 434 435 spi_pins: spi_pins { 436 mux { 437 pins = "gpio18", "gpio19", "gpio21"; 438 function = "gsbi5"; 439 drive-strength = <10>; 440 bias-none; 441 }; 442 }; 443 444 leds_pins: leds_pins { 445 mux { 446 pins = "gpio7", "gpio8", "gpio9", 447 "gpio26", "gpio53"; 448 function = "gpio"; 449 drive-strength = <2>; 450 bias-pull-down; 451 output-low; 452 }; 453 }; 454 455 buttons_pins: buttons_pins { 456 mux { 457 pins = "gpio54"; 458 drive-strength = <2>; 459 bias-pull-up; 460 }; 461 }; 462 463 nand_pins: nand_pins { 464 mux { 465 pins = "gpio34", "gpio35", "gpio36", 466 "gpio37", "gpio38", "gpio39", 467 "gpio40", "gpio41", "gpio42", 468 "gpio43", "gpio44", "gpio45", 469 "gpio46", "gpio47"; 470 function = "nand"; 471 drive-strength = <10>; 472 bias-disable; 473 }; 474 475 pullups { 476 pins = "gpio39"; 477 function = "nand"; 478 drive-strength = <10>; 479 bias-pull-up; 480 }; 481 482 hold { 483 pins = "gpio40", "gpio41", "gpio42", 484 "gpio43", "gpio44", "gpio45", 485 "gpio46", "gpio47"; 486 function = "nand"; 487 drive-strength = <10>; 488 bias-bus-hold; 489 }; 490 }; 491 492 mdio0_pins: mdio0-pins { 493 mux { 494 pins = "gpio0", "gpio1"; 495 function = "mdio"; 496 drive-strength = <8>; 497 bias-disable; 498 }; 499 }; 500 501 rgmii2_pins: rgmii2-pins { 502 mux { 503 pins = "gpio27", "gpio28", "gpio29", 504 "gpio30", "gpio31", "gpio32", 505 "gpio51", "gpio52", "gpio59", 506 "gpio60", "gpio61", "gpio62"; 507 function = "rgmii2"; 508 drive-strength = <8>; 509 bias-disable; 510 }; 511 }; 512 }; 513 514 gcc: clock-controller@900000 { 515 compatible = "qcom,gcc-ipq8064", "syscon"; 516 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>; 517 clock-names = "pxo", "cxo", "pll4"; 518 reg = <0x00900000 0x4000>; 519 #clock-cells = <1>; 520 #reset-cells = <1>; 521 #power-domain-cells = <1>; 522 523 tsens: thermal-sensor { 524 compatible = "qcom,ipq8064-tsens"; 525 526 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; 527 nvmem-cell-names = "calib", "calib_backup"; 528 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 529 interrupt-names = "uplow"; 530 531 #qcom,sensors = <11>; 532 #thermal-sensor-cells = <1>; 533 }; 534 }; 535 536 sfpb_mutex: hwlock@1200600 { 537 compatible = "qcom,sfpb-mutex"; 538 reg = <0x01200600 0x100>; 539 540 #hwlock-cells = <1>; 541 }; 542 543 intc: interrupt-controller@2000000 { 544 compatible = "qcom,msm-qgic2"; 545 interrupt-controller; 546 #interrupt-cells = <3>; 547 reg = <0x02000000 0x1000>, 548 <0x02002000 0x1000>; 549 }; 550 551 timer@200a000 { 552 compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", 553 "qcom,msm-timer"; 554 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | 555 IRQ_TYPE_EDGE_RISING)>, 556 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | 557 IRQ_TYPE_EDGE_RISING)>, 558 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | 559 IRQ_TYPE_EDGE_RISING)>, 560 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | 561 IRQ_TYPE_EDGE_RISING)>, 562 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | 563 IRQ_TYPE_EDGE_RISING)>; 564 reg = <0x0200a000 0x100>; 565 clock-frequency = <25000000>; 566 clocks = <&sleep_clk>; 567 clock-names = "sleep"; 568 cpu-offset = <0x80000>; 569 }; 570 571 l2cc: clock-controller@2011000 { 572 compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; 573 reg = <0x02011000 0x1000>; 574 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 575 clock-names = "pll8_vote", "pxo"; 576 #clock-cells = <0>; 577 }; 578 579 acc0: clock-controller@2088000 { 580 compatible = "qcom,kpss-acc-v1"; 581 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 582 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 583 clock-names = "pll8_vote", "pxo"; 584 clock-output-names = "acpu0_aux"; 585 #clock-cells = <0>; 586 }; 587 588 saw0: regulator@2089000 { 589 compatible = "qcom,saw2"; 590 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 591 regulator; 592 }; 593 594 acc1: clock-controller@2098000 { 595 compatible = "qcom,kpss-acc-v1"; 596 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 597 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 598 clock-names = "pll8_vote", "pxo"; 599 clock-output-names = "acpu1_aux"; 600 #clock-cells = <0>; 601 }; 602 603 saw1: regulator@2099000 { 604 compatible = "qcom,saw2"; 605 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 606 regulator; 607 }; 608 609 nss_common: syscon@3000000 { 610 compatible = "syscon"; 611 reg = <0x03000000 0x0000FFFF>; 612 }; 613 614 usb3_0: usb@100f8800 { 615 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; 616 #address-cells = <1>; 617 #size-cells = <1>; 618 reg = <0x100f8800 0x8000>; 619 clocks = <&gcc USB30_0_MASTER_CLK>; 620 clock-names = "core"; 621 622 ranges; 623 624 resets = <&gcc USB30_0_MASTER_RESET>; 625 reset-names = "master"; 626 627 status = "disabled"; 628 629 dwc3_0: usb@10000000 { 630 compatible = "snps,dwc3"; 631 reg = <0x10000000 0xcd00>; 632 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 633 phys = <&hs_phy_0>, <&ss_phy_0>; 634 phy-names = "usb2-phy", "usb3-phy"; 635 dr_mode = "host"; 636 snps,dis_u3_susphy_quirk; 637 }; 638 }; 639 640 hs_phy_0: phy@100f8800 { 641 compatible = "qcom,ipq806x-usb-phy-hs"; 642 reg = <0x100f8800 0x30>; 643 clocks = <&gcc USB30_0_UTMI_CLK>; 644 clock-names = "ref"; 645 #phy-cells = <0>; 646 647 status = "disabled"; 648 }; 649 650 ss_phy_0: phy@100f8830 { 651 compatible = "qcom,ipq806x-usb-phy-ss"; 652 reg = <0x100f8830 0x30>; 653 clocks = <&gcc USB30_0_MASTER_CLK>; 654 clock-names = "ref"; 655 #phy-cells = <0>; 656 657 status = "disabled"; 658 }; 659 660 usb3_1: usb@110f8800 { 661 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; 662 #address-cells = <1>; 663 #size-cells = <1>; 664 reg = <0x110f8800 0x8000>; 665 clocks = <&gcc USB30_1_MASTER_CLK>; 666 clock-names = "core"; 667 668 ranges; 669 670 resets = <&gcc USB30_1_MASTER_RESET>; 671 reset-names = "master"; 672 673 status = "disabled"; 674 675 dwc3_1: usb@11000000 { 676 compatible = "snps,dwc3"; 677 reg = <0x11000000 0xcd00>; 678 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 679 phys = <&hs_phy_1>, <&ss_phy_1>; 680 phy-names = "usb2-phy", "usb3-phy"; 681 dr_mode = "host"; 682 snps,dis_u3_susphy_quirk; 683 }; 684 }; 685 686 hs_phy_1: phy@110f8800 { 687 compatible = "qcom,ipq806x-usb-phy-hs"; 688 reg = <0x110f8800 0x30>; 689 clocks = <&gcc USB30_1_UTMI_CLK>; 690 clock-names = "ref"; 691 #phy-cells = <0>; 692 693 status = "disabled"; 694 }; 695 696 ss_phy_1: phy@110f8830 { 697 compatible = "qcom,ipq806x-usb-phy-ss"; 698 reg = <0x110f8830 0x30>; 699 clocks = <&gcc USB30_1_MASTER_CLK>; 700 clock-names = "ref"; 701 #phy-cells = <0>; 702 703 status = "disabled"; 704 }; 705 706 sdcc3bam: dma-controller@12182000 { 707 compatible = "qcom,bam-v1.3.0"; 708 reg = <0x12182000 0x8000>; 709 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&gcc SDC3_H_CLK>; 711 clock-names = "bam_clk"; 712 #dma-cells = <1>; 713 qcom,ee = <0>; 714 }; 715 716 sdcc1bam: dma-controller@12402000 { 717 compatible = "qcom,bam-v1.3.0"; 718 reg = <0x12402000 0x8000>; 719 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&gcc SDC1_H_CLK>; 721 clock-names = "bam_clk"; 722 #dma-cells = <1>; 723 qcom,ee = <0>; 724 }; 725 726 amba: amba { 727 compatible = "simple-bus"; 728 #address-cells = <1>; 729 #size-cells = <1>; 730 ranges; 731 732 sdcc3: mmc@12180000 { 733 compatible = "arm,pl18x", "arm,primecell"; 734 arm,primecell-periphid = <0x00051180>; 735 status = "disabled"; 736 reg = <0x12180000 0x2000>; 737 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 739 clock-names = "mclk", "apb_pclk"; 740 bus-width = <8>; 741 cap-sd-highspeed; 742 cap-mmc-highspeed; 743 max-frequency = <192000000>; 744 sd-uhs-sdr104; 745 sd-uhs-ddr50; 746 vqmmc-supply = <&vsdcc_fixed>; 747 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 748 dma-names = "tx", "rx"; 749 }; 750 751 sdcc1: mmc@12400000 { 752 status = "disabled"; 753 compatible = "arm,pl18x", "arm,primecell"; 754 arm,primecell-periphid = <0x00051180>; 755 reg = <0x12400000 0x2000>; 756 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 758 clock-names = "mclk", "apb_pclk"; 759 bus-width = <8>; 760 max-frequency = <96000000>; 761 non-removable; 762 cap-sd-highspeed; 763 cap-mmc-highspeed; 764 vmmc-supply = <&vsdcc_fixed>; 765 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 766 dma-names = "tx", "rx"; 767 }; 768 }; 769 770 gsbi1: gsbi@12440000 { 771 compatible = "qcom,gsbi-v1.0.0"; 772 reg = <0x12440000 0x100>; 773 cell-index = <1>; 774 clocks = <&gcc GSBI1_H_CLK>; 775 clock-names = "iface"; 776 #address-cells = <1>; 777 #size-cells = <1>; 778 ranges; 779 780 syscon-tcsr = <&tcsr>; 781 782 status = "disabled"; 783 784 gsbi1_serial: serial@12450000 { 785 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 786 reg = <0x12450000 0x100>, 787 <0x12400000 0x03>; 788 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 789 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 790 clock-names = "core", "iface"; 791 792 status = "disabled"; 793 }; 794 795 gsbi1_i2c: i2c@12460000 { 796 compatible = "qcom,i2c-qup-v1.1.1"; 797 reg = <0x12460000 0x1000>; 798 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 799 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 800 clock-names = "core", "iface"; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 804 status = "disabled"; 805 }; 806 }; 807 808 gsbi2: gsbi@12480000 { 809 compatible = "qcom,gsbi-v1.0.0"; 810 cell-index = <2>; 811 reg = <0x12480000 0x100>; 812 clocks = <&gcc GSBI2_H_CLK>; 813 clock-names = "iface"; 814 #address-cells = <1>; 815 #size-cells = <1>; 816 ranges; 817 status = "disabled"; 818 819 syscon-tcsr = <&tcsr>; 820 821 gsbi2_serial: serial@12490000 { 822 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 823 reg = <0x12490000 0x1000>, 824 <0x12480000 0x1000>; 825 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; 827 clock-names = "core", "iface"; 828 status = "disabled"; 829 }; 830 831 gsbi2_i2c: i2c@124a0000 { 832 compatible = "qcom,i2c-qup-v1.1.1"; 833 reg = <0x124a0000 0x1000>; 834 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 835 836 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 837 clock-names = "core", "iface"; 838 status = "disabled"; 839 840 #address-cells = <1>; 841 #size-cells = <0>; 842 }; 843 }; 844 845 gsbi4: gsbi@16300000 { 846 compatible = "qcom,gsbi-v1.0.0"; 847 cell-index = <4>; 848 reg = <0x16300000 0x100>; 849 clocks = <&gcc GSBI4_H_CLK>; 850 clock-names = "iface"; 851 #address-cells = <1>; 852 #size-cells = <1>; 853 ranges; 854 status = "disabled"; 855 856 syscon-tcsr = <&tcsr>; 857 858 gsbi4_serial: serial@16340000 { 859 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 860 reg = <0x16340000 0x1000>, 861 <0x16300000 0x1000>; 862 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 864 clock-names = "core", "iface"; 865 status = "disabled"; 866 }; 867 868 i2c@16380000 { 869 compatible = "qcom,i2c-qup-v1.1.1"; 870 reg = <0x16380000 0x1000>; 871 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 872 873 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; 874 clock-names = "core", "iface"; 875 status = "disabled"; 876 877 #address-cells = <1>; 878 #size-cells = <0>; 879 }; 880 }; 881 882 gsbi6: gsbi@16500000 { 883 compatible = "qcom,gsbi-v1.0.0"; 884 reg = <0x16500000 0x100>; 885 cell-index = <6>; 886 clocks = <&gcc GSBI6_H_CLK>; 887 clock-names = "iface"; 888 #address-cells = <1>; 889 #size-cells = <1>; 890 ranges; 891 892 syscon-tcsr = <&tcsr>; 893 894 status = "disabled"; 895 896 gsbi6_i2c: i2c@16580000 { 897 compatible = "qcom,i2c-qup-v1.1.1"; 898 reg = <0x16580000 0x1000>; 899 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 900 901 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 902 clock-names = "core", "iface"; 903 904 #address-cells = <1>; 905 #size-cells = <0>; 906 907 status = "disabled"; 908 }; 909 910 gsbi6_spi: spi@16580000 { 911 compatible = "qcom,spi-qup-v1.1.1"; 912 reg = <0x16580000 0x1000>; 913 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 914 915 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 916 clock-names = "core", "iface"; 917 918 #address-cells = <1>; 919 #size-cells = <0>; 920 921 status = "disabled"; 922 }; 923 }; 924 925 gsbi7: gsbi@16600000 { 926 status = "disabled"; 927 compatible = "qcom,gsbi-v1.0.0"; 928 cell-index = <7>; 929 reg = <0x16600000 0x100>; 930 clocks = <&gcc GSBI7_H_CLK>; 931 clock-names = "iface"; 932 #address-cells = <1>; 933 #size-cells = <1>; 934 ranges; 935 syscon-tcsr = <&tcsr>; 936 937 gsbi7_serial: serial@16640000 { 938 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 939 reg = <0x16640000 0x1000>, 940 <0x16600000 0x1000>; 941 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 942 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 943 clock-names = "core", "iface"; 944 status = "disabled"; 945 }; 946 947 gsbi7_i2c: i2c@16680000 { 948 compatible = "qcom,i2c-qup-v1.1.1"; 949 reg = <0x16680000 0x1000>; 950 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 951 952 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; 953 clock-names = "core", "iface"; 954 955 #address-cells = <1>; 956 #size-cells = <0>; 957 958 status = "disabled"; 959 }; 960 }; 961 962 adm_dma: dma-controller@18300000 { 963 compatible = "qcom,adm"; 964 reg = <0x18300000 0x100000>; 965 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 966 #dma-cells = <1>; 967 968 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; 969 clock-names = "core", "iface"; 970 971 resets = <&gcc ADM0_RESET>, 972 <&gcc ADM0_PBUS_RESET>, 973 <&gcc ADM0_C0_RESET>, 974 <&gcc ADM0_C1_RESET>, 975 <&gcc ADM0_C2_RESET>; 976 reset-names = "clk", "pbus", "c0", "c1", "c2"; 977 qcom,ee = <0>; 978 979 status = "disabled"; 980 }; 981 982 gsbi5: gsbi@1a200000 { 983 compatible = "qcom,gsbi-v1.0.0"; 984 cell-index = <5>; 985 reg = <0x1a200000 0x100>; 986 clocks = <&gcc GSBI5_H_CLK>; 987 clock-names = "iface"; 988 #address-cells = <1>; 989 990 #size-cells = <1>; 991 ranges; 992 status = "disabled"; 993 994 syscon-tcsr = <&tcsr>; 995 996 gsbi5_serial: serial@1a240000 { 997 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 998 reg = <0x1a240000 0x1000>, 999 <0x1a200000 0x1000>; 1000 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 1002 clock-names = "core", "iface"; 1003 status = "disabled"; 1004 }; 1005 1006 i2c@1a280000 { 1007 compatible = "qcom,i2c-qup-v1.1.1"; 1008 reg = <0x1a280000 0x1000>; 1009 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1010 1011 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 1012 clock-names = "core", "iface"; 1013 status = "disabled"; 1014 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 }; 1018 1019 spi@1a280000 { 1020 compatible = "qcom,spi-qup-v1.1.1"; 1021 reg = <0x1a280000 0x1000>; 1022 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1023 1024 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 1025 clock-names = "core", "iface"; 1026 status = "disabled"; 1027 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 }; 1031 }; 1032 1033 tcsr: syscon@1a400000 { 1034 compatible = "qcom,tcsr-ipq8064", "syscon"; 1035 reg = <0x1a400000 0x100>; 1036 }; 1037 1038 rng@1a500000 { 1039 compatible = "qcom,prng"; 1040 reg = <0x1a500000 0x200>; 1041 clocks = <&gcc PRNG_CLK>; 1042 clock-names = "core"; 1043 }; 1044 1045 nand: nand-controller@1ac00000 { 1046 compatible = "qcom,ipq806x-nand"; 1047 reg = <0x1ac00000 0x800>; 1048 1049 pinctrl-0 = <&nand_pins>; 1050 pinctrl-names = "default"; 1051 1052 clocks = <&gcc EBI2_CLK>, 1053 <&gcc EBI2_AON_CLK>; 1054 clock-names = "core", "aon"; 1055 1056 dmas = <&adm_dma 3>; 1057 dma-names = "rxtx"; 1058 qcom,cmd-crci = <15>; 1059 qcom,data-crci = <3>; 1060 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 1064 status = "disabled"; 1065 }; 1066 1067 sata_phy: sata-phy@1b400000 { 1068 compatible = "qcom,ipq806x-sata-phy"; 1069 reg = <0x1b400000 0x200>; 1070 1071 clocks = <&gcc SATA_PHY_CFG_CLK>; 1072 clock-names = "cfg"; 1073 1074 #phy-cells = <0>; 1075 status = "disabled"; 1076 }; 1077 1078 pcie0: pci@1b500000 { 1079 compatible = "qcom,pcie-ipq8064"; 1080 reg = <0x1b500000 0x1000 1081 0x1b502000 0x80 1082 0x1b600000 0x100 1083 0x0ff00000 0x100000>; 1084 reg-names = "dbi", "elbi", "parf", "config"; 1085 device_type = "pci"; 1086 linux,pci-domain = <0>; 1087 bus-range = <0x00 0xff>; 1088 num-lanes = <1>; 1089 #address-cells = <3>; 1090 #size-cells = <2>; 1091 1092 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */ 1093 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */ 1094 1095 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1096 interrupt-names = "msi"; 1097 #interrupt-cells = <1>; 1098 interrupt-map-mask = <0 0 0 0x7>; 1099 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1100 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1101 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1102 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1103 1104 clocks = <&gcc PCIE_A_CLK>, 1105 <&gcc PCIE_H_CLK>, 1106 <&gcc PCIE_PHY_CLK>, 1107 <&gcc PCIE_AUX_CLK>, 1108 <&gcc PCIE_ALT_REF_CLK>; 1109 clock-names = "core", "iface", "phy", "aux", "ref"; 1110 1111 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; 1112 assigned-clock-rates = <100000000>; 1113 1114 resets = <&gcc PCIE_ACLK_RESET>, 1115 <&gcc PCIE_HCLK_RESET>, 1116 <&gcc PCIE_POR_RESET>, 1117 <&gcc PCIE_PCI_RESET>, 1118 <&gcc PCIE_PHY_RESET>, 1119 <&gcc PCIE_EXT_RESET>; 1120 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1121 1122 pinctrl-0 = <&pcie0_pins>; 1123 pinctrl-names = "default"; 1124 1125 status = "disabled"; 1126 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; 1127 }; 1128 1129 pcie1: pci@1b700000 { 1130 compatible = "qcom,pcie-ipq8064"; 1131 reg = <0x1b700000 0x1000 1132 0x1b702000 0x80 1133 0x1b800000 0x100 1134 0x31f00000 0x100000>; 1135 reg-names = "dbi", "elbi", "parf", "config"; 1136 device_type = "pci"; 1137 linux,pci-domain = <1>; 1138 bus-range = <0x00 0xff>; 1139 num-lanes = <1>; 1140 #address-cells = <3>; 1141 #size-cells = <2>; 1142 1143 ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */ 1144 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */ 1145 1146 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1147 interrupt-names = "msi"; 1148 #interrupt-cells = <1>; 1149 interrupt-map-mask = <0 0 0 0x7>; 1150 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1151 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1152 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1153 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1154 1155 clocks = <&gcc PCIE_1_A_CLK>, 1156 <&gcc PCIE_1_H_CLK>, 1157 <&gcc PCIE_1_PHY_CLK>, 1158 <&gcc PCIE_1_AUX_CLK>, 1159 <&gcc PCIE_1_ALT_REF_CLK>; 1160 clock-names = "core", "iface", "phy", "aux", "ref"; 1161 1162 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; 1163 assigned-clock-rates = <100000000>; 1164 1165 resets = <&gcc PCIE_1_ACLK_RESET>, 1166 <&gcc PCIE_1_HCLK_RESET>, 1167 <&gcc PCIE_1_POR_RESET>, 1168 <&gcc PCIE_1_PCI_RESET>, 1169 <&gcc PCIE_1_PHY_RESET>, 1170 <&gcc PCIE_1_EXT_RESET>; 1171 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1172 1173 pinctrl-0 = <&pcie1_pins>; 1174 pinctrl-names = "default"; 1175 1176 status = "disabled"; 1177 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; 1178 }; 1179 1180 pcie2: pci@1b900000 { 1181 compatible = "qcom,pcie-ipq8064"; 1182 reg = <0x1b900000 0x1000 1183 0x1b902000 0x80 1184 0x1ba00000 0x100 1185 0x35f00000 0x100000>; 1186 reg-names = "dbi", "elbi", "parf", "config"; 1187 device_type = "pci"; 1188 linux,pci-domain = <2>; 1189 bus-range = <0x00 0xff>; 1190 num-lanes = <1>; 1191 #address-cells = <3>; 1192 #size-cells = <2>; 1193 1194 ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */ 1195 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */ 1196 1197 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1198 interrupt-names = "msi"; 1199 #interrupt-cells = <1>; 1200 interrupt-map-mask = <0 0 0 0x7>; 1201 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1202 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1203 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1204 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1205 1206 clocks = <&gcc PCIE_2_A_CLK>, 1207 <&gcc PCIE_2_H_CLK>, 1208 <&gcc PCIE_2_PHY_CLK>, 1209 <&gcc PCIE_2_AUX_CLK>, 1210 <&gcc PCIE_2_ALT_REF_CLK>; 1211 clock-names = "core", "iface", "phy", "aux", "ref"; 1212 1213 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; 1214 assigned-clock-rates = <100000000>; 1215 1216 resets = <&gcc PCIE_2_ACLK_RESET>, 1217 <&gcc PCIE_2_HCLK_RESET>, 1218 <&gcc PCIE_2_POR_RESET>, 1219 <&gcc PCIE_2_PCI_RESET>, 1220 <&gcc PCIE_2_PHY_RESET>, 1221 <&gcc PCIE_2_EXT_RESET>; 1222 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1223 1224 pinctrl-0 = <&pcie2_pins>; 1225 pinctrl-names = "default"; 1226 1227 status = "disabled"; 1228 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; 1229 }; 1230 1231 qsgmii_csr: syscon@1bb00000 { 1232 compatible = "syscon"; 1233 reg = <0x1bb00000 0x000001FF>; 1234 }; 1235 1236 lcc: clock-controller@28000000 { 1237 compatible = "qcom,lcc-ipq8064"; 1238 reg = <0x28000000 0x1000>; 1239 #clock-cells = <1>; 1240 #reset-cells = <1>; 1241 }; 1242 1243 lpass@28100000 { 1244 compatible = "qcom,lpass-cpu"; 1245 status = "disabled"; 1246 clocks = <&lcc AHBIX_CLK>, 1247 <&lcc MI2S_OSR_CLK>, 1248 <&lcc MI2S_BIT_CLK>; 1249 clock-names = "ahbix-clk", 1250 "mi2s-osr-clk", 1251 "mi2s-bit-clk"; 1252 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1253 interrupt-names = "lpass-irq-lpaif"; 1254 reg = <0x28100000 0x10000>; 1255 reg-names = "lpass-lpaif"; 1256 }; 1257 1258 sata: sata@29000000 { 1259 compatible = "qcom,ipq806x-ahci", "generic-ahci"; 1260 reg = <0x29000000 0x180>; 1261 1262 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1263 1264 clocks = <&gcc SFAB_SATA_S_H_CLK>, 1265 <&gcc SATA_H_CLK>, 1266 <&gcc SATA_A_CLK>, 1267 <&gcc SATA_RXOOB_CLK>, 1268 <&gcc SATA_PMALIVE_CLK>; 1269 clock-names = "slave_face", "iface", "core", 1270 "rxoob", "pmalive"; 1271 1272 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; 1273 assigned-clock-rates = <100000000>, <100000000>; 1274 1275 phys = <&sata_phy>; 1276 phy-names = "sata-phy"; 1277 status = "disabled"; 1278 }; 1279 1280 gmac0: ethernet@37000000 { 1281 device_type = "network"; 1282 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1283 reg = <0x37000000 0x200000>; 1284 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1285 interrupt-names = "macirq"; 1286 1287 snps,axi-config = <&stmmac_axi_setup>; 1288 snps,pbl = <32>; 1289 snps,aal; 1290 1291 qcom,nss-common = <&nss_common>; 1292 qcom,qsgmii-csr = <&qsgmii_csr>; 1293 1294 clocks = <&gcc GMAC_CORE1_CLK>; 1295 clock-names = "stmmaceth"; 1296 1297 resets = <&gcc GMAC_CORE1_RESET>, 1298 <&gcc GMAC_AHB_RESET>; 1299 reset-names = "stmmaceth", "ahb"; 1300 1301 status = "disabled"; 1302 }; 1303 1304 gmac1: ethernet@37200000 { 1305 device_type = "network"; 1306 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1307 reg = <0x37200000 0x200000>; 1308 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1309 interrupt-names = "macirq"; 1310 1311 snps,axi-config = <&stmmac_axi_setup>; 1312 snps,pbl = <32>; 1313 snps,aal; 1314 1315 qcom,nss-common = <&nss_common>; 1316 qcom,qsgmii-csr = <&qsgmii_csr>; 1317 1318 clocks = <&gcc GMAC_CORE2_CLK>; 1319 clock-names = "stmmaceth"; 1320 1321 resets = <&gcc GMAC_CORE2_RESET>, 1322 <&gcc GMAC_AHB_RESET>; 1323 reset-names = "stmmaceth", "ahb"; 1324 1325 status = "disabled"; 1326 }; 1327 1328 gmac2: ethernet@37400000 { 1329 device_type = "network"; 1330 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1331 reg = <0x37400000 0x200000>; 1332 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1333 interrupt-names = "macirq"; 1334 1335 snps,axi-config = <&stmmac_axi_setup>; 1336 snps,pbl = <32>; 1337 snps,aal; 1338 1339 qcom,nss-common = <&nss_common>; 1340 qcom,qsgmii-csr = <&qsgmii_csr>; 1341 1342 clocks = <&gcc GMAC_CORE3_CLK>; 1343 clock-names = "stmmaceth"; 1344 1345 resets = <&gcc GMAC_CORE3_RESET>, 1346 <&gcc GMAC_AHB_RESET>; 1347 reset-names = "stmmaceth", "ahb"; 1348 1349 status = "disabled"; 1350 }; 1351 1352 gmac3: ethernet@37600000 { 1353 device_type = "network"; 1354 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1355 reg = <0x37600000 0x200000>; 1356 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1357 interrupt-names = "macirq"; 1358 1359 snps,axi-config = <&stmmac_axi_setup>; 1360 snps,pbl = <32>; 1361 snps,aal; 1362 1363 qcom,nss-common = <&nss_common>; 1364 qcom,qsgmii-csr = <&qsgmii_csr>; 1365 1366 clocks = <&gcc GMAC_CORE4_CLK>; 1367 clock-names = "stmmaceth"; 1368 1369 resets = <&gcc GMAC_CORE4_RESET>, 1370 <&gcc GMAC_AHB_RESET>; 1371 reset-names = "stmmaceth", "ahb"; 1372 1373 status = "disabled"; 1374 }; 1375 }; 1376}; 1377