1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MediaTek DPI and DP_INTF Controller 8 9maintainers: 10 - CK Hu <ck.hu@mediatek.com> 11 - Jitao shi <jitao.shi@mediatek.com> 12 13description: | 14 The MediaTek DPI and DP_INTF function blocks are a sink of the display 15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a 16 parallel output bus. 17 18properties: 19 compatible: 20 enum: 21 - mediatek,mt2701-dpi 22 - mediatek,mt7623-dpi 23 - mediatek,mt8173-dpi 24 - mediatek,mt8183-dpi 25 - mediatek,mt8186-dpi 26 - mediatek,mt8192-dpi 27 - mediatek,mt8195-dp-intf 28 29 reg: 30 maxItems: 1 31 32 interrupts: 33 maxItems: 1 34 35 clocks: 36 items: 37 - description: Pixel Clock 38 - description: Engine Clock 39 - description: DPI PLL 40 41 clock-names: 42 items: 43 - const: pixel 44 - const: engine 45 - const: pll 46 47 pinctrl-0: true 48 pinctrl-1: true 49 50 pinctrl-names: 51 items: 52 - const: default 53 - const: sleep 54 55 port: 56 $ref: /schemas/graph.yaml#/properties/port 57 description: 58 Output port node. This port should be connected to the input port of an 59 attached HDMI, LVDS or DisplayPort encoder chip. 60 61required: 62 - compatible 63 - reg 64 - interrupts 65 - clocks 66 - clock-names 67 - port 68 69additionalProperties: false 70 71examples: 72 - | 73 #include <dt-bindings/interrupt-controller/arm-gic.h> 74 #include <dt-bindings/clock/mt8173-clk.h> 75 76 dpi0: dpi@1401d000 { 77 compatible = "mediatek,mt8173-dpi"; 78 reg = <0x1401d000 0x1000>; 79 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 80 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 81 <&mmsys CLK_MM_DPI_ENGINE>, 82 <&apmixedsys CLK_APMIXED_TVDPLL>; 83 clock-names = "pixel", "engine", "pll"; 84 pinctrl-names = "default", "sleep"; 85 pinctrl-0 = <&dpi_pin_func>; 86 pinctrl-1 = <&dpi_pin_idle>; 87 88 port { 89 dpi0_out: endpoint { 90 remote-endpoint = <&hdmi0_in>; 91 }; 92 }; 93 }; 94 95... 96