1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Renesas R-Car I2C unit 4 * 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2011-2019 Renesas Electronics Corporation 7 * 8 * Copyright (C) 2012-14 Renesas Solutions Corp. 9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 10 * 11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 13 */ 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dmaengine.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/i2c.h> 24 #include <linux/i2c-smbus.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/reset.h> 31 #include <linux/slab.h> 32 33 /* register offsets */ 34 #define ICSCR 0x00 /* slave ctrl */ 35 #define ICMCR 0x04 /* master ctrl */ 36 #define ICSSR 0x08 /* slave status */ 37 #define ICMSR 0x0C /* master status */ 38 #define ICSIER 0x10 /* slave irq enable */ 39 #define ICMIER 0x14 /* master irq enable */ 40 #define ICCCR 0x18 /* clock dividers */ 41 #define ICSAR 0x1C /* slave address */ 42 #define ICMAR 0x20 /* master address */ 43 #define ICRXTX 0x24 /* data port */ 44 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */ 45 #define ICDMAER 0x3c /* DMA enable (Gen3) */ 46 47 /* ICSCR */ 48 #define SDBS (1 << 3) /* slave data buffer select */ 49 #define SIE (1 << 2) /* slave interface enable */ 50 #define GCAE (1 << 1) /* general call address enable */ 51 #define FNA (1 << 0) /* forced non acknowledgment */ 52 53 /* ICMCR */ 54 #define MDBS (1 << 7) /* non-fifo mode switch */ 55 #define FSCL (1 << 6) /* override SCL pin */ 56 #define FSDA (1 << 5) /* override SDA pin */ 57 #define OBPC (1 << 4) /* override pins */ 58 #define MIE (1 << 3) /* master if enable */ 59 #define TSBE (1 << 2) 60 #define FSB (1 << 1) /* force stop bit */ 61 #define ESG (1 << 0) /* enable start bit gen */ 62 63 /* ICSSR (also for ICSIER) */ 64 #define GCAR (1 << 6) /* general call received */ 65 #define STM (1 << 5) /* slave transmit mode */ 66 #define SSR (1 << 4) /* stop received */ 67 #define SDE (1 << 3) /* slave data empty */ 68 #define SDT (1 << 2) /* slave data transmitted */ 69 #define SDR (1 << 1) /* slave data received */ 70 #define SAR (1 << 0) /* slave addr received */ 71 72 /* ICMSR (also for ICMIE) */ 73 #define MNR (1 << 6) /* nack received */ 74 #define MAL (1 << 5) /* arbitration lost */ 75 #define MST (1 << 4) /* sent a stop */ 76 #define MDE (1 << 3) 77 #define MDT (1 << 2) 78 #define MDR (1 << 1) 79 #define MAT (1 << 0) /* slave addr xfer done */ 80 81 /* ICDMAER */ 82 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */ 83 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */ 84 #define RMDMAE (1 << 1) /* DMA Master Received Enable */ 85 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ 86 87 /* ICFBSCR */ 88 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 89 90 #define RCAR_MIN_DMA_LEN 8 91 92 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 93 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 94 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 95 96 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 97 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 98 #define RCAR_IRQ_STOP (MST) 99 100 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F) 101 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F) 102 103 #define ID_LAST_MSG (1 << 0) 104 #define ID_FIRST_MSG (1 << 1) 105 #define ID_DONE (1 << 2) 106 #define ID_ARBLOST (1 << 3) 107 #define ID_NACK (1 << 4) 108 /* persistent flags */ 109 #define ID_P_HOST_NOTIFY BIT(28) 110 #define ID_P_REP_AFTER_RD BIT(29) 111 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */ 112 #define ID_P_PM_BLOCKED BIT(31) 113 #define ID_P_MASK GENMASK(31, 28) 114 115 enum rcar_i2c_type { 116 I2C_RCAR_GEN1, 117 I2C_RCAR_GEN2, 118 I2C_RCAR_GEN3, 119 }; 120 121 struct rcar_i2c_priv { 122 u32 flags; 123 void __iomem *io; 124 struct i2c_adapter adap; 125 struct i2c_msg *msg; 126 int msgs_left; 127 struct clk *clk; 128 129 wait_queue_head_t wait; 130 131 int pos; 132 u32 icccr; 133 u8 recovery_icmcr; /* protected by adapter lock */ 134 enum rcar_i2c_type devtype; 135 struct i2c_client *slave; 136 137 struct resource *res; 138 struct dma_chan *dma_tx; 139 struct dma_chan *dma_rx; 140 struct scatterlist sg; 141 enum dma_data_direction dma_direction; 142 143 struct reset_control *rstc; 144 bool atomic_xfer; 145 int irq; 146 147 struct i2c_client *host_notify_client; 148 }; 149 150 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 151 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 152 153 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 154 { 155 writel(val, priv->io + reg); 156 } 157 158 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 159 { 160 return readl(priv->io + reg); 161 } 162 163 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 164 { 165 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 166 167 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 168 169 }; 170 171 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 172 { 173 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 174 175 if (val) 176 priv->recovery_icmcr |= FSCL; 177 else 178 priv->recovery_icmcr &= ~FSCL; 179 180 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 181 }; 182 183 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 184 { 185 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 186 187 if (val) 188 priv->recovery_icmcr |= FSDA; 189 else 190 priv->recovery_icmcr &= ~FSDA; 191 192 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 193 }; 194 195 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap) 196 { 197 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 198 199 return !(rcar_i2c_read(priv, ICMCR) & FSDA); 200 201 }; 202 203 static struct i2c_bus_recovery_info rcar_i2c_bri = { 204 .get_scl = rcar_i2c_get_scl, 205 .set_scl = rcar_i2c_set_scl, 206 .set_sda = rcar_i2c_set_sda, 207 .get_bus_free = rcar_i2c_get_bus_free, 208 .recover_bus = i2c_generic_scl_recovery, 209 }; 210 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 211 { 212 /* reset master mode */ 213 rcar_i2c_write(priv, ICMIER, 0); 214 rcar_i2c_write(priv, ICMCR, MDBS); 215 rcar_i2c_write(priv, ICMSR, 0); 216 /* start clock */ 217 rcar_i2c_write(priv, ICCCR, priv->icccr); 218 219 if (priv->devtype == I2C_RCAR_GEN3) 220 rcar_i2c_write(priv, ICFBSCR, TCYC17); 221 222 } 223 224 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 225 { 226 int ret; 227 u32 val; 228 229 ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10, 230 priv->adap.timeout); 231 if (ret) { 232 /* Waiting did not help, try to recover */ 233 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 234 ret = i2c_recover_bus(&priv->adap); 235 } 236 237 return ret; 238 } 239 240 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv) 241 { 242 u32 scgd, cdf, round, ick, sum, scl, cdf_width; 243 unsigned long rate; 244 struct device *dev = rcar_i2c_priv_to_dev(priv); 245 struct i2c_timings t = { 246 .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ, 247 .scl_fall_ns = 35, 248 .scl_rise_ns = 200, 249 .scl_int_delay_ns = 50, 250 }; 251 252 /* Fall back to previously used values if not supplied */ 253 i2c_parse_fw_timings(dev, &t, false); 254 255 switch (priv->devtype) { 256 case I2C_RCAR_GEN1: 257 cdf_width = 2; 258 break; 259 case I2C_RCAR_GEN2: 260 case I2C_RCAR_GEN3: 261 cdf_width = 3; 262 break; 263 default: 264 dev_err(dev, "device type error\n"); 265 return -EIO; 266 } 267 268 /* 269 * calculate SCL clock 270 * see 271 * ICCCR 272 * 273 * ick = clkp / (1 + CDF) 274 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 275 * 276 * ick : I2C internal clock < 20 MHz 277 * ticf : I2C SCL falling time 278 * tr : I2C SCL rising time 279 * intd : LSI internal delay 280 * clkp : peripheral_clk 281 * F[] : integer up-valuation 282 */ 283 rate = clk_get_rate(priv->clk); 284 cdf = rate / 20000000; 285 if (cdf >= 1U << cdf_width) { 286 dev_err(dev, "Input clock %lu too high\n", rate); 287 return -EIO; 288 } 289 ick = rate / (cdf + 1); 290 291 /* 292 * it is impossible to calculate large scale 293 * number on u32. separate it 294 * 295 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 296 * = F[sum * ick / 1000000000] 297 * = F[(ick / 1000000) * sum / 1000] 298 */ 299 sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns; 300 round = (ick + 500000) / 1000000 * sum; 301 round = (round + 500) / 1000; 302 303 /* 304 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 305 * 306 * Calculation result (= SCL) should be less than 307 * bus_speed for hardware safety 308 * 309 * We could use something along the lines of 310 * div = ick / (bus_speed + 1) + 1; 311 * scgd = (div - 20 - round + 7) / 8; 312 * scl = ick / (20 + (scgd * 8) + round); 313 * (not fully verified) but that would get pretty involved 314 */ 315 for (scgd = 0; scgd < 0x40; scgd++) { 316 scl = ick / (20 + (scgd * 8) + round); 317 if (scl <= t.bus_freq_hz) 318 goto scgd_find; 319 } 320 dev_err(dev, "it is impossible to calculate best SCL\n"); 321 return -EIO; 322 323 scgd_find: 324 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", 325 scl, t.bus_freq_hz, rate, round, cdf, scgd); 326 327 /* keep icccr value */ 328 priv->icccr = scgd << cdf_width | cdf; 329 330 return 0; 331 } 332 333 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 334 { 335 int read = !!rcar_i2c_is_recv(priv); 336 337 priv->pos = 0; 338 if (priv->msgs_left == 1) 339 priv->flags |= ID_LAST_MSG; 340 341 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); 342 if (!priv->atomic_xfer) 343 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 344 345 /* 346 * We don't have a test case but the HW engineers say that the write order 347 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since 348 * it didn't cause a drawback for me, let's rather be safe than sorry. 349 */ 350 if (priv->flags & ID_FIRST_MSG) { 351 rcar_i2c_write(priv, ICMSR, 0); 352 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 353 } else { 354 if (priv->flags & ID_P_REP_AFTER_RD) 355 priv->flags &= ~ID_P_REP_AFTER_RD; 356 else 357 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 358 rcar_i2c_write(priv, ICMSR, 0); 359 } 360 } 361 362 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 363 { 364 priv->msg++; 365 priv->msgs_left--; 366 priv->flags &= ID_P_MASK; 367 rcar_i2c_prepare_msg(priv); 368 } 369 370 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv, bool terminate) 371 { 372 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 373 ? priv->dma_rx : priv->dma_tx; 374 375 /* only allowed from thread context! */ 376 if (terminate) 377 dmaengine_terminate_sync(chan); 378 379 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 380 sg_dma_len(&priv->sg), priv->dma_direction); 381 382 /* Gen3 can only do one RXDMA per transfer and we just completed it */ 383 if (priv->devtype == I2C_RCAR_GEN3 && 384 priv->dma_direction == DMA_FROM_DEVICE) 385 priv->flags |= ID_P_NO_RXDMA; 386 387 priv->dma_direction = DMA_NONE; 388 389 /* Disable DMA Master Received/Transmitted, must be last! */ 390 rcar_i2c_write(priv, ICDMAER, 0); 391 } 392 393 static void rcar_i2c_dma_callback(void *data) 394 { 395 struct rcar_i2c_priv *priv = data; 396 397 priv->pos += sg_dma_len(&priv->sg); 398 399 rcar_i2c_cleanup_dma(priv, false); 400 } 401 402 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv) 403 { 404 struct device *dev = rcar_i2c_priv_to_dev(priv); 405 struct i2c_msg *msg = priv->msg; 406 bool read = msg->flags & I2C_M_RD; 407 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 408 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 409 struct dma_async_tx_descriptor *txdesc; 410 dma_addr_t dma_addr; 411 dma_cookie_t cookie; 412 unsigned char *buf; 413 int len; 414 415 /* Do various checks to see if DMA is feasible at all */ 416 if (priv->atomic_xfer || IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN || 417 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA)) 418 return false; 419 420 if (read) { 421 /* 422 * The last two bytes needs to be fetched using PIO in 423 * order for the STOP phase to work. 424 */ 425 buf = priv->msg->buf; 426 len = priv->msg->len - 2; 427 } else { 428 /* 429 * First byte in message was sent using PIO. 430 */ 431 buf = priv->msg->buf + 1; 432 len = priv->msg->len - 1; 433 } 434 435 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 436 if (dma_mapping_error(chan->device->dev, dma_addr)) { 437 dev_dbg(dev, "dma map failed, using PIO\n"); 438 return false; 439 } 440 441 sg_dma_len(&priv->sg) = len; 442 sg_dma_address(&priv->sg) = dma_addr; 443 444 priv->dma_direction = dir; 445 446 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 447 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 448 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 449 if (!txdesc) { 450 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 451 rcar_i2c_cleanup_dma(priv, false); 452 return false; 453 } 454 455 txdesc->callback = rcar_i2c_dma_callback; 456 txdesc->callback_param = priv; 457 458 cookie = dmaengine_submit(txdesc); 459 if (dma_submit_error(cookie)) { 460 dev_dbg(dev, "submitting dma failed, using PIO\n"); 461 rcar_i2c_cleanup_dma(priv, false); 462 return false; 463 } 464 465 /* Enable DMA Master Received/Transmitted */ 466 if (read) 467 rcar_i2c_write(priv, ICDMAER, RMDMAE); 468 else 469 rcar_i2c_write(priv, ICDMAER, TMDMAE); 470 471 dma_async_issue_pending(chan); 472 return true; 473 } 474 475 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 476 { 477 struct i2c_msg *msg = priv->msg; 478 479 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 480 if (!(msr & MDE)) 481 return; 482 483 /* Check if DMA can be enabled and take over */ 484 if (priv->pos == 1 && rcar_i2c_dma(priv)) 485 return; 486 487 if (priv->pos < msg->len) { 488 /* 489 * Prepare next data to ICRXTX register. 490 * This data will go to _SHIFT_ register. 491 * 492 * * 493 * [ICRXTX] -> [SHIFT] -> [I2C bus] 494 */ 495 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 496 priv->pos++; 497 } else { 498 /* 499 * The last data was pushed to ICRXTX on _PREV_ empty irq. 500 * It is on _SHIFT_ register, and will sent to I2C bus. 501 * 502 * * 503 * [ICRXTX] -> [SHIFT] -> [I2C bus] 504 */ 505 506 if (priv->flags & ID_LAST_MSG) { 507 /* 508 * If current msg is the _LAST_ msg, 509 * prepare stop condition here. 510 * ID_DONE will be set on STOP irq. 511 */ 512 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 513 } else { 514 rcar_i2c_next_msg(priv); 515 return; 516 } 517 } 518 519 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); 520 } 521 522 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 523 { 524 struct i2c_msg *msg = priv->msg; 525 526 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 527 if (!(msr & MDR)) 528 return; 529 530 if (msr & MAT) { 531 /* 532 * Address transfer phase finished, but no data at this point. 533 * Try to use DMA to receive data. 534 */ 535 rcar_i2c_dma(priv); 536 } else if (priv->pos < msg->len) { 537 /* get received data */ 538 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); 539 priv->pos++; 540 } 541 542 /* If next received data is the _LAST_, go to new phase. */ 543 if (priv->pos + 1 == msg->len) { 544 if (priv->flags & ID_LAST_MSG) { 545 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 546 } else { 547 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 548 priv->flags |= ID_P_REP_AFTER_RD; 549 } 550 } 551 552 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 553 rcar_i2c_next_msg(priv); 554 else 555 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); 556 } 557 558 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 559 { 560 u32 ssr_raw, ssr_filtered; 561 u8 value; 562 563 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 564 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 565 566 if (!ssr_filtered) 567 return false; 568 569 /* address detected */ 570 if (ssr_filtered & SAR) { 571 /* read or write request */ 572 if (ssr_raw & STM) { 573 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 574 rcar_i2c_write(priv, ICRXTX, value); 575 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 576 } else { 577 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 578 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 579 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 580 } 581 582 /* Clear SSR, too, because of old STOPs to other clients than us */ 583 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff); 584 } 585 586 /* master sent stop */ 587 if (ssr_filtered & SSR) { 588 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 589 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */ 590 rcar_i2c_write(priv, ICSIER, SAR); 591 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 592 } 593 594 /* master wants to write to us */ 595 if (ssr_filtered & SDR) { 596 int ret; 597 598 value = rcar_i2c_read(priv, ICRXTX); 599 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 600 /* Send NACK in case of error */ 601 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 602 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 603 } 604 605 /* master wants to read from us */ 606 if (ssr_filtered & SDE) { 607 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 608 rcar_i2c_write(priv, ICRXTX, value); 609 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 610 } 611 612 return true; 613 } 614 615 /* 616 * This driver has a lock-free design because there are IP cores (at least 617 * R-Car Gen2) which have an inherent race condition in their hardware design. 618 * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after 619 * the interrupt was generated, otherwise an unwanted repeated message gets 620 * generated. It turned out that taking a spinlock at the beginning of the ISR 621 * was already causing repeated messages. Thus, this driver was converted to 622 * the now lockless behaviour. Please keep this in mind when hacking the driver. 623 * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are 624 * likely affected. Therefore, we have different interrupt handler entries. 625 */ 626 static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr) 627 { 628 if (!msr) { 629 if (rcar_i2c_slave_irq(priv)) 630 return IRQ_HANDLED; 631 632 return IRQ_NONE; 633 } 634 635 /* Arbitration lost */ 636 if (msr & MAL) { 637 priv->flags |= ID_DONE | ID_ARBLOST; 638 goto out; 639 } 640 641 /* Nack */ 642 if (msr & MNR) { 643 /* HW automatically sends STOP after received NACK */ 644 if (!priv->atomic_xfer) 645 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 646 priv->flags |= ID_NACK; 647 goto out; 648 } 649 650 /* Stop */ 651 if (msr & MST) { 652 priv->msgs_left--; /* The last message also made it */ 653 priv->flags |= ID_DONE; 654 goto out; 655 } 656 657 if (rcar_i2c_is_recv(priv)) 658 rcar_i2c_irq_recv(priv, msr); 659 else 660 rcar_i2c_irq_send(priv, msr); 661 662 out: 663 if (priv->flags & ID_DONE) { 664 rcar_i2c_write(priv, ICMIER, 0); 665 rcar_i2c_write(priv, ICMSR, 0); 666 if (!priv->atomic_xfer) 667 wake_up(&priv->wait); 668 } 669 670 return IRQ_HANDLED; 671 } 672 673 static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr) 674 { 675 struct rcar_i2c_priv *priv = ptr; 676 u32 msr; 677 678 /* Clear START or STOP immediately, except for REPSTART after read */ 679 if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) 680 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 681 682 /* Only handle interrupts that are currently enabled */ 683 msr = rcar_i2c_read(priv, ICMSR); 684 if (!priv->atomic_xfer) 685 msr &= rcar_i2c_read(priv, ICMIER); 686 687 return rcar_i2c_irq(irq, priv, msr); 688 } 689 690 static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr) 691 { 692 struct rcar_i2c_priv *priv = ptr; 693 u32 msr; 694 695 /* Only handle interrupts that are currently enabled */ 696 msr = rcar_i2c_read(priv, ICMSR); 697 if (!priv->atomic_xfer) 698 msr &= rcar_i2c_read(priv, ICMIER); 699 700 /* 701 * Clear START or STOP immediately, except for REPSTART after read or 702 * if a spurious interrupt was detected. 703 */ 704 if (likely(!(priv->flags & ID_P_REP_AFTER_RD) && msr)) 705 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 706 707 return rcar_i2c_irq(irq, priv, msr); 708 } 709 710 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 711 enum dma_transfer_direction dir, 712 dma_addr_t port_addr) 713 { 714 struct dma_chan *chan; 715 struct dma_slave_config cfg; 716 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 717 int ret; 718 719 chan = dma_request_chan(dev, chan_name); 720 if (IS_ERR(chan)) { 721 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 722 chan_name, PTR_ERR(chan)); 723 return chan; 724 } 725 726 memset(&cfg, 0, sizeof(cfg)); 727 cfg.direction = dir; 728 if (dir == DMA_MEM_TO_DEV) { 729 cfg.dst_addr = port_addr; 730 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 731 } else { 732 cfg.src_addr = port_addr; 733 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 734 } 735 736 ret = dmaengine_slave_config(chan, &cfg); 737 if (ret) { 738 dev_dbg(dev, "slave_config failed for %s (%d)\n", 739 chan_name, ret); 740 dma_release_channel(chan); 741 return ERR_PTR(ret); 742 } 743 744 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 745 return chan; 746 } 747 748 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 749 struct i2c_msg *msg) 750 { 751 struct device *dev = rcar_i2c_priv_to_dev(priv); 752 bool read; 753 struct dma_chan *chan; 754 enum dma_transfer_direction dir; 755 756 read = msg->flags & I2C_M_RD; 757 758 chan = read ? priv->dma_rx : priv->dma_tx; 759 if (PTR_ERR(chan) != -EPROBE_DEFER) 760 return; 761 762 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 763 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 764 765 if (read) 766 priv->dma_rx = chan; 767 else 768 priv->dma_tx = chan; 769 } 770 771 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 772 { 773 if (!IS_ERR(priv->dma_tx)) { 774 dma_release_channel(priv->dma_tx); 775 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 776 } 777 778 if (!IS_ERR(priv->dma_rx)) { 779 dma_release_channel(priv->dma_rx); 780 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 781 } 782 } 783 784 /* I2C is a special case, we need to poll the status of a reset */ 785 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) 786 { 787 int ret; 788 789 ret = reset_control_reset(priv->rstc); 790 if (ret) 791 return ret; 792 793 return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 1, 794 100, false, priv->rstc); 795 } 796 797 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 798 struct i2c_msg *msgs, 799 int num) 800 { 801 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 802 struct device *dev = rcar_i2c_priv_to_dev(priv); 803 int i, ret; 804 long time_left; 805 806 priv->atomic_xfer = false; 807 808 pm_runtime_get_sync(dev); 809 810 /* Check bus state before init otherwise bus busy info will be lost */ 811 ret = rcar_i2c_bus_barrier(priv); 812 if (ret < 0) 813 goto out; 814 815 /* Gen3 needs a reset before allowing RXDMA once */ 816 if (priv->devtype == I2C_RCAR_GEN3) { 817 priv->flags |= ID_P_NO_RXDMA; 818 if (!IS_ERR(priv->rstc)) { 819 ret = rcar_i2c_do_reset(priv); 820 if (ret == 0) 821 priv->flags &= ~ID_P_NO_RXDMA; 822 } 823 } 824 825 rcar_i2c_init(priv); 826 827 for (i = 0; i < num; i++) 828 rcar_i2c_request_dma(priv, msgs + i); 829 830 /* init first message */ 831 priv->msg = msgs; 832 priv->msgs_left = num; 833 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; 834 rcar_i2c_prepare_msg(priv); 835 836 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 837 num * adap->timeout); 838 839 /* cleanup DMA if it couldn't complete properly due to an error */ 840 if (priv->dma_direction != DMA_NONE) 841 rcar_i2c_cleanup_dma(priv, true); 842 843 if (!time_left) { 844 rcar_i2c_init(priv); 845 ret = -ETIMEDOUT; 846 } else if (priv->flags & ID_NACK) { 847 ret = -ENXIO; 848 } else if (priv->flags & ID_ARBLOST) { 849 ret = -EAGAIN; 850 } else { 851 ret = num - priv->msgs_left; /* The number of transfer */ 852 } 853 out: 854 pm_runtime_put(dev); 855 856 if (ret < 0 && ret != -ENXIO) 857 dev_err(dev, "error %d : %x\n", ret, priv->flags); 858 859 return ret; 860 } 861 862 static int rcar_i2c_master_xfer_atomic(struct i2c_adapter *adap, 863 struct i2c_msg *msgs, 864 int num) 865 { 866 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 867 struct device *dev = rcar_i2c_priv_to_dev(priv); 868 unsigned long j; 869 bool time_left; 870 int ret; 871 872 priv->atomic_xfer = true; 873 874 pm_runtime_get_sync(dev); 875 876 /* Check bus state before init otherwise bus busy info will be lost */ 877 ret = rcar_i2c_bus_barrier(priv); 878 if (ret < 0) 879 goto out; 880 881 rcar_i2c_init(priv); 882 883 /* init first message */ 884 priv->msg = msgs; 885 priv->msgs_left = num; 886 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; 887 rcar_i2c_prepare_msg(priv); 888 889 j = jiffies + num * adap->timeout; 890 do { 891 u32 msr = rcar_i2c_read(priv, ICMSR); 892 893 msr &= (rcar_i2c_is_recv(priv) ? RCAR_IRQ_RECV : RCAR_IRQ_SEND) | RCAR_IRQ_STOP; 894 895 if (msr) { 896 if (priv->devtype < I2C_RCAR_GEN3) 897 rcar_i2c_gen2_irq(0, priv); 898 else 899 rcar_i2c_gen3_irq(0, priv); 900 } 901 902 time_left = time_before_eq(jiffies, j); 903 } while (!(priv->flags & ID_DONE) && time_left); 904 905 if (!time_left) { 906 rcar_i2c_init(priv); 907 ret = -ETIMEDOUT; 908 } else if (priv->flags & ID_NACK) { 909 ret = -ENXIO; 910 } else if (priv->flags & ID_ARBLOST) { 911 ret = -EAGAIN; 912 } else { 913 ret = num - priv->msgs_left; /* The number of transfer */ 914 } 915 out: 916 pm_runtime_put(dev); 917 918 if (ret < 0 && ret != -ENXIO) 919 dev_err(dev, "error %d : %x\n", ret, priv->flags); 920 921 return ret; 922 } 923 924 static int rcar_reg_slave(struct i2c_client *slave) 925 { 926 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 927 928 if (priv->slave) 929 return -EBUSY; 930 931 if (slave->flags & I2C_CLIENT_TEN) 932 return -EAFNOSUPPORT; 933 934 /* Keep device active for slave address detection logic */ 935 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 936 937 priv->slave = slave; 938 rcar_i2c_write(priv, ICSAR, slave->addr); 939 rcar_i2c_write(priv, ICSSR, 0); 940 rcar_i2c_write(priv, ICSIER, SAR); 941 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 942 943 return 0; 944 } 945 946 static int rcar_unreg_slave(struct i2c_client *slave) 947 { 948 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 949 950 WARN_ON(!priv->slave); 951 952 /* ensure no irq is running before clearing ptr */ 953 disable_irq(priv->irq); 954 rcar_i2c_write(priv, ICSIER, 0); 955 rcar_i2c_write(priv, ICSSR, 0); 956 enable_irq(priv->irq); 957 rcar_i2c_write(priv, ICSCR, SDBS); 958 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 959 960 priv->slave = NULL; 961 962 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 963 964 return 0; 965 } 966 967 static u32 rcar_i2c_func(struct i2c_adapter *adap) 968 { 969 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 970 971 /* 972 * This HW can't do: 973 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 974 * I2C_M_NOSTART (automatically sends address after START) 975 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 976 */ 977 u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE | 978 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 979 980 if (priv->flags & ID_P_HOST_NOTIFY) 981 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 982 983 return func; 984 } 985 986 static const struct i2c_algorithm rcar_i2c_algo = { 987 .master_xfer = rcar_i2c_master_xfer, 988 .master_xfer_atomic = rcar_i2c_master_xfer_atomic, 989 .functionality = rcar_i2c_func, 990 .reg_slave = rcar_reg_slave, 991 .unreg_slave = rcar_unreg_slave, 992 }; 993 994 static const struct i2c_adapter_quirks rcar_i2c_quirks = { 995 .flags = I2C_AQ_NO_ZERO_LEN, 996 }; 997 998 static const struct of_device_id rcar_i2c_dt_ids[] = { 999 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 1000 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 1001 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 1002 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 1003 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 1004 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 1005 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 1006 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 1007 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 1008 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 1009 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 1010 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 1011 {}, 1012 }; 1013 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 1014 1015 static int rcar_i2c_probe(struct platform_device *pdev) 1016 { 1017 struct rcar_i2c_priv *priv; 1018 struct i2c_adapter *adap; 1019 struct device *dev = &pdev->dev; 1020 unsigned long irqflags = 0; 1021 irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq; 1022 int ret; 1023 1024 /* Otherwise logic will break because some bytes must always use PIO */ 1025 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length"); 1026 1027 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 1028 if (!priv) 1029 return -ENOMEM; 1030 1031 priv->clk = devm_clk_get(dev, NULL); 1032 if (IS_ERR(priv->clk)) { 1033 dev_err(dev, "cannot get clock\n"); 1034 return PTR_ERR(priv->clk); 1035 } 1036 1037 priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res); 1038 if (IS_ERR(priv->io)) 1039 return PTR_ERR(priv->io); 1040 1041 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); 1042 init_waitqueue_head(&priv->wait); 1043 1044 adap = &priv->adap; 1045 adap->nr = pdev->id; 1046 adap->algo = &rcar_i2c_algo; 1047 adap->class = I2C_CLASS_DEPRECATED; 1048 adap->retries = 3; 1049 adap->dev.parent = dev; 1050 adap->dev.of_node = dev->of_node; 1051 adap->bus_recovery_info = &rcar_i2c_bri; 1052 adap->quirks = &rcar_i2c_quirks; 1053 i2c_set_adapdata(adap, priv); 1054 strlcpy(adap->name, pdev->name, sizeof(adap->name)); 1055 1056 /* Init DMA */ 1057 sg_init_table(&priv->sg, 1); 1058 priv->dma_direction = DMA_NONE; 1059 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 1060 1061 /* Activate device for clock calculation */ 1062 pm_runtime_enable(dev); 1063 pm_runtime_get_sync(dev); 1064 ret = rcar_i2c_clock_calculate(priv); 1065 if (ret < 0) 1066 goto out_pm_put; 1067 1068 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 1069 1070 if (priv->devtype < I2C_RCAR_GEN3) { 1071 irqflags |= IRQF_NO_THREAD; 1072 irqhandler = rcar_i2c_gen2_irq; 1073 } 1074 1075 if (priv->devtype == I2C_RCAR_GEN3) { 1076 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1077 if (!IS_ERR(priv->rstc)) { 1078 ret = reset_control_status(priv->rstc); 1079 if (ret < 0) 1080 priv->rstc = ERR_PTR(-ENOTSUPP); 1081 } 1082 } 1083 1084 /* Stay always active when multi-master to keep arbitration working */ 1085 if (of_property_read_bool(dev->of_node, "multi-master")) 1086 priv->flags |= ID_P_PM_BLOCKED; 1087 else 1088 pm_runtime_put(dev); 1089 1090 if (of_property_read_bool(dev->of_node, "smbus")) 1091 priv->flags |= ID_P_HOST_NOTIFY; 1092 1093 ret = platform_get_irq(pdev, 0); 1094 if (ret < 0) 1095 goto out_pm_disable; 1096 priv->irq = ret; 1097 ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv); 1098 if (ret < 0) { 1099 dev_err(dev, "cannot get irq %d\n", priv->irq); 1100 goto out_pm_disable; 1101 } 1102 1103 platform_set_drvdata(pdev, priv); 1104 1105 ret = i2c_add_numbered_adapter(adap); 1106 if (ret < 0) 1107 goto out_pm_disable; 1108 1109 if (priv->flags & ID_P_HOST_NOTIFY) { 1110 priv->host_notify_client = i2c_new_slave_host_notify_device(adap); 1111 if (IS_ERR(priv->host_notify_client)) { 1112 ret = PTR_ERR(priv->host_notify_client); 1113 goto out_del_device; 1114 } 1115 } 1116 1117 dev_info(dev, "probed\n"); 1118 1119 return 0; 1120 1121 out_del_device: 1122 i2c_del_adapter(&priv->adap); 1123 out_pm_put: 1124 pm_runtime_put(dev); 1125 out_pm_disable: 1126 pm_runtime_disable(dev); 1127 return ret; 1128 } 1129 1130 static int rcar_i2c_remove(struct platform_device *pdev) 1131 { 1132 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 1133 struct device *dev = &pdev->dev; 1134 1135 if (priv->host_notify_client) 1136 i2c_free_slave_host_notify_device(priv->host_notify_client); 1137 i2c_del_adapter(&priv->adap); 1138 rcar_i2c_release_dma(priv); 1139 if (priv->flags & ID_P_PM_BLOCKED) 1140 pm_runtime_put(dev); 1141 pm_runtime_disable(dev); 1142 1143 return 0; 1144 } 1145 1146 #ifdef CONFIG_PM_SLEEP 1147 static int rcar_i2c_suspend(struct device *dev) 1148 { 1149 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1150 1151 i2c_mark_adapter_suspended(&priv->adap); 1152 return 0; 1153 } 1154 1155 static int rcar_i2c_resume(struct device *dev) 1156 { 1157 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1158 1159 i2c_mark_adapter_resumed(&priv->adap); 1160 return 0; 1161 } 1162 1163 static const struct dev_pm_ops rcar_i2c_pm_ops = { 1164 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume) 1165 }; 1166 1167 #define DEV_PM_OPS (&rcar_i2c_pm_ops) 1168 #else 1169 #define DEV_PM_OPS NULL 1170 #endif /* CONFIG_PM_SLEEP */ 1171 1172 static struct platform_driver rcar_i2c_driver = { 1173 .driver = { 1174 .name = "i2c-rcar", 1175 .of_match_table = rcar_i2c_dt_ids, 1176 .pm = DEV_PM_OPS, 1177 }, 1178 .probe = rcar_i2c_probe, 1179 .remove = rcar_i2c_remove, 1180 }; 1181 1182 module_platform_driver(rcar_i2c_driver); 1183 1184 MODULE_LICENSE("GPL v2"); 1185 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 1186 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 1187