1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 * Copyright 2019-2020 Variscite Ltd. 5 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org> 6 */ 7 8#include "imx8mn.dtsi" 9 10/ { 11 model = "Variscite VAR-SOM-MX8MN module"; 12 compatible = "variscite,var-som-mx8mn", "fsl,imx8mn"; 13 14 chosen { 15 stdout-path = &uart4; 16 }; 17 18 memory@40000000 { 19 device_type = "memory"; 20 reg = <0x0 0x40000000 0 0x40000000>; 21 }; 22 23 reg_eth_phy: regulator-eth-phy { 24 compatible = "regulator-fixed"; 25 pinctrl-names = "default"; 26 pinctrl-0 = <&pinctrl_reg_eth_phy>; 27 regulator-name = "eth_phy_pwr"; 28 regulator-min-microvolt = <3300000>; 29 regulator-max-microvolt = <3300000>; 30 regulator-enable-ramp-delay = <20000>; 31 gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; 32 enable-active-high; 33 }; 34}; 35 36&A53_0 { 37 cpu-supply = <&buck2_reg>; 38}; 39 40&A53_1 { 41 cpu-supply = <&buck2_reg>; 42}; 43 44&A53_2 { 45 cpu-supply = <&buck2_reg>; 46}; 47 48&A53_3 { 49 cpu-supply = <&buck2_reg>; 50}; 51 52&ecspi1 { 53 pinctrl-names = "default"; 54 pinctrl-0 = <&pinctrl_ecspi1>; 55 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, 56 <&gpio1 0 GPIO_ACTIVE_LOW>; 57 /delete-property/ dmas; 58 /delete-property/ dma-names; 59 status = "okay"; 60 61 /* Resistive touch controller */ 62 touchscreen@0 { 63 reg = <0>; 64 compatible = "ti,ads7846"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pinctrl_restouch>; 67 interrupt-parent = <&gpio1>; 68 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 69 70 spi-max-frequency = <1500000>; 71 pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; 72 73 ti,x-min = /bits/ 16 <125>; 74 touchscreen-size-x = <4008>; 75 ti,y-min = /bits/ 16 <282>; 76 touchscreen-size-y = <3864>; 77 ti,x-plate-ohms = /bits/ 16 <180>; 78 touchscreen-max-pressure = <255>; 79 touchscreen-average-samples = <10>; 80 ti,debounce-tol = /bits/ 16 <3>; 81 ti,debounce-rep = /bits/ 16 <1>; 82 ti,settle-delay-usec = /bits/ 16 <150>; 83 ti,keep-vref-on; 84 wakeup-source; 85 }; 86}; 87 88&fec1 { 89 pinctrl-names = "default", "sleep"; 90 pinctrl-0 = <&pinctrl_fec1>; 91 pinctrl-1 = <&pinctrl_fec1_sleep>; 92 phy-mode = "rgmii"; 93 phy-handle = <ðphy>; 94 phy-supply = <®_eth_phy>; 95 fsl,magic-packet; 96 status = "okay"; 97 98 mdio { 99 #address-cells = <1>; 100 #size-cells = <0>; 101 102 ethphy: ethernet-phy@4 { 103 compatible = "ethernet-phy-ieee802.3-c22"; 104 reg = <4>; 105 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 106 reset-assert-us = <10000>; 107 }; 108 }; 109}; 110 111&i2c1 { 112 clock-frequency = <400000>; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_i2c1>; 115 status = "okay"; 116 117 pmic@4b { 118 compatible = "rohm,bd71847"; 119 reg = <0x4b>; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_pmic>; 122 interrupt-parent = <&gpio2>; 123 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 124 rohm,reset-snvs-powered; 125 126 regulators { 127 buck1_reg: BUCK1 { 128 regulator-name = "buck1"; 129 regulator-min-microvolt = <700000>; 130 regulator-max-microvolt = <1300000>; 131 regulator-boot-on; 132 regulator-always-on; 133 regulator-ramp-delay = <1250>; 134 }; 135 136 buck2_reg: BUCK2 { 137 regulator-name = "buck2"; 138 regulator-min-microvolt = <700000>; 139 regulator-max-microvolt = <1300000>; 140 regulator-boot-on; 141 regulator-always-on; 142 regulator-ramp-delay = <1250>; 143 rohm,dvs-run-voltage = <1000000>; 144 rohm,dvs-idle-voltage = <900000>; 145 }; 146 147 buck3_reg: BUCK3 { 148 regulator-name = "buck3"; 149 regulator-min-microvolt = <700000>; 150 regulator-max-microvolt = <1350000>; 151 regulator-boot-on; 152 regulator-always-on; 153 }; 154 155 buck4_reg: BUCK4 { 156 regulator-name = "buck4"; 157 regulator-min-microvolt = <2600000>; 158 regulator-max-microvolt = <3300000>; 159 regulator-boot-on; 160 regulator-always-on; 161 }; 162 163 buck5_reg: BUCK5 { 164 regulator-name = "buck5"; 165 regulator-min-microvolt = <1605000>; 166 regulator-max-microvolt = <1995000>; 167 regulator-boot-on; 168 regulator-always-on; 169 }; 170 171 buck6_reg: BUCK6 { 172 regulator-name = "buck6"; 173 regulator-min-microvolt = <800000>; 174 regulator-max-microvolt = <1400000>; 175 regulator-boot-on; 176 regulator-always-on; 177 }; 178 179 ldo1_reg: LDO1 { 180 regulator-name = "ldo1"; 181 regulator-min-microvolt = <1600000>; 182 regulator-max-microvolt = <1900000>; 183 regulator-boot-on; 184 regulator-always-on; 185 }; 186 187 ldo2_reg: LDO2 { 188 regulator-name = "ldo2"; 189 regulator-min-microvolt = <800000>; 190 regulator-max-microvolt = <900000>; 191 regulator-boot-on; 192 regulator-always-on; 193 }; 194 195 ldo3_reg: LDO3 { 196 regulator-name = "ldo3"; 197 regulator-min-microvolt = <1800000>; 198 regulator-max-microvolt = <3300000>; 199 regulator-boot-on; 200 regulator-always-on; 201 }; 202 203 ldo4_reg: LDO4 { 204 regulator-name = "ldo4"; 205 regulator-min-microvolt = <900000>; 206 regulator-max-microvolt = <1800000>; 207 regulator-always-on; 208 }; 209 210 ldo5_reg: LDO5 { 211 regulator-name = "ldo5"; 212 regulator-min-microvolt = <1800000>; 213 regulator-max-microvolt = <1800000>; 214 regulator-always-on; 215 }; 216 217 ldo6_reg: LDO6 { 218 regulator-name = "ldo6"; 219 regulator-min-microvolt = <900000>; 220 regulator-max-microvolt = <1800000>; 221 regulator-boot-on; 222 regulator-always-on; 223 }; 224 }; 225 }; 226 227 eeprom_som: eeprom@52 { 228 compatible = "atmel,24c04"; 229 reg = <0x52>; 230 pagesize = <16>; 231 }; 232}; 233 234&i2c3 { 235 clock-frequency = <400000>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_i2c3>; 238 status = "okay"; 239 240 /* TODO: configure audio, as of now just put a placeholder */ 241 wm8904: codec@1a { 242 compatible = "wlf,wm8904"; 243 reg = <0x1a>; 244 status = "disabled"; 245 }; 246}; 247 248&snvs_pwrkey { 249 status = "okay"; 250}; 251 252/* Bluetooth */ 253&uart2 { 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_uart2>; 256 assigned-clocks = <&clk IMX8MN_CLK_UART2>; 257 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; 258 uart-has-rtscts; 259 status = "okay"; 260}; 261 262/* Console */ 263&uart4 { 264 pinctrl-names = "default"; 265 pinctrl-0 = <&pinctrl_uart4>; 266 status = "okay"; 267}; 268 269&usbotg1 { 270 dr_mode = "otg"; 271 usb-role-switch; 272 status = "okay"; 273}; 274 275/* WIFI */ 276&usdhc1 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 280 pinctrl-0 = <&pinctrl_usdhc1>; 281 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 282 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 283 bus-width = <4>; 284 non-removable; 285 keep-power-in-suspend; 286 status = "okay"; 287 288 brcmf: bcrmf@1 { 289 reg = <1>; 290 compatible = "brcm,bcm4329-fmac"; 291 }; 292}; 293 294/* SD */ 295&usdhc2 { 296 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; 297 assigned-clock-rates = <200000000>; 298 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 299 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 300 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 301 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 302 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 303 bus-width = <4>; 304 vmmc-supply = <®_usdhc2_vmmc>; 305 status = "okay"; 306}; 307 308/* eMMC */ 309&usdhc3 { 310 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; 311 assigned-clock-rates = <400000000>; 312 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 313 pinctrl-0 = <&pinctrl_usdhc3>; 314 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 315 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 316 bus-width = <8>; 317 non-removable; 318 status = "okay"; 319}; 320 321&wdog1 { 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_wdog>; 324 fsl,ext-reset-output; 325 status = "okay"; 326}; 327 328&iomuxc { 329 pinctrl_ecspi1: ecspi1grp { 330 fsl,pins = < 331 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 332 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 333 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 334 MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13 335 MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13 336 >; 337 }; 338 339 pinctrl_fec1: fec1grp { 340 fsl,pins = < 341 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 342 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 343 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 344 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 345 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 346 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 347 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 348 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 349 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 350 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 351 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 352 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 353 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 354 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 355 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 356 >; 357 }; 358 359 pinctrl_fec1_sleep: fec1sleepgrp { 360 fsl,pins = < 361 MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120 362 MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120 363 MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120 364 MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120 365 MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120 366 MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120 367 MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120 368 MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120 369 MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120 370 MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120 371 MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120 372 MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120 373 MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120 374 MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120 375 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120 376 >; 377 }; 378 379 pinctrl_i2c1: i2c1grp { 380 fsl,pins = < 381 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 382 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 383 >; 384 }; 385 386 pinctrl_i2c3: i2c3grp { 387 fsl,pins = < 388 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 389 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 390 >; 391 }; 392 393 pinctrl_pmic: pmicirqgrp { 394 fsl,pins = < 395 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 396 >; 397 }; 398 399 pinctrl_reg_eth_phy: regethphygrp { 400 fsl,pins = < 401 MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 402 >; 403 }; 404 405 pinctrl_restouch: restouchgrp { 406 fsl,pins = < 407 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 408 >; 409 }; 410 411 pinctrl_uart2: uart2grp { 412 fsl,pins = < 413 MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 414 MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 415 MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 416 MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 417 >; 418 }; 419 420 pinctrl_uart4: uart4grp { 421 fsl,pins = < 422 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 423 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 424 >; 425 }; 426 427 pinctrl_usdhc1: usdhc1grp { 428 fsl,pins = < 429 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 430 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 431 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 432 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 433 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 434 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 435 >; 436 }; 437 438 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 439 fsl,pins = < 440 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 441 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 442 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 443 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 444 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 445 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 446 >; 447 }; 448 449 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 450 fsl,pins = < 451 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 452 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 453 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 454 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 455 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 456 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 457 >; 458 }; 459 460 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 461 fsl,pins = < 462 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 463 >; 464 }; 465 466 pinctrl_usdhc2: usdhc2grp { 467 fsl,pins = < 468 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 469 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 470 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 471 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 472 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 473 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 474 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 475 >; 476 }; 477 478 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 479 fsl,pins = < 480 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 481 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 482 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 483 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 484 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 485 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 486 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 487 >; 488 }; 489 490 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 491 fsl,pins = < 492 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 493 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 494 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 495 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 496 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 497 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 498 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 499 >; 500 }; 501 502 pinctrl_usdhc3: usdhc3grp { 503 fsl,pins = < 504 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 505 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 506 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 507 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 508 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 509 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 510 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 511 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 512 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 513 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 514 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 515 >; 516 }; 517 518 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 519 fsl,pins = < 520 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 521 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 522 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 523 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 524 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 525 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 526 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 527 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 528 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 529 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 530 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 531 >; 532 }; 533 534 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 535 fsl,pins = < 536 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 537 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 538 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 539 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 540 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 541 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 542 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 543 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 544 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 545 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 546 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 547 >; 548 }; 549 550 pinctrl_wdog: wdoggrp { 551 fsl,pins = < 552 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 553 >; 554 }; 555}; 556