1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 9#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 12#include <dt-bindings/interconnect/qcom,osm-l3.h> 13#include <dt-bindings/interconnect/qcom,sc8280xp.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,gpr.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/sound/qcom,q6afe.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 clocks { 30 xo_board_clk: xo-board-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a78c"; 49 reg = <0x0 0x0>; 50 clocks = <&cpufreq_hw 0>; 51 enable-method = "psci"; 52 capacity-dmips-mhz = <602>; 53 next-level-cache = <&L2_0>; 54 power-domains = <&CPU_PD0>; 55 power-domain-names = "psci"; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 59 #cooling-cells = <2>; 60 L2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 next-level-cache = <&L3_0>; 64 L3_0: l3-cache { 65 compatible = "cache"; 66 cache-level = <3>; 67 }; 68 }; 69 }; 70 71 CPU1: cpu@100 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a78c"; 74 reg = <0x0 0x100>; 75 clocks = <&cpufreq_hw 0>; 76 enable-method = "psci"; 77 capacity-dmips-mhz = <602>; 78 next-level-cache = <&L2_100>; 79 power-domains = <&CPU_PD1>; 80 power-domain-names = "psci"; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 operating-points-v2 = <&cpu0_opp_table>; 83 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 84 #cooling-cells = <2>; 85 L2_100: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 next-level-cache = <&L3_0>; 89 }; 90 }; 91 92 CPU2: cpu@200 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a78c"; 95 reg = <0x0 0x200>; 96 clocks = <&cpufreq_hw 0>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <602>; 99 next-level-cache = <&L2_200>; 100 power-domains = <&CPU_PD2>; 101 power-domain-names = "psci"; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 operating-points-v2 = <&cpu0_opp_table>; 104 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 105 #cooling-cells = <2>; 106 L2_200: l2-cache { 107 compatible = "cache"; 108 cache-level = <2>; 109 next-level-cache = <&L3_0>; 110 }; 111 }; 112 113 CPU3: cpu@300 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a78c"; 116 reg = <0x0 0x300>; 117 clocks = <&cpufreq_hw 0>; 118 enable-method = "psci"; 119 capacity-dmips-mhz = <602>; 120 next-level-cache = <&L2_300>; 121 power-domains = <&CPU_PD3>; 122 power-domain-names = "psci"; 123 qcom,freq-domain = <&cpufreq_hw 0>; 124 operating-points-v2 = <&cpu0_opp_table>; 125 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 126 #cooling-cells = <2>; 127 L2_300: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 next-level-cache = <&L3_0>; 131 }; 132 }; 133 134 CPU4: cpu@400 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-x1c"; 137 reg = <0x0 0x400>; 138 clocks = <&cpufreq_hw 1>; 139 enable-method = "psci"; 140 capacity-dmips-mhz = <1024>; 141 next-level-cache = <&L2_400>; 142 power-domains = <&CPU_PD4>; 143 power-domain-names = "psci"; 144 qcom,freq-domain = <&cpufreq_hw 1>; 145 operating-points-v2 = <&cpu4_opp_table>; 146 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 147 #cooling-cells = <2>; 148 L2_400: l2-cache { 149 compatible = "cache"; 150 cache-level = <2>; 151 next-level-cache = <&L3_0>; 152 }; 153 }; 154 155 CPU5: cpu@500 { 156 device_type = "cpu"; 157 compatible = "arm,cortex-x1c"; 158 reg = <0x0 0x500>; 159 clocks = <&cpufreq_hw 1>; 160 enable-method = "psci"; 161 capacity-dmips-mhz = <1024>; 162 next-level-cache = <&L2_500>; 163 power-domains = <&CPU_PD5>; 164 power-domain-names = "psci"; 165 qcom,freq-domain = <&cpufreq_hw 1>; 166 operating-points-v2 = <&cpu4_opp_table>; 167 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 168 #cooling-cells = <2>; 169 L2_500: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 next-level-cache = <&L3_0>; 173 }; 174 }; 175 176 CPU6: cpu@600 { 177 device_type = "cpu"; 178 compatible = "arm,cortex-x1c"; 179 reg = <0x0 0x600>; 180 clocks = <&cpufreq_hw 1>; 181 enable-method = "psci"; 182 capacity-dmips-mhz = <1024>; 183 next-level-cache = <&L2_600>; 184 power-domains = <&CPU_PD6>; 185 power-domain-names = "psci"; 186 qcom,freq-domain = <&cpufreq_hw 1>; 187 operating-points-v2 = <&cpu4_opp_table>; 188 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 189 #cooling-cells = <2>; 190 L2_600: l2-cache { 191 compatible = "cache"; 192 cache-level = <2>; 193 next-level-cache = <&L3_0>; 194 }; 195 }; 196 197 CPU7: cpu@700 { 198 device_type = "cpu"; 199 compatible = "arm,cortex-x1c"; 200 reg = <0x0 0x700>; 201 clocks = <&cpufreq_hw 1>; 202 enable-method = "psci"; 203 capacity-dmips-mhz = <1024>; 204 next-level-cache = <&L2_700>; 205 power-domains = <&CPU_PD7>; 206 power-domain-names = "psci"; 207 qcom,freq-domain = <&cpufreq_hw 1>; 208 operating-points-v2 = <&cpu4_opp_table>; 209 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 210 #cooling-cells = <2>; 211 L2_700: l2-cache { 212 compatible = "cache"; 213 cache-level = <2>; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 cpu-map { 219 cluster0 { 220 core0 { 221 cpu = <&CPU0>; 222 }; 223 224 core1 { 225 cpu = <&CPU1>; 226 }; 227 228 core2 { 229 cpu = <&CPU2>; 230 }; 231 232 core3 { 233 cpu = <&CPU3>; 234 }; 235 236 core4 { 237 cpu = <&CPU4>; 238 }; 239 240 core5 { 241 cpu = <&CPU5>; 242 }; 243 244 core6 { 245 cpu = <&CPU6>; 246 }; 247 248 core7 { 249 cpu = <&CPU7>; 250 }; 251 }; 252 }; 253 254 idle-states { 255 entry-method = "psci"; 256 257 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "little-rail-power-collapse"; 260 arm,psci-suspend-param = <0x40000004>; 261 entry-latency-us = <355>; 262 exit-latency-us = <909>; 263 min-residency-us = <3934>; 264 local-timer-stop; 265 }; 266 267 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "big-rail-power-collapse"; 270 arm,psci-suspend-param = <0x40000004>; 271 entry-latency-us = <241>; 272 exit-latency-us = <1461>; 273 min-residency-us = <4488>; 274 local-timer-stop; 275 }; 276 }; 277 278 domain-idle-states { 279 CLUSTER_SLEEP_0: cluster-sleep-0 { 280 compatible = "domain-idle-state"; 281 arm,psci-suspend-param = <0x4100c344>; 282 entry-latency-us = <3263>; 283 exit-latency-us = <6562>; 284 min-residency-us = <9987>; 285 }; 286 }; 287 }; 288 289 firmware { 290 scm: scm { 291 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 292 }; 293 }; 294 295 aggre1_noc: interconnect-aggre1-noc { 296 compatible = "qcom,sc8280xp-aggre1-noc"; 297 #interconnect-cells = <2>; 298 qcom,bcm-voters = <&apps_bcm_voter>; 299 }; 300 301 aggre2_noc: interconnect-aggre2-noc { 302 compatible = "qcom,sc8280xp-aggre2-noc"; 303 #interconnect-cells = <2>; 304 qcom,bcm-voters = <&apps_bcm_voter>; 305 }; 306 307 clk_virt: interconnect-clk-virt { 308 compatible = "qcom,sc8280xp-clk-virt"; 309 #interconnect-cells = <2>; 310 qcom,bcm-voters = <&apps_bcm_voter>; 311 }; 312 313 config_noc: interconnect-config-noc { 314 compatible = "qcom,sc8280xp-config-noc"; 315 #interconnect-cells = <2>; 316 qcom,bcm-voters = <&apps_bcm_voter>; 317 }; 318 319 dc_noc: interconnect-dc-noc { 320 compatible = "qcom,sc8280xp-dc-noc"; 321 #interconnect-cells = <2>; 322 qcom,bcm-voters = <&apps_bcm_voter>; 323 }; 324 325 gem_noc: interconnect-gem-noc { 326 compatible = "qcom,sc8280xp-gem-noc"; 327 #interconnect-cells = <2>; 328 qcom,bcm-voters = <&apps_bcm_voter>; 329 }; 330 331 lpass_noc: interconnect-lpass-ag-noc { 332 compatible = "qcom,sc8280xp-lpass-ag-noc"; 333 #interconnect-cells = <2>; 334 qcom,bcm-voters = <&apps_bcm_voter>; 335 }; 336 337 mc_virt: interconnect-mc-virt { 338 compatible = "qcom,sc8280xp-mc-virt"; 339 #interconnect-cells = <2>; 340 qcom,bcm-voters = <&apps_bcm_voter>; 341 }; 342 343 mmss_noc: interconnect-mmss-noc { 344 compatible = "qcom,sc8280xp-mmss-noc"; 345 #interconnect-cells = <2>; 346 qcom,bcm-voters = <&apps_bcm_voter>; 347 }; 348 349 nspa_noc: interconnect-nspa-noc { 350 compatible = "qcom,sc8280xp-nspa-noc"; 351 #interconnect-cells = <2>; 352 qcom,bcm-voters = <&apps_bcm_voter>; 353 }; 354 355 nspb_noc: interconnect-nspb-noc { 356 compatible = "qcom,sc8280xp-nspb-noc"; 357 #interconnect-cells = <2>; 358 qcom,bcm-voters = <&apps_bcm_voter>; 359 }; 360 361 system_noc: interconnect-system-noc { 362 compatible = "qcom,sc8280xp-system-noc"; 363 #interconnect-cells = <2>; 364 qcom,bcm-voters = <&apps_bcm_voter>; 365 }; 366 367 memory@80000000 { 368 device_type = "memory"; 369 /* We expect the bootloader to fill in the size */ 370 reg = <0x0 0x80000000 0x0 0x0>; 371 }; 372 373 cpu0_opp_table: opp-table-cpu0 { 374 compatible = "operating-points-v2"; 375 opp-shared; 376 377 opp-300000000 { 378 opp-hz = /bits/ 64 <300000000>; 379 opp-peak-kBps = <(300000 * 32)>; 380 }; 381 opp-403200000 { 382 opp-hz = /bits/ 64 <403200000>; 383 opp-peak-kBps = <(384000 * 32)>; 384 }; 385 opp-499200000 { 386 opp-hz = /bits/ 64 <499200000>; 387 opp-peak-kBps = <(480000 * 32)>; 388 }; 389 opp-595200000 { 390 opp-hz = /bits/ 64 <595200000>; 391 opp-peak-kBps = <(576000 * 32)>; 392 }; 393 opp-691200000 { 394 opp-hz = /bits/ 64 <691200000>; 395 opp-peak-kBps = <(672000 * 32)>; 396 }; 397 opp-806400000 { 398 opp-hz = /bits/ 64 <806400000>; 399 opp-peak-kBps = <(768000 * 32)>; 400 }; 401 opp-902400000 { 402 opp-hz = /bits/ 64 <902400000>; 403 opp-peak-kBps = <(864000 * 32)>; 404 }; 405 opp-1017600000 { 406 opp-hz = /bits/ 64 <1017600000>; 407 opp-peak-kBps = <(960000 * 32)>; 408 }; 409 opp-1113600000 { 410 opp-hz = /bits/ 64 <1113600000>; 411 opp-peak-kBps = <(1075200 * 32)>; 412 }; 413 opp-1209600000 { 414 opp-hz = /bits/ 64 <1209600000>; 415 opp-peak-kBps = <(1171200 * 32)>; 416 }; 417 opp-1324800000 { 418 opp-hz = /bits/ 64 <1324800000>; 419 opp-peak-kBps = <(1267200 * 32)>; 420 }; 421 opp-1440000000 { 422 opp-hz = /bits/ 64 <1440000000>; 423 opp-peak-kBps = <(1363200 * 32)>; 424 }; 425 opp-1555200000 { 426 opp-hz = /bits/ 64 <1555200000>; 427 opp-peak-kBps = <(1536000 * 32)>; 428 }; 429 opp-1670400000 { 430 opp-hz = /bits/ 64 <1670400000>; 431 opp-peak-kBps = <(1612800 * 32)>; 432 }; 433 opp-1785600000 { 434 opp-hz = /bits/ 64 <1785600000>; 435 opp-peak-kBps = <(1689600 * 32)>; 436 }; 437 opp-1881600000 { 438 opp-hz = /bits/ 64 <1881600000>; 439 opp-peak-kBps = <(1689600 * 32)>; 440 }; 441 opp-1996800000 { 442 opp-hz = /bits/ 64 <1996800000>; 443 opp-peak-kBps = <(1689600 * 32)>; 444 }; 445 opp-2112000000 { 446 opp-hz = /bits/ 64 <2112000000>; 447 opp-peak-kBps = <(1689600 * 32)>; 448 }; 449 opp-2227200000 { 450 opp-hz = /bits/ 64 <2227200000>; 451 opp-peak-kBps = <(1689600 * 32)>; 452 }; 453 opp-2342400000 { 454 opp-hz = /bits/ 64 <2342400000>; 455 opp-peak-kBps = <(1689600 * 32)>; 456 }; 457 opp-2438400000 { 458 opp-hz = /bits/ 64 <2438400000>; 459 opp-peak-kBps = <(1689600 * 32)>; 460 }; 461 }; 462 463 cpu4_opp_table: opp-table-cpu4 { 464 compatible = "operating-points-v2"; 465 opp-shared; 466 467 opp-825600000 { 468 opp-hz = /bits/ 64 <825600000>; 469 opp-peak-kBps = <(768000 * 32)>; 470 }; 471 opp-940800000 { 472 opp-hz = /bits/ 64 <940800000>; 473 opp-peak-kBps = <(864000 * 32)>; 474 }; 475 opp-1056000000 { 476 opp-hz = /bits/ 64 <1056000000>; 477 opp-peak-kBps = <(960000 * 32)>; 478 }; 479 opp-1171200000 { 480 opp-hz = /bits/ 64 <1171200000>; 481 opp-peak-kBps = <(1171200 * 32)>; 482 }; 483 opp-1286400000 { 484 opp-hz = /bits/ 64 <1286400000>; 485 opp-peak-kBps = <(1267200 * 32)>; 486 }; 487 opp-1401600000 { 488 opp-hz = /bits/ 64 <1401600000>; 489 opp-peak-kBps = <(1363200 * 32)>; 490 }; 491 opp-1516800000 { 492 opp-hz = /bits/ 64 <1516800000>; 493 opp-peak-kBps = <(1459200 * 32)>; 494 }; 495 opp-1632000000 { 496 opp-hz = /bits/ 64 <1632000000>; 497 opp-peak-kBps = <(1612800 * 32)>; 498 }; 499 opp-1747200000 { 500 opp-hz = /bits/ 64 <1747200000>; 501 opp-peak-kBps = <(1689600 * 32)>; 502 }; 503 opp-1862400000 { 504 opp-hz = /bits/ 64 <1862400000>; 505 opp-peak-kBps = <(1689600 * 32)>; 506 }; 507 opp-1977600000 { 508 opp-hz = /bits/ 64 <1977600000>; 509 opp-peak-kBps = <(1689600 * 32)>; 510 }; 511 opp-2073600000 { 512 opp-hz = /bits/ 64 <2073600000>; 513 opp-peak-kBps = <(1689600 * 32)>; 514 }; 515 opp-2169600000 { 516 opp-hz = /bits/ 64 <2169600000>; 517 opp-peak-kBps = <(1689600 * 32)>; 518 }; 519 opp-2284800000 { 520 opp-hz = /bits/ 64 <2284800000>; 521 opp-peak-kBps = <(1689600 * 32)>; 522 }; 523 opp-2400000000 { 524 opp-hz = /bits/ 64 <2400000000>; 525 opp-peak-kBps = <(1689600 * 32)>; 526 }; 527 opp-2496000000 { 528 opp-hz = /bits/ 64 <2496000000>; 529 opp-peak-kBps = <(1689600 * 32)>; 530 }; 531 opp-2592000000 { 532 opp-hz = /bits/ 64 <2592000000>; 533 opp-peak-kBps = <(1689600 * 32)>; 534 }; 535 opp-2688000000 { 536 opp-hz = /bits/ 64 <2688000000>; 537 opp-peak-kBps = <(1689600 * 32)>; 538 }; 539 opp-2803200000 { 540 opp-hz = /bits/ 64 <2803200000>; 541 opp-peak-kBps = <(1689600 * 32)>; 542 }; 543 opp-2899200000 { 544 opp-hz = /bits/ 64 <2899200000>; 545 opp-peak-kBps = <(1689600 * 32)>; 546 }; 547 opp-2995200000 { 548 opp-hz = /bits/ 64 <2995200000>; 549 opp-peak-kBps = <(1689600 * 32)>; 550 }; 551 }; 552 553 qup_opp_table_100mhz: opp-table-qup100mhz { 554 compatible = "operating-points-v2"; 555 556 opp-75000000 { 557 opp-hz = /bits/ 64 <75000000>; 558 required-opps = <&rpmhpd_opp_low_svs>; 559 }; 560 561 opp-100000000 { 562 opp-hz = /bits/ 64 <100000000>; 563 required-opps = <&rpmhpd_opp_svs>; 564 }; 565 }; 566 567 pmu { 568 compatible = "arm,armv8-pmuv3"; 569 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 570 }; 571 572 psci { 573 compatible = "arm,psci-1.0"; 574 method = "smc"; 575 576 CPU_PD0: power-domain-cpu0 { 577 #power-domain-cells = <0>; 578 power-domains = <&CLUSTER_PD>; 579 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 580 }; 581 582 CPU_PD1: power-domain-cpu1 { 583 #power-domain-cells = <0>; 584 power-domains = <&CLUSTER_PD>; 585 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 586 }; 587 588 CPU_PD2: power-domain-cpu2 { 589 #power-domain-cells = <0>; 590 power-domains = <&CLUSTER_PD>; 591 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 592 }; 593 594 CPU_PD3: power-domain-cpu3 { 595 #power-domain-cells = <0>; 596 power-domains = <&CLUSTER_PD>; 597 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 598 }; 599 600 CPU_PD4: power-domain-cpu4 { 601 #power-domain-cells = <0>; 602 power-domains = <&CLUSTER_PD>; 603 domain-idle-states = <&BIG_CPU_SLEEP_0>; 604 }; 605 606 CPU_PD5: power-domain-cpu5 { 607 #power-domain-cells = <0>; 608 power-domains = <&CLUSTER_PD>; 609 domain-idle-states = <&BIG_CPU_SLEEP_0>; 610 }; 611 612 CPU_PD6: power-domain-cpu6 { 613 #power-domain-cells = <0>; 614 power-domains = <&CLUSTER_PD>; 615 domain-idle-states = <&BIG_CPU_SLEEP_0>; 616 }; 617 618 CPU_PD7: power-domain-cpu7 { 619 #power-domain-cells = <0>; 620 power-domains = <&CLUSTER_PD>; 621 domain-idle-states = <&BIG_CPU_SLEEP_0>; 622 }; 623 624 CLUSTER_PD: power-domain-cpu-cluster0 { 625 #power-domain-cells = <0>; 626 domain-idle-states = <&CLUSTER_SLEEP_0>; 627 }; 628 }; 629 630 reserved-memory { 631 #address-cells = <2>; 632 #size-cells = <2>; 633 ranges; 634 635 reserved-region@80000000 { 636 reg = <0 0x80000000 0 0x860000>; 637 no-map; 638 }; 639 640 cmd_db: cmd-db-region@80860000 { 641 compatible = "qcom,cmd-db"; 642 reg = <0 0x80860000 0 0x20000>; 643 no-map; 644 }; 645 646 reserved-region@80880000 { 647 reg = <0 0x80880000 0 0x80000>; 648 no-map; 649 }; 650 651 smem_mem: smem-region@80900000 { 652 compatible = "qcom,smem"; 653 reg = <0 0x80900000 0 0x200000>; 654 no-map; 655 hwlocks = <&tcsr_mutex 3>; 656 }; 657 658 reserved-region@80b00000 { 659 reg = <0 0x80b00000 0 0x100000>; 660 no-map; 661 }; 662 663 reserved-region@83b00000 { 664 reg = <0 0x83b00000 0 0x1700000>; 665 no-map; 666 }; 667 668 reserved-region@85b00000 { 669 reg = <0 0x85b00000 0 0xc00000>; 670 no-map; 671 }; 672 673 pil_adsp_mem: adsp-region@86c00000 { 674 reg = <0 0x86c00000 0 0x2000000>; 675 no-map; 676 }; 677 678 pil_nsp0_mem: cdsp0-region@8a100000 { 679 reg = <0 0x8a100000 0 0x1e00000>; 680 no-map; 681 }; 682 683 pil_nsp1_mem: cdsp1-region@8c600000 { 684 reg = <0 0x8c600000 0 0x1e00000>; 685 no-map; 686 }; 687 688 reserved-region@aeb00000 { 689 reg = <0 0xaeb00000 0 0x16600000>; 690 no-map; 691 }; 692 }; 693 694 smp2p-adsp { 695 compatible = "qcom,smp2p"; 696 qcom,smem = <443>, <429>; 697 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 698 IPCC_MPROC_SIGNAL_SMP2P 699 IRQ_TYPE_EDGE_RISING>; 700 mboxes = <&ipcc IPCC_CLIENT_LPASS 701 IPCC_MPROC_SIGNAL_SMP2P>; 702 703 qcom,local-pid = <0>; 704 qcom,remote-pid = <2>; 705 706 smp2p_adsp_out: master-kernel { 707 qcom,entry-name = "master-kernel"; 708 #qcom,smem-state-cells = <1>; 709 }; 710 711 smp2p_adsp_in: slave-kernel { 712 qcom,entry-name = "slave-kernel"; 713 interrupt-controller; 714 #interrupt-cells = <2>; 715 }; 716 }; 717 718 smp2p-nsp0 { 719 compatible = "qcom,smp2p"; 720 qcom,smem = <94>, <432>; 721 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 722 IPCC_MPROC_SIGNAL_SMP2P 723 IRQ_TYPE_EDGE_RISING>; 724 mboxes = <&ipcc IPCC_CLIENT_CDSP 725 IPCC_MPROC_SIGNAL_SMP2P>; 726 727 qcom,local-pid = <0>; 728 qcom,remote-pid = <5>; 729 730 smp2p_nsp0_out: master-kernel { 731 qcom,entry-name = "master-kernel"; 732 #qcom,smem-state-cells = <1>; 733 }; 734 735 smp2p_nsp0_in: slave-kernel { 736 qcom,entry-name = "slave-kernel"; 737 interrupt-controller; 738 #interrupt-cells = <2>; 739 }; 740 }; 741 742 smp2p-nsp1 { 743 compatible = "qcom,smp2p"; 744 qcom,smem = <617>, <616>; 745 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 746 IPCC_MPROC_SIGNAL_SMP2P 747 IRQ_TYPE_EDGE_RISING>; 748 mboxes = <&ipcc IPCC_CLIENT_NSP1 749 IPCC_MPROC_SIGNAL_SMP2P>; 750 751 qcom,local-pid = <0>; 752 qcom,remote-pid = <12>; 753 754 smp2p_nsp1_out: master-kernel { 755 qcom,entry-name = "master-kernel"; 756 #qcom,smem-state-cells = <1>; 757 }; 758 759 smp2p_nsp1_in: slave-kernel { 760 qcom,entry-name = "slave-kernel"; 761 interrupt-controller; 762 #interrupt-cells = <2>; 763 }; 764 }; 765 766 soc: soc@0 { 767 compatible = "simple-bus"; 768 #address-cells = <2>; 769 #size-cells = <2>; 770 ranges = <0 0 0 0 0x10 0>; 771 dma-ranges = <0 0 0 0 0x10 0>; 772 773 ethernet0: ethernet@20000 { 774 compatible = "qcom,sc8280xp-ethqos"; 775 reg = <0x0 0x00020000 0x0 0x10000>, 776 <0x0 0x00036000 0x0 0x100>; 777 reg-names = "stmmaceth", "rgmii"; 778 779 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 780 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 781 <&gcc GCC_EMAC0_PTP_CLK>, 782 <&gcc GCC_EMAC0_RGMII_CLK>; 783 clock-names = "stmmaceth", 784 "pclk", 785 "ptp_ref", 786 "rgmii"; 787 788 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; 790 interrupt-names = "macirq", "eth_lpi"; 791 792 iommus = <&apps_smmu 0x4c0 0xf>; 793 power-domains = <&gcc EMAC_0_GDSC>; 794 795 snps,tso; 796 snps,pbl = <32>; 797 rx-fifo-depth = <4096>; 798 tx-fifo-depth = <4096>; 799 800 status = "disabled"; 801 }; 802 803 gcc: clock-controller@100000 { 804 compatible = "qcom,gcc-sc8280xp"; 805 reg = <0x0 0x00100000 0x0 0x1f0000>; 806 #clock-cells = <1>; 807 #reset-cells = <1>; 808 #power-domain-cells = <1>; 809 clocks = <&rpmhcc RPMH_CXO_CLK>, 810 <&sleep_clk>, 811 <0>, 812 <0>, 813 <0>, 814 <0>, 815 <0>, 816 <0>, 817 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 818 <0>, 819 <0>, 820 <0>, 821 <0>, 822 <0>, 823 <0>, 824 <0>, 825 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 826 <0>, 827 <0>, 828 <0>, 829 <0>, 830 <0>, 831 <0>, 832 <0>, 833 <0>, 834 <0>, 835 <&pcie2a_phy>, 836 <&pcie2b_phy>, 837 <&pcie3a_phy>, 838 <&pcie3b_phy>, 839 <&pcie4_phy>, 840 <0>, 841 <0>; 842 power-domains = <&rpmhpd SC8280XP_CX>; 843 }; 844 845 ipcc: mailbox@408000 { 846 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 847 reg = <0 0x00408000 0 0x1000>; 848 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 849 interrupt-controller; 850 #interrupt-cells = <3>; 851 #mbox-cells = <2>; 852 }; 853 854 qup2: geniqup@8c0000 { 855 compatible = "qcom,geni-se-qup"; 856 reg = <0 0x008c0000 0 0x2000>; 857 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 858 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 859 clock-names = "m-ahb", "s-ahb"; 860 iommus = <&apps_smmu 0xa3 0>; 861 862 #address-cells = <2>; 863 #size-cells = <2>; 864 ranges; 865 866 status = "disabled"; 867 868 i2c16: i2c@880000 { 869 compatible = "qcom,geni-i2c"; 870 reg = <0 0x00880000 0 0x4000>; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 874 clock-names = "se"; 875 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 876 power-domains = <&rpmhpd SC8280XP_CX>; 877 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 878 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 879 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 880 interconnect-names = "qup-core", "qup-config", "qup-memory"; 881 status = "disabled"; 882 }; 883 884 spi16: spi@880000 { 885 compatible = "qcom,geni-spi"; 886 reg = <0 0x00880000 0 0x4000>; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 890 clock-names = "se"; 891 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 892 power-domains = <&rpmhpd SC8280XP_CX>; 893 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 894 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 895 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 896 interconnect-names = "qup-core", "qup-config", "qup-memory"; 897 status = "disabled"; 898 }; 899 900 i2c17: i2c@884000 { 901 compatible = "qcom,geni-i2c"; 902 reg = <0 0x00884000 0 0x4000>; 903 #address-cells = <1>; 904 #size-cells = <0>; 905 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 906 clock-names = "se"; 907 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 908 power-domains = <&rpmhpd SC8280XP_CX>; 909 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 910 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 911 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 912 interconnect-names = "qup-core", "qup-config", "qup-memory"; 913 status = "disabled"; 914 }; 915 916 spi17: spi@884000 { 917 compatible = "qcom,geni-spi"; 918 reg = <0 0x00884000 0 0x4000>; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 922 clock-names = "se"; 923 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 924 power-domains = <&rpmhpd SC8280XP_CX>; 925 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 926 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 927 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 928 interconnect-names = "qup-core", "qup-config", "qup-memory"; 929 status = "disabled"; 930 }; 931 932 uart17: serial@884000 { 933 compatible = "qcom,geni-uart"; 934 reg = <0 0x00884000 0 0x4000>; 935 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 936 clock-names = "se"; 937 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 938 operating-points-v2 = <&qup_opp_table_100mhz>; 939 power-domains = <&rpmhpd SC8280XP_CX>; 940 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 941 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 942 interconnect-names = "qup-core", "qup-config"; 943 status = "disabled"; 944 }; 945 946 i2c18: i2c@888000 { 947 compatible = "qcom,geni-i2c"; 948 reg = <0 0x00888000 0 0x4000>; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 952 clock-names = "se"; 953 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 954 power-domains = <&rpmhpd SC8280XP_CX>; 955 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 956 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 957 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 958 interconnect-names = "qup-core", "qup-config", "qup-memory"; 959 status = "disabled"; 960 }; 961 962 spi18: spi@888000 { 963 compatible = "qcom,geni-spi"; 964 reg = <0 0x00888000 0 0x4000>; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 968 clock-names = "se"; 969 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 970 power-domains = <&rpmhpd SC8280XP_CX>; 971 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 972 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 973 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 974 interconnect-names = "qup-core", "qup-config", "qup-memory"; 975 status = "disabled"; 976 }; 977 978 i2c19: i2c@88c000 { 979 compatible = "qcom,geni-i2c"; 980 reg = <0 0x0088c000 0 0x4000>; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 984 clock-names = "se"; 985 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 986 power-domains = <&rpmhpd SC8280XP_CX>; 987 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 989 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 990 interconnect-names = "qup-core", "qup-config", "qup-memory"; 991 status = "disabled"; 992 }; 993 994 spi19: spi@88c000 { 995 compatible = "qcom,geni-spi"; 996 reg = <0 0x0088c000 0 0x4000>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1000 clock-names = "se"; 1001 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1002 power-domains = <&rpmhpd SC8280XP_CX>; 1003 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1004 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1005 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1006 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1007 status = "disabled"; 1008 }; 1009 1010 i2c20: i2c@890000 { 1011 compatible = "qcom,geni-i2c"; 1012 reg = <0 0x00890000 0 0x4000>; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1016 clock-names = "se"; 1017 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1018 power-domains = <&rpmhpd SC8280XP_CX>; 1019 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1020 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1021 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1022 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1023 status = "disabled"; 1024 }; 1025 1026 spi20: spi@890000 { 1027 compatible = "qcom,geni-spi"; 1028 reg = <0 0x00890000 0 0x4000>; 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1032 clock-names = "se"; 1033 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1034 power-domains = <&rpmhpd SC8280XP_CX>; 1035 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1036 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1037 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1038 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1039 status = "disabled"; 1040 }; 1041 1042 i2c21: i2c@894000 { 1043 compatible = "qcom,geni-i2c"; 1044 reg = <0 0x00894000 0 0x4000>; 1045 clock-names = "se"; 1046 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1047 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 power-domains = <&rpmhpd SC8280XP_CX>; 1051 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1052 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1053 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1054 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1055 status = "disabled"; 1056 }; 1057 1058 spi21: spi@894000 { 1059 compatible = "qcom,geni-spi"; 1060 reg = <0 0x00894000 0 0x4000>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1064 clock-names = "se"; 1065 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1066 power-domains = <&rpmhpd SC8280XP_CX>; 1067 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1068 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1069 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1070 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1071 status = "disabled"; 1072 }; 1073 1074 i2c22: i2c@898000 { 1075 compatible = "qcom,geni-i2c"; 1076 reg = <0 0x00898000 0 0x4000>; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 clock-names = "se"; 1080 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1081 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1082 power-domains = <&rpmhpd SC8280XP_CX>; 1083 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1084 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1085 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1086 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1087 status = "disabled"; 1088 }; 1089 1090 spi22: spi@898000 { 1091 compatible = "qcom,geni-spi"; 1092 reg = <0 0x00898000 0 0x4000>; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1096 clock-names = "se"; 1097 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1098 power-domains = <&rpmhpd SC8280XP_CX>; 1099 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1100 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1101 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1102 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1103 status = "disabled"; 1104 }; 1105 1106 i2c23: i2c@89c000 { 1107 compatible = "qcom,geni-i2c"; 1108 reg = <0 0x0089c000 0 0x4000>; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 clock-names = "se"; 1112 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1113 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1114 power-domains = <&rpmhpd SC8280XP_CX>; 1115 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1116 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1117 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1118 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1119 status = "disabled"; 1120 }; 1121 1122 spi23: spi@89c000 { 1123 compatible = "qcom,geni-spi"; 1124 reg = <0 0x0089c000 0 0x4000>; 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1128 clock-names = "se"; 1129 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1130 power-domains = <&rpmhpd SC8280XP_CX>; 1131 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1132 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1133 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1134 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1135 status = "disabled"; 1136 }; 1137 }; 1138 1139 qup0: geniqup@9c0000 { 1140 compatible = "qcom,geni-se-qup"; 1141 reg = <0 0x009c0000 0 0x6000>; 1142 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1143 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1144 clock-names = "m-ahb", "s-ahb"; 1145 iommus = <&apps_smmu 0x563 0>; 1146 1147 #address-cells = <2>; 1148 #size-cells = <2>; 1149 ranges; 1150 1151 status = "disabled"; 1152 1153 i2c0: i2c@980000 { 1154 compatible = "qcom,geni-i2c"; 1155 reg = <0 0x00980000 0 0x4000>; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 clock-names = "se"; 1159 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1160 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1161 power-domains = <&rpmhpd SC8280XP_CX>; 1162 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1163 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1164 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1165 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1166 status = "disabled"; 1167 }; 1168 1169 spi0: spi@980000 { 1170 compatible = "qcom,geni-spi"; 1171 reg = <0 0x00980000 0 0x4000>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1175 clock-names = "se"; 1176 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1177 power-domains = <&rpmhpd SC8280XP_CX>; 1178 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1179 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1180 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1181 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1182 status = "disabled"; 1183 }; 1184 1185 i2c1: i2c@984000 { 1186 compatible = "qcom,geni-i2c"; 1187 reg = <0 0x00984000 0 0x4000>; 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1192 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1193 power-domains = <&rpmhpd SC8280XP_CX>; 1194 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1195 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1196 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1197 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1198 status = "disabled"; 1199 }; 1200 1201 spi1: spi@984000 { 1202 compatible = "qcom,geni-spi"; 1203 reg = <0 0x00984000 0 0x4000>; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1207 clock-names = "se"; 1208 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1209 power-domains = <&rpmhpd SC8280XP_CX>; 1210 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1211 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1212 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1213 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1214 status = "disabled"; 1215 }; 1216 1217 i2c2: i2c@988000 { 1218 compatible = "qcom,geni-i2c"; 1219 reg = <0 0x00988000 0 0x4000>; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 clock-names = "se"; 1223 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1224 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1225 power-domains = <&rpmhpd SC8280XP_CX>; 1226 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1227 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1228 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1229 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1230 status = "disabled"; 1231 }; 1232 1233 spi2: spi@988000 { 1234 compatible = "qcom,geni-spi"; 1235 reg = <0 0x00988000 0 0x4000>; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1239 clock-names = "se"; 1240 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1241 power-domains = <&rpmhpd SC8280XP_CX>; 1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1243 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1244 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1245 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1246 status = "disabled"; 1247 }; 1248 1249 uart2: serial@988000 { 1250 compatible = "qcom,geni-uart"; 1251 reg = <0 0x00988000 0 0x4000>; 1252 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1253 clock-names = "se"; 1254 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1255 operating-points-v2 = <&qup_opp_table_100mhz>; 1256 power-domains = <&rpmhpd SC8280XP_CX>; 1257 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1258 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1259 interconnect-names = "qup-core", "qup-config"; 1260 status = "disabled"; 1261 }; 1262 1263 i2c3: i2c@98c000 { 1264 compatible = "qcom,geni-i2c"; 1265 reg = <0 0x0098c000 0 0x4000>; 1266 #address-cells = <1>; 1267 #size-cells = <0>; 1268 clock-names = "se"; 1269 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1270 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1271 power-domains = <&rpmhpd SC8280XP_CX>; 1272 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1273 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1274 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1275 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1276 status = "disabled"; 1277 }; 1278 1279 spi3: spi@98c000 { 1280 compatible = "qcom,geni-spi"; 1281 reg = <0 0x0098c000 0 0x4000>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1285 clock-names = "se"; 1286 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1287 power-domains = <&rpmhpd SC8280XP_CX>; 1288 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1289 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1290 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1291 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1292 status = "disabled"; 1293 }; 1294 1295 i2c4: i2c@990000 { 1296 compatible = "qcom,geni-i2c"; 1297 reg = <0 0x00990000 0 0x4000>; 1298 clock-names = "se"; 1299 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1300 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 power-domains = <&rpmhpd SC8280XP_CX>; 1304 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1305 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1306 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1307 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1308 status = "disabled"; 1309 }; 1310 1311 spi4: spi@990000 { 1312 compatible = "qcom,geni-spi"; 1313 reg = <0 0x00990000 0 0x4000>; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1317 clock-names = "se"; 1318 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1319 power-domains = <&rpmhpd SC8280XP_CX>; 1320 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1321 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1322 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1323 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1324 status = "disabled"; 1325 }; 1326 1327 i2c5: i2c@994000 { 1328 compatible = "qcom,geni-i2c"; 1329 reg = <0 0x00994000 0 0x4000>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 clock-names = "se"; 1333 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1334 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1335 power-domains = <&rpmhpd SC8280XP_CX>; 1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1337 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1338 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1339 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1340 status = "disabled"; 1341 }; 1342 1343 spi5: spi@994000 { 1344 compatible = "qcom,geni-spi"; 1345 reg = <0 0x00994000 0 0x4000>; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1349 clock-names = "se"; 1350 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1351 power-domains = <&rpmhpd SC8280XP_CX>; 1352 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1353 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1354 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1355 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1356 status = "disabled"; 1357 }; 1358 1359 i2c6: i2c@998000 { 1360 compatible = "qcom,geni-i2c"; 1361 reg = <0 0x00998000 0 0x4000>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 clock-names = "se"; 1365 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1366 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1367 power-domains = <&rpmhpd SC8280XP_CX>; 1368 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1369 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1370 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1371 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1372 status = "disabled"; 1373 }; 1374 1375 spi6: spi@998000 { 1376 compatible = "qcom,geni-spi"; 1377 reg = <0 0x00998000 0 0x4000>; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1381 clock-names = "se"; 1382 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1383 power-domains = <&rpmhpd SC8280XP_CX>; 1384 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1385 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1386 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1387 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1388 status = "disabled"; 1389 }; 1390 1391 i2c7: i2c@99c000 { 1392 compatible = "qcom,geni-i2c"; 1393 reg = <0 0x0099c000 0 0x4000>; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 clock-names = "se"; 1397 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1398 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1399 power-domains = <&rpmhpd SC8280XP_CX>; 1400 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1401 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1402 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1403 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1404 status = "disabled"; 1405 }; 1406 1407 spi7: spi@99c000 { 1408 compatible = "qcom,geni-spi"; 1409 reg = <0 0x0099c000 0 0x4000>; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1413 clock-names = "se"; 1414 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1415 power-domains = <&rpmhpd SC8280XP_CX>; 1416 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1417 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1418 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1419 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1420 status = "disabled"; 1421 }; 1422 }; 1423 1424 qup1: geniqup@ac0000 { 1425 compatible = "qcom,geni-se-qup"; 1426 reg = <0 0x00ac0000 0 0x6000>; 1427 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1428 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1429 clock-names = "m-ahb", "s-ahb"; 1430 iommus = <&apps_smmu 0x83 0>; 1431 1432 #address-cells = <2>; 1433 #size-cells = <2>; 1434 ranges; 1435 1436 status = "disabled"; 1437 1438 i2c8: i2c@a80000 { 1439 compatible = "qcom,geni-i2c"; 1440 reg = <0 0x00a80000 0 0x4000>; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1444 clock-names = "se"; 1445 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1446 power-domains = <&rpmhpd SC8280XP_CX>; 1447 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1448 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1449 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1450 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1451 status = "disabled"; 1452 }; 1453 1454 spi8: spi@a80000 { 1455 compatible = "qcom,geni-spi"; 1456 reg = <0 0x00a80000 0 0x4000>; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1460 clock-names = "se"; 1461 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1462 power-domains = <&rpmhpd SC8280XP_CX>; 1463 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1464 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1465 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1466 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1467 status = "disabled"; 1468 }; 1469 1470 i2c9: i2c@a84000 { 1471 compatible = "qcom,geni-i2c"; 1472 reg = <0 0x00a84000 0 0x4000>; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1476 clock-names = "se"; 1477 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1478 power-domains = <&rpmhpd SC8280XP_CX>; 1479 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1480 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1481 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1482 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1483 status = "disabled"; 1484 }; 1485 1486 spi9: spi@a84000 { 1487 compatible = "qcom,geni-spi"; 1488 reg = <0 0x00a84000 0 0x4000>; 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1492 clock-names = "se"; 1493 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1494 power-domains = <&rpmhpd SC8280XP_CX>; 1495 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1496 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1497 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1498 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1499 status = "disabled"; 1500 }; 1501 1502 i2c10: i2c@a88000 { 1503 compatible = "qcom,geni-i2c"; 1504 reg = <0 0x00a88000 0 0x4000>; 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1508 clock-names = "se"; 1509 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1510 power-domains = <&rpmhpd SC8280XP_CX>; 1511 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1512 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1513 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1514 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1515 status = "disabled"; 1516 }; 1517 1518 spi10: spi@a88000 { 1519 compatible = "qcom,geni-spi"; 1520 reg = <0 0x00a88000 0 0x4000>; 1521 #address-cells = <1>; 1522 #size-cells = <0>; 1523 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1524 clock-names = "se"; 1525 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1526 power-domains = <&rpmhpd SC8280XP_CX>; 1527 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1528 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1529 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1530 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1531 status = "disabled"; 1532 }; 1533 1534 i2c11: i2c@a8c000 { 1535 compatible = "qcom,geni-i2c"; 1536 reg = <0 0x00a8c000 0 0x4000>; 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1540 clock-names = "se"; 1541 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1542 power-domains = <&rpmhpd SC8280XP_CX>; 1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1544 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1545 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1546 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1547 status = "disabled"; 1548 }; 1549 1550 spi11: spi@a8c000 { 1551 compatible = "qcom,geni-spi"; 1552 reg = <0 0x00a8c000 0 0x4000>; 1553 #address-cells = <1>; 1554 #size-cells = <0>; 1555 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1556 clock-names = "se"; 1557 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1558 power-domains = <&rpmhpd SC8280XP_CX>; 1559 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1560 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1561 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1562 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1563 status = "disabled"; 1564 }; 1565 1566 i2c12: i2c@a90000 { 1567 compatible = "qcom,geni-i2c"; 1568 reg = <0 0x00a90000 0 0x4000>; 1569 #address-cells = <1>; 1570 #size-cells = <0>; 1571 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1572 clock-names = "se"; 1573 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1574 power-domains = <&rpmhpd SC8280XP_CX>; 1575 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1576 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1577 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1578 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1579 status = "disabled"; 1580 }; 1581 1582 spi12: spi@a90000 { 1583 compatible = "qcom,geni-spi"; 1584 reg = <0 0x00a90000 0 0x4000>; 1585 #address-cells = <1>; 1586 #size-cells = <0>; 1587 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1588 clock-names = "se"; 1589 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1590 power-domains = <&rpmhpd SC8280XP_CX>; 1591 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1592 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1593 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1594 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1595 status = "disabled"; 1596 }; 1597 1598 i2c13: i2c@a94000 { 1599 compatible = "qcom,geni-i2c"; 1600 reg = <0 0x00a94000 0 0x4000>; 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1604 clock-names = "se"; 1605 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1606 power-domains = <&rpmhpd SC8280XP_CX>; 1607 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1608 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1609 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1610 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1611 status = "disabled"; 1612 }; 1613 1614 spi13: spi@a94000 { 1615 compatible = "qcom,geni-spi"; 1616 reg = <0 0x00a94000 0 0x4000>; 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1620 clock-names = "se"; 1621 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1622 power-domains = <&rpmhpd SC8280XP_CX>; 1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1624 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1625 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1626 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1627 status = "disabled"; 1628 }; 1629 1630 i2c14: i2c@a98000 { 1631 compatible = "qcom,geni-i2c"; 1632 reg = <0 0x00a98000 0 0x4000>; 1633 #address-cells = <1>; 1634 #size-cells = <0>; 1635 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1636 clock-names = "se"; 1637 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1638 power-domains = <&rpmhpd SC8280XP_CX>; 1639 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1640 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1641 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1642 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1643 status = "disabled"; 1644 }; 1645 1646 spi14: spi@a98000 { 1647 compatible = "qcom,geni-spi"; 1648 reg = <0 0x00a98000 0 0x4000>; 1649 #address-cells = <1>; 1650 #size-cells = <0>; 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1652 clock-names = "se"; 1653 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1654 power-domains = <&rpmhpd SC8280XP_CX>; 1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1656 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1657 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1658 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1659 status = "disabled"; 1660 }; 1661 1662 i2c15: i2c@a9c000 { 1663 compatible = "qcom,geni-i2c"; 1664 reg = <0 0x00a9c000 0 0x4000>; 1665 #address-cells = <1>; 1666 #size-cells = <0>; 1667 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1668 clock-names = "se"; 1669 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1670 power-domains = <&rpmhpd SC8280XP_CX>; 1671 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1672 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1673 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1674 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1675 status = "disabled"; 1676 }; 1677 1678 spi15: spi@a9c000 { 1679 compatible = "qcom,geni-spi"; 1680 reg = <0 0x00a9c000 0 0x4000>; 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1684 clock-names = "se"; 1685 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1686 power-domains = <&rpmhpd SC8280XP_CX>; 1687 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1688 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1689 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1690 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1691 status = "disabled"; 1692 }; 1693 }; 1694 1695 rng: rng@10d3000 { 1696 compatible = "qcom,prng-ee"; 1697 reg = <0 0x010d3000 0 0x1000>; 1698 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1699 clock-names = "core"; 1700 }; 1701 1702 pcie4: pcie@1c00000 { 1703 device_type = "pci"; 1704 compatible = "qcom,pcie-sc8280xp"; 1705 reg = <0x0 0x01c00000 0x0 0x3000>, 1706 <0x0 0x30000000 0x0 0xf1d>, 1707 <0x0 0x30000f20 0x0 0xa8>, 1708 <0x0 0x30001000 0x0 0x1000>, 1709 <0x0 0x30100000 0x0 0x100000>, 1710 <0x0 0x01c03000 0x0 0x1000>; 1711 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1712 #address-cells = <3>; 1713 #size-cells = <2>; 1714 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 1715 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 1716 bus-range = <0x00 0xff>; 1717 1718 dma-coherent; 1719 1720 linux,pci-domain = <6>; 1721 num-lanes = <1>; 1722 1723 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1727 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1728 1729 #interrupt-cells = <1>; 1730 interrupt-map-mask = <0 0 0 0x7>; 1731 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1732 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1733 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1734 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1735 1736 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1737 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1738 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 1739 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 1740 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 1741 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1742 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1743 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 1744 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 1745 clock-names = "aux", 1746 "cfg", 1747 "bus_master", 1748 "bus_slave", 1749 "slave_q2a", 1750 "ddrss_sf_tbu", 1751 "noc_aggr_4", 1752 "noc_aggr_south_sf", 1753 "cnoc_qx"; 1754 1755 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 1756 assigned-clock-rates = <19200000>; 1757 1758 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 1759 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 1760 interconnect-names = "pcie-mem", "cpu-pcie"; 1761 1762 resets = <&gcc GCC_PCIE_4_BCR>; 1763 reset-names = "pci"; 1764 1765 power-domains = <&gcc PCIE_4_GDSC>; 1766 1767 phys = <&pcie4_phy>; 1768 phy-names = "pciephy"; 1769 1770 status = "disabled"; 1771 }; 1772 1773 pcie4_phy: phy@1c06000 { 1774 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 1775 reg = <0x0 0x01c06000 0x0 0x2000>; 1776 1777 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1778 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1779 <&gcc GCC_PCIE_4_CLKREF_CLK>, 1780 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 1781 <&gcc GCC_PCIE_4_PIPE_CLK>, 1782 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 1783 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1784 "pipe", "pipediv2"; 1785 1786 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 1787 assigned-clock-rates = <100000000>; 1788 1789 power-domains = <&gcc PCIE_4_GDSC>; 1790 1791 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 1792 reset-names = "phy"; 1793 1794 #clock-cells = <0>; 1795 clock-output-names = "pcie_4_pipe_clk"; 1796 1797 #phy-cells = <0>; 1798 1799 status = "disabled"; 1800 }; 1801 1802 pcie3b: pcie@1c08000 { 1803 device_type = "pci"; 1804 compatible = "qcom,pcie-sc8280xp"; 1805 reg = <0x0 0x01c08000 0x0 0x3000>, 1806 <0x0 0x32000000 0x0 0xf1d>, 1807 <0x0 0x32000f20 0x0 0xa8>, 1808 <0x0 0x32001000 0x0 0x1000>, 1809 <0x0 0x32100000 0x0 0x100000>, 1810 <0x0 0x01c0b000 0x0 0x1000>; 1811 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1812 #address-cells = <3>; 1813 #size-cells = <2>; 1814 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 1815 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 1816 bus-range = <0x00 0xff>; 1817 1818 dma-coherent; 1819 1820 linux,pci-domain = <5>; 1821 num-lanes = <2>; 1822 1823 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1827 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1828 1829 #interrupt-cells = <1>; 1830 interrupt-map-mask = <0 0 0 0x7>; 1831 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 1832 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 1833 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 1834 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1835 1836 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1837 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1838 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 1839 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 1840 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 1841 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1842 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1843 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1844 clock-names = "aux", 1845 "cfg", 1846 "bus_master", 1847 "bus_slave", 1848 "slave_q2a", 1849 "ddrss_sf_tbu", 1850 "noc_aggr_4", 1851 "noc_aggr_south_sf"; 1852 1853 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 1854 assigned-clock-rates = <19200000>; 1855 1856 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 1857 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 1858 interconnect-names = "pcie-mem", "cpu-pcie"; 1859 1860 resets = <&gcc GCC_PCIE_3B_BCR>; 1861 reset-names = "pci"; 1862 1863 power-domains = <&gcc PCIE_3B_GDSC>; 1864 1865 phys = <&pcie3b_phy>; 1866 phy-names = "pciephy"; 1867 1868 status = "disabled"; 1869 }; 1870 1871 pcie3b_phy: phy@1c0e000 { 1872 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 1873 reg = <0x0 0x01c0e000 0x0 0x2000>; 1874 1875 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1876 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1877 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1878 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 1879 <&gcc GCC_PCIE_3B_PIPE_CLK>, 1880 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 1881 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1882 "pipe", "pipediv2"; 1883 1884 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 1885 assigned-clock-rates = <100000000>; 1886 1887 power-domains = <&gcc PCIE_3B_GDSC>; 1888 1889 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 1890 reset-names = "phy"; 1891 1892 #clock-cells = <0>; 1893 clock-output-names = "pcie_3b_pipe_clk"; 1894 1895 #phy-cells = <0>; 1896 1897 status = "disabled"; 1898 }; 1899 1900 pcie3a: pcie@1c10000 { 1901 device_type = "pci"; 1902 compatible = "qcom,pcie-sc8280xp"; 1903 reg = <0x0 0x01c10000 0x0 0x3000>, 1904 <0x0 0x34000000 0x0 0xf1d>, 1905 <0x0 0x34000f20 0x0 0xa8>, 1906 <0x0 0x34001000 0x0 0x1000>, 1907 <0x0 0x34100000 0x0 0x100000>, 1908 <0x0 0x01c13000 0x0 0x1000>; 1909 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1910 #address-cells = <3>; 1911 #size-cells = <2>; 1912 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 1913 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 1914 bus-range = <0x00 0xff>; 1915 1916 dma-coherent; 1917 1918 linux,pci-domain = <4>; 1919 num-lanes = <4>; 1920 1921 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1925 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1926 1927 #interrupt-cells = <1>; 1928 interrupt-map-mask = <0 0 0 0x7>; 1929 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1930 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 1931 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 1932 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 1933 1934 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1935 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1936 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 1937 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 1938 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 1939 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1940 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1941 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1942 clock-names = "aux", 1943 "cfg", 1944 "bus_master", 1945 "bus_slave", 1946 "slave_q2a", 1947 "ddrss_sf_tbu", 1948 "noc_aggr_4", 1949 "noc_aggr_south_sf"; 1950 1951 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 1952 assigned-clock-rates = <19200000>; 1953 1954 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 1955 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 1956 interconnect-names = "pcie-mem", "cpu-pcie"; 1957 1958 resets = <&gcc GCC_PCIE_3A_BCR>; 1959 reset-names = "pci"; 1960 1961 power-domains = <&gcc PCIE_3A_GDSC>; 1962 1963 phys = <&pcie3a_phy>; 1964 phy-names = "pciephy"; 1965 1966 status = "disabled"; 1967 }; 1968 1969 pcie3a_phy: phy@1c14000 { 1970 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 1971 reg = <0x0 0x01c14000 0x0 0x2000>, 1972 <0x0 0x01c16000 0x0 0x2000>; 1973 1974 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1975 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1976 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1977 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 1978 <&gcc GCC_PCIE_3A_PIPE_CLK>, 1979 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 1980 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1981 "pipe", "pipediv2"; 1982 1983 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 1984 assigned-clock-rates = <100000000>; 1985 1986 power-domains = <&gcc PCIE_3A_GDSC>; 1987 1988 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 1989 reset-names = "phy"; 1990 1991 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 1992 1993 #clock-cells = <0>; 1994 clock-output-names = "pcie_3a_pipe_clk"; 1995 1996 #phy-cells = <0>; 1997 1998 status = "disabled"; 1999 }; 2000 2001 pcie2b: pcie@1c18000 { 2002 device_type = "pci"; 2003 compatible = "qcom,pcie-sc8280xp"; 2004 reg = <0x0 0x01c18000 0x0 0x3000>, 2005 <0x0 0x38000000 0x0 0xf1d>, 2006 <0x0 0x38000f20 0x0 0xa8>, 2007 <0x0 0x38001000 0x0 0x1000>, 2008 <0x0 0x38100000 0x0 0x100000>, 2009 <0x0 0x01c1b000 0x0 0x1000>; 2010 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2011 #address-cells = <3>; 2012 #size-cells = <2>; 2013 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 2014 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 2015 bus-range = <0x00 0xff>; 2016 2017 dma-coherent; 2018 2019 linux,pci-domain = <3>; 2020 num-lanes = <2>; 2021 2022 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2026 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2027 2028 #interrupt-cells = <1>; 2029 interrupt-map-mask = <0 0 0 0x7>; 2030 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2031 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2032 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2033 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2034 2035 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2036 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2037 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2038 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2039 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2040 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2041 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2042 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2043 clock-names = "aux", 2044 "cfg", 2045 "bus_master", 2046 "bus_slave", 2047 "slave_q2a", 2048 "ddrss_sf_tbu", 2049 "noc_aggr_4", 2050 "noc_aggr_south_sf"; 2051 2052 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2053 assigned-clock-rates = <19200000>; 2054 2055 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2056 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2057 interconnect-names = "pcie-mem", "cpu-pcie"; 2058 2059 resets = <&gcc GCC_PCIE_2B_BCR>; 2060 reset-names = "pci"; 2061 2062 power-domains = <&gcc PCIE_2B_GDSC>; 2063 2064 phys = <&pcie2b_phy>; 2065 phy-names = "pciephy"; 2066 2067 status = "disabled"; 2068 }; 2069 2070 pcie2b_phy: phy@1c1e000 { 2071 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2072 reg = <0x0 0x01c1e000 0x0 0x2000>; 2073 2074 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2075 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2076 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2077 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2078 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2079 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2080 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2081 "pipe", "pipediv2"; 2082 2083 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2084 assigned-clock-rates = <100000000>; 2085 2086 power-domains = <&gcc PCIE_2B_GDSC>; 2087 2088 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2089 reset-names = "phy"; 2090 2091 #clock-cells = <0>; 2092 clock-output-names = "pcie_2b_pipe_clk"; 2093 2094 #phy-cells = <0>; 2095 2096 status = "disabled"; 2097 }; 2098 2099 pcie2a: pcie@1c20000 { 2100 device_type = "pci"; 2101 compatible = "qcom,pcie-sc8280xp"; 2102 reg = <0x0 0x01c20000 0x0 0x3000>, 2103 <0x0 0x3c000000 0x0 0xf1d>, 2104 <0x0 0x3c000f20 0x0 0xa8>, 2105 <0x0 0x3c001000 0x0 0x1000>, 2106 <0x0 0x3c100000 0x0 0x100000>, 2107 <0x0 0x01c23000 0x0 0x1000>; 2108 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2109 #address-cells = <3>; 2110 #size-cells = <2>; 2111 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2112 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2113 bus-range = <0x00 0xff>; 2114 2115 dma-coherent; 2116 2117 linux,pci-domain = <2>; 2118 num-lanes = <4>; 2119 2120 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2124 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2125 2126 #interrupt-cells = <1>; 2127 interrupt-map-mask = <0 0 0 0x7>; 2128 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2129 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2130 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2131 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2132 2133 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2134 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2135 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2136 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2137 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2138 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2139 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2140 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2141 clock-names = "aux", 2142 "cfg", 2143 "bus_master", 2144 "bus_slave", 2145 "slave_q2a", 2146 "ddrss_sf_tbu", 2147 "noc_aggr_4", 2148 "noc_aggr_south_sf"; 2149 2150 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2151 assigned-clock-rates = <19200000>; 2152 2153 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2154 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2155 interconnect-names = "pcie-mem", "cpu-pcie"; 2156 2157 resets = <&gcc GCC_PCIE_2A_BCR>; 2158 reset-names = "pci"; 2159 2160 power-domains = <&gcc PCIE_2A_GDSC>; 2161 2162 phys = <&pcie2a_phy>; 2163 phy-names = "pciephy"; 2164 2165 status = "disabled"; 2166 }; 2167 2168 pcie2a_phy: phy@1c24000 { 2169 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2170 reg = <0x0 0x01c24000 0x0 0x2000>, 2171 <0x0 0x01c26000 0x0 0x2000>; 2172 2173 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2174 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2175 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2176 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2177 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2178 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2179 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2180 "pipe", "pipediv2"; 2181 2182 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2183 assigned-clock-rates = <100000000>; 2184 2185 power-domains = <&gcc PCIE_2A_GDSC>; 2186 2187 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2188 reset-names = "phy"; 2189 2190 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2191 2192 #clock-cells = <0>; 2193 clock-output-names = "pcie_2a_pipe_clk"; 2194 2195 #phy-cells = <0>; 2196 2197 status = "disabled"; 2198 }; 2199 2200 ufs_mem_hc: ufs@1d84000 { 2201 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2202 "jedec,ufs-2.0"; 2203 reg = <0 0x01d84000 0 0x3000>; 2204 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2205 phys = <&ufs_mem_phy>; 2206 phy-names = "ufsphy"; 2207 lanes-per-direction = <2>; 2208 #reset-cells = <1>; 2209 resets = <&gcc GCC_UFS_PHY_BCR>; 2210 reset-names = "rst"; 2211 2212 power-domains = <&gcc UFS_PHY_GDSC>; 2213 required-opps = <&rpmhpd_opp_nom>; 2214 2215 iommus = <&apps_smmu 0xe0 0x0>; 2216 dma-coherent; 2217 2218 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2219 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2220 <&gcc GCC_UFS_PHY_AHB_CLK>, 2221 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2222 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2223 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2224 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2225 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2226 clock-names = "core_clk", 2227 "bus_aggr_clk", 2228 "iface_clk", 2229 "core_clk_unipro", 2230 "ref_clk", 2231 "tx_lane0_sync_clk", 2232 "rx_lane0_sync_clk", 2233 "rx_lane1_sync_clk"; 2234 freq-table-hz = <75000000 300000000>, 2235 <0 0>, 2236 <0 0>, 2237 <75000000 300000000>, 2238 <0 0>, 2239 <0 0>, 2240 <0 0>, 2241 <0 0>; 2242 status = "disabled"; 2243 }; 2244 2245 ufs_mem_phy: phy@1d87000 { 2246 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2247 reg = <0 0x01d87000 0 0x1000>; 2248 2249 clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>, 2250 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2251 clock-names = "ref", "ref_aux"; 2252 2253 power-domains = <&gcc UFS_PHY_GDSC>; 2254 2255 resets = <&ufs_mem_hc 0>; 2256 reset-names = "ufsphy"; 2257 2258 #phy-cells = <0>; 2259 2260 status = "disabled"; 2261 }; 2262 2263 ufs_card_hc: ufs@1da4000 { 2264 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2265 "jedec,ufs-2.0"; 2266 reg = <0 0x01da4000 0 0x3000>; 2267 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2268 phys = <&ufs_card_phy>; 2269 phy-names = "ufsphy"; 2270 lanes-per-direction = <2>; 2271 #reset-cells = <1>; 2272 resets = <&gcc GCC_UFS_CARD_BCR>; 2273 reset-names = "rst"; 2274 2275 power-domains = <&gcc UFS_CARD_GDSC>; 2276 2277 iommus = <&apps_smmu 0x4a0 0x0>; 2278 dma-coherent; 2279 2280 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2281 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2282 <&gcc GCC_UFS_CARD_AHB_CLK>, 2283 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2284 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2285 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2286 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2287 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2288 clock-names = "core_clk", 2289 "bus_aggr_clk", 2290 "iface_clk", 2291 "core_clk_unipro", 2292 "ref_clk", 2293 "tx_lane0_sync_clk", 2294 "rx_lane0_sync_clk", 2295 "rx_lane1_sync_clk"; 2296 freq-table-hz = <75000000 300000000>, 2297 <0 0>, 2298 <0 0>, 2299 <75000000 300000000>, 2300 <0 0>, 2301 <0 0>, 2302 <0 0>, 2303 <0 0>; 2304 status = "disabled"; 2305 }; 2306 2307 ufs_card_phy: phy@1da7000 { 2308 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2309 reg = <0 0x01da7000 0 0x1000>; 2310 2311 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, 2312 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; 2313 clock-names = "ref", "ref_aux"; 2314 2315 power-domains = <&gcc UFS_CARD_GDSC>; 2316 2317 resets = <&ufs_card_hc 0>; 2318 reset-names = "ufsphy"; 2319 2320 #phy-cells = <0>; 2321 2322 status = "disabled"; 2323 }; 2324 2325 tcsr_mutex: hwlock@1f40000 { 2326 compatible = "qcom,tcsr-mutex"; 2327 reg = <0x0 0x01f40000 0x0 0x20000>; 2328 #hwlock-cells = <1>; 2329 }; 2330 2331 tcsr: syscon@1fc0000 { 2332 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2333 reg = <0x0 0x01fc0000 0x0 0x30000>; 2334 }; 2335 2336 gpu: gpu@3d00000 { 2337 compatible = "qcom,adreno-690.0", "qcom,adreno"; 2338 2339 reg = <0 0x03d00000 0 0x40000>, 2340 <0 0x03d9e000 0 0x1000>, 2341 <0 0x03d61000 0 0x800>; 2342 reg-names = "kgsl_3d0_reg_memory", 2343 "cx_mem", 2344 "cx_dbgc"; 2345 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2346 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; 2347 operating-points-v2 = <&gpu_opp_table>; 2348 2349 qcom,gmu = <&gmu>; 2350 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2351 interconnect-names = "gfx-mem"; 2352 #cooling-cells = <2>; 2353 2354 status = "disabled"; 2355 2356 gpu_opp_table: opp-table { 2357 compatible = "operating-points-v2"; 2358 2359 opp-270000000 { 2360 opp-hz = /bits/ 64 <270000000>; 2361 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2362 opp-peak-kBps = <451000>; 2363 }; 2364 2365 opp-410000000 { 2366 opp-hz = /bits/ 64 <410000000>; 2367 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2368 opp-peak-kBps = <1555000>; 2369 }; 2370 2371 opp-500000000 { 2372 opp-hz = /bits/ 64 <500000000>; 2373 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2374 opp-peak-kBps = <1555000>; 2375 }; 2376 2377 opp-547000000 { 2378 opp-hz = /bits/ 64 <547000000>; 2379 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2380 opp-peak-kBps = <1555000>; 2381 }; 2382 2383 opp-606000000 { 2384 opp-hz = /bits/ 64 <606000000>; 2385 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2386 opp-peak-kBps = <2736000>; 2387 }; 2388 2389 opp-640000000 { 2390 opp-hz = /bits/ 64 <640000000>; 2391 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2392 opp-peak-kBps = <2736000>; 2393 }; 2394 2395 opp-655000000 { 2396 opp-hz = /bits/ 64 <655000000>; 2397 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2398 opp-peak-kBps = <2736000>; 2399 }; 2400 2401 opp-690000000 { 2402 opp-hz = /bits/ 64 <690000000>; 2403 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2404 opp-peak-kBps = <2736000>; 2405 }; 2406 }; 2407 }; 2408 2409 gmu: gmu@3d6a000 { 2410 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; 2411 reg = <0 0x03d6a000 0 0x34000>, 2412 <0 0x03de0000 0 0x10000>, 2413 <0 0x0b290000 0 0x10000>; 2414 reg-names = "gmu", "rscc", "gmu_pdc"; 2415 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2416 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2417 interrupt-names = "hfi", "gmu"; 2418 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2419 <&gpucc GPU_CC_CXO_CLK>, 2420 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2421 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2422 <&gpucc GPU_CC_AHB_CLK>, 2423 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2424 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2425 clock-names = "gmu", 2426 "cxo", 2427 "axi", 2428 "memnoc", 2429 "ahb", 2430 "hub", 2431 "smmu_vote"; 2432 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2433 <&gpucc GPU_CC_GX_GDSC>; 2434 power-domain-names = "cx", 2435 "gx"; 2436 iommus = <&gpu_smmu 5 0xc00>; 2437 operating-points-v2 = <&gmu_opp_table>; 2438 2439 gmu_opp_table: opp-table { 2440 compatible = "operating-points-v2"; 2441 2442 opp-200000000 { 2443 opp-hz = /bits/ 64 <200000000>; 2444 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2445 }; 2446 2447 opp-500000000 { 2448 opp-hz = /bits/ 64 <500000000>; 2449 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2450 }; 2451 }; 2452 }; 2453 2454 gpucc: clock-controller@3d90000 { 2455 compatible = "qcom,sc8280xp-gpucc"; 2456 reg = <0 0x03d90000 0 0x9000>; 2457 clocks = <&rpmhcc RPMH_CXO_CLK>, 2458 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2459 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2460 clock-names = "bi_tcxo", 2461 "gcc_gpu_gpll0_clk_src", 2462 "gcc_gpu_gpll0_div_clk_src"; 2463 2464 power-domains = <&rpmhpd SC8280XP_GFX>; 2465 #clock-cells = <1>; 2466 #reset-cells = <1>; 2467 #power-domain-cells = <1>; 2468 }; 2469 2470 gpu_smmu: iommu@3da0000 { 2471 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", 2472 "qcom,smmu-500", "arm,mmu-500"; 2473 reg = <0 0x03da0000 0 0x20000>; 2474 #iommu-cells = <2>; 2475 #global-interrupts = <2>; 2476 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2481 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2483 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2484 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2487 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2488 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; 2490 2491 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2492 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2493 <&gpucc GPU_CC_AHB_CLK>, 2494 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2495 <&gpucc GPU_CC_CX_GMU_CLK>, 2496 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2497 <&gpucc GPU_CC_HUB_AON_CLK>; 2498 clock-names = "gcc_gpu_memnoc_gfx_clk", 2499 "gcc_gpu_snoc_dvm_gfx_clk", 2500 "gpu_cc_ahb_clk", 2501 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2502 "gpu_cc_cx_gmu_clk", 2503 "gpu_cc_hub_cx_int_clk", 2504 "gpu_cc_hub_aon_clk"; 2505 2506 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2507 dma-coherent; 2508 }; 2509 2510 usb_0_hsphy: phy@88e5000 { 2511 compatible = "qcom,sc8280xp-usb-hs-phy", 2512 "qcom,usb-snps-hs-5nm-phy"; 2513 reg = <0 0x088e5000 0 0x400>; 2514 clocks = <&rpmhcc RPMH_CXO_CLK>; 2515 clock-names = "ref"; 2516 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2517 2518 #phy-cells = <0>; 2519 2520 status = "disabled"; 2521 }; 2522 2523 usb_2_hsphy0: phy@88e7000 { 2524 compatible = "qcom,sc8280xp-usb-hs-phy", 2525 "qcom,usb-snps-hs-5nm-phy"; 2526 reg = <0 0x088e7000 0 0x400>; 2527 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 2528 clock-names = "ref"; 2529 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2530 2531 #phy-cells = <0>; 2532 2533 status = "disabled"; 2534 }; 2535 2536 usb_2_hsphy1: phy@88e8000 { 2537 compatible = "qcom,sc8280xp-usb-hs-phy", 2538 "qcom,usb-snps-hs-5nm-phy"; 2539 reg = <0 0x088e8000 0 0x400>; 2540 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 2541 clock-names = "ref"; 2542 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2543 2544 #phy-cells = <0>; 2545 2546 status = "disabled"; 2547 }; 2548 2549 usb_2_hsphy2: phy@88e9000 { 2550 compatible = "qcom,sc8280xp-usb-hs-phy", 2551 "qcom,usb-snps-hs-5nm-phy"; 2552 reg = <0 0x088e9000 0 0x400>; 2553 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 2554 clock-names = "ref"; 2555 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 2556 2557 #phy-cells = <0>; 2558 2559 status = "disabled"; 2560 }; 2561 2562 usb_2_hsphy3: phy@88ea000 { 2563 compatible = "qcom,sc8280xp-usb-hs-phy", 2564 "qcom,usb-snps-hs-5nm-phy"; 2565 reg = <0 0x088ea000 0 0x400>; 2566 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 2567 clock-names = "ref"; 2568 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 2569 2570 #phy-cells = <0>; 2571 2572 status = "disabled"; 2573 }; 2574 2575 usb_2_qmpphy0: phy@88ef000 { 2576 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2577 reg = <0 0x088ef000 0 0x2000>; 2578 2579 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2580 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 2581 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2582 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2583 clock-names = "aux", "ref", "com_aux", "pipe"; 2584 2585 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2586 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2587 reset-names = "phy", "phy_phy"; 2588 2589 power-domains = <&gcc USB30_MP_GDSC>; 2590 2591 #clock-cells = <0>; 2592 clock-output-names = "usb2_phy0_pipe_clk"; 2593 2594 #phy-cells = <0>; 2595 2596 status = "disabled"; 2597 }; 2598 2599 usb_2_qmpphy1: phy@88f1000 { 2600 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2601 reg = <0 0x088f1000 0 0x2000>; 2602 2603 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2604 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 2605 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2606 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2607 clock-names = "aux", "ref", "com_aux", "pipe"; 2608 2609 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2610 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2611 reset-names = "phy", "phy_phy"; 2612 2613 power-domains = <&gcc USB30_MP_GDSC>; 2614 2615 #clock-cells = <0>; 2616 clock-output-names = "usb2_phy1_pipe_clk"; 2617 2618 #phy-cells = <0>; 2619 2620 status = "disabled"; 2621 }; 2622 2623 remoteproc_adsp: remoteproc@3000000 { 2624 compatible = "qcom,sc8280xp-adsp-pas"; 2625 reg = <0 0x03000000 0 0x100>; 2626 2627 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2628 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2629 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2630 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2631 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2632 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2633 interrupt-names = "wdog", "fatal", "ready", 2634 "handover", "stop-ack", "shutdown-ack"; 2635 2636 clocks = <&rpmhcc RPMH_CXO_CLK>; 2637 clock-names = "xo"; 2638 2639 power-domains = <&rpmhpd SC8280XP_LCX>, 2640 <&rpmhpd SC8280XP_LMX>; 2641 power-domain-names = "lcx", "lmx"; 2642 2643 memory-region = <&pil_adsp_mem>; 2644 2645 qcom,qmp = <&aoss_qmp>; 2646 2647 qcom,smem-states = <&smp2p_adsp_out 0>; 2648 qcom,smem-state-names = "stop"; 2649 2650 status = "disabled"; 2651 2652 remoteproc_adsp_glink: glink-edge { 2653 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2654 IPCC_MPROC_SIGNAL_GLINK_QMP 2655 IRQ_TYPE_EDGE_RISING>; 2656 mboxes = <&ipcc IPCC_CLIENT_LPASS 2657 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2658 2659 label = "lpass"; 2660 qcom,remote-pid = <2>; 2661 2662 gpr { 2663 compatible = "qcom,gpr"; 2664 qcom,glink-channels = "adsp_apps"; 2665 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2666 qcom,intents = <512 20>; 2667 #address-cells = <1>; 2668 #size-cells = <0>; 2669 2670 q6apm: service@1 { 2671 compatible = "qcom,q6apm"; 2672 reg = <GPR_APM_MODULE_IID>; 2673 #sound-dai-cells = <0>; 2674 qcom,protection-domain = "avs/audio", 2675 "msm/adsp/audio_pd"; 2676 q6apmdai: dais { 2677 compatible = "qcom,q6apm-dais"; 2678 iommus = <&apps_smmu 0x0c01 0x0>; 2679 }; 2680 2681 q6apmbedai: bedais { 2682 compatible = "qcom,q6apm-lpass-dais"; 2683 #sound-dai-cells = <1>; 2684 }; 2685 }; 2686 2687 q6prm: service@2 { 2688 compatible = "qcom,q6prm"; 2689 reg = <GPR_PRM_MODULE_IID>; 2690 qcom,protection-domain = "avs/audio", 2691 "msm/adsp/audio_pd"; 2692 q6prmcc: clock-controller { 2693 compatible = "qcom,q6prm-lpass-clocks"; 2694 #clock-cells = <2>; 2695 }; 2696 }; 2697 }; 2698 }; 2699 }; 2700 2701 rxmacro: rxmacro@3200000 { 2702 compatible = "qcom,sc8280xp-lpass-rx-macro"; 2703 reg = <0 0x03200000 0 0x1000>; 2704 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2705 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2706 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2707 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2708 <&vamacro>; 2709 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2710 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2711 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2712 assigned-clock-rates = <19200000>, <19200000>; 2713 2714 clock-output-names = "mclk"; 2715 #clock-cells = <0>; 2716 #sound-dai-cells = <1>; 2717 2718 pinctrl-names = "default"; 2719 pinctrl-0 = <&rx_swr_default>; 2720 2721 status = "disabled"; 2722 }; 2723 2724 swr1: soundwire-controller@3210000 { 2725 compatible = "qcom,soundwire-v1.6.0"; 2726 reg = <0 0x03210000 0 0x2000>; 2727 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2728 clocks = <&rxmacro>; 2729 clock-names = "iface"; 2730 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2731 reset-names = "swr_audio_cgcr"; 2732 label = "RX"; 2733 2734 qcom,din-ports = <0>; 2735 qcom,dout-ports = <5>; 2736 2737 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2738 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2739 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2740 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 2741 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 2742 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2743 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 2744 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2745 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2746 2747 #sound-dai-cells = <1>; 2748 #address-cells = <2>; 2749 #size-cells = <0>; 2750 2751 status = "disabled"; 2752 }; 2753 2754 txmacro: txmacro@3220000 { 2755 compatible = "qcom,sc8280xp-lpass-tx-macro"; 2756 reg = <0 0x03220000 0 0x1000>; 2757 pinctrl-names = "default"; 2758 pinctrl-0 = <&tx_swr_default>; 2759 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2760 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2761 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2762 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2763 <&vamacro>; 2764 2765 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2766 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2767 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2768 assigned-clock-rates = <19200000>, <19200000>; 2769 clock-output-names = "mclk"; 2770 2771 #clock-cells = <0>; 2772 #sound-dai-cells = <1>; 2773 2774 status = "disabled"; 2775 }; 2776 2777 wsamacro: codec@3240000 { 2778 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 2779 reg = <0 0x03240000 0 0x1000>; 2780 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2781 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2782 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2783 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2784 <&vamacro>; 2785 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2786 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2787 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2788 assigned-clock-rates = <19200000>, <19200000>; 2789 2790 #clock-cells = <0>; 2791 clock-output-names = "mclk"; 2792 #sound-dai-cells = <1>; 2793 2794 pinctrl-names = "default"; 2795 pinctrl-0 = <&wsa_swr_default>; 2796 2797 status = "disabled"; 2798 }; 2799 2800 swr0: soundwire-controller@3250000 { 2801 reg = <0 0x03250000 0 0x2000>; 2802 compatible = "qcom,soundwire-v1.6.0"; 2803 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2804 clocks = <&wsamacro>; 2805 clock-names = "iface"; 2806 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 2807 reset-names = "swr_audio_cgcr"; 2808 label = "WSA"; 2809 2810 qcom,din-ports = <2>; 2811 qcom,dout-ports = <6>; 2812 2813 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2814 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2815 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2816 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2817 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2818 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2819 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2820 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2821 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2822 2823 #sound-dai-cells = <1>; 2824 #address-cells = <2>; 2825 #size-cells = <0>; 2826 2827 status = "disabled"; 2828 }; 2829 2830 lpass_audiocc: clock-controller@32a9000 { 2831 compatible = "qcom,sc8280xp-lpassaudiocc"; 2832 reg = <0 0x032a9000 0 0x1000>; 2833 #clock-cells = <1>; 2834 #reset-cells = <1>; 2835 }; 2836 2837 swr2: soundwire-controller@3330000 { 2838 compatible = "qcom,soundwire-v1.6.0"; 2839 reg = <0 0x03330000 0 0x2000>; 2840 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 2841 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2842 interrupt-names = "core", "wakeup"; 2843 2844 clocks = <&txmacro>; 2845 clock-names = "iface"; 2846 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 2847 reset-names = "swr_audio_cgcr"; 2848 label = "TX"; 2849 #sound-dai-cells = <1>; 2850 #address-cells = <2>; 2851 #size-cells = <0>; 2852 2853 qcom,din-ports = <4>; 2854 qcom,dout-ports = <0>; 2855 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2856 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 2857 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2858 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2859 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2860 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2861 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2862 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2863 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 2864 2865 status = "disabled"; 2866 }; 2867 2868 vamacro: codec@3370000 { 2869 compatible = "qcom,sc8280xp-lpass-va-macro"; 2870 reg = <0 0x03370000 0 0x1000>; 2871 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2872 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2873 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2874 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2875 clock-names = "mclk", "macro", "dcodec", "npl"; 2876 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2877 assigned-clock-rates = <19200000>; 2878 2879 #clock-cells = <0>; 2880 clock-output-names = "fsgen"; 2881 #sound-dai-cells = <1>; 2882 2883 status = "disabled"; 2884 }; 2885 2886 lpass_tlmm: pinctrl@33c0000 { 2887 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 2888 reg = <0 0x33c0000 0x0 0x20000>, 2889 <0 0x3550000 0x0 0x10000>; 2890 gpio-controller; 2891 #gpio-cells = <2>; 2892 gpio-ranges = <&lpass_tlmm 0 0 19>; 2893 2894 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2895 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2896 clock-names = "core", "audio"; 2897 2898 status = "disabled"; 2899 2900 tx_swr_default: tx-swr-default-state { 2901 clk-pins { 2902 pins = "gpio0"; 2903 function = "swr_tx_clk"; 2904 drive-strength = <2>; 2905 slew-rate = <1>; 2906 bias-disable; 2907 }; 2908 2909 data-pins { 2910 pins = "gpio1", "gpio2"; 2911 function = "swr_tx_data"; 2912 drive-strength = <2>; 2913 slew-rate = <1>; 2914 bias-bus-hold; 2915 }; 2916 }; 2917 2918 rx_swr_default: rx-swr-default-state { 2919 clk-pins { 2920 pins = "gpio3"; 2921 function = "swr_rx_clk"; 2922 drive-strength = <2>; 2923 slew-rate = <1>; 2924 bias-disable; 2925 }; 2926 2927 data-pins { 2928 pins = "gpio4", "gpio5"; 2929 function = "swr_rx_data"; 2930 drive-strength = <2>; 2931 slew-rate = <1>; 2932 bias-bus-hold; 2933 }; 2934 }; 2935 2936 dmic01_default: dmic01-default-state { 2937 clk-pins { 2938 pins = "gpio6"; 2939 function = "dmic1_clk"; 2940 drive-strength = <8>; 2941 output-high; 2942 }; 2943 2944 data-pins { 2945 pins = "gpio7"; 2946 function = "dmic1_data"; 2947 drive-strength = <8>; 2948 }; 2949 }; 2950 2951 dmic01_sleep: dmic01-sleep-state { 2952 clk-pins { 2953 pins = "gpio6"; 2954 function = "dmic1_clk"; 2955 drive-strength = <2>; 2956 bias-disable; 2957 output-low; 2958 }; 2959 2960 data-pins { 2961 pins = "gpio7"; 2962 function = "dmic1_data"; 2963 drive-strength = <2>; 2964 bias-pull-down; 2965 }; 2966 }; 2967 2968 dmic02_default: dmic02-default-state { 2969 clk-pins { 2970 pins = "gpio8"; 2971 function = "dmic2_clk"; 2972 drive-strength = <8>; 2973 output-high; 2974 }; 2975 2976 data-pins { 2977 pins = "gpio9"; 2978 function = "dmic2_data"; 2979 drive-strength = <8>; 2980 }; 2981 }; 2982 2983 dmic02_sleep: dmic02-sleep-state { 2984 clk-pins { 2985 pins = "gpio8"; 2986 function = "dmic2_clk"; 2987 drive-strength = <2>; 2988 bias-disable; 2989 output-low; 2990 }; 2991 2992 data-pins { 2993 pins = "gpio9"; 2994 function = "dmic2_data"; 2995 drive-strength = <2>; 2996 bias-pull-down; 2997 }; 2998 }; 2999 3000 wsa_swr_default: wsa-swr-default-state { 3001 clk-pins { 3002 pins = "gpio10"; 3003 function = "wsa_swr_clk"; 3004 drive-strength = <2>; 3005 slew-rate = <1>; 3006 bias-disable; 3007 }; 3008 3009 data-pins { 3010 pins = "gpio11"; 3011 function = "wsa_swr_data"; 3012 drive-strength = <2>; 3013 slew-rate = <1>; 3014 bias-bus-hold; 3015 }; 3016 }; 3017 3018 wsa2_swr_default: wsa2-swr-default-state { 3019 clk-pins { 3020 pins = "gpio15"; 3021 function = "wsa2_swr_clk"; 3022 drive-strength = <2>; 3023 slew-rate = <1>; 3024 bias-disable; 3025 }; 3026 3027 data-pins { 3028 pins = "gpio16"; 3029 function = "wsa2_swr_data"; 3030 drive-strength = <2>; 3031 slew-rate = <1>; 3032 bias-bus-hold; 3033 }; 3034 }; 3035 }; 3036 3037 lpasscc: clock-controller@33e0000 { 3038 compatible = "qcom,sc8280xp-lpasscc"; 3039 reg = <0 0x033e0000 0 0x12000>; 3040 #clock-cells = <1>; 3041 #reset-cells = <1>; 3042 }; 3043 3044 sdc2: mmc@8804000 { 3045 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; 3046 reg = <0 0x08804000 0 0x1000>; 3047 3048 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3049 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3050 interrupt-names = "hc_irq", "pwr_irq"; 3051 3052 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3053 <&gcc GCC_SDCC2_APPS_CLK>, 3054 <&rpmhcc RPMH_CXO_CLK>; 3055 clock-names = "iface", "core", "xo"; 3056 resets = <&gcc GCC_SDCC2_BCR>; 3057 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3058 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3059 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3060 iommus = <&apps_smmu 0x4e0 0x0>; 3061 power-domains = <&rpmhpd SC8280XP_CX>; 3062 operating-points-v2 = <&sdc2_opp_table>; 3063 bus-width = <4>; 3064 dma-coherent; 3065 3066 status = "disabled"; 3067 3068 sdc2_opp_table: opp-table { 3069 compatible = "operating-points-v2"; 3070 3071 opp-100000000 { 3072 opp-hz = /bits/ 64 <100000000>; 3073 required-opps = <&rpmhpd_opp_low_svs>; 3074 opp-peak-kBps = <1800000 400000>; 3075 opp-avg-kBps = <100000 0>; 3076 }; 3077 3078 opp-202000000 { 3079 opp-hz = /bits/ 64 <202000000>; 3080 required-opps = <&rpmhpd_opp_svs_l1>; 3081 opp-peak-kBps = <5400000 1600000>; 3082 opp-avg-kBps = <200000 0>; 3083 }; 3084 }; 3085 }; 3086 3087 usb_0_qmpphy: phy@88eb000 { 3088 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3089 reg = <0 0x088eb000 0 0x4000>; 3090 3091 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3092 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 3093 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3094 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3095 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3096 3097 power-domains = <&gcc USB30_PRIM_GDSC>; 3098 3099 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3100 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 3101 reset-names = "phy", "common"; 3102 3103 #clock-cells = <1>; 3104 #phy-cells = <1>; 3105 3106 status = "disabled"; 3107 3108 ports { 3109 #address-cells = <1>; 3110 #size-cells = <0>; 3111 3112 port@0 { 3113 reg = <0>; 3114 3115 usb_0_qmpphy_out: endpoint {}; 3116 }; 3117 3118 port@2 { 3119 reg = <2>; 3120 3121 usb_0_qmpphy_dp_in: endpoint {}; 3122 }; 3123 }; 3124 }; 3125 3126 usb_1_hsphy: phy@8902000 { 3127 compatible = "qcom,sc8280xp-usb-hs-phy", 3128 "qcom,usb-snps-hs-5nm-phy"; 3129 reg = <0 0x08902000 0 0x400>; 3130 #phy-cells = <0>; 3131 3132 clocks = <&rpmhcc RPMH_CXO_CLK>; 3133 clock-names = "ref"; 3134 3135 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3136 3137 status = "disabled"; 3138 }; 3139 3140 usb_1_qmpphy: phy@8903000 { 3141 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3142 reg = <0 0x08903000 0 0x4000>; 3143 3144 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3145 <&gcc GCC_USB4_CLKREF_CLK>, 3146 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3147 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3148 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3149 3150 power-domains = <&gcc USB30_SEC_GDSC>; 3151 3152 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3153 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 3154 reset-names = "phy", "common"; 3155 3156 #clock-cells = <1>; 3157 #phy-cells = <1>; 3158 3159 status = "disabled"; 3160 3161 ports { 3162 #address-cells = <1>; 3163 #size-cells = <0>; 3164 3165 port@0 { 3166 reg = <0>; 3167 3168 usb_1_qmpphy_out: endpoint {}; 3169 }; 3170 3171 port@2 { 3172 reg = <2>; 3173 3174 usb_1_qmpphy_dp_in: endpoint {}; 3175 }; 3176 }; 3177 }; 3178 3179 mdss1_dp0_phy: phy@8909a00 { 3180 compatible = "qcom,sc8280xp-dp-phy"; 3181 reg = <0 0x08909a00 0 0x19c>, 3182 <0 0x08909200 0 0xec>, 3183 <0 0x08909600 0 0xec>, 3184 <0 0x08909000 0 0x1c8>; 3185 3186 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3187 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3188 clock-names = "aux", "cfg_ahb"; 3189 power-domains = <&rpmhpd SC8280XP_MX>; 3190 3191 #clock-cells = <1>; 3192 #phy-cells = <0>; 3193 3194 status = "disabled"; 3195 }; 3196 3197 mdss1_dp1_phy: phy@890ca00 { 3198 compatible = "qcom,sc8280xp-dp-phy"; 3199 reg = <0 0x0890ca00 0 0x19c>, 3200 <0 0x0890c200 0 0xec>, 3201 <0 0x0890c600 0 0xec>, 3202 <0 0x0890c000 0 0x1c8>; 3203 3204 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3205 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3206 clock-names = "aux", "cfg_ahb"; 3207 power-domains = <&rpmhpd SC8280XP_MX>; 3208 3209 #clock-cells = <1>; 3210 #phy-cells = <0>; 3211 3212 status = "disabled"; 3213 }; 3214 3215 pmu@9091000 { 3216 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3217 reg = <0 0x09091000 0 0x1000>; 3218 3219 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3220 3221 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3222 3223 operating-points-v2 = <&llcc_bwmon_opp_table>; 3224 3225 llcc_bwmon_opp_table: opp-table { 3226 compatible = "operating-points-v2"; 3227 3228 opp-0 { 3229 opp-peak-kBps = <762000>; 3230 }; 3231 opp-1 { 3232 opp-peak-kBps = <1720000>; 3233 }; 3234 opp-2 { 3235 opp-peak-kBps = <2086000>; 3236 }; 3237 opp-3 { 3238 opp-peak-kBps = <2597000>; 3239 }; 3240 opp-4 { 3241 opp-peak-kBps = <2929000>; 3242 }; 3243 opp-5 { 3244 opp-peak-kBps = <3879000>; 3245 }; 3246 opp-6 { 3247 opp-peak-kBps = <5161000>; 3248 }; 3249 opp-7 { 3250 opp-peak-kBps = <5931000>; 3251 }; 3252 opp-8 { 3253 opp-peak-kBps = <6515000>; 3254 }; 3255 opp-9 { 3256 opp-peak-kBps = <7980000>; 3257 }; 3258 opp-10 { 3259 opp-peak-kBps = <8136000>; 3260 }; 3261 opp-11 { 3262 opp-peak-kBps = <10437000>; 3263 }; 3264 opp-12 { 3265 opp-peak-kBps = <12191000>; 3266 }; 3267 }; 3268 }; 3269 3270 pmu@90b6400 { 3271 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 3272 reg = <0 0x090b6400 0 0x600>; 3273 3274 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3275 3276 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3277 operating-points-v2 = <&cpu_bwmon_opp_table>; 3278 3279 cpu_bwmon_opp_table: opp-table { 3280 compatible = "operating-points-v2"; 3281 3282 opp-0 { 3283 opp-peak-kBps = <2288000>; 3284 }; 3285 opp-1 { 3286 opp-peak-kBps = <4577000>; 3287 }; 3288 opp-2 { 3289 opp-peak-kBps = <7110000>; 3290 }; 3291 opp-3 { 3292 opp-peak-kBps = <9155000>; 3293 }; 3294 opp-4 { 3295 opp-peak-kBps = <12298000>; 3296 }; 3297 opp-5 { 3298 opp-peak-kBps = <14236000>; 3299 }; 3300 opp-6 { 3301 opp-peak-kBps = <15258001>; 3302 }; 3303 }; 3304 }; 3305 3306 system-cache-controller@9200000 { 3307 compatible = "qcom,sc8280xp-llcc"; 3308 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3309 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3310 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3311 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3312 <0 0x09600000 0 0x58000>; 3313 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3314 "llcc3_base", "llcc4_base", "llcc5_base", 3315 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3316 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3317 }; 3318 3319 usb_0: usb@a6f8800 { 3320 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3321 reg = <0 0x0a6f8800 0 0x400>; 3322 #address-cells = <2>; 3323 #size-cells = <2>; 3324 ranges; 3325 3326 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3327 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3328 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3329 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3330 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3331 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3332 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3333 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3334 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3335 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3336 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3337 3338 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3339 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3340 assigned-clock-rates = <19200000>, <200000000>; 3341 3342 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 3343 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3344 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3345 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 3346 interrupt-names = "pwr_event", 3347 "dp_hs_phy_irq", 3348 "dm_hs_phy_irq", 3349 "ss_phy_irq"; 3350 3351 power-domains = <&gcc USB30_PRIM_GDSC>; 3352 required-opps = <&rpmhpd_opp_nom>; 3353 3354 resets = <&gcc GCC_USB30_PRIM_BCR>; 3355 3356 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3357 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3358 interconnect-names = "usb-ddr", "apps-usb"; 3359 3360 wakeup-source; 3361 3362 status = "disabled"; 3363 3364 usb_0_dwc3: usb@a600000 { 3365 compatible = "snps,dwc3"; 3366 reg = <0 0x0a600000 0 0xcd00>; 3367 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 3368 iommus = <&apps_smmu 0x820 0x0>; 3369 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3370 phy-names = "usb2-phy", "usb3-phy"; 3371 3372 port { 3373 usb_0_role_switch: endpoint { 3374 }; 3375 }; 3376 }; 3377 }; 3378 3379 usb_1: usb@a8f8800 { 3380 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3381 reg = <0 0x0a8f8800 0 0x400>; 3382 #address-cells = <2>; 3383 #size-cells = <2>; 3384 ranges; 3385 3386 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3387 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3388 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3389 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3390 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3391 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3392 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3393 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3394 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3395 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3396 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3397 3398 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3399 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3400 assigned-clock-rates = <19200000>, <200000000>; 3401 3402 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 3403 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3404 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3405 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 3406 interrupt-names = "pwr_event", 3407 "dp_hs_phy_irq", 3408 "dm_hs_phy_irq", 3409 "ss_phy_irq"; 3410 3411 power-domains = <&gcc USB30_SEC_GDSC>; 3412 required-opps = <&rpmhpd_opp_nom>; 3413 3414 resets = <&gcc GCC_USB30_SEC_BCR>; 3415 3416 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3417 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3418 interconnect-names = "usb-ddr", "apps-usb"; 3419 3420 wakeup-source; 3421 3422 status = "disabled"; 3423 3424 usb_1_dwc3: usb@a800000 { 3425 compatible = "snps,dwc3"; 3426 reg = <0 0x0a800000 0 0xcd00>; 3427 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 3428 iommus = <&apps_smmu 0x860 0x0>; 3429 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3430 phy-names = "usb2-phy", "usb3-phy"; 3431 3432 port { 3433 usb_1_role_switch: endpoint { 3434 }; 3435 }; 3436 }; 3437 }; 3438 3439 mdss0: display-subsystem@ae00000 { 3440 compatible = "qcom,sc8280xp-mdss"; 3441 reg = <0 0x0ae00000 0 0x1000>; 3442 reg-names = "mdss"; 3443 3444 clocks = <&gcc GCC_DISP_AHB_CLK>, 3445 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3446 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 3447 clock-names = "iface", 3448 "ahb", 3449 "core"; 3450 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3451 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 3452 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 3453 interconnect-names = "mdp0-mem", "mdp1-mem"; 3454 iommus = <&apps_smmu 0x1000 0x402>; 3455 power-domains = <&dispcc0 MDSS_GDSC>; 3456 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 3457 3458 interrupt-controller; 3459 #interrupt-cells = <1>; 3460 #address-cells = <2>; 3461 #size-cells = <2>; 3462 ranges; 3463 3464 status = "disabled"; 3465 3466 mdss0_mdp: display-controller@ae01000 { 3467 compatible = "qcom,sc8280xp-dpu"; 3468 reg = <0 0x0ae01000 0 0x8f000>, 3469 <0 0x0aeb0000 0 0x2008>; 3470 reg-names = "mdp", "vbif"; 3471 3472 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3473 <&gcc GCC_DISP_SF_AXI_CLK>, 3474 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3475 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 3476 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 3477 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3478 clock-names = "bus", 3479 "nrt_bus", 3480 "iface", 3481 "lut", 3482 "core", 3483 "vsync"; 3484 interrupt-parent = <&mdss0>; 3485 interrupts = <0>; 3486 power-domains = <&rpmhpd SC8280XP_MMCX>; 3487 3488 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3489 assigned-clock-rates = <19200000>; 3490 operating-points-v2 = <&mdss0_mdp_opp_table>; 3491 3492 ports { 3493 #address-cells = <1>; 3494 #size-cells = <0>; 3495 3496 port@0 { 3497 reg = <0>; 3498 mdss0_intf0_out: endpoint { 3499 remote-endpoint = <&mdss0_dp0_in>; 3500 }; 3501 }; 3502 3503 port@4 { 3504 reg = <4>; 3505 mdss0_intf4_out: endpoint { 3506 remote-endpoint = <&mdss0_dp1_in>; 3507 }; 3508 }; 3509 3510 port@5 { 3511 reg = <5>; 3512 mdss0_intf5_out: endpoint { 3513 remote-endpoint = <&mdss0_dp3_in>; 3514 }; 3515 }; 3516 3517 port@6 { 3518 reg = <6>; 3519 mdss0_intf6_out: endpoint { 3520 remote-endpoint = <&mdss0_dp2_in>; 3521 }; 3522 }; 3523 }; 3524 3525 mdss0_mdp_opp_table: opp-table { 3526 compatible = "operating-points-v2"; 3527 3528 opp-200000000 { 3529 opp-hz = /bits/ 64 <200000000>; 3530 required-opps = <&rpmhpd_opp_low_svs>; 3531 }; 3532 3533 opp-300000000 { 3534 opp-hz = /bits/ 64 <300000000>; 3535 required-opps = <&rpmhpd_opp_svs>; 3536 }; 3537 3538 opp-375000000 { 3539 opp-hz = /bits/ 64 <375000000>; 3540 required-opps = <&rpmhpd_opp_svs_l1>; 3541 }; 3542 3543 opp-500000000 { 3544 opp-hz = /bits/ 64 <500000000>; 3545 required-opps = <&rpmhpd_opp_nom>; 3546 }; 3547 opp-600000000 { 3548 opp-hz = /bits/ 64 <600000000>; 3549 required-opps = <&rpmhpd_opp_turbo_l1>; 3550 }; 3551 }; 3552 }; 3553 3554 mdss0_dp0: displayport-controller@ae90000 { 3555 compatible = "qcom,sc8280xp-dp"; 3556 reg = <0 0xae90000 0 0x200>, 3557 <0 0xae90200 0 0x200>, 3558 <0 0xae90400 0 0x600>, 3559 <0 0xae91000 0 0x400>, 3560 <0 0xae91400 0 0x400>; 3561 interrupt-parent = <&mdss0>; 3562 interrupts = <12>; 3563 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3564 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3565 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 3566 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3567 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3568 clock-names = "core_iface", "core_aux", 3569 "ctrl_link", 3570 "ctrl_link_iface", 3571 "stream_pixel"; 3572 3573 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3574 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3575 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3576 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3577 3578 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 3579 phy-names = "dp"; 3580 3581 #sound-dai-cells = <0>; 3582 3583 operating-points-v2 = <&mdss0_dp0_opp_table>; 3584 power-domains = <&rpmhpd SC8280XP_MMCX>; 3585 3586 status = "disabled"; 3587 3588 ports { 3589 #address-cells = <1>; 3590 #size-cells = <0>; 3591 3592 port@0 { 3593 reg = <0>; 3594 3595 mdss0_dp0_in: endpoint { 3596 remote-endpoint = <&mdss0_intf0_out>; 3597 }; 3598 }; 3599 3600 port@1 { 3601 reg = <1>; 3602 3603 mdss0_dp0_out: endpoint { 3604 }; 3605 }; 3606 }; 3607 3608 mdss0_dp0_opp_table: opp-table { 3609 compatible = "operating-points-v2"; 3610 3611 opp-160000000 { 3612 opp-hz = /bits/ 64 <160000000>; 3613 required-opps = <&rpmhpd_opp_low_svs>; 3614 }; 3615 3616 opp-270000000 { 3617 opp-hz = /bits/ 64 <270000000>; 3618 required-opps = <&rpmhpd_opp_svs>; 3619 }; 3620 3621 opp-540000000 { 3622 opp-hz = /bits/ 64 <540000000>; 3623 required-opps = <&rpmhpd_opp_svs_l1>; 3624 }; 3625 3626 opp-810000000 { 3627 opp-hz = /bits/ 64 <810000000>; 3628 required-opps = <&rpmhpd_opp_nom>; 3629 }; 3630 }; 3631 }; 3632 3633 mdss0_dp1: displayport-controller@ae98000 { 3634 compatible = "qcom,sc8280xp-dp"; 3635 reg = <0 0xae98000 0 0x200>, 3636 <0 0xae98200 0 0x200>, 3637 <0 0xae98400 0 0x600>, 3638 <0 0xae99000 0 0x400>, 3639 <0 0xae99400 0 0x400>; 3640 interrupt-parent = <&mdss0>; 3641 interrupts = <13>; 3642 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3643 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3644 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 3645 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 3646 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 3647 clock-names = "core_iface", "core_aux", 3648 "ctrl_link", 3649 "ctrl_link_iface", "stream_pixel"; 3650 3651 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 3652 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 3653 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3654 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3655 3656 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3657 phy-names = "dp"; 3658 3659 #sound-dai-cells = <0>; 3660 3661 operating-points-v2 = <&mdss0_dp1_opp_table>; 3662 power-domains = <&rpmhpd SC8280XP_MMCX>; 3663 3664 status = "disabled"; 3665 3666 ports { 3667 #address-cells = <1>; 3668 #size-cells = <0>; 3669 3670 port@0 { 3671 reg = <0>; 3672 3673 mdss0_dp1_in: endpoint { 3674 remote-endpoint = <&mdss0_intf4_out>; 3675 }; 3676 }; 3677 3678 port@1 { 3679 reg = <1>; 3680 3681 mdss0_dp1_out: endpoint { 3682 }; 3683 }; 3684 }; 3685 3686 mdss0_dp1_opp_table: opp-table { 3687 compatible = "operating-points-v2"; 3688 3689 opp-160000000 { 3690 opp-hz = /bits/ 64 <160000000>; 3691 required-opps = <&rpmhpd_opp_low_svs>; 3692 }; 3693 3694 opp-270000000 { 3695 opp-hz = /bits/ 64 <270000000>; 3696 required-opps = <&rpmhpd_opp_svs>; 3697 }; 3698 3699 opp-540000000 { 3700 opp-hz = /bits/ 64 <540000000>; 3701 required-opps = <&rpmhpd_opp_svs_l1>; 3702 }; 3703 3704 opp-810000000 { 3705 opp-hz = /bits/ 64 <810000000>; 3706 required-opps = <&rpmhpd_opp_nom>; 3707 }; 3708 }; 3709 }; 3710 3711 mdss0_dp2: displayport-controller@ae9a000 { 3712 compatible = "qcom,sc8280xp-dp"; 3713 reg = <0 0xae9a000 0 0x200>, 3714 <0 0xae9a200 0 0x200>, 3715 <0 0xae9a400 0 0x600>, 3716 <0 0xae9b000 0 0x400>, 3717 <0 0xae9b400 0 0x400>; 3718 3719 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3720 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3721 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 3722 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 3723 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 3724 clock-names = "core_iface", "core_aux", 3725 "ctrl_link", 3726 "ctrl_link_iface", "stream_pixel"; 3727 interrupt-parent = <&mdss0>; 3728 interrupts = <14>; 3729 phys = <&mdss0_dp2_phy>; 3730 phy-names = "dp"; 3731 power-domains = <&rpmhpd SC8280XP_MMCX>; 3732 3733 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 3734 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 3735 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; 3736 operating-points-v2 = <&mdss0_dp2_opp_table>; 3737 3738 #sound-dai-cells = <0>; 3739 3740 status = "disabled"; 3741 3742 ports { 3743 #address-cells = <1>; 3744 #size-cells = <0>; 3745 3746 port@0 { 3747 reg = <0>; 3748 mdss0_dp2_in: endpoint { 3749 remote-endpoint = <&mdss0_intf6_out>; 3750 }; 3751 }; 3752 3753 port@1 { 3754 reg = <1>; 3755 }; 3756 }; 3757 3758 mdss0_dp2_opp_table: opp-table { 3759 compatible = "operating-points-v2"; 3760 3761 opp-160000000 { 3762 opp-hz = /bits/ 64 <160000000>; 3763 required-opps = <&rpmhpd_opp_low_svs>; 3764 }; 3765 3766 opp-270000000 { 3767 opp-hz = /bits/ 64 <270000000>; 3768 required-opps = <&rpmhpd_opp_svs>; 3769 }; 3770 3771 opp-540000000 { 3772 opp-hz = /bits/ 64 <540000000>; 3773 required-opps = <&rpmhpd_opp_svs_l1>; 3774 }; 3775 3776 opp-810000000 { 3777 opp-hz = /bits/ 64 <810000000>; 3778 required-opps = <&rpmhpd_opp_nom>; 3779 }; 3780 }; 3781 }; 3782 3783 mdss0_dp3: displayport-controller@aea0000 { 3784 compatible = "qcom,sc8280xp-dp"; 3785 reg = <0 0xaea0000 0 0x200>, 3786 <0 0xaea0200 0 0x200>, 3787 <0 0xaea0400 0 0x600>, 3788 <0 0xaea1000 0 0x400>, 3789 <0 0xaea1400 0 0x400>; 3790 3791 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3792 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3793 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 3794 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 3795 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 3796 clock-names = "core_iface", "core_aux", 3797 "ctrl_link", 3798 "ctrl_link_iface", "stream_pixel"; 3799 interrupt-parent = <&mdss0>; 3800 interrupts = <15>; 3801 phys = <&mdss0_dp3_phy>; 3802 phy-names = "dp"; 3803 power-domains = <&rpmhpd SC8280XP_MMCX>; 3804 3805 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 3806 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 3807 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 3808 operating-points-v2 = <&mdss0_dp3_opp_table>; 3809 3810 #sound-dai-cells = <0>; 3811 3812 status = "disabled"; 3813 3814 ports { 3815 #address-cells = <1>; 3816 #size-cells = <0>; 3817 3818 port@0 { 3819 reg = <0>; 3820 mdss0_dp3_in: endpoint { 3821 remote-endpoint = <&mdss0_intf5_out>; 3822 }; 3823 }; 3824 3825 port@1 { 3826 reg = <1>; 3827 }; 3828 }; 3829 3830 mdss0_dp3_opp_table: opp-table { 3831 compatible = "operating-points-v2"; 3832 3833 opp-160000000 { 3834 opp-hz = /bits/ 64 <160000000>; 3835 required-opps = <&rpmhpd_opp_low_svs>; 3836 }; 3837 3838 opp-270000000 { 3839 opp-hz = /bits/ 64 <270000000>; 3840 required-opps = <&rpmhpd_opp_svs>; 3841 }; 3842 3843 opp-540000000 { 3844 opp-hz = /bits/ 64 <540000000>; 3845 required-opps = <&rpmhpd_opp_svs_l1>; 3846 }; 3847 3848 opp-810000000 { 3849 opp-hz = /bits/ 64 <810000000>; 3850 required-opps = <&rpmhpd_opp_nom>; 3851 }; 3852 }; 3853 }; 3854 }; 3855 3856 mdss0_dp2_phy: phy@aec2a00 { 3857 compatible = "qcom,sc8280xp-dp-phy"; 3858 reg = <0 0x0aec2a00 0 0x19c>, 3859 <0 0x0aec2200 0 0xec>, 3860 <0 0x0aec2600 0 0xec>, 3861 <0 0x0aec2000 0 0x1c8>; 3862 3863 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3864 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3865 clock-names = "aux", "cfg_ahb"; 3866 power-domains = <&rpmhpd SC8280XP_MX>; 3867 3868 #clock-cells = <1>; 3869 #phy-cells = <0>; 3870 3871 status = "disabled"; 3872 }; 3873 3874 mdss0_dp3_phy: phy@aec5a00 { 3875 compatible = "qcom,sc8280xp-dp-phy"; 3876 reg = <0 0x0aec5a00 0 0x19c>, 3877 <0 0x0aec5200 0 0xec>, 3878 <0 0x0aec5600 0 0xec>, 3879 <0 0x0aec5000 0 0x1c8>; 3880 3881 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3882 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3883 clock-names = "aux", "cfg_ahb"; 3884 power-domains = <&rpmhpd SC8280XP_MX>; 3885 3886 #clock-cells = <1>; 3887 #phy-cells = <0>; 3888 3889 status = "disabled"; 3890 }; 3891 3892 dispcc0: clock-controller@af00000 { 3893 compatible = "qcom,sc8280xp-dispcc0"; 3894 reg = <0 0x0af00000 0 0x20000>; 3895 3896 clocks = <&gcc GCC_DISP_AHB_CLK>, 3897 <&rpmhcc RPMH_CXO_CLK>, 3898 <&sleep_clk>, 3899 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3900 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3901 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3902 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3903 <&mdss0_dp2_phy 0>, 3904 <&mdss0_dp2_phy 1>, 3905 <&mdss0_dp3_phy 0>, 3906 <&mdss0_dp3_phy 1>, 3907 <0>, 3908 <0>, 3909 <0>, 3910 <0>; 3911 power-domains = <&rpmhpd SC8280XP_MMCX>; 3912 3913 #clock-cells = <1>; 3914 #power-domain-cells = <1>; 3915 #reset-cells = <1>; 3916 3917 status = "disabled"; 3918 }; 3919 3920 pdc: interrupt-controller@b220000 { 3921 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 3922 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3923 qcom,pdc-ranges = <0 480 40>, 3924 <40 140 14>, 3925 <54 263 1>, 3926 <55 306 4>, 3927 <59 312 3>, 3928 <62 374 2>, 3929 <64 434 2>, 3930 <66 438 3>, 3931 <69 86 1>, 3932 <70 520 54>, 3933 <124 609 28>, 3934 <159 638 1>, 3935 <160 720 8>, 3936 <168 801 1>, 3937 <169 728 30>, 3938 <199 416 2>, 3939 <201 449 1>, 3940 <202 89 1>, 3941 <203 451 1>, 3942 <204 462 1>, 3943 <205 264 1>, 3944 <206 579 1>, 3945 <207 653 1>, 3946 <208 656 1>, 3947 <209 659 1>, 3948 <210 122 1>, 3949 <211 699 1>, 3950 <212 705 1>, 3951 <213 450 1>, 3952 <214 643 1>, 3953 <216 646 5>, 3954 <221 390 5>, 3955 <226 700 3>, 3956 <229 240 3>, 3957 <232 269 1>, 3958 <233 377 1>, 3959 <234 372 1>, 3960 <235 138 1>, 3961 <236 857 1>, 3962 <237 860 1>, 3963 <238 137 1>, 3964 <239 668 1>, 3965 <240 366 1>, 3966 <241 949 1>, 3967 <242 815 5>, 3968 <247 769 1>, 3969 <248 768 1>, 3970 <249 663 1>, 3971 <250 799 2>, 3972 <252 798 1>, 3973 <253 765 1>, 3974 <254 763 1>, 3975 <255 454 1>, 3976 <258 139 1>, 3977 <259 786 2>, 3978 <261 370 2>, 3979 <263 158 2>; 3980 #interrupt-cells = <2>; 3981 interrupt-parent = <&intc>; 3982 interrupt-controller; 3983 }; 3984 3985 tsens0: thermal-sensor@c263000 { 3986 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 3987 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3988 <0 0x0c222000 0 0x8>; /* SROT */ 3989 #qcom,sensors = <14>; 3990 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 3991 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 3992 interrupt-names = "uplow", "critical"; 3993 #thermal-sensor-cells = <1>; 3994 }; 3995 3996 tsens1: thermal-sensor@c265000 { 3997 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 3998 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3999 <0 0x0c223000 0 0x8>; /* SROT */ 4000 #qcom,sensors = <16>; 4001 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 4002 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 4003 interrupt-names = "uplow", "critical"; 4004 #thermal-sensor-cells = <1>; 4005 }; 4006 4007 aoss_qmp: power-management@c300000 { 4008 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 4009 reg = <0 0x0c300000 0 0x400>; 4010 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 4011 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4012 4013 #clock-cells = <0>; 4014 }; 4015 4016 sram@c3f0000 { 4017 compatible = "qcom,rpmh-stats"; 4018 reg = <0 0x0c3f0000 0 0x400>; 4019 }; 4020 4021 spmi_bus: spmi@c440000 { 4022 compatible = "qcom,spmi-pmic-arb"; 4023 reg = <0 0x0c440000 0 0x1100>, 4024 <0 0x0c600000 0 0x2000000>, 4025 <0 0x0e600000 0 0x100000>, 4026 <0 0x0e700000 0 0xa0000>, 4027 <0 0x0c40a000 0 0x26000>; 4028 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4029 interrupt-names = "periph_irq"; 4030 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4031 qcom,ee = <0>; 4032 qcom,channel = <0>; 4033 #address-cells = <2>; 4034 #size-cells = <0>; 4035 interrupt-controller; 4036 #interrupt-cells = <4>; 4037 }; 4038 4039 tlmm: pinctrl@f100000 { 4040 compatible = "qcom,sc8280xp-tlmm"; 4041 reg = <0 0x0f100000 0 0x300000>; 4042 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4043 gpio-controller; 4044 #gpio-cells = <2>; 4045 interrupt-controller; 4046 #interrupt-cells = <2>; 4047 gpio-ranges = <&tlmm 0 0 230>; 4048 }; 4049 4050 apps_smmu: iommu@15000000 { 4051 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 4052 reg = <0 0x15000000 0 0x100000>; 4053 #iommu-cells = <2>; 4054 #global-interrupts = <2>; 4055 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 4056 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4057 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4067 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4129 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4130 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4138 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4140 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4141 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4142 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4143 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4144 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4145 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4146 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4147 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 4148 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 4149 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4150 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 4151 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4152 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4153 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 4154 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 4155 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 4156 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 4157 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4158 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 4159 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 4160 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 4161 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 4162 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 4163 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 4164 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 4165 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 4166 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 4167 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 4168 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 4169 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 4170 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 4171 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 4172 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 4173 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 4174 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 4175 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 4176 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 4178 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 4179 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 4180 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 4181 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 4182 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 4183 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 4184 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 4185 }; 4186 4187 intc: interrupt-controller@17a00000 { 4188 compatible = "arm,gic-v3"; 4189 interrupt-controller; 4190 #interrupt-cells = <3>; 4191 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4192 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4193 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4194 #redistributor-regions = <1>; 4195 redistributor-stride = <0 0x20000>; 4196 4197 #address-cells = <2>; 4198 #size-cells = <2>; 4199 ranges; 4200 4201 msi-controller@17a40000 { 4202 compatible = "arm,gic-v3-its"; 4203 reg = <0 0x17a40000 0 0x20000>; 4204 msi-controller; 4205 #msi-cells = <1>; 4206 }; 4207 }; 4208 4209 watchdog@17c10000 { 4210 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 4211 reg = <0 0x17c10000 0 0x1000>; 4212 clocks = <&sleep_clk>; 4213 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4214 }; 4215 4216 timer@17c20000 { 4217 compatible = "arm,armv7-timer-mem"; 4218 reg = <0x0 0x17c20000 0x0 0x1000>; 4219 #address-cells = <1>; 4220 #size-cells = <1>; 4221 ranges = <0x0 0x0 0x0 0x20000000>; 4222 4223 frame@17c21000 { 4224 frame-number = <0>; 4225 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4226 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4227 reg = <0x17c21000 0x1000>, 4228 <0x17c22000 0x1000>; 4229 }; 4230 4231 frame@17c23000 { 4232 frame-number = <1>; 4233 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4234 reg = <0x17c23000 0x1000>; 4235 status = "disabled"; 4236 }; 4237 4238 frame@17c25000 { 4239 frame-number = <2>; 4240 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4241 reg = <0x17c25000 0x1000>; 4242 status = "disabled"; 4243 }; 4244 4245 frame@17c27000 { 4246 frame-number = <3>; 4247 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4248 reg = <0x17c26000 0x1000>; 4249 status = "disabled"; 4250 }; 4251 4252 frame@17c29000 { 4253 frame-number = <4>; 4254 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4255 reg = <0x17c29000 0x1000>; 4256 status = "disabled"; 4257 }; 4258 4259 frame@17c2b000 { 4260 frame-number = <5>; 4261 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4262 reg = <0x17c2b000 0x1000>; 4263 status = "disabled"; 4264 }; 4265 4266 frame@17c2d000 { 4267 frame-number = <6>; 4268 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4269 reg = <0x17c2d000 0x1000>; 4270 status = "disabled"; 4271 }; 4272 }; 4273 4274 apps_rsc: rsc@18200000 { 4275 compatible = "qcom,rpmh-rsc"; 4276 reg = <0x0 0x18200000 0x0 0x10000>, 4277 <0x0 0x18210000 0x0 0x10000>, 4278 <0x0 0x18220000 0x0 0x10000>; 4279 reg-names = "drv-0", "drv-1", "drv-2"; 4280 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4281 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4282 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4283 qcom,tcs-offset = <0xd00>; 4284 qcom,drv-id = <2>; 4285 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4286 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4287 label = "apps_rsc"; 4288 4289 apps_bcm_voter: bcm-voter { 4290 compatible = "qcom,bcm-voter"; 4291 }; 4292 4293 rpmhcc: clock-controller { 4294 compatible = "qcom,sc8280xp-rpmh-clk"; 4295 #clock-cells = <1>; 4296 clock-names = "xo"; 4297 clocks = <&xo_board_clk>; 4298 }; 4299 4300 rpmhpd: power-controller { 4301 compatible = "qcom,sc8280xp-rpmhpd"; 4302 #power-domain-cells = <1>; 4303 operating-points-v2 = <&rpmhpd_opp_table>; 4304 4305 rpmhpd_opp_table: opp-table { 4306 compatible = "operating-points-v2"; 4307 4308 rpmhpd_opp_ret: opp1 { 4309 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4310 }; 4311 4312 rpmhpd_opp_min_svs: opp2 { 4313 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4314 }; 4315 4316 rpmhpd_opp_low_svs: opp3 { 4317 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4318 }; 4319 4320 rpmhpd_opp_svs: opp4 { 4321 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4322 }; 4323 4324 rpmhpd_opp_svs_l1: opp5 { 4325 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4326 }; 4327 4328 rpmhpd_opp_nom: opp6 { 4329 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4330 }; 4331 4332 rpmhpd_opp_nom_l1: opp7 { 4333 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4334 }; 4335 4336 rpmhpd_opp_nom_l2: opp8 { 4337 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4338 }; 4339 4340 rpmhpd_opp_turbo: opp9 { 4341 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4342 }; 4343 4344 rpmhpd_opp_turbo_l1: opp10 { 4345 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4346 }; 4347 }; 4348 }; 4349 }; 4350 4351 epss_l3: interconnect@18590000 { 4352 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 4353 reg = <0 0x18590000 0 0x1000>; 4354 4355 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4356 clock-names = "xo", "alternate"; 4357 4358 #interconnect-cells = <1>; 4359 }; 4360 4361 cpufreq_hw: cpufreq@18591000 { 4362 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 4363 reg = <0 0x18591000 0 0x1000>, 4364 <0 0x18592000 0 0x1000>; 4365 reg-names = "freq-domain0", "freq-domain1"; 4366 4367 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4368 clock-names = "xo", "alternate"; 4369 4370 #freq-domain-cells = <1>; 4371 #clock-cells = <1>; 4372 }; 4373 4374 remoteproc_nsp0: remoteproc@1b300000 { 4375 compatible = "qcom,sc8280xp-nsp0-pas"; 4376 reg = <0 0x1b300000 0 0x100>; 4377 4378 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 4379 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 4380 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 4381 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 4382 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 4383 interrupt-names = "wdog", "fatal", "ready", 4384 "handover", "stop-ack"; 4385 4386 clocks = <&rpmhcc RPMH_CXO_CLK>; 4387 clock-names = "xo"; 4388 4389 power-domains = <&rpmhpd SC8280XP_NSP>; 4390 power-domain-names = "nsp"; 4391 4392 memory-region = <&pil_nsp0_mem>; 4393 4394 qcom,smem-states = <&smp2p_nsp0_out 0>; 4395 qcom,smem-state-names = "stop"; 4396 4397 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4398 4399 status = "disabled"; 4400 4401 glink-edge { 4402 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4403 IPCC_MPROC_SIGNAL_GLINK_QMP 4404 IRQ_TYPE_EDGE_RISING>; 4405 mboxes = <&ipcc IPCC_CLIENT_CDSP 4406 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4407 4408 label = "nsp0"; 4409 qcom,remote-pid = <5>; 4410 4411 fastrpc { 4412 compatible = "qcom,fastrpc"; 4413 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4414 label = "cdsp"; 4415 #address-cells = <1>; 4416 #size-cells = <0>; 4417 4418 compute-cb@1 { 4419 compatible = "qcom,fastrpc-compute-cb"; 4420 reg = <1>; 4421 iommus = <&apps_smmu 0x3181 0x0420>; 4422 }; 4423 4424 compute-cb@2 { 4425 compatible = "qcom,fastrpc-compute-cb"; 4426 reg = <2>; 4427 iommus = <&apps_smmu 0x3182 0x0420>; 4428 }; 4429 4430 compute-cb@3 { 4431 compatible = "qcom,fastrpc-compute-cb"; 4432 reg = <3>; 4433 iommus = <&apps_smmu 0x3183 0x0420>; 4434 }; 4435 4436 compute-cb@4 { 4437 compatible = "qcom,fastrpc-compute-cb"; 4438 reg = <4>; 4439 iommus = <&apps_smmu 0x3184 0x0420>; 4440 }; 4441 4442 compute-cb@5 { 4443 compatible = "qcom,fastrpc-compute-cb"; 4444 reg = <5>; 4445 iommus = <&apps_smmu 0x3185 0x0420>; 4446 }; 4447 4448 compute-cb@6 { 4449 compatible = "qcom,fastrpc-compute-cb"; 4450 reg = <6>; 4451 iommus = <&apps_smmu 0x3186 0x0420>; 4452 }; 4453 4454 compute-cb@7 { 4455 compatible = "qcom,fastrpc-compute-cb"; 4456 reg = <7>; 4457 iommus = <&apps_smmu 0x3187 0x0420>; 4458 }; 4459 4460 compute-cb@8 { 4461 compatible = "qcom,fastrpc-compute-cb"; 4462 reg = <8>; 4463 iommus = <&apps_smmu 0x3188 0x0420>; 4464 }; 4465 4466 compute-cb@9 { 4467 compatible = "qcom,fastrpc-compute-cb"; 4468 reg = <9>; 4469 iommus = <&apps_smmu 0x318b 0x0420>; 4470 }; 4471 4472 compute-cb@10 { 4473 compatible = "qcom,fastrpc-compute-cb"; 4474 reg = <10>; 4475 iommus = <&apps_smmu 0x318b 0x0420>; 4476 }; 4477 4478 compute-cb@11 { 4479 compatible = "qcom,fastrpc-compute-cb"; 4480 reg = <11>; 4481 iommus = <&apps_smmu 0x318c 0x0420>; 4482 }; 4483 4484 compute-cb@12 { 4485 compatible = "qcom,fastrpc-compute-cb"; 4486 reg = <12>; 4487 iommus = <&apps_smmu 0x318d 0x0420>; 4488 }; 4489 4490 compute-cb@13 { 4491 compatible = "qcom,fastrpc-compute-cb"; 4492 reg = <13>; 4493 iommus = <&apps_smmu 0x318e 0x0420>; 4494 }; 4495 4496 compute-cb@14 { 4497 compatible = "qcom,fastrpc-compute-cb"; 4498 reg = <14>; 4499 iommus = <&apps_smmu 0x318f 0x0420>; 4500 }; 4501 }; 4502 }; 4503 }; 4504 4505 remoteproc_nsp1: remoteproc@21300000 { 4506 compatible = "qcom,sc8280xp-nsp1-pas"; 4507 reg = <0 0x21300000 0 0x100>; 4508 4509 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 4510 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 4511 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 4512 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 4513 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 4514 interrupt-names = "wdog", "fatal", "ready", 4515 "handover", "stop-ack"; 4516 4517 clocks = <&rpmhcc RPMH_CXO_CLK>; 4518 clock-names = "xo"; 4519 4520 power-domains = <&rpmhpd SC8280XP_NSP>; 4521 power-domain-names = "nsp"; 4522 4523 memory-region = <&pil_nsp1_mem>; 4524 4525 qcom,smem-states = <&smp2p_nsp1_out 0>; 4526 qcom,smem-state-names = "stop"; 4527 4528 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 4529 4530 status = "disabled"; 4531 4532 glink-edge { 4533 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 4534 IPCC_MPROC_SIGNAL_GLINK_QMP 4535 IRQ_TYPE_EDGE_RISING>; 4536 mboxes = <&ipcc IPCC_CLIENT_NSP1 4537 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4538 4539 label = "nsp1"; 4540 qcom,remote-pid = <12>; 4541 }; 4542 }; 4543 4544 mdss1: display-subsystem@22000000 { 4545 compatible = "qcom,sc8280xp-mdss"; 4546 reg = <0 0x22000000 0 0x1000>; 4547 reg-names = "mdss"; 4548 4549 clocks = <&gcc GCC_DISP_AHB_CLK>, 4550 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4551 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 4552 clock-names = "iface", 4553 "ahb", 4554 "core"; 4555 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 4556 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 4557 interconnect-names = "mdp0-mem", "mdp1-mem"; 4558 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 4559 4560 iommus = <&apps_smmu 0x1800 0x402>; 4561 power-domains = <&dispcc1 MDSS_GDSC>; 4562 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 4563 4564 interrupt-controller; 4565 #interrupt-cells = <1>; 4566 #address-cells = <2>; 4567 #size-cells = <2>; 4568 ranges; 4569 4570 status = "disabled"; 4571 4572 mdss1_mdp: display-controller@22001000 { 4573 compatible = "qcom,sc8280xp-dpu"; 4574 reg = <0 0x22001000 0 0x8f000>, 4575 <0 0x220b0000 0 0x2008>; 4576 reg-names = "mdp", "vbif"; 4577 4578 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4579 <&gcc GCC_DISP_SF_AXI_CLK>, 4580 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4581 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 4582 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 4583 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4584 clock-names = "bus", 4585 "nrt_bus", 4586 "iface", 4587 "lut", 4588 "core", 4589 "vsync"; 4590 interrupt-parent = <&mdss1>; 4591 interrupts = <0>; 4592 power-domains = <&rpmhpd SC8280XP_MMCX>; 4593 4594 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4595 assigned-clock-rates = <19200000>; 4596 operating-points-v2 = <&mdss1_mdp_opp_table>; 4597 4598 ports { 4599 #address-cells = <1>; 4600 #size-cells = <0>; 4601 4602 port@0 { 4603 reg = <0>; 4604 mdss1_intf0_out: endpoint { 4605 remote-endpoint = <&mdss1_dp0_in>; 4606 }; 4607 }; 4608 4609 port@4 { 4610 reg = <4>; 4611 mdss1_intf4_out: endpoint { 4612 remote-endpoint = <&mdss1_dp1_in>; 4613 }; 4614 }; 4615 4616 port@5 { 4617 reg = <5>; 4618 mdss1_intf5_out: endpoint { 4619 remote-endpoint = <&mdss1_dp3_in>; 4620 }; 4621 }; 4622 4623 port@6 { 4624 reg = <6>; 4625 mdss1_intf6_out: endpoint { 4626 remote-endpoint = <&mdss1_dp2_in>; 4627 }; 4628 }; 4629 }; 4630 4631 mdss1_mdp_opp_table: opp-table { 4632 compatible = "operating-points-v2"; 4633 4634 opp-200000000 { 4635 opp-hz = /bits/ 64 <200000000>; 4636 required-opps = <&rpmhpd_opp_low_svs>; 4637 }; 4638 4639 opp-300000000 { 4640 opp-hz = /bits/ 64 <300000000>; 4641 required-opps = <&rpmhpd_opp_svs>; 4642 }; 4643 4644 opp-375000000 { 4645 opp-hz = /bits/ 64 <375000000>; 4646 required-opps = <&rpmhpd_opp_svs_l1>; 4647 }; 4648 4649 opp-500000000 { 4650 opp-hz = /bits/ 64 <500000000>; 4651 required-opps = <&rpmhpd_opp_nom>; 4652 }; 4653 opp-600000000 { 4654 opp-hz = /bits/ 64 <600000000>; 4655 required-opps = <&rpmhpd_opp_turbo_l1>; 4656 }; 4657 }; 4658 }; 4659 4660 mdss1_dp0: displayport-controller@22090000 { 4661 compatible = "qcom,sc8280xp-dp"; 4662 reg = <0 0x22090000 0 0x200>, 4663 <0 0x22090200 0 0x200>, 4664 <0 0x22090400 0 0x600>, 4665 <0 0x22091000 0 0x400>, 4666 <0 0x22091400 0 0x400>; 4667 4668 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4669 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4670 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4671 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4672 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4673 clock-names = "core_iface", "core_aux", 4674 "ctrl_link", 4675 "ctrl_link_iface", "stream_pixel"; 4676 interrupt-parent = <&mdss1>; 4677 interrupts = <12>; 4678 phys = <&mdss1_dp0_phy>; 4679 phy-names = "dp"; 4680 power-domains = <&rpmhpd SC8280XP_MMCX>; 4681 4682 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4683 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4684 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; 4685 operating-points-v2 = <&mdss1_dp0_opp_table>; 4686 4687 #sound-dai-cells = <0>; 4688 4689 status = "disabled"; 4690 4691 ports { 4692 #address-cells = <1>; 4693 #size-cells = <0>; 4694 4695 port@0 { 4696 reg = <0>; 4697 mdss1_dp0_in: endpoint { 4698 remote-endpoint = <&mdss1_intf0_out>; 4699 }; 4700 }; 4701 4702 port@1 { 4703 reg = <1>; 4704 }; 4705 }; 4706 4707 mdss1_dp0_opp_table: opp-table { 4708 compatible = "operating-points-v2"; 4709 4710 opp-160000000 { 4711 opp-hz = /bits/ 64 <160000000>; 4712 required-opps = <&rpmhpd_opp_low_svs>; 4713 }; 4714 4715 opp-270000000 { 4716 opp-hz = /bits/ 64 <270000000>; 4717 required-opps = <&rpmhpd_opp_svs>; 4718 }; 4719 4720 opp-540000000 { 4721 opp-hz = /bits/ 64 <540000000>; 4722 required-opps = <&rpmhpd_opp_svs_l1>; 4723 }; 4724 4725 opp-810000000 { 4726 opp-hz = /bits/ 64 <810000000>; 4727 required-opps = <&rpmhpd_opp_nom>; 4728 }; 4729 }; 4730 }; 4731 4732 mdss1_dp1: displayport-controller@22098000 { 4733 compatible = "qcom,sc8280xp-dp"; 4734 reg = <0 0x22098000 0 0x200>, 4735 <0 0x22098200 0 0x200>, 4736 <0 0x22098400 0 0x600>, 4737 <0 0x22099000 0 0x400>, 4738 <0 0x22099400 0 0x400>; 4739 4740 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4741 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 4742 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 4743 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4744 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4745 clock-names = "core_iface", "core_aux", 4746 "ctrl_link", 4747 "ctrl_link_iface", "stream_pixel"; 4748 interrupt-parent = <&mdss1>; 4749 interrupts = <13>; 4750 phys = <&mdss1_dp1_phy>; 4751 phy-names = "dp"; 4752 power-domains = <&rpmhpd SC8280XP_MMCX>; 4753 4754 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4755 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4756 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; 4757 operating-points-v2 = <&mdss1_dp1_opp_table>; 4758 4759 #sound-dai-cells = <0>; 4760 4761 status = "disabled"; 4762 4763 ports { 4764 #address-cells = <1>; 4765 #size-cells = <0>; 4766 4767 port@0 { 4768 reg = <0>; 4769 mdss1_dp1_in: endpoint { 4770 remote-endpoint = <&mdss1_intf4_out>; 4771 }; 4772 }; 4773 4774 port@1 { 4775 reg = <1>; 4776 }; 4777 }; 4778 4779 mdss1_dp1_opp_table: opp-table { 4780 compatible = "operating-points-v2"; 4781 4782 opp-160000000 { 4783 opp-hz = /bits/ 64 <160000000>; 4784 required-opps = <&rpmhpd_opp_low_svs>; 4785 }; 4786 4787 opp-270000000 { 4788 opp-hz = /bits/ 64 <270000000>; 4789 required-opps = <&rpmhpd_opp_svs>; 4790 }; 4791 4792 opp-540000000 { 4793 opp-hz = /bits/ 64 <540000000>; 4794 required-opps = <&rpmhpd_opp_svs_l1>; 4795 }; 4796 4797 opp-810000000 { 4798 opp-hz = /bits/ 64 <810000000>; 4799 required-opps = <&rpmhpd_opp_nom>; 4800 }; 4801 }; 4802 }; 4803 4804 mdss1_dp2: displayport-controller@2209a000 { 4805 compatible = "qcom,sc8280xp-dp"; 4806 reg = <0 0x2209a000 0 0x200>, 4807 <0 0x2209a200 0 0x200>, 4808 <0 0x2209a400 0 0x600>, 4809 <0 0x2209b000 0 0x400>, 4810 <0 0x2209b400 0 0x400>; 4811 4812 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4813 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4814 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 4815 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4816 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4817 clock-names = "core_iface", "core_aux", 4818 "ctrl_link", 4819 "ctrl_link_iface", "stream_pixel"; 4820 interrupt-parent = <&mdss1>; 4821 interrupts = <14>; 4822 phys = <&mdss1_dp2_phy>; 4823 phy-names = "dp"; 4824 power-domains = <&rpmhpd SC8280XP_MMCX>; 4825 4826 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4827 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4828 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; 4829 operating-points-v2 = <&mdss1_dp2_opp_table>; 4830 4831 #sound-dai-cells = <0>; 4832 4833 status = "disabled"; 4834 4835 ports { 4836 #address-cells = <1>; 4837 #size-cells = <0>; 4838 4839 port@0 { 4840 reg = <0>; 4841 mdss1_dp2_in: endpoint { 4842 remote-endpoint = <&mdss1_intf6_out>; 4843 }; 4844 }; 4845 4846 port@1 { 4847 reg = <1>; 4848 }; 4849 }; 4850 4851 mdss1_dp2_opp_table: opp-table { 4852 compatible = "operating-points-v2"; 4853 4854 opp-160000000 { 4855 opp-hz = /bits/ 64 <160000000>; 4856 required-opps = <&rpmhpd_opp_low_svs>; 4857 }; 4858 4859 opp-270000000 { 4860 opp-hz = /bits/ 64 <270000000>; 4861 required-opps = <&rpmhpd_opp_svs>; 4862 }; 4863 4864 opp-540000000 { 4865 opp-hz = /bits/ 64 <540000000>; 4866 required-opps = <&rpmhpd_opp_svs_l1>; 4867 }; 4868 4869 opp-810000000 { 4870 opp-hz = /bits/ 64 <810000000>; 4871 required-opps = <&rpmhpd_opp_nom>; 4872 }; 4873 }; 4874 }; 4875 4876 mdss1_dp3: displayport-controller@220a0000 { 4877 compatible = "qcom,sc8280xp-dp"; 4878 reg = <0 0x220a0000 0 0x200>, 4879 <0 0x220a0200 0 0x200>, 4880 <0 0x220a0400 0 0x600>, 4881 <0 0x220a1000 0 0x400>, 4882 <0 0x220a1400 0 0x400>; 4883 4884 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4885 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4886 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 4887 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4888 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4889 clock-names = "core_iface", "core_aux", 4890 "ctrl_link", 4891 "ctrl_link_iface", "stream_pixel"; 4892 interrupt-parent = <&mdss1>; 4893 interrupts = <15>; 4894 phys = <&mdss1_dp3_phy>; 4895 phy-names = "dp"; 4896 power-domains = <&rpmhpd SC8280XP_MMCX>; 4897 4898 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4899 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4900 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 4901 operating-points-v2 = <&mdss1_dp3_opp_table>; 4902 4903 #sound-dai-cells = <0>; 4904 4905 status = "disabled"; 4906 4907 ports { 4908 #address-cells = <1>; 4909 #size-cells = <0>; 4910 4911 port@0 { 4912 reg = <0>; 4913 mdss1_dp3_in: endpoint { 4914 remote-endpoint = <&mdss1_intf5_out>; 4915 }; 4916 }; 4917 4918 port@1 { 4919 reg = <1>; 4920 }; 4921 }; 4922 4923 mdss1_dp3_opp_table: opp-table { 4924 compatible = "operating-points-v2"; 4925 4926 opp-160000000 { 4927 opp-hz = /bits/ 64 <160000000>; 4928 required-opps = <&rpmhpd_opp_low_svs>; 4929 }; 4930 4931 opp-270000000 { 4932 opp-hz = /bits/ 64 <270000000>; 4933 required-opps = <&rpmhpd_opp_svs>; 4934 }; 4935 4936 opp-540000000 { 4937 opp-hz = /bits/ 64 <540000000>; 4938 required-opps = <&rpmhpd_opp_svs_l1>; 4939 }; 4940 4941 opp-810000000 { 4942 opp-hz = /bits/ 64 <810000000>; 4943 required-opps = <&rpmhpd_opp_nom>; 4944 }; 4945 }; 4946 }; 4947 }; 4948 4949 mdss1_dp2_phy: phy@220c2a00 { 4950 compatible = "qcom,sc8280xp-dp-phy"; 4951 reg = <0 0x220c2a00 0 0x19c>, 4952 <0 0x220c2200 0 0xec>, 4953 <0 0x220c2600 0 0xec>, 4954 <0 0x220c2000 0 0x1c8>; 4955 4956 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4957 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4958 clock-names = "aux", "cfg_ahb"; 4959 power-domains = <&rpmhpd SC8280XP_MX>; 4960 4961 #clock-cells = <1>; 4962 #phy-cells = <0>; 4963 4964 status = "disabled"; 4965 }; 4966 4967 mdss1_dp3_phy: phy@220c5a00 { 4968 compatible = "qcom,sc8280xp-dp-phy"; 4969 reg = <0 0x220c5a00 0 0x19c>, 4970 <0 0x220c5200 0 0xec>, 4971 <0 0x220c5600 0 0xec>, 4972 <0 0x220c5000 0 0x1c8>; 4973 4974 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4975 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4976 clock-names = "aux", "cfg_ahb"; 4977 power-domains = <&rpmhpd SC8280XP_MX>; 4978 4979 #clock-cells = <1>; 4980 #phy-cells = <0>; 4981 4982 status = "disabled"; 4983 }; 4984 4985 dispcc1: clock-controller@22100000 { 4986 compatible = "qcom,sc8280xp-dispcc1"; 4987 reg = <0 0x22100000 0 0x20000>; 4988 4989 clocks = <&gcc GCC_DISP_AHB_CLK>, 4990 <&rpmhcc RPMH_CXO_CLK>, 4991 <0>, 4992 <&mdss1_dp0_phy 0>, 4993 <&mdss1_dp0_phy 1>, 4994 <&mdss1_dp1_phy 0>, 4995 <&mdss1_dp1_phy 1>, 4996 <&mdss1_dp2_phy 0>, 4997 <&mdss1_dp2_phy 1>, 4998 <&mdss1_dp3_phy 0>, 4999 <&mdss1_dp3_phy 1>, 5000 <0>, 5001 <0>, 5002 <0>, 5003 <0>; 5004 power-domains = <&rpmhpd SC8280XP_MMCX>; 5005 5006 #clock-cells = <1>; 5007 #power-domain-cells = <1>; 5008 #reset-cells = <1>; 5009 5010 status = "disabled"; 5011 }; 5012 5013 ethernet1: ethernet@23000000 { 5014 compatible = "qcom,sc8280xp-ethqos"; 5015 reg = <0x0 0x23000000 0x0 0x10000>, 5016 <0x0 0x23016000 0x0 0x100>; 5017 reg-names = "stmmaceth", "rgmii"; 5018 5019 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 5020 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 5021 <&gcc GCC_EMAC1_PTP_CLK>, 5022 <&gcc GCC_EMAC1_RGMII_CLK>; 5023 clock-names = "stmmaceth", 5024 "pclk", 5025 "ptp_ref", 5026 "rgmii"; 5027 5028 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 5029 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; 5030 interrupt-names = "macirq", "eth_lpi"; 5031 5032 iommus = <&apps_smmu 0x40 0xf>; 5033 power-domains = <&gcc EMAC_1_GDSC>; 5034 5035 snps,tso; 5036 snps,pbl = <32>; 5037 rx-fifo-depth = <4096>; 5038 tx-fifo-depth = <4096>; 5039 5040 status = "disabled"; 5041 }; 5042 }; 5043 5044 sound: sound { 5045 }; 5046 5047 thermal-zones { 5048 cpu0-thermal { 5049 polling-delay-passive = <250>; 5050 polling-delay = <1000>; 5051 5052 thermal-sensors = <&tsens0 1>; 5053 5054 trips { 5055 cpu-crit { 5056 temperature = <110000>; 5057 hysteresis = <1000>; 5058 type = "critical"; 5059 }; 5060 }; 5061 }; 5062 5063 cpu1-thermal { 5064 polling-delay-passive = <250>; 5065 polling-delay = <1000>; 5066 5067 thermal-sensors = <&tsens0 2>; 5068 5069 trips { 5070 cpu-crit { 5071 temperature = <110000>; 5072 hysteresis = <1000>; 5073 type = "critical"; 5074 }; 5075 }; 5076 }; 5077 5078 cpu2-thermal { 5079 polling-delay-passive = <250>; 5080 polling-delay = <1000>; 5081 5082 thermal-sensors = <&tsens0 3>; 5083 5084 trips { 5085 cpu-crit { 5086 temperature = <110000>; 5087 hysteresis = <1000>; 5088 type = "critical"; 5089 }; 5090 }; 5091 }; 5092 5093 cpu3-thermal { 5094 polling-delay-passive = <250>; 5095 polling-delay = <1000>; 5096 5097 thermal-sensors = <&tsens0 4>; 5098 5099 trips { 5100 cpu-crit { 5101 temperature = <110000>; 5102 hysteresis = <1000>; 5103 type = "critical"; 5104 }; 5105 }; 5106 }; 5107 5108 cpu4-thermal { 5109 polling-delay-passive = <250>; 5110 polling-delay = <1000>; 5111 5112 thermal-sensors = <&tsens0 5>; 5113 5114 trips { 5115 cpu-crit { 5116 temperature = <110000>; 5117 hysteresis = <1000>; 5118 type = "critical"; 5119 }; 5120 }; 5121 }; 5122 5123 cpu5-thermal { 5124 polling-delay-passive = <250>; 5125 polling-delay = <1000>; 5126 5127 thermal-sensors = <&tsens0 6>; 5128 5129 trips { 5130 cpu-crit { 5131 temperature = <110000>; 5132 hysteresis = <1000>; 5133 type = "critical"; 5134 }; 5135 }; 5136 }; 5137 5138 cpu6-thermal { 5139 polling-delay-passive = <250>; 5140 polling-delay = <1000>; 5141 5142 thermal-sensors = <&tsens0 7>; 5143 5144 trips { 5145 cpu-crit { 5146 temperature = <110000>; 5147 hysteresis = <1000>; 5148 type = "critical"; 5149 }; 5150 }; 5151 }; 5152 5153 cpu7-thermal { 5154 polling-delay-passive = <250>; 5155 polling-delay = <1000>; 5156 5157 thermal-sensors = <&tsens0 8>; 5158 5159 trips { 5160 cpu-crit { 5161 temperature = <110000>; 5162 hysteresis = <1000>; 5163 type = "critical"; 5164 }; 5165 }; 5166 }; 5167 5168 cluster0-thermal { 5169 polling-delay-passive = <250>; 5170 polling-delay = <1000>; 5171 5172 thermal-sensors = <&tsens0 9>; 5173 5174 trips { 5175 cpu-crit { 5176 temperature = <110000>; 5177 hysteresis = <1000>; 5178 type = "critical"; 5179 }; 5180 }; 5181 }; 5182 5183 mem-thermal { 5184 polling-delay-passive = <250>; 5185 polling-delay = <1000>; 5186 5187 thermal-sensors = <&tsens1 15>; 5188 5189 trips { 5190 trip-point0 { 5191 temperature = <90000>; 5192 hysteresis = <2000>; 5193 type = "hot"; 5194 }; 5195 }; 5196 }; 5197 }; 5198 5199 timer { 5200 compatible = "arm,armv8-timer"; 5201 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5202 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5203 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5204 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5205 }; 5206}; 5207