1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include <linux/sched/mm.h> 31 32 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 33 #define AMDGPU_MES_MAX_GFX_PIPES 2 34 #define AMDGPU_MES_MAX_SDMA_PIPES 2 35 36 #define AMDGPU_MES_API_VERSION_SHIFT 12 37 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 38 39 #define AMDGPU_MES_VERSION_MASK 0x00000fff 40 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 41 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 42 43 enum amdgpu_mes_priority_level { 44 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 45 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 46 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 47 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 48 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 49 AMDGPU_MES_PRIORITY_NUM_LEVELS 50 }; 51 52 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 53 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 54 55 struct amdgpu_mes_funcs; 56 57 enum admgpu_mes_pipe { 58 AMDGPU_MES_SCHED_PIPE = 0, 59 AMDGPU_MES_KIQ_PIPE, 60 AMDGPU_MAX_MES_PIPES = 2, 61 }; 62 63 struct amdgpu_mes { 64 struct amdgpu_device *adev; 65 66 struct mutex mutex_hidden; 67 68 struct idr pasid_idr; 69 struct idr gang_id_idr; 70 struct idr queue_id_idr; 71 struct ida doorbell_ida; 72 73 spinlock_t queue_id_lock; 74 75 uint32_t sched_version; 76 uint32_t kiq_version; 77 78 uint32_t total_max_queue; 79 uint32_t doorbell_id_offset; 80 uint32_t max_doorbell_slices; 81 82 uint64_t default_process_quantum; 83 uint64_t default_gang_quantum; 84 85 struct amdgpu_ring ring; 86 spinlock_t ring_lock; 87 88 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 89 90 /* mes ucode */ 91 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES]; 92 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 93 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES]; 94 uint32_t ucode_fw_version[AMDGPU_MAX_MES_PIPES]; 95 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 96 97 /* mes ucode data */ 98 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES]; 99 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 100 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES]; 101 uint32_t data_fw_version[AMDGPU_MAX_MES_PIPES]; 102 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 103 104 /* eop gpu obj */ 105 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES]; 106 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES]; 107 108 void *mqd_backup[AMDGPU_MAX_MES_PIPES]; 109 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES]; 110 111 uint32_t vmid_mask_gfxhub; 112 uint32_t vmid_mask_mmhub; 113 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 114 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 115 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 116 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 117 uint32_t sch_ctx_offs; 118 uint64_t sch_ctx_gpu_addr; 119 uint64_t *sch_ctx_ptr; 120 uint32_t query_status_fence_offs; 121 uint64_t query_status_fence_gpu_addr; 122 uint64_t *query_status_fence_ptr; 123 uint32_t read_val_offs; 124 uint64_t read_val_gpu_addr; 125 uint32_t *read_val_ptr; 126 127 uint32_t saved_flags; 128 129 /* initialize kiq pipe */ 130 int (*kiq_hw_init)(struct amdgpu_device *adev); 131 int (*kiq_hw_fini)(struct amdgpu_device *adev); 132 133 /* ip specific functions */ 134 const struct amdgpu_mes_funcs *funcs; 135 }; 136 137 struct amdgpu_mes_process { 138 int pasid; 139 struct amdgpu_vm *vm; 140 uint64_t pd_gpu_addr; 141 struct amdgpu_bo *proc_ctx_bo; 142 uint64_t proc_ctx_gpu_addr; 143 void *proc_ctx_cpu_ptr; 144 uint64_t process_quantum; 145 struct list_head gang_list; 146 uint32_t doorbell_index; 147 unsigned long *doorbell_bitmap; 148 struct mutex doorbell_lock; 149 }; 150 151 struct amdgpu_mes_gang { 152 int gang_id; 153 int priority; 154 int inprocess_gang_priority; 155 int global_priority_level; 156 struct list_head list; 157 struct amdgpu_mes_process *process; 158 struct amdgpu_bo *gang_ctx_bo; 159 uint64_t gang_ctx_gpu_addr; 160 void *gang_ctx_cpu_ptr; 161 uint64_t gang_quantum; 162 struct list_head queue_list; 163 }; 164 165 struct amdgpu_mes_queue { 166 struct list_head list; 167 struct amdgpu_mes_gang *gang; 168 int queue_id; 169 uint64_t doorbell_off; 170 struct amdgpu_bo *mqd_obj; 171 void *mqd_cpu_ptr; 172 uint64_t mqd_gpu_addr; 173 uint64_t wptr_gpu_addr; 174 int queue_type; 175 int paging; 176 struct amdgpu_ring *ring; 177 }; 178 179 struct amdgpu_mes_queue_properties { 180 int queue_type; 181 uint64_t hqd_base_gpu_addr; 182 uint64_t rptr_gpu_addr; 183 uint64_t wptr_gpu_addr; 184 uint64_t wptr_mc_addr; 185 uint32_t queue_size; 186 uint64_t eop_gpu_addr; 187 uint32_t hqd_pipe_priority; 188 uint32_t hqd_queue_priority; 189 bool paging; 190 struct amdgpu_ring *ring; 191 /* out */ 192 uint64_t doorbell_off; 193 }; 194 195 struct amdgpu_mes_gang_properties { 196 uint32_t priority; 197 uint32_t gang_quantum; 198 uint32_t inprocess_gang_priority; 199 uint32_t priority_level; 200 int global_priority_level; 201 }; 202 203 struct mes_add_queue_input { 204 uint32_t process_id; 205 uint64_t page_table_base_addr; 206 uint64_t process_va_start; 207 uint64_t process_va_end; 208 uint64_t process_quantum; 209 uint64_t process_context_addr; 210 uint64_t gang_quantum; 211 uint64_t gang_context_addr; 212 uint32_t inprocess_gang_priority; 213 uint32_t gang_global_priority_level; 214 uint32_t doorbell_offset; 215 uint64_t mqd_addr; 216 uint64_t wptr_addr; 217 uint64_t wptr_mc_addr; 218 uint32_t queue_type; 219 uint32_t paging; 220 uint32_t gws_base; 221 uint32_t gws_size; 222 uint64_t tba_addr; 223 uint64_t tma_addr; 224 uint32_t is_kfd_process; 225 uint32_t is_aql_queue; 226 uint32_t queue_size; 227 }; 228 229 struct mes_remove_queue_input { 230 uint32_t doorbell_offset; 231 uint64_t gang_context_addr; 232 }; 233 234 struct mes_unmap_legacy_queue_input { 235 enum amdgpu_unmap_queues_action action; 236 uint32_t queue_type; 237 uint32_t doorbell_offset; 238 uint32_t pipe_id; 239 uint32_t queue_id; 240 uint64_t trail_fence_addr; 241 uint64_t trail_fence_data; 242 }; 243 244 struct mes_suspend_gang_input { 245 bool suspend_all_gangs; 246 uint64_t gang_context_addr; 247 uint64_t suspend_fence_addr; 248 uint32_t suspend_fence_value; 249 }; 250 251 struct mes_resume_gang_input { 252 bool resume_all_gangs; 253 uint64_t gang_context_addr; 254 }; 255 256 enum mes_misc_opcode { 257 MES_MISC_OP_WRITE_REG, 258 MES_MISC_OP_READ_REG, 259 MES_MISC_OP_WRM_REG_WAIT, 260 MES_MISC_OP_WRM_REG_WR_WAIT, 261 }; 262 263 struct mes_misc_op_input { 264 enum mes_misc_opcode op; 265 266 union { 267 struct { 268 uint32_t reg_offset; 269 uint64_t buffer_addr; 270 } read_reg; 271 272 struct { 273 uint32_t reg_offset; 274 uint32_t reg_value; 275 } write_reg; 276 277 struct { 278 uint32_t ref; 279 uint32_t mask; 280 uint32_t reg0; 281 uint32_t reg1; 282 } wrm_reg; 283 }; 284 }; 285 286 struct amdgpu_mes_funcs { 287 int (*add_hw_queue)(struct amdgpu_mes *mes, 288 struct mes_add_queue_input *input); 289 290 int (*remove_hw_queue)(struct amdgpu_mes *mes, 291 struct mes_remove_queue_input *input); 292 293 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 294 struct mes_unmap_legacy_queue_input *input); 295 296 int (*suspend_gang)(struct amdgpu_mes *mes, 297 struct mes_suspend_gang_input *input); 298 299 int (*resume_gang)(struct amdgpu_mes *mes, 300 struct mes_resume_gang_input *input); 301 302 int (*misc_op)(struct amdgpu_mes *mes, 303 struct mes_misc_op_input *input); 304 }; 305 306 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) 307 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev)) 308 309 int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs); 310 311 int amdgpu_mes_init(struct amdgpu_device *adev); 312 void amdgpu_mes_fini(struct amdgpu_device *adev); 313 314 int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid, 315 struct amdgpu_vm *vm); 316 void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid); 317 318 int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid, 319 struct amdgpu_mes_gang_properties *gprops, 320 int *gang_id); 321 int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id); 322 323 int amdgpu_mes_suspend(struct amdgpu_device *adev); 324 int amdgpu_mes_resume(struct amdgpu_device *adev); 325 326 int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, 327 struct amdgpu_mes_queue_properties *qprops, 328 int *queue_id); 329 int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id); 330 331 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 332 struct amdgpu_ring *ring, 333 enum amdgpu_unmap_queues_action action, 334 u64 gpu_addr, u64 seq); 335 336 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); 337 int amdgpu_mes_wreg(struct amdgpu_device *adev, 338 uint32_t reg, uint32_t val); 339 int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, 340 uint32_t val, uint32_t mask); 341 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 342 uint32_t reg0, uint32_t reg1, 343 uint32_t ref, uint32_t mask); 344 345 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id, 346 int queue_type, int idx, 347 struct amdgpu_mes_ctx_data *ctx_data, 348 struct amdgpu_ring **out); 349 void amdgpu_mes_remove_ring(struct amdgpu_device *adev, 350 struct amdgpu_ring *ring); 351 352 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 353 enum amdgpu_mes_priority_level prio); 354 355 int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, 356 struct amdgpu_mes_ctx_data *ctx_data); 357 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data); 358 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev, 359 struct amdgpu_vm *vm, 360 struct amdgpu_mes_ctx_data *ctx_data); 361 int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev, 362 struct amdgpu_mes_ctx_data *ctx_data); 363 364 int amdgpu_mes_self_test(struct amdgpu_device *adev); 365 366 int amdgpu_mes_alloc_process_doorbells(struct amdgpu_device *adev, 367 unsigned int *doorbell_index); 368 void amdgpu_mes_free_process_doorbells(struct amdgpu_device *adev, 369 unsigned int doorbell_index); 370 unsigned int amdgpu_mes_get_doorbell_dw_offset_in_bar( 371 struct amdgpu_device *adev, 372 uint32_t doorbell_index, 373 unsigned int doorbell_id); 374 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 375 376 /* 377 * MES lock can be taken in MMU notifiers. 378 * 379 * A bit more detail about why to set no-FS reclaim with MES lock: 380 * 381 * The purpose of the MMU notifier is to stop GPU access to memory so 382 * that the Linux VM subsystem can move pages around safely. This is 383 * done by preempting user mode queues for the affected process. When 384 * MES is used, MES lock needs to be taken to preempt the queues. 385 * 386 * The MMU notifier callback entry point in the driver is 387 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 388 * there is: 389 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 390 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 391 * 392 * The last part of the chain is a function pointer where we take the 393 * MES lock. 394 * 395 * The problem with taking locks in the MMU notifier is, that MMU 396 * notifiers can be called in reclaim-FS context. That's where the 397 * kernel frees up pages to make room for new page allocations under 398 * memory pressure. While we are running in reclaim-FS context, we must 399 * not trigger another memory reclaim operation because that would 400 * recursively reenter the reclaim code and cause a deadlock. The 401 * memalloc_nofs_save/restore calls guarantee that. 402 * 403 * In addition we also need to avoid lock dependencies on other locks taken 404 * under the MES lock, for example reservation locks. Here is a possible 405 * scenario of a deadlock: 406 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 407 * MMU notifier | blocks trying to take MES lock 408 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 409 * 410 * In this scenario Thread B gets involved in a deadlock even without 411 * triggering a reclaim-FS operation itself. 412 * To fix this and break the lock dependency chain you'd need to either: 413 * 1. protect reservation locks with memalloc_nofs_save/restore, or 414 * 2. avoid taking reservation locks under the MES lock. 415 * 416 * Reservation locks are taken all over the kernel in different subsystems, we 417 * have no control over them and their lock dependencies.So the only workable 418 * solution is to avoid taking other locks under the MES lock. 419 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 420 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 421 */ 422 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 423 { 424 mutex_lock(&mes->mutex_hidden); 425 mes->saved_flags = memalloc_noreclaim_save(); 426 } 427 428 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 429 { 430 memalloc_noreclaim_restore(mes->saved_flags); 431 mutex_unlock(&mes->mutex_hidden); 432 } 433 #endif /* __AMDGPU_MES_H__ */ 434