1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm PCIe Endpoint controller driver 4 * 5 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 6 * Author: Siddartha Mohanadoss <smohanad@codeaurora.org 7 * 8 * Copyright (c) 2021, Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_domain.h> 20 #include <linux/regmap.h> 21 #include <linux/reset.h> 22 #include <linux/module.h> 23 24 #include "pcie-designware.h" 25 26 /* PARF registers */ 27 #define PARF_SYS_CTRL 0x00 28 #define PARF_DB_CTRL 0x10 29 #define PARF_PM_CTRL 0x20 30 #define PARF_MHI_CLOCK_RESET_CTRL 0x174 31 #define PARF_MHI_BASE_ADDR_LOWER 0x178 32 #define PARF_MHI_BASE_ADDR_UPPER 0x17c 33 #define PARF_DEBUG_INT_EN 0x190 34 #define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a4 35 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a8 36 #define PARF_Q2A_FLUSH 0x1ac 37 #define PARF_LTSSM 0x1b0 38 #define PARF_CFG_BITS 0x210 39 #define PARF_INT_ALL_STATUS 0x224 40 #define PARF_INT_ALL_CLEAR 0x228 41 #define PARF_INT_ALL_MASK 0x22c 42 #define PARF_SLV_ADDR_MSB_CTRL 0x2c0 43 #define PARF_DBI_BASE_ADDR 0x350 44 #define PARF_DBI_BASE_ADDR_HI 0x354 45 #define PARF_SLV_ADDR_SPACE_SIZE 0x358 46 #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c 47 #define PARF_ATU_BASE_ADDR 0x634 48 #define PARF_ATU_BASE_ADDR_HI 0x638 49 #define PARF_SRIS_MODE 0x644 50 #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 51 #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c 52 #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 53 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 54 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 55 #define PARF_DEVICE_TYPE 0x1000 56 #define PARF_BDF_TO_SID_CFG 0x2c00 57 58 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ 59 #define PARF_INT_ALL_LINK_DOWN BIT(1) 60 #define PARF_INT_ALL_BME BIT(2) 61 #define PARF_INT_ALL_PM_TURNOFF BIT(3) 62 #define PARF_INT_ALL_DEBUG BIT(4) 63 #define PARF_INT_ALL_LTR BIT(5) 64 #define PARF_INT_ALL_MHI_Q6 BIT(6) 65 #define PARF_INT_ALL_MHI_A7 BIT(7) 66 #define PARF_INT_ALL_DSTATE_CHANGE BIT(8) 67 #define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9) 68 #define PARF_INT_ALL_MMIO_WRITE BIT(10) 69 #define PARF_INT_ALL_CFG_WRITE BIT(11) 70 #define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12) 71 #define PARF_INT_ALL_LINK_UP BIT(13) 72 #define PARF_INT_ALL_AER_LEGACY BIT(14) 73 #define PARF_INT_ALL_PLS_ERR BIT(15) 74 #define PARF_INT_ALL_PME_LEGACY BIT(16) 75 #define PARF_INT_ALL_PLS_PME BIT(17) 76 77 /* PARF_BDF_TO_SID_CFG register fields */ 78 #define PARF_BDF_TO_SID_BYPASS BIT(0) 79 80 /* PARF_DEBUG_INT_EN register fields */ 81 #define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1) 82 #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2) 83 #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3) 84 85 /* PARF_DEVICE_TYPE register fields */ 86 #define PARF_DEVICE_TYPE_EP 0x0 87 88 /* PARF_PM_CTRL register fields */ 89 #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1) 90 #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2) 91 #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5) 92 93 /* PARF_MHI_CLOCK_RESET_CTRL fields */ 94 #define PARF_MSTR_AXI_CLK_EN BIT(1) 95 96 /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */ 97 #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0) 98 99 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ 100 #define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31) 101 102 /* PARF_Q2A_FLUSH register fields */ 103 #define PARF_Q2A_FLUSH_EN BIT(16) 104 105 /* PARF_SYS_CTRL register fields */ 106 #define PARF_SYS_CTRL_AUX_PWR_DET BIT(4) 107 #define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6) 108 #define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10) 109 #define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11) 110 111 /* PARF_DB_CTRL register fields */ 112 #define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0) 113 #define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1) 114 #define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4) 115 #define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5) 116 #define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6) 117 118 /* PARF_CFG_BITS register fields */ 119 #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1) 120 121 /* ELBI registers */ 122 #define ELBI_SYS_STTS 0x08 123 124 /* DBI registers */ 125 #define DBI_CON_STATUS 0x44 126 127 /* DBI register fields */ 128 #define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0) 129 130 #define XMLH_LINK_UP 0x400 131 #define CORE_RESET_TIME_US_MIN 1000 132 #define CORE_RESET_TIME_US_MAX 1005 133 #define WAKE_DELAY_US 2000 /* 2 ms */ 134 135 #define to_pcie_ep(x) dev_get_drvdata((x)->dev) 136 137 enum qcom_pcie_ep_link_status { 138 QCOM_PCIE_EP_LINK_DISABLED, 139 QCOM_PCIE_EP_LINK_ENABLED, 140 QCOM_PCIE_EP_LINK_UP, 141 QCOM_PCIE_EP_LINK_DOWN, 142 }; 143 144 /** 145 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller 146 * @pci: Designware PCIe controller struct 147 * @parf: Qualcomm PCIe specific PARF register base 148 * @elbi: Designware PCIe specific ELBI register base 149 * @mmio: MMIO register base 150 * @perst_map: PERST regmap 151 * @mmio_res: MMIO region resource 152 * @core_reset: PCIe Endpoint core reset 153 * @reset: PERST# GPIO 154 * @wake: WAKE# GPIO 155 * @phy: PHY controller block 156 * @debugfs: PCIe Endpoint Debugfs directory 157 * @clks: PCIe clocks 158 * @num_clks: PCIe clocks count 159 * @perst_en: Flag for PERST enable 160 * @perst_sep_en: Flag for PERST separation enable 161 * @link_status: PCIe Link status 162 * @global_irq: Qualcomm PCIe specific Global IRQ 163 * @perst_irq: PERST# IRQ 164 */ 165 struct qcom_pcie_ep { 166 struct dw_pcie pci; 167 168 void __iomem *parf; 169 void __iomem *elbi; 170 void __iomem *mmio; 171 struct regmap *perst_map; 172 struct resource *mmio_res; 173 174 struct reset_control *core_reset; 175 struct gpio_desc *reset; 176 struct gpio_desc *wake; 177 struct phy *phy; 178 struct dentry *debugfs; 179 180 struct clk_bulk_data *clks; 181 int num_clks; 182 183 u32 perst_en; 184 u32 perst_sep_en; 185 186 enum qcom_pcie_ep_link_status link_status; 187 int global_irq; 188 int perst_irq; 189 }; 190 191 static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep) 192 { 193 struct dw_pcie *pci = &pcie_ep->pci; 194 struct device *dev = pci->dev; 195 int ret; 196 197 ret = reset_control_assert(pcie_ep->core_reset); 198 if (ret) { 199 dev_err(dev, "Cannot assert core reset\n"); 200 return ret; 201 } 202 203 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); 204 205 ret = reset_control_deassert(pcie_ep->core_reset); 206 if (ret) { 207 dev_err(dev, "Cannot de-assert core reset\n"); 208 return ret; 209 } 210 211 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); 212 213 return 0; 214 } 215 216 /* 217 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid 218 * device reset during host reboot and hibernation. The driver is 219 * expected to handle this situation. 220 */ 221 static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep) 222 { 223 if (pcie_ep->perst_map) { 224 regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0); 225 regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0); 226 } 227 } 228 229 static int qcom_pcie_dw_link_up(struct dw_pcie *pci) 230 { 231 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 232 u32 reg; 233 234 reg = readl_relaxed(pcie_ep->elbi + ELBI_SYS_STTS); 235 236 return reg & XMLH_LINK_UP; 237 } 238 239 static int qcom_pcie_dw_start_link(struct dw_pcie *pci) 240 { 241 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 242 243 enable_irq(pcie_ep->perst_irq); 244 245 return 0; 246 } 247 248 static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) 249 { 250 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 251 252 disable_irq(pcie_ep->perst_irq); 253 } 254 255 static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) 256 { 257 int ret; 258 259 ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); 260 if (ret) 261 return ret; 262 263 ret = qcom_pcie_ep_core_reset(pcie_ep); 264 if (ret) 265 goto err_disable_clk; 266 267 ret = phy_init(pcie_ep->phy); 268 if (ret) 269 goto err_disable_clk; 270 271 ret = phy_power_on(pcie_ep->phy); 272 if (ret) 273 goto err_phy_exit; 274 275 return 0; 276 277 err_phy_exit: 278 phy_exit(pcie_ep->phy); 279 err_disable_clk: 280 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); 281 282 return ret; 283 } 284 285 static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) 286 { 287 phy_power_off(pcie_ep->phy); 288 phy_exit(pcie_ep->phy); 289 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); 290 } 291 292 static int qcom_pcie_perst_deassert(struct dw_pcie *pci) 293 { 294 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 295 struct device *dev = pci->dev; 296 u32 val, offset; 297 int ret; 298 299 ret = qcom_pcie_enable_resources(pcie_ep); 300 if (ret) { 301 dev_err(dev, "Failed to enable resources: %d\n", ret); 302 return ret; 303 } 304 305 /* Assert WAKE# to RC to indicate device is ready */ 306 gpiod_set_value_cansleep(pcie_ep->wake, 1); 307 usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500); 308 gpiod_set_value_cansleep(pcie_ep->wake, 0); 309 310 qcom_pcie_ep_configure_tcsr(pcie_ep); 311 312 /* Disable BDF to SID mapping */ 313 val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG); 314 val |= PARF_BDF_TO_SID_BYPASS; 315 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG); 316 317 /* Enable debug IRQ */ 318 val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN); 319 val |= PARF_DEBUG_INT_RADM_PM_TURNOFF | 320 PARF_DEBUG_INT_CFG_BUS_MASTER_EN | 321 PARF_DEBUG_INT_PM_DSTATE_CHANGE; 322 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN); 323 324 /* Configure PCIe to endpoint mode */ 325 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE); 326 327 /* Allow entering L1 state */ 328 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 329 val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1; 330 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 331 332 /* Read halts write */ 333 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES); 334 val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN; 335 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES); 336 337 /* Write after write halt */ 338 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 339 val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN; 340 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 341 342 /* Q2A flush disable */ 343 val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH); 344 val &= ~PARF_Q2A_FLUSH_EN; 345 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH); 346 347 /* 348 * Disable Master AXI clock during idle. Do not allow DBI access 349 * to take the core out of L1. Disable core clock gating that 350 * gates PIPE clock from propagating to core clock. Report to the 351 * host that Vaux is present. 352 */ 353 val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL); 354 val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS; 355 val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE | 356 PARF_SYS_CTRL_CORE_CLK_CGC_DIS | 357 PARF_SYS_CTRL_AUX_PWR_DET; 358 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL); 359 360 /* Disable the debouncers */ 361 val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL); 362 val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK | 363 PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK | 364 PARF_DB_CTRL_MST_WKP_BLOCK; 365 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL); 366 367 /* Request to exit from L1SS for MSI and LTR MSG */ 368 val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS); 369 val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN; 370 writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS); 371 372 dw_pcie_dbi_ro_wr_en(pci); 373 374 /* Set the L0s Exit Latency to 2us-4us = 0x6 */ 375 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 376 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 377 val &= ~PCI_EXP_LNKCAP_L0SEL; 378 val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6); 379 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); 380 381 /* Set the L1 Exit Latency to be 32us-64 us = 0x6 */ 382 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 383 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 384 val &= ~PCI_EXP_LNKCAP_L1EL; 385 val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6); 386 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); 387 388 dw_pcie_dbi_ro_wr_dis(pci); 389 390 writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK); 391 val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME | 392 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE | 393 PARF_INT_ALL_LINK_UP; 394 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK); 395 396 ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep); 397 if (ret) { 398 dev_err(dev, "Failed to complete initialization: %d\n", ret); 399 goto err_disable_resources; 400 } 401 402 /* 403 * The physical address of the MMIO region which is exposed as the BAR 404 * should be written to MHI BASE registers. 405 */ 406 writel_relaxed(pcie_ep->mmio_res->start, 407 pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER); 408 writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER); 409 410 /* Gate Master AXI clock to MHI bus during L1SS */ 411 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); 412 val &= ~PARF_MSTR_AXI_CLK_EN; 413 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); 414 415 dw_pcie_ep_init_notify(&pcie_ep->pci.ep); 416 417 /* Enable LTSSM */ 418 val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); 419 val |= BIT(8); 420 writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); 421 422 return 0; 423 424 err_disable_resources: 425 qcom_pcie_disable_resources(pcie_ep); 426 427 return ret; 428 } 429 430 static void qcom_pcie_perst_assert(struct dw_pcie *pci) 431 { 432 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 433 struct device *dev = pci->dev; 434 435 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) { 436 dev_dbg(dev, "Link is already disabled\n"); 437 return; 438 } 439 440 qcom_pcie_disable_resources(pcie_ep); 441 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED; 442 } 443 444 /* Common DWC controller ops */ 445 static const struct dw_pcie_ops pci_ops = { 446 .link_up = qcom_pcie_dw_link_up, 447 .start_link = qcom_pcie_dw_start_link, 448 .stop_link = qcom_pcie_dw_stop_link, 449 }; 450 451 static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev, 452 struct qcom_pcie_ep *pcie_ep) 453 { 454 struct device *dev = &pdev->dev; 455 struct dw_pcie *pci = &pcie_ep->pci; 456 struct device_node *syscon; 457 struct resource *res; 458 int ret; 459 460 pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); 461 if (IS_ERR(pcie_ep->parf)) 462 return PTR_ERR(pcie_ep->parf); 463 464 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 465 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); 466 if (IS_ERR(pci->dbi_base)) 467 return PTR_ERR(pci->dbi_base); 468 pci->dbi_base2 = pci->dbi_base; 469 470 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); 471 pcie_ep->elbi = devm_pci_remap_cfg_resource(dev, res); 472 if (IS_ERR(pcie_ep->elbi)) 473 return PTR_ERR(pcie_ep->elbi); 474 475 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 476 "mmio"); 477 if (!pcie_ep->mmio_res) { 478 dev_err(dev, "Failed to get mmio resource\n"); 479 return -EINVAL; 480 } 481 482 pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res); 483 if (IS_ERR(pcie_ep->mmio)) 484 return PTR_ERR(pcie_ep->mmio); 485 486 syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0); 487 if (!syscon) { 488 dev_dbg(dev, "PERST separation not available\n"); 489 return 0; 490 } 491 492 pcie_ep->perst_map = syscon_node_to_regmap(syscon); 493 of_node_put(syscon); 494 if (IS_ERR(pcie_ep->perst_map)) 495 return PTR_ERR(pcie_ep->perst_map); 496 497 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs", 498 1, &pcie_ep->perst_en); 499 if (ret < 0) { 500 dev_err(dev, "No Perst Enable offset in syscon\n"); 501 return ret; 502 } 503 504 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs", 505 2, &pcie_ep->perst_sep_en); 506 if (ret < 0) { 507 dev_err(dev, "No Perst Separation Enable offset in syscon\n"); 508 return ret; 509 } 510 511 return 0; 512 } 513 514 static int qcom_pcie_ep_get_resources(struct platform_device *pdev, 515 struct qcom_pcie_ep *pcie_ep) 516 { 517 struct device *dev = &pdev->dev; 518 int ret; 519 520 ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep); 521 if (ret) { 522 dev_err(dev, "Failed to get io resources %d\n", ret); 523 return ret; 524 } 525 526 pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks); 527 if (pcie_ep->num_clks < 0) { 528 dev_err(dev, "Failed to get clocks\n"); 529 return pcie_ep->num_clks; 530 } 531 532 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core"); 533 if (IS_ERR(pcie_ep->core_reset)) 534 return PTR_ERR(pcie_ep->core_reset); 535 536 pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN); 537 if (IS_ERR(pcie_ep->reset)) 538 return PTR_ERR(pcie_ep->reset); 539 540 pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW); 541 if (IS_ERR(pcie_ep->wake)) 542 return PTR_ERR(pcie_ep->wake); 543 544 pcie_ep->phy = devm_phy_optional_get(dev, "pciephy"); 545 if (IS_ERR(pcie_ep->phy)) 546 ret = PTR_ERR(pcie_ep->phy); 547 548 return ret; 549 } 550 551 /* TODO: Notify clients about PCIe state change */ 552 static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) 553 { 554 struct qcom_pcie_ep *pcie_ep = data; 555 struct dw_pcie *pci = &pcie_ep->pci; 556 struct device *dev = pci->dev; 557 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); 558 u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK); 559 u32 dstate, val; 560 561 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); 562 status &= mask; 563 564 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { 565 dev_dbg(dev, "Received Linkdown event\n"); 566 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN; 567 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { 568 dev_dbg(dev, "Received BME event. Link is enabled!\n"); 569 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED; 570 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { 571 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n"); 572 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 573 val |= PARF_PM_CTRL_READY_ENTR_L23; 574 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 575 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) { 576 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) & 577 DBI_CON_STATUS_POWER_STATE_MASK; 578 dev_dbg(dev, "Received D%d state event\n", dstate); 579 if (dstate == 3) { 580 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 581 val |= PARF_PM_CTRL_REQ_EXIT_L1; 582 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 583 } 584 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { 585 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n"); 586 dw_pcie_ep_linkup(&pci->ep); 587 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP; 588 } else { 589 dev_dbg(dev, "Received unknown event: %d\n", status); 590 } 591 592 return IRQ_HANDLED; 593 } 594 595 static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data) 596 { 597 struct qcom_pcie_ep *pcie_ep = data; 598 struct dw_pcie *pci = &pcie_ep->pci; 599 struct device *dev = pci->dev; 600 u32 perst; 601 602 perst = gpiod_get_value(pcie_ep->reset); 603 if (perst) { 604 dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n"); 605 qcom_pcie_perst_assert(pci); 606 } else { 607 dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n"); 608 qcom_pcie_perst_deassert(pci); 609 } 610 611 irq_set_irq_type(gpiod_to_irq(pcie_ep->reset), 612 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW)); 613 614 return IRQ_HANDLED; 615 } 616 617 static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, 618 struct qcom_pcie_ep *pcie_ep) 619 { 620 int ret; 621 622 pcie_ep->global_irq = platform_get_irq_byname(pdev, "global"); 623 if (pcie_ep->global_irq < 0) 624 return pcie_ep->global_irq; 625 626 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL, 627 qcom_pcie_ep_global_irq_thread, 628 IRQF_ONESHOT, 629 "global_irq", pcie_ep); 630 if (ret) { 631 dev_err(&pdev->dev, "Failed to request Global IRQ\n"); 632 return ret; 633 } 634 635 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); 636 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); 637 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, 638 qcom_pcie_ep_perst_irq_thread, 639 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 640 "perst_irq", pcie_ep); 641 if (ret) { 642 dev_err(&pdev->dev, "Failed to request PERST IRQ\n"); 643 disable_irq(pcie_ep->global_irq); 644 return ret; 645 } 646 647 return 0; 648 } 649 650 static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 651 enum pci_epc_irq_type type, u16 interrupt_num) 652 { 653 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 654 655 switch (type) { 656 case PCI_EPC_IRQ_LEGACY: 657 return dw_pcie_ep_raise_legacy_irq(ep, func_no); 658 case PCI_EPC_IRQ_MSI: 659 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 660 default: 661 dev_err(pci->dev, "Unknown IRQ type\n"); 662 return -EINVAL; 663 } 664 } 665 666 static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data) 667 { 668 struct qcom_pcie_ep *pcie_ep = (struct qcom_pcie_ep *) 669 dev_get_drvdata(s->private); 670 671 seq_printf(s, "L0s transition count: %u\n", 672 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); 673 674 seq_printf(s, "L1 transition count: %u\n", 675 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); 676 677 seq_printf(s, "L1.1 transition count: %u\n", 678 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); 679 680 seq_printf(s, "L1.2 transition count: %u\n", 681 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); 682 683 seq_printf(s, "L2 transition count: %u\n", 684 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); 685 686 return 0; 687 } 688 689 static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep) 690 { 691 struct dw_pcie *pci = &pcie_ep->pci; 692 693 debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie_ep->debugfs, 694 qcom_pcie_ep_link_transition_count); 695 } 696 697 static const struct pci_epc_features qcom_pcie_epc_features = { 698 .linkup_notifier = true, 699 .core_init_notifier = true, 700 .msi_capable = true, 701 .msix_capable = false, 702 }; 703 704 static const struct pci_epc_features * 705 qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep) 706 { 707 return &qcom_pcie_epc_features; 708 } 709 710 static void qcom_pcie_ep_init(struct dw_pcie_ep *ep) 711 { 712 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 713 enum pci_barno bar; 714 715 for (bar = BAR_0; bar <= BAR_5; bar++) 716 dw_pcie_ep_reset_bar(pci, bar); 717 } 718 719 static const struct dw_pcie_ep_ops pci_ep_ops = { 720 .ep_init = qcom_pcie_ep_init, 721 .raise_irq = qcom_pcie_ep_raise_irq, 722 .get_features = qcom_pcie_epc_get_features, 723 }; 724 725 static int qcom_pcie_ep_probe(struct platform_device *pdev) 726 { 727 struct device *dev = &pdev->dev; 728 struct qcom_pcie_ep *pcie_ep; 729 char *name; 730 int ret; 731 732 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL); 733 if (!pcie_ep) 734 return -ENOMEM; 735 736 pcie_ep->pci.dev = dev; 737 pcie_ep->pci.ops = &pci_ops; 738 pcie_ep->pci.ep.ops = &pci_ep_ops; 739 platform_set_drvdata(pdev, pcie_ep); 740 741 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); 742 if (ret) 743 return ret; 744 745 ret = qcom_pcie_enable_resources(pcie_ep); 746 if (ret) { 747 dev_err(dev, "Failed to enable resources: %d\n", ret); 748 return ret; 749 } 750 751 ret = dw_pcie_ep_init(&pcie_ep->pci.ep); 752 if (ret) { 753 dev_err(dev, "Failed to initialize endpoint: %d\n", ret); 754 goto err_disable_resources; 755 } 756 757 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep); 758 if (ret) 759 goto err_disable_resources; 760 761 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); 762 if (!name) { 763 ret = -ENOMEM; 764 goto err_disable_irqs; 765 } 766 767 pcie_ep->debugfs = debugfs_create_dir(name, NULL); 768 qcom_pcie_ep_init_debugfs(pcie_ep); 769 770 return 0; 771 772 err_disable_irqs: 773 disable_irq(pcie_ep->global_irq); 774 disable_irq(pcie_ep->perst_irq); 775 776 err_disable_resources: 777 qcom_pcie_disable_resources(pcie_ep); 778 779 return ret; 780 } 781 782 static int qcom_pcie_ep_remove(struct platform_device *pdev) 783 { 784 struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev); 785 786 disable_irq(pcie_ep->global_irq); 787 disable_irq(pcie_ep->perst_irq); 788 789 debugfs_remove_recursive(pcie_ep->debugfs); 790 791 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) 792 return 0; 793 794 qcom_pcie_disable_resources(pcie_ep); 795 796 return 0; 797 } 798 799 static const struct of_device_id qcom_pcie_ep_match[] = { 800 { .compatible = "qcom,sdx55-pcie-ep", }, 801 { .compatible = "qcom,sm8450-pcie-ep", }, 802 { } 803 }; 804 MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match); 805 806 static struct platform_driver qcom_pcie_ep_driver = { 807 .probe = qcom_pcie_ep_probe, 808 .remove = qcom_pcie_ep_remove, 809 .driver = { 810 .name = "qcom-pcie-ep", 811 .of_match_table = qcom_pcie_ep_match, 812 }, 813 }; 814 builtin_platform_driver(qcom_pcie_ep_driver); 815 816 MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>"); 817 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 818 MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver"); 819 MODULE_LICENSE("GPL v2"); 820