1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gcc-sdm845.h> 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12#include <dt-bindings/clock/qcom,lpass-sdm845.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sdm845.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sdm845.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/phy/phy-qcom-qusb2.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/reset/qcom,sdm845-aoss.h> 21#include <dt-bindings/reset/qcom,sdm845-pdc.h> 22#include <dt-bindings/soc/qcom,apr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/clock/qcom,gcc-sdm845.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 aliases { 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 i2c8 = &i2c8; 43 i2c9 = &i2c9; 44 i2c10 = &i2c10; 45 i2c11 = &i2c11; 46 i2c12 = &i2c12; 47 i2c13 = &i2c13; 48 i2c14 = &i2c14; 49 i2c15 = &i2c15; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 spi4 = &spi4; 55 spi5 = &spi5; 56 spi6 = &spi6; 57 spi7 = &spi7; 58 spi8 = &spi8; 59 spi9 = &spi9; 60 spi10 = &spi10; 61 spi11 = &spi11; 62 spi12 = &spi12; 63 spi13 = &spi13; 64 spi14 = &spi14; 65 spi15 = &spi15; 66 }; 67 68 chosen { }; 69 70 memory@80000000 { 71 device_type = "memory"; 72 /* We expect the bootloader to fill in the size */ 73 reg = <0 0x80000000 0 0>; 74 }; 75 76 reserved-memory { 77 #address-cells = <2>; 78 #size-cells = <2>; 79 ranges; 80 81 hyp_mem: memory@85700000 { 82 reg = <0 0x85700000 0 0x600000>; 83 no-map; 84 }; 85 86 xbl_mem: memory@85e00000 { 87 reg = <0 0x85e00000 0 0x100000>; 88 no-map; 89 }; 90 91 aop_mem: memory@85fc0000 { 92 reg = <0 0x85fc0000 0 0x20000>; 93 no-map; 94 }; 95 96 aop_cmd_db_mem: memory@85fe0000 { 97 compatible = "qcom,cmd-db"; 98 reg = <0x0 0x85fe0000 0 0x20000>; 99 no-map; 100 }; 101 102 smem_mem: memory@86000000 { 103 reg = <0x0 0x86000000 0 0x200000>; 104 no-map; 105 }; 106 107 tz_mem: memory@86200000 { 108 reg = <0 0x86200000 0 0x2d00000>; 109 no-map; 110 }; 111 112 rmtfs_mem: memory@88f00000 { 113 compatible = "qcom,rmtfs-mem"; 114 reg = <0 0x88f00000 0 0x200000>; 115 no-map; 116 117 qcom,client-id = <1>; 118 qcom,vmid = <15>; 119 }; 120 121 qseecom_mem: memory@8ab00000 { 122 reg = <0 0x8ab00000 0 0x1400000>; 123 no-map; 124 }; 125 126 camera_mem: memory@8bf00000 { 127 reg = <0 0x8bf00000 0 0x500000>; 128 no-map; 129 }; 130 131 wlan_msa_mem: memory@8c400000 { 132 reg = <0 0x8c400000 0 0x100000>; 133 no-map; 134 }; 135 136 gpu_mem: memory@8c515000 { 137 reg = <0 0x8c515000 0 0x2000>; 138 no-map; 139 }; 140 141 ipa_fw_mem: memory@8c517000 { 142 reg = <0 0x8c517000 0 0x5a000>; 143 no-map; 144 }; 145 146 adsp_mem: memory@8c600000 { 147 reg = <0 0x8c600000 0 0x1a00000>; 148 no-map; 149 }; 150 151 mpss_region: memory@8e000000 { 152 reg = <0 0x8e000000 0 0x7800000>; 153 no-map; 154 }; 155 156 venus_mem: memory@95800000 { 157 reg = <0 0x95800000 0 0x500000>; 158 no-map; 159 }; 160 161 cdsp_mem: memory@95d00000 { 162 reg = <0 0x95d00000 0 0x800000>; 163 no-map; 164 }; 165 166 mba_region: memory@96500000 { 167 reg = <0 0x96500000 0 0x200000>; 168 no-map; 169 }; 170 171 slpi_mem: memory@96700000 { 172 reg = <0 0x96700000 0 0x1400000>; 173 no-map; 174 }; 175 176 spss_mem: memory@97b00000 { 177 reg = <0 0x97b00000 0 0x100000>; 178 no-map; 179 }; 180 }; 181 182 cpus { 183 #address-cells = <2>; 184 #size-cells = <0>; 185 186 CPU0: cpu@0 { 187 device_type = "cpu"; 188 compatible = "qcom,kryo385"; 189 reg = <0x0 0x0>; 190 enable-method = "psci"; 191 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 192 &LITTLE_CPU_SLEEP_1 193 &CLUSTER_SLEEP_0>; 194 capacity-dmips-mhz = <607>; 195 dynamic-power-coefficient = <100>; 196 qcom,freq-domain = <&cpufreq_hw 0>; 197 operating-points-v2 = <&cpu0_opp_table>; 198 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 199 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 200 #cooling-cells = <2>; 201 next-level-cache = <&L2_0>; 202 L2_0: l2-cache { 203 compatible = "cache"; 204 next-level-cache = <&L3_0>; 205 L3_0: l3-cache { 206 compatible = "cache"; 207 }; 208 }; 209 }; 210 211 CPU1: cpu@100 { 212 device_type = "cpu"; 213 compatible = "qcom,kryo385"; 214 reg = <0x0 0x100>; 215 enable-method = "psci"; 216 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 217 &LITTLE_CPU_SLEEP_1 218 &CLUSTER_SLEEP_0>; 219 capacity-dmips-mhz = <607>; 220 dynamic-power-coefficient = <100>; 221 qcom,freq-domain = <&cpufreq_hw 0>; 222 operating-points-v2 = <&cpu0_opp_table>; 223 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 224 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 225 #cooling-cells = <2>; 226 next-level-cache = <&L2_100>; 227 L2_100: l2-cache { 228 compatible = "cache"; 229 next-level-cache = <&L3_0>; 230 }; 231 }; 232 233 CPU2: cpu@200 { 234 device_type = "cpu"; 235 compatible = "qcom,kryo385"; 236 reg = <0x0 0x200>; 237 enable-method = "psci"; 238 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 239 &LITTLE_CPU_SLEEP_1 240 &CLUSTER_SLEEP_0>; 241 capacity-dmips-mhz = <607>; 242 dynamic-power-coefficient = <100>; 243 qcom,freq-domain = <&cpufreq_hw 0>; 244 operating-points-v2 = <&cpu0_opp_table>; 245 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 246 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 247 #cooling-cells = <2>; 248 next-level-cache = <&L2_200>; 249 L2_200: l2-cache { 250 compatible = "cache"; 251 next-level-cache = <&L3_0>; 252 }; 253 }; 254 255 CPU3: cpu@300 { 256 device_type = "cpu"; 257 compatible = "qcom,kryo385"; 258 reg = <0x0 0x300>; 259 enable-method = "psci"; 260 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 261 &LITTLE_CPU_SLEEP_1 262 &CLUSTER_SLEEP_0>; 263 capacity-dmips-mhz = <607>; 264 dynamic-power-coefficient = <100>; 265 qcom,freq-domain = <&cpufreq_hw 0>; 266 operating-points-v2 = <&cpu0_opp_table>; 267 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 268 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 269 #cooling-cells = <2>; 270 next-level-cache = <&L2_300>; 271 L2_300: l2-cache { 272 compatible = "cache"; 273 next-level-cache = <&L3_0>; 274 }; 275 }; 276 277 CPU4: cpu@400 { 278 device_type = "cpu"; 279 compatible = "qcom,kryo385"; 280 reg = <0x0 0x400>; 281 enable-method = "psci"; 282 capacity-dmips-mhz = <1024>; 283 cpu-idle-states = <&BIG_CPU_SLEEP_0 284 &BIG_CPU_SLEEP_1 285 &CLUSTER_SLEEP_0>; 286 dynamic-power-coefficient = <396>; 287 qcom,freq-domain = <&cpufreq_hw 1>; 288 operating-points-v2 = <&cpu4_opp_table>; 289 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 290 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 291 #cooling-cells = <2>; 292 next-level-cache = <&L2_400>; 293 L2_400: l2-cache { 294 compatible = "cache"; 295 next-level-cache = <&L3_0>; 296 }; 297 }; 298 299 CPU5: cpu@500 { 300 device_type = "cpu"; 301 compatible = "qcom,kryo385"; 302 reg = <0x0 0x500>; 303 enable-method = "psci"; 304 capacity-dmips-mhz = <1024>; 305 cpu-idle-states = <&BIG_CPU_SLEEP_0 306 &BIG_CPU_SLEEP_1 307 &CLUSTER_SLEEP_0>; 308 dynamic-power-coefficient = <396>; 309 qcom,freq-domain = <&cpufreq_hw 1>; 310 operating-points-v2 = <&cpu4_opp_table>; 311 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 312 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 313 #cooling-cells = <2>; 314 next-level-cache = <&L2_500>; 315 L2_500: l2-cache { 316 compatible = "cache"; 317 next-level-cache = <&L3_0>; 318 }; 319 }; 320 321 CPU6: cpu@600 { 322 device_type = "cpu"; 323 compatible = "qcom,kryo385"; 324 reg = <0x0 0x600>; 325 enable-method = "psci"; 326 capacity-dmips-mhz = <1024>; 327 cpu-idle-states = <&BIG_CPU_SLEEP_0 328 &BIG_CPU_SLEEP_1 329 &CLUSTER_SLEEP_0>; 330 dynamic-power-coefficient = <396>; 331 qcom,freq-domain = <&cpufreq_hw 1>; 332 operating-points-v2 = <&cpu4_opp_table>; 333 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 334 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 335 #cooling-cells = <2>; 336 next-level-cache = <&L2_600>; 337 L2_600: l2-cache { 338 compatible = "cache"; 339 next-level-cache = <&L3_0>; 340 }; 341 }; 342 343 CPU7: cpu@700 { 344 device_type = "cpu"; 345 compatible = "qcom,kryo385"; 346 reg = <0x0 0x700>; 347 enable-method = "psci"; 348 capacity-dmips-mhz = <1024>; 349 cpu-idle-states = <&BIG_CPU_SLEEP_0 350 &BIG_CPU_SLEEP_1 351 &CLUSTER_SLEEP_0>; 352 dynamic-power-coefficient = <396>; 353 qcom,freq-domain = <&cpufreq_hw 1>; 354 operating-points-v2 = <&cpu4_opp_table>; 355 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 356 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 357 #cooling-cells = <2>; 358 next-level-cache = <&L2_700>; 359 L2_700: l2-cache { 360 compatible = "cache"; 361 next-level-cache = <&L3_0>; 362 }; 363 }; 364 365 cpu-map { 366 cluster0 { 367 core0 { 368 cpu = <&CPU0>; 369 }; 370 371 core1 { 372 cpu = <&CPU1>; 373 }; 374 375 core2 { 376 cpu = <&CPU2>; 377 }; 378 379 core3 { 380 cpu = <&CPU3>; 381 }; 382 383 core4 { 384 cpu = <&CPU4>; 385 }; 386 387 core5 { 388 cpu = <&CPU5>; 389 }; 390 391 core6 { 392 cpu = <&CPU6>; 393 }; 394 395 core7 { 396 cpu = <&CPU7>; 397 }; 398 }; 399 }; 400 401 idle-states { 402 entry-method = "psci"; 403 404 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 405 compatible = "arm,idle-state"; 406 idle-state-name = "little-power-down"; 407 arm,psci-suspend-param = <0x40000003>; 408 entry-latency-us = <350>; 409 exit-latency-us = <461>; 410 min-residency-us = <1890>; 411 local-timer-stop; 412 }; 413 414 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 415 compatible = "arm,idle-state"; 416 idle-state-name = "little-rail-power-down"; 417 arm,psci-suspend-param = <0x40000004>; 418 entry-latency-us = <360>; 419 exit-latency-us = <531>; 420 min-residency-us = <3934>; 421 local-timer-stop; 422 }; 423 424 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 425 compatible = "arm,idle-state"; 426 idle-state-name = "big-power-down"; 427 arm,psci-suspend-param = <0x40000003>; 428 entry-latency-us = <264>; 429 exit-latency-us = <621>; 430 min-residency-us = <952>; 431 local-timer-stop; 432 }; 433 434 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 435 compatible = "arm,idle-state"; 436 idle-state-name = "big-rail-power-down"; 437 arm,psci-suspend-param = <0x40000004>; 438 entry-latency-us = <702>; 439 exit-latency-us = <1061>; 440 min-residency-us = <4488>; 441 local-timer-stop; 442 }; 443 444 CLUSTER_SLEEP_0: cluster-sleep-0 { 445 compatible = "arm,idle-state"; 446 idle-state-name = "cluster-power-down"; 447 arm,psci-suspend-param = <0x400000F4>; 448 entry-latency-us = <3263>; 449 exit-latency-us = <6562>; 450 min-residency-us = <9987>; 451 local-timer-stop; 452 }; 453 }; 454 }; 455 456 cpu0_opp_table: cpu0_opp_table { 457 compatible = "operating-points-v2"; 458 opp-shared; 459 460 cpu0_opp1: opp-300000000 { 461 opp-hz = /bits/ 64 <300000000>; 462 opp-peak-kBps = <800000 4800000>; 463 }; 464 465 cpu0_opp2: opp-403200000 { 466 opp-hz = /bits/ 64 <403200000>; 467 opp-peak-kBps = <800000 4800000>; 468 }; 469 470 cpu0_opp3: opp-480000000 { 471 opp-hz = /bits/ 64 <480000000>; 472 opp-peak-kBps = <800000 6451200>; 473 }; 474 475 cpu0_opp4: opp-576000000 { 476 opp-hz = /bits/ 64 <576000000>; 477 opp-peak-kBps = <800000 6451200>; 478 }; 479 480 cpu0_opp5: opp-652800000 { 481 opp-hz = /bits/ 64 <652800000>; 482 opp-peak-kBps = <800000 7680000>; 483 }; 484 485 cpu0_opp6: opp-748800000 { 486 opp-hz = /bits/ 64 <748800000>; 487 opp-peak-kBps = <1804000 9216000>; 488 }; 489 490 cpu0_opp7: opp-825600000 { 491 opp-hz = /bits/ 64 <825600000>; 492 opp-peak-kBps = <1804000 9216000>; 493 }; 494 495 cpu0_opp8: opp-902400000 { 496 opp-hz = /bits/ 64 <902400000>; 497 opp-peak-kBps = <1804000 10444800>; 498 }; 499 500 cpu0_opp9: opp-979200000 { 501 opp-hz = /bits/ 64 <979200000>; 502 opp-peak-kBps = <1804000 11980800>; 503 }; 504 505 cpu0_opp10: opp-1056000000 { 506 opp-hz = /bits/ 64 <1056000000>; 507 opp-peak-kBps = <1804000 11980800>; 508 }; 509 510 cpu0_opp11: opp-1132800000 { 511 opp-hz = /bits/ 64 <1132800000>; 512 opp-peak-kBps = <2188000 13516800>; 513 }; 514 515 cpu0_opp12: opp-1228800000 { 516 opp-hz = /bits/ 64 <1228800000>; 517 opp-peak-kBps = <2188000 15052800>; 518 }; 519 520 cpu0_opp13: opp-1324800000 { 521 opp-hz = /bits/ 64 <1324800000>; 522 opp-peak-kBps = <2188000 16588800>; 523 }; 524 525 cpu0_opp14: opp-1420800000 { 526 opp-hz = /bits/ 64 <1420800000>; 527 opp-peak-kBps = <3072000 18124800>; 528 }; 529 530 cpu0_opp15: opp-1516800000 { 531 opp-hz = /bits/ 64 <1516800000>; 532 opp-peak-kBps = <3072000 19353600>; 533 }; 534 535 cpu0_opp16: opp-1612800000 { 536 opp-hz = /bits/ 64 <1612800000>; 537 opp-peak-kBps = <4068000 19353600>; 538 }; 539 540 cpu0_opp17: opp-1689600000 { 541 opp-hz = /bits/ 64 <1689600000>; 542 opp-peak-kBps = <4068000 20889600>; 543 }; 544 545 cpu0_opp18: opp-1766400000 { 546 opp-hz = /bits/ 64 <1766400000>; 547 opp-peak-kBps = <4068000 22425600>; 548 }; 549 }; 550 551 cpu4_opp_table: cpu4_opp_table { 552 compatible = "operating-points-v2"; 553 opp-shared; 554 555 cpu4_opp1: opp-300000000 { 556 opp-hz = /bits/ 64 <300000000>; 557 opp-peak-kBps = <800000 4800000>; 558 }; 559 560 cpu4_opp2: opp-403200000 { 561 opp-hz = /bits/ 64 <403200000>; 562 opp-peak-kBps = <800000 4800000>; 563 }; 564 565 cpu4_opp3: opp-480000000 { 566 opp-hz = /bits/ 64 <480000000>; 567 opp-peak-kBps = <1804000 4800000>; 568 }; 569 570 cpu4_opp4: opp-576000000 { 571 opp-hz = /bits/ 64 <576000000>; 572 opp-peak-kBps = <1804000 4800000>; 573 }; 574 575 cpu4_opp5: opp-652800000 { 576 opp-hz = /bits/ 64 <652800000>; 577 opp-peak-kBps = <1804000 4800000>; 578 }; 579 580 cpu4_opp6: opp-748800000 { 581 opp-hz = /bits/ 64 <748800000>; 582 opp-peak-kBps = <1804000 4800000>; 583 }; 584 585 cpu4_opp7: opp-825600000 { 586 opp-hz = /bits/ 64 <825600000>; 587 opp-peak-kBps = <2188000 9216000>; 588 }; 589 590 cpu4_opp8: opp-902400000 { 591 opp-hz = /bits/ 64 <902400000>; 592 opp-peak-kBps = <2188000 9216000>; 593 }; 594 595 cpu4_opp9: opp-979200000 { 596 opp-hz = /bits/ 64 <979200000>; 597 opp-peak-kBps = <2188000 9216000>; 598 }; 599 600 cpu4_opp10: opp-1056000000 { 601 opp-hz = /bits/ 64 <1056000000>; 602 opp-peak-kBps = <3072000 9216000>; 603 }; 604 605 cpu4_opp11: opp-1132800000 { 606 opp-hz = /bits/ 64 <1132800000>; 607 opp-peak-kBps = <3072000 11980800>; 608 }; 609 610 cpu4_opp12: opp-1209600000 { 611 opp-hz = /bits/ 64 <1209600000>; 612 opp-peak-kBps = <4068000 11980800>; 613 }; 614 615 cpu4_opp13: opp-1286400000 { 616 opp-hz = /bits/ 64 <1286400000>; 617 opp-peak-kBps = <4068000 11980800>; 618 }; 619 620 cpu4_opp14: opp-1363200000 { 621 opp-hz = /bits/ 64 <1363200000>; 622 opp-peak-kBps = <4068000 15052800>; 623 }; 624 625 cpu4_opp15: opp-1459200000 { 626 opp-hz = /bits/ 64 <1459200000>; 627 opp-peak-kBps = <4068000 15052800>; 628 }; 629 630 cpu4_opp16: opp-1536000000 { 631 opp-hz = /bits/ 64 <1536000000>; 632 opp-peak-kBps = <5412000 15052800>; 633 }; 634 635 cpu4_opp17: opp-1612800000 { 636 opp-hz = /bits/ 64 <1612800000>; 637 opp-peak-kBps = <5412000 15052800>; 638 }; 639 640 cpu4_opp18: opp-1689600000 { 641 opp-hz = /bits/ 64 <1689600000>; 642 opp-peak-kBps = <5412000 19353600>; 643 }; 644 645 cpu4_opp19: opp-1766400000 { 646 opp-hz = /bits/ 64 <1766400000>; 647 opp-peak-kBps = <6220000 19353600>; 648 }; 649 650 cpu4_opp20: opp-1843200000 { 651 opp-hz = /bits/ 64 <1843200000>; 652 opp-peak-kBps = <6220000 19353600>; 653 }; 654 655 cpu4_opp21: opp-1920000000 { 656 opp-hz = /bits/ 64 <1920000000>; 657 opp-peak-kBps = <7216000 19353600>; 658 }; 659 660 cpu4_opp22: opp-1996800000 { 661 opp-hz = /bits/ 64 <1996800000>; 662 opp-peak-kBps = <7216000 20889600>; 663 }; 664 665 cpu4_opp23: opp-2092800000 { 666 opp-hz = /bits/ 64 <2092800000>; 667 opp-peak-kBps = <7216000 20889600>; 668 }; 669 670 cpu4_opp24: opp-2169600000 { 671 opp-hz = /bits/ 64 <2169600000>; 672 opp-peak-kBps = <7216000 20889600>; 673 }; 674 675 cpu4_opp25: opp-2246400000 { 676 opp-hz = /bits/ 64 <2246400000>; 677 opp-peak-kBps = <7216000 20889600>; 678 }; 679 680 cpu4_opp26: opp-2323200000 { 681 opp-hz = /bits/ 64 <2323200000>; 682 opp-peak-kBps = <7216000 20889600>; 683 }; 684 685 cpu4_opp27: opp-2400000000 { 686 opp-hz = /bits/ 64 <2400000000>; 687 opp-peak-kBps = <7216000 22425600>; 688 }; 689 690 cpu4_opp28: opp-2476800000 { 691 opp-hz = /bits/ 64 <2476800000>; 692 opp-peak-kBps = <7216000 22425600>; 693 }; 694 695 cpu4_opp29: opp-2553600000 { 696 opp-hz = /bits/ 64 <2553600000>; 697 opp-peak-kBps = <7216000 22425600>; 698 }; 699 700 cpu4_opp30: opp-2649600000 { 701 opp-hz = /bits/ 64 <2649600000>; 702 opp-peak-kBps = <7216000 22425600>; 703 }; 704 705 cpu4_opp31: opp-2745600000 { 706 opp-hz = /bits/ 64 <2745600000>; 707 opp-peak-kBps = <7216000 25497600>; 708 }; 709 710 cpu4_opp32: opp-2803200000 { 711 opp-hz = /bits/ 64 <2803200000>; 712 opp-peak-kBps = <7216000 25497600>; 713 }; 714 }; 715 716 pmu { 717 compatible = "arm,armv8-pmuv3"; 718 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 719 }; 720 721 timer { 722 compatible = "arm,armv8-timer"; 723 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 724 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 725 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 726 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 727 }; 728 729 clocks { 730 xo_board: xo-board { 731 compatible = "fixed-clock"; 732 #clock-cells = <0>; 733 clock-frequency = <38400000>; 734 clock-output-names = "xo_board"; 735 }; 736 737 sleep_clk: sleep-clk { 738 compatible = "fixed-clock"; 739 #clock-cells = <0>; 740 clock-frequency = <32764>; 741 }; 742 }; 743 744 firmware { 745 scm { 746 compatible = "qcom,scm-sdm845", "qcom,scm"; 747 }; 748 }; 749 750 adsp_pas: remoteproc-adsp { 751 compatible = "qcom,sdm845-adsp-pas"; 752 753 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 754 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 755 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 756 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 757 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 758 interrupt-names = "wdog", "fatal", "ready", 759 "handover", "stop-ack"; 760 761 clocks = <&rpmhcc RPMH_CXO_CLK>; 762 clock-names = "xo"; 763 764 memory-region = <&adsp_mem>; 765 766 qcom,qmp = <&aoss_qmp>; 767 768 qcom,smem-states = <&adsp_smp2p_out 0>; 769 qcom,smem-state-names = "stop"; 770 771 status = "disabled"; 772 773 glink-edge { 774 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 775 label = "lpass"; 776 qcom,remote-pid = <2>; 777 mboxes = <&apss_shared 8>; 778 779 apr { 780 compatible = "qcom,apr-v2"; 781 qcom,glink-channels = "apr_audio_svc"; 782 qcom,apr-domain = <APR_DOMAIN_ADSP>; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 qcom,intents = <512 20>; 786 787 apr-service@3 { 788 reg = <APR_SVC_ADSP_CORE>; 789 compatible = "qcom,q6core"; 790 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 791 }; 792 793 q6afe: apr-service@4 { 794 compatible = "qcom,q6afe"; 795 reg = <APR_SVC_AFE>; 796 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 797 q6afedai: dais { 798 compatible = "qcom,q6afe-dais"; 799 #address-cells = <1>; 800 #size-cells = <0>; 801 #sound-dai-cells = <1>; 802 }; 803 }; 804 805 q6asm: apr-service@7 { 806 compatible = "qcom,q6asm"; 807 reg = <APR_SVC_ASM>; 808 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 809 q6asmdai: dais { 810 compatible = "qcom,q6asm-dais"; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 #sound-dai-cells = <1>; 814 iommus = <&apps_smmu 0x1821 0x0>; 815 }; 816 }; 817 818 q6adm: apr-service@8 { 819 compatible = "qcom,q6adm"; 820 reg = <APR_SVC_ADM>; 821 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 822 q6routing: routing { 823 compatible = "qcom,q6adm-routing"; 824 #sound-dai-cells = <0>; 825 }; 826 }; 827 }; 828 829 fastrpc { 830 compatible = "qcom,fastrpc"; 831 qcom,glink-channels = "fastrpcglink-apps-dsp"; 832 label = "adsp"; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 836 compute-cb@3 { 837 compatible = "qcom,fastrpc-compute-cb"; 838 reg = <3>; 839 iommus = <&apps_smmu 0x1823 0x0>; 840 }; 841 842 compute-cb@4 { 843 compatible = "qcom,fastrpc-compute-cb"; 844 reg = <4>; 845 iommus = <&apps_smmu 0x1824 0x0>; 846 }; 847 }; 848 }; 849 }; 850 851 cdsp_pas: remoteproc-cdsp { 852 compatible = "qcom,sdm845-cdsp-pas"; 853 854 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 855 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 856 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 857 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 858 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 859 interrupt-names = "wdog", "fatal", "ready", 860 "handover", "stop-ack"; 861 862 clocks = <&rpmhcc RPMH_CXO_CLK>; 863 clock-names = "xo"; 864 865 memory-region = <&cdsp_mem>; 866 867 qcom,qmp = <&aoss_qmp>; 868 869 qcom,smem-states = <&cdsp_smp2p_out 0>; 870 qcom,smem-state-names = "stop"; 871 872 status = "disabled"; 873 874 glink-edge { 875 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 876 label = "turing"; 877 qcom,remote-pid = <5>; 878 mboxes = <&apss_shared 4>; 879 fastrpc { 880 compatible = "qcom,fastrpc"; 881 qcom,glink-channels = "fastrpcglink-apps-dsp"; 882 label = "cdsp"; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 886 compute-cb@1 { 887 compatible = "qcom,fastrpc-compute-cb"; 888 reg = <1>; 889 iommus = <&apps_smmu 0x1401 0x30>; 890 }; 891 892 compute-cb@2 { 893 compatible = "qcom,fastrpc-compute-cb"; 894 reg = <2>; 895 iommus = <&apps_smmu 0x1402 0x30>; 896 }; 897 898 compute-cb@3 { 899 compatible = "qcom,fastrpc-compute-cb"; 900 reg = <3>; 901 iommus = <&apps_smmu 0x1403 0x30>; 902 }; 903 904 compute-cb@4 { 905 compatible = "qcom,fastrpc-compute-cb"; 906 reg = <4>; 907 iommus = <&apps_smmu 0x1404 0x30>; 908 }; 909 910 compute-cb@5 { 911 compatible = "qcom,fastrpc-compute-cb"; 912 reg = <5>; 913 iommus = <&apps_smmu 0x1405 0x30>; 914 }; 915 916 compute-cb@6 { 917 compatible = "qcom,fastrpc-compute-cb"; 918 reg = <6>; 919 iommus = <&apps_smmu 0x1406 0x30>; 920 }; 921 922 compute-cb@7 { 923 compatible = "qcom,fastrpc-compute-cb"; 924 reg = <7>; 925 iommus = <&apps_smmu 0x1407 0x30>; 926 }; 927 928 compute-cb@8 { 929 compatible = "qcom,fastrpc-compute-cb"; 930 reg = <8>; 931 iommus = <&apps_smmu 0x1408 0x30>; 932 }; 933 }; 934 }; 935 }; 936 937 tcsr_mutex: hwlock { 938 compatible = "qcom,tcsr-mutex"; 939 syscon = <&tcsr_mutex_regs 0 0x1000>; 940 #hwlock-cells = <1>; 941 }; 942 943 smem { 944 compatible = "qcom,smem"; 945 memory-region = <&smem_mem>; 946 hwlocks = <&tcsr_mutex 3>; 947 }; 948 949 smp2p-cdsp { 950 compatible = "qcom,smp2p"; 951 qcom,smem = <94>, <432>; 952 953 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 954 955 mboxes = <&apss_shared 6>; 956 957 qcom,local-pid = <0>; 958 qcom,remote-pid = <5>; 959 960 cdsp_smp2p_out: master-kernel { 961 qcom,entry-name = "master-kernel"; 962 #qcom,smem-state-cells = <1>; 963 }; 964 965 cdsp_smp2p_in: slave-kernel { 966 qcom,entry-name = "slave-kernel"; 967 968 interrupt-controller; 969 #interrupt-cells = <2>; 970 }; 971 }; 972 973 smp2p-lpass { 974 compatible = "qcom,smp2p"; 975 qcom,smem = <443>, <429>; 976 977 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 978 979 mboxes = <&apss_shared 10>; 980 981 qcom,local-pid = <0>; 982 qcom,remote-pid = <2>; 983 984 adsp_smp2p_out: master-kernel { 985 qcom,entry-name = "master-kernel"; 986 #qcom,smem-state-cells = <1>; 987 }; 988 989 adsp_smp2p_in: slave-kernel { 990 qcom,entry-name = "slave-kernel"; 991 992 interrupt-controller; 993 #interrupt-cells = <2>; 994 }; 995 }; 996 997 smp2p-mpss { 998 compatible = "qcom,smp2p"; 999 qcom,smem = <435>, <428>; 1000 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1001 mboxes = <&apss_shared 14>; 1002 qcom,local-pid = <0>; 1003 qcom,remote-pid = <1>; 1004 1005 modem_smp2p_out: master-kernel { 1006 qcom,entry-name = "master-kernel"; 1007 #qcom,smem-state-cells = <1>; 1008 }; 1009 1010 modem_smp2p_in: slave-kernel { 1011 qcom,entry-name = "slave-kernel"; 1012 interrupt-controller; 1013 #interrupt-cells = <2>; 1014 }; 1015 1016 ipa_smp2p_out: ipa-ap-to-modem { 1017 qcom,entry-name = "ipa"; 1018 #qcom,smem-state-cells = <1>; 1019 }; 1020 1021 ipa_smp2p_in: ipa-modem-to-ap { 1022 qcom,entry-name = "ipa"; 1023 interrupt-controller; 1024 #interrupt-cells = <2>; 1025 }; 1026 }; 1027 1028 smp2p-slpi { 1029 compatible = "qcom,smp2p"; 1030 qcom,smem = <481>, <430>; 1031 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1032 mboxes = <&apss_shared 26>; 1033 qcom,local-pid = <0>; 1034 qcom,remote-pid = <3>; 1035 1036 slpi_smp2p_out: master-kernel { 1037 qcom,entry-name = "master-kernel"; 1038 #qcom,smem-state-cells = <1>; 1039 }; 1040 1041 slpi_smp2p_in: slave-kernel { 1042 qcom,entry-name = "slave-kernel"; 1043 interrupt-controller; 1044 #interrupt-cells = <2>; 1045 }; 1046 }; 1047 1048 psci { 1049 compatible = "arm,psci-1.0"; 1050 method = "smc"; 1051 }; 1052 1053 soc: soc@0 { 1054 #address-cells = <2>; 1055 #size-cells = <2>; 1056 ranges = <0 0 0 0 0x10 0>; 1057 dma-ranges = <0 0 0 0 0x10 0>; 1058 compatible = "simple-bus"; 1059 1060 gcc: clock-controller@100000 { 1061 compatible = "qcom,gcc-sdm845"; 1062 reg = <0 0x00100000 0 0x1f0000>; 1063 clocks = <&rpmhcc RPMH_CXO_CLK>, 1064 <&rpmhcc RPMH_CXO_CLK_A>, 1065 <&sleep_clk>, 1066 <&pcie0_lane>, 1067 <&pcie1_lane>; 1068 clock-names = "bi_tcxo", 1069 "bi_tcxo_ao", 1070 "sleep_clk", 1071 "pcie_0_pipe_clk", 1072 "pcie_1_pipe_clk"; 1073 #clock-cells = <1>; 1074 #reset-cells = <1>; 1075 #power-domain-cells = <1>; 1076 }; 1077 1078 qfprom@784000 { 1079 compatible = "qcom,qfprom"; 1080 reg = <0 0x00784000 0 0x8ff>; 1081 #address-cells = <1>; 1082 #size-cells = <1>; 1083 1084 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1085 reg = <0x1eb 0x1>; 1086 bits = <1 4>; 1087 }; 1088 1089 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1090 reg = <0x1eb 0x2>; 1091 bits = <6 4>; 1092 }; 1093 }; 1094 1095 rng: rng@793000 { 1096 compatible = "qcom,prng-ee"; 1097 reg = <0 0x00793000 0 0x1000>; 1098 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1099 clock-names = "core"; 1100 }; 1101 1102 qup_opp_table: qup-opp-table { 1103 compatible = "operating-points-v2"; 1104 1105 opp-50000000 { 1106 opp-hz = /bits/ 64 <50000000>; 1107 required-opps = <&rpmhpd_opp_min_svs>; 1108 }; 1109 1110 opp-75000000 { 1111 opp-hz = /bits/ 64 <75000000>; 1112 required-opps = <&rpmhpd_opp_low_svs>; 1113 }; 1114 1115 opp-100000000 { 1116 opp-hz = /bits/ 64 <100000000>; 1117 required-opps = <&rpmhpd_opp_svs>; 1118 }; 1119 1120 opp-128000000 { 1121 opp-hz = /bits/ 64 <128000000>; 1122 required-opps = <&rpmhpd_opp_nom>; 1123 }; 1124 }; 1125 1126 qupv3_id_0: geniqup@8c0000 { 1127 compatible = "qcom,geni-se-qup"; 1128 reg = <0 0x008c0000 0 0x6000>; 1129 clock-names = "m-ahb", "s-ahb"; 1130 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1131 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1132 iommus = <&apps_smmu 0x3 0x0>; 1133 #address-cells = <2>; 1134 #size-cells = <2>; 1135 ranges; 1136 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; 1137 interconnect-names = "qup-core"; 1138 status = "disabled"; 1139 1140 i2c0: i2c@880000 { 1141 compatible = "qcom,geni-i2c"; 1142 reg = <0 0x00880000 0 0x4000>; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&qup_i2c0_default>; 1147 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 power-domains = <&rpmhpd SDM845_CX>; 1151 operating-points-v2 = <&qup_opp_table>; 1152 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1153 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1154 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1155 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1156 status = "disabled"; 1157 }; 1158 1159 spi0: spi@880000 { 1160 compatible = "qcom,geni-spi"; 1161 reg = <0 0x00880000 0 0x4000>; 1162 clock-names = "se"; 1163 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&qup_spi0_default>; 1166 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1170 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1171 interconnect-names = "qup-core", "qup-config"; 1172 status = "disabled"; 1173 }; 1174 1175 uart0: serial@880000 { 1176 compatible = "qcom,geni-uart"; 1177 reg = <0 0x00880000 0 0x4000>; 1178 clock-names = "se"; 1179 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1180 pinctrl-names = "default"; 1181 pinctrl-0 = <&qup_uart0_default>; 1182 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1183 power-domains = <&rpmhpd SDM845_CX>; 1184 operating-points-v2 = <&qup_opp_table>; 1185 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1186 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1187 interconnect-names = "qup-core", "qup-config"; 1188 status = "disabled"; 1189 }; 1190 1191 i2c1: i2c@884000 { 1192 compatible = "qcom,geni-i2c"; 1193 reg = <0 0x00884000 0 0x4000>; 1194 clock-names = "se"; 1195 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&qup_i2c1_default>; 1198 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 power-domains = <&rpmhpd SDM845_CX>; 1202 operating-points-v2 = <&qup_opp_table>; 1203 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1204 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1205 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1206 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1207 status = "disabled"; 1208 }; 1209 1210 spi1: spi@884000 { 1211 compatible = "qcom,geni-spi"; 1212 reg = <0 0x00884000 0 0x4000>; 1213 clock-names = "se"; 1214 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1215 pinctrl-names = "default"; 1216 pinctrl-0 = <&qup_spi1_default>; 1217 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1221 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1222 interconnect-names = "qup-core", "qup-config"; 1223 status = "disabled"; 1224 }; 1225 1226 uart1: serial@884000 { 1227 compatible = "qcom,geni-uart"; 1228 reg = <0 0x00884000 0 0x4000>; 1229 clock-names = "se"; 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1231 pinctrl-names = "default"; 1232 pinctrl-0 = <&qup_uart1_default>; 1233 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1234 power-domains = <&rpmhpd SDM845_CX>; 1235 operating-points-v2 = <&qup_opp_table>; 1236 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1237 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1238 interconnect-names = "qup-core", "qup-config"; 1239 status = "disabled"; 1240 }; 1241 1242 i2c2: i2c@888000 { 1243 compatible = "qcom,geni-i2c"; 1244 reg = <0 0x00888000 0 0x4000>; 1245 clock-names = "se"; 1246 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1247 pinctrl-names = "default"; 1248 pinctrl-0 = <&qup_i2c2_default>; 1249 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 power-domains = <&rpmhpd SDM845_CX>; 1253 operating-points-v2 = <&qup_opp_table>; 1254 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1255 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1256 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1257 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1258 status = "disabled"; 1259 }; 1260 1261 spi2: spi@888000 { 1262 compatible = "qcom,geni-spi"; 1263 reg = <0 0x00888000 0 0x4000>; 1264 clock-names = "se"; 1265 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&qup_spi2_default>; 1268 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1272 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1273 interconnect-names = "qup-core", "qup-config"; 1274 status = "disabled"; 1275 }; 1276 1277 uart2: serial@888000 { 1278 compatible = "qcom,geni-uart"; 1279 reg = <0 0x00888000 0 0x4000>; 1280 clock-names = "se"; 1281 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_uart2_default>; 1284 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1285 power-domains = <&rpmhpd SDM845_CX>; 1286 operating-points-v2 = <&qup_opp_table>; 1287 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1288 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1289 interconnect-names = "qup-core", "qup-config"; 1290 status = "disabled"; 1291 }; 1292 1293 i2c3: i2c@88c000 { 1294 compatible = "qcom,geni-i2c"; 1295 reg = <0 0x0088c000 0 0x4000>; 1296 clock-names = "se"; 1297 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1298 pinctrl-names = "default"; 1299 pinctrl-0 = <&qup_i2c3_default>; 1300 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 power-domains = <&rpmhpd SDM845_CX>; 1304 operating-points-v2 = <&qup_opp_table>; 1305 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1306 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1307 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1308 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1309 status = "disabled"; 1310 }; 1311 1312 spi3: spi@88c000 { 1313 compatible = "qcom,geni-spi"; 1314 reg = <0 0x0088c000 0 0x4000>; 1315 clock-names = "se"; 1316 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1317 pinctrl-names = "default"; 1318 pinctrl-0 = <&qup_spi3_default>; 1319 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1323 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1324 interconnect-names = "qup-core", "qup-config"; 1325 status = "disabled"; 1326 }; 1327 1328 uart3: serial@88c000 { 1329 compatible = "qcom,geni-uart"; 1330 reg = <0 0x0088c000 0 0x4000>; 1331 clock-names = "se"; 1332 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1333 pinctrl-names = "default"; 1334 pinctrl-0 = <&qup_uart3_default>; 1335 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1336 power-domains = <&rpmhpd SDM845_CX>; 1337 operating-points-v2 = <&qup_opp_table>; 1338 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1339 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1340 interconnect-names = "qup-core", "qup-config"; 1341 status = "disabled"; 1342 }; 1343 1344 i2c4: i2c@890000 { 1345 compatible = "qcom,geni-i2c"; 1346 reg = <0 0x00890000 0 0x4000>; 1347 clock-names = "se"; 1348 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1349 pinctrl-names = "default"; 1350 pinctrl-0 = <&qup_i2c4_default>; 1351 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1352 #address-cells = <1>; 1353 #size-cells = <0>; 1354 power-domains = <&rpmhpd SDM845_CX>; 1355 operating-points-v2 = <&qup_opp_table>; 1356 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1357 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1358 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1359 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1360 status = "disabled"; 1361 }; 1362 1363 spi4: spi@890000 { 1364 compatible = "qcom,geni-spi"; 1365 reg = <0 0x00890000 0 0x4000>; 1366 clock-names = "se"; 1367 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1368 pinctrl-names = "default"; 1369 pinctrl-0 = <&qup_spi4_default>; 1370 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1374 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1375 interconnect-names = "qup-core", "qup-config"; 1376 status = "disabled"; 1377 }; 1378 1379 uart4: serial@890000 { 1380 compatible = "qcom,geni-uart"; 1381 reg = <0 0x00890000 0 0x4000>; 1382 clock-names = "se"; 1383 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1384 pinctrl-names = "default"; 1385 pinctrl-0 = <&qup_uart4_default>; 1386 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1387 power-domains = <&rpmhpd SDM845_CX>; 1388 operating-points-v2 = <&qup_opp_table>; 1389 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1390 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1391 interconnect-names = "qup-core", "qup-config"; 1392 status = "disabled"; 1393 }; 1394 1395 i2c5: i2c@894000 { 1396 compatible = "qcom,geni-i2c"; 1397 reg = <0 0x00894000 0 0x4000>; 1398 clock-names = "se"; 1399 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1400 pinctrl-names = "default"; 1401 pinctrl-0 = <&qup_i2c5_default>; 1402 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 power-domains = <&rpmhpd SDM845_CX>; 1406 operating-points-v2 = <&qup_opp_table>; 1407 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1408 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1409 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1410 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1411 status = "disabled"; 1412 }; 1413 1414 spi5: spi@894000 { 1415 compatible = "qcom,geni-spi"; 1416 reg = <0 0x00894000 0 0x4000>; 1417 clock-names = "se"; 1418 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1419 pinctrl-names = "default"; 1420 pinctrl-0 = <&qup_spi5_default>; 1421 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1425 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1426 interconnect-names = "qup-core", "qup-config"; 1427 status = "disabled"; 1428 }; 1429 1430 uart5: serial@894000 { 1431 compatible = "qcom,geni-uart"; 1432 reg = <0 0x00894000 0 0x4000>; 1433 clock-names = "se"; 1434 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_uart5_default>; 1437 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1438 power-domains = <&rpmhpd SDM845_CX>; 1439 operating-points-v2 = <&qup_opp_table>; 1440 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1441 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1442 interconnect-names = "qup-core", "qup-config"; 1443 status = "disabled"; 1444 }; 1445 1446 i2c6: i2c@898000 { 1447 compatible = "qcom,geni-i2c"; 1448 reg = <0 0x00898000 0 0x4000>; 1449 clock-names = "se"; 1450 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1451 pinctrl-names = "default"; 1452 pinctrl-0 = <&qup_i2c6_default>; 1453 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1454 #address-cells = <1>; 1455 #size-cells = <0>; 1456 power-domains = <&rpmhpd SDM845_CX>; 1457 operating-points-v2 = <&qup_opp_table>; 1458 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1459 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1460 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1461 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1462 status = "disabled"; 1463 }; 1464 1465 spi6: spi@898000 { 1466 compatible = "qcom,geni-spi"; 1467 reg = <0 0x00898000 0 0x4000>; 1468 clock-names = "se"; 1469 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1470 pinctrl-names = "default"; 1471 pinctrl-0 = <&qup_spi6_default>; 1472 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1476 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1477 interconnect-names = "qup-core", "qup-config"; 1478 status = "disabled"; 1479 }; 1480 1481 uart6: serial@898000 { 1482 compatible = "qcom,geni-uart"; 1483 reg = <0 0x00898000 0 0x4000>; 1484 clock-names = "se"; 1485 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1486 pinctrl-names = "default"; 1487 pinctrl-0 = <&qup_uart6_default>; 1488 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1489 power-domains = <&rpmhpd SDM845_CX>; 1490 operating-points-v2 = <&qup_opp_table>; 1491 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1492 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1493 interconnect-names = "qup-core", "qup-config"; 1494 status = "disabled"; 1495 }; 1496 1497 i2c7: i2c@89c000 { 1498 compatible = "qcom,geni-i2c"; 1499 reg = <0 0x0089c000 0 0x4000>; 1500 clock-names = "se"; 1501 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1502 pinctrl-names = "default"; 1503 pinctrl-0 = <&qup_i2c7_default>; 1504 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 power-domains = <&rpmhpd SDM845_CX>; 1508 operating-points-v2 = <&qup_opp_table>; 1509 status = "disabled"; 1510 }; 1511 1512 spi7: spi@89c000 { 1513 compatible = "qcom,geni-spi"; 1514 reg = <0 0x0089c000 0 0x4000>; 1515 clock-names = "se"; 1516 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1517 pinctrl-names = "default"; 1518 pinctrl-0 = <&qup_spi7_default>; 1519 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1523 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1524 interconnect-names = "qup-core", "qup-config"; 1525 status = "disabled"; 1526 }; 1527 1528 uart7: serial@89c000 { 1529 compatible = "qcom,geni-uart"; 1530 reg = <0 0x0089c000 0 0x4000>; 1531 clock-names = "se"; 1532 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1533 pinctrl-names = "default"; 1534 pinctrl-0 = <&qup_uart7_default>; 1535 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1536 power-domains = <&rpmhpd SDM845_CX>; 1537 operating-points-v2 = <&qup_opp_table>; 1538 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1539 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1540 interconnect-names = "qup-core", "qup-config"; 1541 status = "disabled"; 1542 }; 1543 }; 1544 1545 qupv3_id_1: geniqup@ac0000 { 1546 compatible = "qcom,geni-se-qup"; 1547 reg = <0 0x00ac0000 0 0x6000>; 1548 clock-names = "m-ahb", "s-ahb"; 1549 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1550 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1551 iommus = <&apps_smmu 0x6c3 0x0>; 1552 #address-cells = <2>; 1553 #size-cells = <2>; 1554 ranges; 1555 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; 1556 interconnect-names = "qup-core"; 1557 status = "disabled"; 1558 1559 i2c8: i2c@a80000 { 1560 compatible = "qcom,geni-i2c"; 1561 reg = <0 0x00a80000 0 0x4000>; 1562 clock-names = "se"; 1563 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1564 pinctrl-names = "default"; 1565 pinctrl-0 = <&qup_i2c8_default>; 1566 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 power-domains = <&rpmhpd SDM845_CX>; 1570 operating-points-v2 = <&qup_opp_table>; 1571 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1572 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1573 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1574 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1575 status = "disabled"; 1576 }; 1577 1578 spi8: spi@a80000 { 1579 compatible = "qcom,geni-spi"; 1580 reg = <0 0x00a80000 0 0x4000>; 1581 clock-names = "se"; 1582 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1583 pinctrl-names = "default"; 1584 pinctrl-0 = <&qup_spi8_default>; 1585 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1589 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1590 interconnect-names = "qup-core", "qup-config"; 1591 status = "disabled"; 1592 }; 1593 1594 uart8: serial@a80000 { 1595 compatible = "qcom,geni-uart"; 1596 reg = <0 0x00a80000 0 0x4000>; 1597 clock-names = "se"; 1598 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1599 pinctrl-names = "default"; 1600 pinctrl-0 = <&qup_uart8_default>; 1601 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1602 power-domains = <&rpmhpd SDM845_CX>; 1603 operating-points-v2 = <&qup_opp_table>; 1604 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1605 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1606 interconnect-names = "qup-core", "qup-config"; 1607 status = "disabled"; 1608 }; 1609 1610 i2c9: i2c@a84000 { 1611 compatible = "qcom,geni-i2c"; 1612 reg = <0 0x00a84000 0 0x4000>; 1613 clock-names = "se"; 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1615 pinctrl-names = "default"; 1616 pinctrl-0 = <&qup_i2c9_default>; 1617 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1618 #address-cells = <1>; 1619 #size-cells = <0>; 1620 power-domains = <&rpmhpd SDM845_CX>; 1621 operating-points-v2 = <&qup_opp_table>; 1622 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1623 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1624 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1625 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1626 status = "disabled"; 1627 }; 1628 1629 spi9: spi@a84000 { 1630 compatible = "qcom,geni-spi"; 1631 reg = <0 0x00a84000 0 0x4000>; 1632 clock-names = "se"; 1633 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1634 pinctrl-names = "default"; 1635 pinctrl-0 = <&qup_spi9_default>; 1636 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1637 #address-cells = <1>; 1638 #size-cells = <0>; 1639 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1640 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1641 interconnect-names = "qup-core", "qup-config"; 1642 status = "disabled"; 1643 }; 1644 1645 uart9: serial@a84000 { 1646 compatible = "qcom,geni-debug-uart"; 1647 reg = <0 0x00a84000 0 0x4000>; 1648 clock-names = "se"; 1649 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1650 pinctrl-names = "default"; 1651 pinctrl-0 = <&qup_uart9_default>; 1652 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1653 power-domains = <&rpmhpd SDM845_CX>; 1654 operating-points-v2 = <&qup_opp_table>; 1655 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1656 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1657 interconnect-names = "qup-core", "qup-config"; 1658 status = "disabled"; 1659 }; 1660 1661 i2c10: i2c@a88000 { 1662 compatible = "qcom,geni-i2c"; 1663 reg = <0 0x00a88000 0 0x4000>; 1664 clock-names = "se"; 1665 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1666 pinctrl-names = "default"; 1667 pinctrl-0 = <&qup_i2c10_default>; 1668 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 power-domains = <&rpmhpd SDM845_CX>; 1672 operating-points-v2 = <&qup_opp_table>; 1673 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1674 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1675 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1676 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1677 status = "disabled"; 1678 }; 1679 1680 spi10: spi@a88000 { 1681 compatible = "qcom,geni-spi"; 1682 reg = <0 0x00a88000 0 0x4000>; 1683 clock-names = "se"; 1684 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1685 pinctrl-names = "default"; 1686 pinctrl-0 = <&qup_spi10_default>; 1687 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1691 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1692 interconnect-names = "qup-core", "qup-config"; 1693 status = "disabled"; 1694 }; 1695 1696 uart10: serial@a88000 { 1697 compatible = "qcom,geni-uart"; 1698 reg = <0 0x00a88000 0 0x4000>; 1699 clock-names = "se"; 1700 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1701 pinctrl-names = "default"; 1702 pinctrl-0 = <&qup_uart10_default>; 1703 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1704 power-domains = <&rpmhpd SDM845_CX>; 1705 operating-points-v2 = <&qup_opp_table>; 1706 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1707 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1708 interconnect-names = "qup-core", "qup-config"; 1709 status = "disabled"; 1710 }; 1711 1712 i2c11: i2c@a8c000 { 1713 compatible = "qcom,geni-i2c"; 1714 reg = <0 0x00a8c000 0 0x4000>; 1715 clock-names = "se"; 1716 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1717 pinctrl-names = "default"; 1718 pinctrl-0 = <&qup_i2c11_default>; 1719 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1720 #address-cells = <1>; 1721 #size-cells = <0>; 1722 power-domains = <&rpmhpd SDM845_CX>; 1723 operating-points-v2 = <&qup_opp_table>; 1724 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1725 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1726 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1727 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1728 status = "disabled"; 1729 }; 1730 1731 spi11: spi@a8c000 { 1732 compatible = "qcom,geni-spi"; 1733 reg = <0 0x00a8c000 0 0x4000>; 1734 clock-names = "se"; 1735 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1736 pinctrl-names = "default"; 1737 pinctrl-0 = <&qup_spi11_default>; 1738 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1739 #address-cells = <1>; 1740 #size-cells = <0>; 1741 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1742 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1743 interconnect-names = "qup-core", "qup-config"; 1744 status = "disabled"; 1745 }; 1746 1747 uart11: serial@a8c000 { 1748 compatible = "qcom,geni-uart"; 1749 reg = <0 0x00a8c000 0 0x4000>; 1750 clock-names = "se"; 1751 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1752 pinctrl-names = "default"; 1753 pinctrl-0 = <&qup_uart11_default>; 1754 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1755 power-domains = <&rpmhpd SDM845_CX>; 1756 operating-points-v2 = <&qup_opp_table>; 1757 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1758 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1759 interconnect-names = "qup-core", "qup-config"; 1760 status = "disabled"; 1761 }; 1762 1763 i2c12: i2c@a90000 { 1764 compatible = "qcom,geni-i2c"; 1765 reg = <0 0x00a90000 0 0x4000>; 1766 clock-names = "se"; 1767 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1768 pinctrl-names = "default"; 1769 pinctrl-0 = <&qup_i2c12_default>; 1770 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1771 #address-cells = <1>; 1772 #size-cells = <0>; 1773 power-domains = <&rpmhpd SDM845_CX>; 1774 operating-points-v2 = <&qup_opp_table>; 1775 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1776 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1777 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1778 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1779 status = "disabled"; 1780 }; 1781 1782 spi12: spi@a90000 { 1783 compatible = "qcom,geni-spi"; 1784 reg = <0 0x00a90000 0 0x4000>; 1785 clock-names = "se"; 1786 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1787 pinctrl-names = "default"; 1788 pinctrl-0 = <&qup_spi12_default>; 1789 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1790 #address-cells = <1>; 1791 #size-cells = <0>; 1792 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1793 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1794 interconnect-names = "qup-core", "qup-config"; 1795 status = "disabled"; 1796 }; 1797 1798 uart12: serial@a90000 { 1799 compatible = "qcom,geni-uart"; 1800 reg = <0 0x00a90000 0 0x4000>; 1801 clock-names = "se"; 1802 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1803 pinctrl-names = "default"; 1804 pinctrl-0 = <&qup_uart12_default>; 1805 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1806 power-domains = <&rpmhpd SDM845_CX>; 1807 operating-points-v2 = <&qup_opp_table>; 1808 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1809 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1810 interconnect-names = "qup-core", "qup-config"; 1811 status = "disabled"; 1812 }; 1813 1814 i2c13: i2c@a94000 { 1815 compatible = "qcom,geni-i2c"; 1816 reg = <0 0x00a94000 0 0x4000>; 1817 clock-names = "se"; 1818 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1819 pinctrl-names = "default"; 1820 pinctrl-0 = <&qup_i2c13_default>; 1821 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1822 #address-cells = <1>; 1823 #size-cells = <0>; 1824 power-domains = <&rpmhpd SDM845_CX>; 1825 operating-points-v2 = <&qup_opp_table>; 1826 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1827 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1828 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1829 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1830 status = "disabled"; 1831 }; 1832 1833 spi13: spi@a94000 { 1834 compatible = "qcom,geni-spi"; 1835 reg = <0 0x00a94000 0 0x4000>; 1836 clock-names = "se"; 1837 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1838 pinctrl-names = "default"; 1839 pinctrl-0 = <&qup_spi13_default>; 1840 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1841 #address-cells = <1>; 1842 #size-cells = <0>; 1843 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1844 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1845 interconnect-names = "qup-core", "qup-config"; 1846 status = "disabled"; 1847 }; 1848 1849 uart13: serial@a94000 { 1850 compatible = "qcom,geni-uart"; 1851 reg = <0 0x00a94000 0 0x4000>; 1852 clock-names = "se"; 1853 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1854 pinctrl-names = "default"; 1855 pinctrl-0 = <&qup_uart13_default>; 1856 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1857 power-domains = <&rpmhpd SDM845_CX>; 1858 operating-points-v2 = <&qup_opp_table>; 1859 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1860 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1861 interconnect-names = "qup-core", "qup-config"; 1862 status = "disabled"; 1863 }; 1864 1865 i2c14: i2c@a98000 { 1866 compatible = "qcom,geni-i2c"; 1867 reg = <0 0x00a98000 0 0x4000>; 1868 clock-names = "se"; 1869 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1870 pinctrl-names = "default"; 1871 pinctrl-0 = <&qup_i2c14_default>; 1872 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1873 #address-cells = <1>; 1874 #size-cells = <0>; 1875 power-domains = <&rpmhpd SDM845_CX>; 1876 operating-points-v2 = <&qup_opp_table>; 1877 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1878 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1879 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1880 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1881 status = "disabled"; 1882 }; 1883 1884 spi14: spi@a98000 { 1885 compatible = "qcom,geni-spi"; 1886 reg = <0 0x00a98000 0 0x4000>; 1887 clock-names = "se"; 1888 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1889 pinctrl-names = "default"; 1890 pinctrl-0 = <&qup_spi14_default>; 1891 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1892 #address-cells = <1>; 1893 #size-cells = <0>; 1894 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1895 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1896 interconnect-names = "qup-core", "qup-config"; 1897 status = "disabled"; 1898 }; 1899 1900 uart14: serial@a98000 { 1901 compatible = "qcom,geni-uart"; 1902 reg = <0 0x00a98000 0 0x4000>; 1903 clock-names = "se"; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1905 pinctrl-names = "default"; 1906 pinctrl-0 = <&qup_uart14_default>; 1907 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1908 power-domains = <&rpmhpd SDM845_CX>; 1909 operating-points-v2 = <&qup_opp_table>; 1910 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1911 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1912 interconnect-names = "qup-core", "qup-config"; 1913 status = "disabled"; 1914 }; 1915 1916 i2c15: i2c@a9c000 { 1917 compatible = "qcom,geni-i2c"; 1918 reg = <0 0x00a9c000 0 0x4000>; 1919 clock-names = "se"; 1920 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1921 pinctrl-names = "default"; 1922 pinctrl-0 = <&qup_i2c15_default>; 1923 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1924 #address-cells = <1>; 1925 #size-cells = <0>; 1926 power-domains = <&rpmhpd SDM845_CX>; 1927 operating-points-v2 = <&qup_opp_table>; 1928 status = "disabled"; 1929 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1930 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1931 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1932 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1933 }; 1934 1935 spi15: spi@a9c000 { 1936 compatible = "qcom,geni-spi"; 1937 reg = <0 0x00a9c000 0 0x4000>; 1938 clock-names = "se"; 1939 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1940 pinctrl-names = "default"; 1941 pinctrl-0 = <&qup_spi15_default>; 1942 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1943 #address-cells = <1>; 1944 #size-cells = <0>; 1945 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1946 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1947 interconnect-names = "qup-core", "qup-config"; 1948 status = "disabled"; 1949 }; 1950 1951 uart15: serial@a9c000 { 1952 compatible = "qcom,geni-uart"; 1953 reg = <0 0x00a9c000 0 0x4000>; 1954 clock-names = "se"; 1955 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1956 pinctrl-names = "default"; 1957 pinctrl-0 = <&qup_uart15_default>; 1958 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1959 power-domains = <&rpmhpd SDM845_CX>; 1960 operating-points-v2 = <&qup_opp_table>; 1961 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1962 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1963 interconnect-names = "qup-core", "qup-config"; 1964 status = "disabled"; 1965 }; 1966 }; 1967 1968 system-cache-controller@1100000 { 1969 compatible = "qcom,sdm845-llcc"; 1970 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; 1971 reg-names = "llcc_base", "llcc_broadcast_base"; 1972 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1973 }; 1974 1975 pcie0: pci@1c00000 { 1976 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1977 reg = <0 0x01c00000 0 0x2000>, 1978 <0 0x60000000 0 0xf1d>, 1979 <0 0x60000f20 0 0xa8>, 1980 <0 0x60100000 0 0x100000>; 1981 reg-names = "parf", "dbi", "elbi", "config"; 1982 device_type = "pci"; 1983 linux,pci-domain = <0>; 1984 bus-range = <0x00 0xff>; 1985 num-lanes = <1>; 1986 1987 #address-cells = <3>; 1988 #size-cells = <2>; 1989 1990 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1991 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; 1992 1993 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1994 interrupt-names = "msi"; 1995 #interrupt-cells = <1>; 1996 interrupt-map-mask = <0 0 0 0x7>; 1997 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1998 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1999 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2000 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2001 2002 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2003 <&gcc GCC_PCIE_0_AUX_CLK>, 2004 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2005 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2006 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2007 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2008 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2009 clock-names = "pipe", 2010 "aux", 2011 "cfg", 2012 "bus_master", 2013 "bus_slave", 2014 "slave_q2a", 2015 "tbu"; 2016 2017 iommus = <&apps_smmu 0x1c10 0xf>; 2018 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 2019 <0x100 &apps_smmu 0x1c11 0x1>, 2020 <0x200 &apps_smmu 0x1c12 0x1>, 2021 <0x300 &apps_smmu 0x1c13 0x1>, 2022 <0x400 &apps_smmu 0x1c14 0x1>, 2023 <0x500 &apps_smmu 0x1c15 0x1>, 2024 <0x600 &apps_smmu 0x1c16 0x1>, 2025 <0x700 &apps_smmu 0x1c17 0x1>, 2026 <0x800 &apps_smmu 0x1c18 0x1>, 2027 <0x900 &apps_smmu 0x1c19 0x1>, 2028 <0xa00 &apps_smmu 0x1c1a 0x1>, 2029 <0xb00 &apps_smmu 0x1c1b 0x1>, 2030 <0xc00 &apps_smmu 0x1c1c 0x1>, 2031 <0xd00 &apps_smmu 0x1c1d 0x1>, 2032 <0xe00 &apps_smmu 0x1c1e 0x1>, 2033 <0xf00 &apps_smmu 0x1c1f 0x1>; 2034 2035 resets = <&gcc GCC_PCIE_0_BCR>; 2036 reset-names = "pci"; 2037 2038 power-domains = <&gcc PCIE_0_GDSC>; 2039 2040 phys = <&pcie0_lane>; 2041 phy-names = "pciephy"; 2042 2043 status = "disabled"; 2044 }; 2045 2046 pcie0_phy: phy@1c06000 { 2047 compatible = "qcom,sdm845-qmp-pcie-phy"; 2048 reg = <0 0x01c06000 0 0x18c>; 2049 #address-cells = <2>; 2050 #size-cells = <2>; 2051 ranges; 2052 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2053 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2054 <&gcc GCC_PCIE_0_CLKREF_CLK>, 2055 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2056 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2057 2058 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2059 reset-names = "phy"; 2060 2061 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2062 assigned-clock-rates = <100000000>; 2063 2064 status = "disabled"; 2065 2066 pcie0_lane: lanes@1c06200 { 2067 reg = <0 0x01c06200 0 0x128>, 2068 <0 0x01c06400 0 0x1fc>, 2069 <0 0x01c06800 0 0x218>, 2070 <0 0x01c06600 0 0x70>; 2071 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 2072 clock-names = "pipe0"; 2073 2074 #clock-cells = <0>; 2075 #phy-cells = <0>; 2076 clock-output-names = "pcie_0_pipe_clk"; 2077 }; 2078 }; 2079 2080 pcie1: pci@1c08000 { 2081 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 2082 reg = <0 0x01c08000 0 0x2000>, 2083 <0 0x40000000 0 0xf1d>, 2084 <0 0x40000f20 0 0xa8>, 2085 <0 0x40100000 0 0x100000>; 2086 reg-names = "parf", "dbi", "elbi", "config"; 2087 device_type = "pci"; 2088 linux,pci-domain = <1>; 2089 bus-range = <0x00 0xff>; 2090 num-lanes = <1>; 2091 2092 #address-cells = <3>; 2093 #size-cells = <2>; 2094 2095 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2096 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2097 2098 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 2099 interrupt-names = "msi"; 2100 #interrupt-cells = <1>; 2101 interrupt-map-mask = <0 0 0 0x7>; 2102 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2103 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2104 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2105 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2106 2107 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2108 <&gcc GCC_PCIE_1_AUX_CLK>, 2109 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2110 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2111 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2112 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2113 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2114 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2115 clock-names = "pipe", 2116 "aux", 2117 "cfg", 2118 "bus_master", 2119 "bus_slave", 2120 "slave_q2a", 2121 "ref", 2122 "tbu"; 2123 2124 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2125 assigned-clock-rates = <19200000>; 2126 2127 iommus = <&apps_smmu 0x1c00 0xf>; 2128 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2129 <0x100 &apps_smmu 0x1c01 0x1>, 2130 <0x200 &apps_smmu 0x1c02 0x1>, 2131 <0x300 &apps_smmu 0x1c03 0x1>, 2132 <0x400 &apps_smmu 0x1c04 0x1>, 2133 <0x500 &apps_smmu 0x1c05 0x1>, 2134 <0x600 &apps_smmu 0x1c06 0x1>, 2135 <0x700 &apps_smmu 0x1c07 0x1>, 2136 <0x800 &apps_smmu 0x1c08 0x1>, 2137 <0x900 &apps_smmu 0x1c09 0x1>, 2138 <0xa00 &apps_smmu 0x1c0a 0x1>, 2139 <0xb00 &apps_smmu 0x1c0b 0x1>, 2140 <0xc00 &apps_smmu 0x1c0c 0x1>, 2141 <0xd00 &apps_smmu 0x1c0d 0x1>, 2142 <0xe00 &apps_smmu 0x1c0e 0x1>, 2143 <0xf00 &apps_smmu 0x1c0f 0x1>; 2144 2145 resets = <&gcc GCC_PCIE_1_BCR>; 2146 reset-names = "pci"; 2147 2148 power-domains = <&gcc PCIE_1_GDSC>; 2149 2150 phys = <&pcie1_lane>; 2151 phy-names = "pciephy"; 2152 2153 status = "disabled"; 2154 }; 2155 2156 pcie1_phy: phy@1c0a000 { 2157 compatible = "qcom,sdm845-qhp-pcie-phy"; 2158 reg = <0 0x01c0a000 0 0x800>; 2159 #address-cells = <2>; 2160 #size-cells = <2>; 2161 ranges; 2162 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2163 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2164 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2165 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2166 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2167 2168 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2169 reset-names = "phy"; 2170 2171 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2172 assigned-clock-rates = <100000000>; 2173 2174 status = "disabled"; 2175 2176 pcie1_lane: lanes@1c06200 { 2177 reg = <0 0x01c0a800 0 0x800>, 2178 <0 0x01c0a800 0 0x800>, 2179 <0 0x01c0b800 0 0x400>; 2180 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2181 clock-names = "pipe0"; 2182 2183 #clock-cells = <0>; 2184 #phy-cells = <0>; 2185 clock-output-names = "pcie_1_pipe_clk"; 2186 }; 2187 }; 2188 2189 mem_noc: interconnect@1380000 { 2190 compatible = "qcom,sdm845-mem-noc"; 2191 reg = <0 0x01380000 0 0x27200>; 2192 #interconnect-cells = <2>; 2193 qcom,bcm-voters = <&apps_bcm_voter>; 2194 }; 2195 2196 dc_noc: interconnect@14e0000 { 2197 compatible = "qcom,sdm845-dc-noc"; 2198 reg = <0 0x014e0000 0 0x400>; 2199 #interconnect-cells = <2>; 2200 qcom,bcm-voters = <&apps_bcm_voter>; 2201 }; 2202 2203 config_noc: interconnect@1500000 { 2204 compatible = "qcom,sdm845-config-noc"; 2205 reg = <0 0x01500000 0 0x5080>; 2206 #interconnect-cells = <2>; 2207 qcom,bcm-voters = <&apps_bcm_voter>; 2208 }; 2209 2210 system_noc: interconnect@1620000 { 2211 compatible = "qcom,sdm845-system-noc"; 2212 reg = <0 0x01620000 0 0x18080>; 2213 #interconnect-cells = <2>; 2214 qcom,bcm-voters = <&apps_bcm_voter>; 2215 }; 2216 2217 aggre1_noc: interconnect@16e0000 { 2218 compatible = "qcom,sdm845-aggre1-noc"; 2219 reg = <0 0x016e0000 0 0x15080>; 2220 #interconnect-cells = <2>; 2221 qcom,bcm-voters = <&apps_bcm_voter>; 2222 }; 2223 2224 aggre2_noc: interconnect@1700000 { 2225 compatible = "qcom,sdm845-aggre2-noc"; 2226 reg = <0 0x01700000 0 0x1f300>; 2227 #interconnect-cells = <2>; 2228 qcom,bcm-voters = <&apps_bcm_voter>; 2229 }; 2230 2231 mmss_noc: interconnect@1740000 { 2232 compatible = "qcom,sdm845-mmss-noc"; 2233 reg = <0 0x01740000 0 0x1c100>; 2234 #interconnect-cells = <2>; 2235 qcom,bcm-voters = <&apps_bcm_voter>; 2236 }; 2237 2238 ufs_mem_hc: ufshc@1d84000 { 2239 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2240 "jedec,ufs-2.0"; 2241 reg = <0 0x01d84000 0 0x2500>, 2242 <0 0x01d90000 0 0x8000>; 2243 reg-names = "std", "ice"; 2244 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2245 phys = <&ufs_mem_phy_lanes>; 2246 phy-names = "ufsphy"; 2247 lanes-per-direction = <2>; 2248 power-domains = <&gcc UFS_PHY_GDSC>; 2249 #reset-cells = <1>; 2250 resets = <&gcc GCC_UFS_PHY_BCR>; 2251 reset-names = "rst"; 2252 2253 iommus = <&apps_smmu 0x100 0xf>; 2254 2255 clock-names = 2256 "core_clk", 2257 "bus_aggr_clk", 2258 "iface_clk", 2259 "core_clk_unipro", 2260 "ref_clk", 2261 "tx_lane0_sync_clk", 2262 "rx_lane0_sync_clk", 2263 "rx_lane1_sync_clk", 2264 "ice_core_clk"; 2265 clocks = 2266 <&gcc GCC_UFS_PHY_AXI_CLK>, 2267 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2268 <&gcc GCC_UFS_PHY_AHB_CLK>, 2269 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2270 <&rpmhcc RPMH_CXO_CLK>, 2271 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2272 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2273 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2274 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2275 freq-table-hz = 2276 <50000000 200000000>, 2277 <0 0>, 2278 <0 0>, 2279 <37500000 150000000>, 2280 <0 0>, 2281 <0 0>, 2282 <0 0>, 2283 <0 0>, 2284 <0 300000000>; 2285 2286 status = "disabled"; 2287 }; 2288 2289 ufs_mem_phy: phy@1d87000 { 2290 compatible = "qcom,sdm845-qmp-ufs-phy"; 2291 reg = <0 0x01d87000 0 0x18c>; 2292 #address-cells = <2>; 2293 #size-cells = <2>; 2294 ranges; 2295 clock-names = "ref", 2296 "ref_aux"; 2297 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2298 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2299 2300 resets = <&ufs_mem_hc 0>; 2301 reset-names = "ufsphy"; 2302 status = "disabled"; 2303 2304 ufs_mem_phy_lanes: lanes@1d87400 { 2305 reg = <0 0x01d87400 0 0x108>, 2306 <0 0x01d87600 0 0x1e0>, 2307 <0 0x01d87c00 0 0x1dc>, 2308 <0 0x01d87800 0 0x108>, 2309 <0 0x01d87a00 0 0x1e0>; 2310 #phy-cells = <0>; 2311 }; 2312 }; 2313 2314 cryptobam: dma-controller@1dc4000 { 2315 compatible = "qcom,bam-v1.7.0"; 2316 reg = <0 0x01dc4000 0 0x24000>; 2317 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2318 clocks = <&rpmhcc RPMH_CE_CLK>; 2319 clock-names = "bam_clk"; 2320 #dma-cells = <1>; 2321 qcom,ee = <0>; 2322 qcom,controlled-remotely; 2323 iommus = <&apps_smmu 0x704 0x1>, 2324 <&apps_smmu 0x706 0x1>, 2325 <&apps_smmu 0x714 0x1>, 2326 <&apps_smmu 0x716 0x1>; 2327 }; 2328 2329 crypto: crypto@1dfa000 { 2330 compatible = "qcom,crypto-v5.4"; 2331 reg = <0 0x01dfa000 0 0x6000>; 2332 clocks = <&gcc GCC_CE1_AHB_CLK>, 2333 <&gcc GCC_CE1_AHB_CLK>, 2334 <&rpmhcc RPMH_CE_CLK>; 2335 clock-names = "iface", "bus", "core"; 2336 dmas = <&cryptobam 6>, <&cryptobam 7>; 2337 dma-names = "rx", "tx"; 2338 iommus = <&apps_smmu 0x704 0x1>, 2339 <&apps_smmu 0x706 0x1>, 2340 <&apps_smmu 0x714 0x1>, 2341 <&apps_smmu 0x716 0x1>; 2342 }; 2343 2344 ipa: ipa@1e40000 { 2345 compatible = "qcom,sdm845-ipa"; 2346 2347 iommus = <&apps_smmu 0x720 0x0>, 2348 <&apps_smmu 0x722 0x0>; 2349 reg = <0 0x1e40000 0 0x7000>, 2350 <0 0x1e47000 0 0x2000>, 2351 <0 0x1e04000 0 0x2c000>; 2352 reg-names = "ipa-reg", 2353 "ipa-shared", 2354 "gsi"; 2355 2356 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 2357 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2358 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2359 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2360 interrupt-names = "ipa", 2361 "gsi", 2362 "ipa-clock-query", 2363 "ipa-setup-ready"; 2364 2365 clocks = <&rpmhcc RPMH_IPA_CLK>; 2366 clock-names = "core"; 2367 2368 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2369 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2370 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2371 interconnect-names = "memory", 2372 "imem", 2373 "config"; 2374 2375 qcom,smem-states = <&ipa_smp2p_out 0>, 2376 <&ipa_smp2p_out 1>; 2377 qcom,smem-state-names = "ipa-clock-enabled-valid", 2378 "ipa-clock-enabled"; 2379 2380 status = "disabled"; 2381 }; 2382 2383 tcsr_mutex_regs: syscon@1f40000 { 2384 compatible = "syscon"; 2385 reg = <0 0x01f40000 0 0x40000>; 2386 }; 2387 2388 tlmm: pinctrl@3400000 { 2389 compatible = "qcom,sdm845-pinctrl"; 2390 reg = <0 0x03400000 0 0xc00000>; 2391 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2392 gpio-controller; 2393 #gpio-cells = <2>; 2394 interrupt-controller; 2395 #interrupt-cells = <2>; 2396 gpio-ranges = <&tlmm 0 0 151>; 2397 wakeup-parent = <&pdc_intc>; 2398 2399 cci0_default: cci0-default { 2400 /* SDA, SCL */ 2401 pins = "gpio17", "gpio18"; 2402 function = "cci_i2c"; 2403 2404 bias-pull-up; 2405 drive-strength = <2>; /* 2 mA */ 2406 }; 2407 2408 cci0_sleep: cci0-sleep { 2409 /* SDA, SCL */ 2410 pins = "gpio17", "gpio18"; 2411 function = "cci_i2c"; 2412 2413 drive-strength = <2>; /* 2 mA */ 2414 bias-pull-down; 2415 }; 2416 2417 cci1_default: cci1-default { 2418 /* SDA, SCL */ 2419 pins = "gpio19", "gpio20"; 2420 function = "cci_i2c"; 2421 2422 bias-pull-up; 2423 drive-strength = <2>; /* 2 mA */ 2424 }; 2425 2426 cci1_sleep: cci1-sleep { 2427 /* SDA, SCL */ 2428 pins = "gpio19", "gpio20"; 2429 function = "cci_i2c"; 2430 2431 drive-strength = <2>; /* 2 mA */ 2432 bias-pull-down; 2433 }; 2434 2435 qspi_clk: qspi-clk { 2436 pinmux { 2437 pins = "gpio95"; 2438 function = "qspi_clk"; 2439 }; 2440 }; 2441 2442 qspi_cs0: qspi-cs0 { 2443 pinmux { 2444 pins = "gpio90"; 2445 function = "qspi_cs"; 2446 }; 2447 }; 2448 2449 qspi_cs1: qspi-cs1 { 2450 pinmux { 2451 pins = "gpio89"; 2452 function = "qspi_cs"; 2453 }; 2454 }; 2455 2456 qspi_data01: qspi-data01 { 2457 pinmux-data { 2458 pins = "gpio91", "gpio92"; 2459 function = "qspi_data"; 2460 }; 2461 }; 2462 2463 qspi_data12: qspi-data12 { 2464 pinmux-data { 2465 pins = "gpio93", "gpio94"; 2466 function = "qspi_data"; 2467 }; 2468 }; 2469 2470 qup_i2c0_default: qup-i2c0-default { 2471 pinmux { 2472 pins = "gpio0", "gpio1"; 2473 function = "qup0"; 2474 }; 2475 }; 2476 2477 qup_i2c1_default: qup-i2c1-default { 2478 pinmux { 2479 pins = "gpio17", "gpio18"; 2480 function = "qup1"; 2481 }; 2482 }; 2483 2484 qup_i2c2_default: qup-i2c2-default { 2485 pinmux { 2486 pins = "gpio27", "gpio28"; 2487 function = "qup2"; 2488 }; 2489 }; 2490 2491 qup_i2c3_default: qup-i2c3-default { 2492 pinmux { 2493 pins = "gpio41", "gpio42"; 2494 function = "qup3"; 2495 }; 2496 }; 2497 2498 qup_i2c4_default: qup-i2c4-default { 2499 pinmux { 2500 pins = "gpio89", "gpio90"; 2501 function = "qup4"; 2502 }; 2503 }; 2504 2505 qup_i2c5_default: qup-i2c5-default { 2506 pinmux { 2507 pins = "gpio85", "gpio86"; 2508 function = "qup5"; 2509 }; 2510 }; 2511 2512 qup_i2c6_default: qup-i2c6-default { 2513 pinmux { 2514 pins = "gpio45", "gpio46"; 2515 function = "qup6"; 2516 }; 2517 }; 2518 2519 qup_i2c7_default: qup-i2c7-default { 2520 pinmux { 2521 pins = "gpio93", "gpio94"; 2522 function = "qup7"; 2523 }; 2524 }; 2525 2526 qup_i2c8_default: qup-i2c8-default { 2527 pinmux { 2528 pins = "gpio65", "gpio66"; 2529 function = "qup8"; 2530 }; 2531 }; 2532 2533 qup_i2c9_default: qup-i2c9-default { 2534 pinmux { 2535 pins = "gpio6", "gpio7"; 2536 function = "qup9"; 2537 }; 2538 }; 2539 2540 qup_i2c10_default: qup-i2c10-default { 2541 pinmux { 2542 pins = "gpio55", "gpio56"; 2543 function = "qup10"; 2544 }; 2545 }; 2546 2547 qup_i2c11_default: qup-i2c11-default { 2548 pinmux { 2549 pins = "gpio31", "gpio32"; 2550 function = "qup11"; 2551 }; 2552 }; 2553 2554 qup_i2c12_default: qup-i2c12-default { 2555 pinmux { 2556 pins = "gpio49", "gpio50"; 2557 function = "qup12"; 2558 }; 2559 }; 2560 2561 qup_i2c13_default: qup-i2c13-default { 2562 pinmux { 2563 pins = "gpio105", "gpio106"; 2564 function = "qup13"; 2565 }; 2566 }; 2567 2568 qup_i2c14_default: qup-i2c14-default { 2569 pinmux { 2570 pins = "gpio33", "gpio34"; 2571 function = "qup14"; 2572 }; 2573 }; 2574 2575 qup_i2c15_default: qup-i2c15-default { 2576 pinmux { 2577 pins = "gpio81", "gpio82"; 2578 function = "qup15"; 2579 }; 2580 }; 2581 2582 qup_spi0_default: qup-spi0-default { 2583 pinmux { 2584 pins = "gpio0", "gpio1", 2585 "gpio2", "gpio3"; 2586 function = "qup0"; 2587 }; 2588 }; 2589 2590 qup_spi1_default: qup-spi1-default { 2591 pinmux { 2592 pins = "gpio17", "gpio18", 2593 "gpio19", "gpio20"; 2594 function = "qup1"; 2595 }; 2596 }; 2597 2598 qup_spi2_default: qup-spi2-default { 2599 pinmux { 2600 pins = "gpio27", "gpio28", 2601 "gpio29", "gpio30"; 2602 function = "qup2"; 2603 }; 2604 }; 2605 2606 qup_spi3_default: qup-spi3-default { 2607 pinmux { 2608 pins = "gpio41", "gpio42", 2609 "gpio43", "gpio44"; 2610 function = "qup3"; 2611 }; 2612 }; 2613 2614 qup_spi4_default: qup-spi4-default { 2615 pinmux { 2616 pins = "gpio89", "gpio90", 2617 "gpio91", "gpio92"; 2618 function = "qup4"; 2619 }; 2620 }; 2621 2622 qup_spi5_default: qup-spi5-default { 2623 pinmux { 2624 pins = "gpio85", "gpio86", 2625 "gpio87", "gpio88"; 2626 function = "qup5"; 2627 }; 2628 }; 2629 2630 qup_spi6_default: qup-spi6-default { 2631 pinmux { 2632 pins = "gpio45", "gpio46", 2633 "gpio47", "gpio48"; 2634 function = "qup6"; 2635 }; 2636 }; 2637 2638 qup_spi7_default: qup-spi7-default { 2639 pinmux { 2640 pins = "gpio93", "gpio94", 2641 "gpio95", "gpio96"; 2642 function = "qup7"; 2643 }; 2644 }; 2645 2646 qup_spi8_default: qup-spi8-default { 2647 pinmux { 2648 pins = "gpio65", "gpio66", 2649 "gpio67", "gpio68"; 2650 function = "qup8"; 2651 }; 2652 }; 2653 2654 qup_spi9_default: qup-spi9-default { 2655 pinmux { 2656 pins = "gpio6", "gpio7", 2657 "gpio4", "gpio5"; 2658 function = "qup9"; 2659 }; 2660 }; 2661 2662 qup_spi10_default: qup-spi10-default { 2663 pinmux { 2664 pins = "gpio55", "gpio56", 2665 "gpio53", "gpio54"; 2666 function = "qup10"; 2667 }; 2668 }; 2669 2670 qup_spi11_default: qup-spi11-default { 2671 pinmux { 2672 pins = "gpio31", "gpio32", 2673 "gpio33", "gpio34"; 2674 function = "qup11"; 2675 }; 2676 }; 2677 2678 qup_spi12_default: qup-spi12-default { 2679 pinmux { 2680 pins = "gpio49", "gpio50", 2681 "gpio51", "gpio52"; 2682 function = "qup12"; 2683 }; 2684 }; 2685 2686 qup_spi13_default: qup-spi13-default { 2687 pinmux { 2688 pins = "gpio105", "gpio106", 2689 "gpio107", "gpio108"; 2690 function = "qup13"; 2691 }; 2692 }; 2693 2694 qup_spi14_default: qup-spi14-default { 2695 pinmux { 2696 pins = "gpio33", "gpio34", 2697 "gpio31", "gpio32"; 2698 function = "qup14"; 2699 }; 2700 }; 2701 2702 qup_spi15_default: qup-spi15-default { 2703 pinmux { 2704 pins = "gpio81", "gpio82", 2705 "gpio83", "gpio84"; 2706 function = "qup15"; 2707 }; 2708 }; 2709 2710 qup_uart0_default: qup-uart0-default { 2711 pinmux { 2712 pins = "gpio2", "gpio3"; 2713 function = "qup0"; 2714 }; 2715 }; 2716 2717 qup_uart1_default: qup-uart1-default { 2718 pinmux { 2719 pins = "gpio19", "gpio20"; 2720 function = "qup1"; 2721 }; 2722 }; 2723 2724 qup_uart2_default: qup-uart2-default { 2725 pinmux { 2726 pins = "gpio29", "gpio30"; 2727 function = "qup2"; 2728 }; 2729 }; 2730 2731 qup_uart3_default: qup-uart3-default { 2732 pinmux { 2733 pins = "gpio43", "gpio44"; 2734 function = "qup3"; 2735 }; 2736 }; 2737 2738 qup_uart4_default: qup-uart4-default { 2739 pinmux { 2740 pins = "gpio91", "gpio92"; 2741 function = "qup4"; 2742 }; 2743 }; 2744 2745 qup_uart5_default: qup-uart5-default { 2746 pinmux { 2747 pins = "gpio87", "gpio88"; 2748 function = "qup5"; 2749 }; 2750 }; 2751 2752 qup_uart6_default: qup-uart6-default { 2753 pinmux { 2754 pins = "gpio47", "gpio48"; 2755 function = "qup6"; 2756 }; 2757 }; 2758 2759 qup_uart7_default: qup-uart7-default { 2760 pinmux { 2761 pins = "gpio95", "gpio96"; 2762 function = "qup7"; 2763 }; 2764 }; 2765 2766 qup_uart8_default: qup-uart8-default { 2767 pinmux { 2768 pins = "gpio67", "gpio68"; 2769 function = "qup8"; 2770 }; 2771 }; 2772 2773 qup_uart9_default: qup-uart9-default { 2774 pinmux { 2775 pins = "gpio4", "gpio5"; 2776 function = "qup9"; 2777 }; 2778 }; 2779 2780 qup_uart10_default: qup-uart10-default { 2781 pinmux { 2782 pins = "gpio53", "gpio54"; 2783 function = "qup10"; 2784 }; 2785 }; 2786 2787 qup_uart11_default: qup-uart11-default { 2788 pinmux { 2789 pins = "gpio33", "gpio34"; 2790 function = "qup11"; 2791 }; 2792 }; 2793 2794 qup_uart12_default: qup-uart12-default { 2795 pinmux { 2796 pins = "gpio51", "gpio52"; 2797 function = "qup12"; 2798 }; 2799 }; 2800 2801 qup_uart13_default: qup-uart13-default { 2802 pinmux { 2803 pins = "gpio107", "gpio108"; 2804 function = "qup13"; 2805 }; 2806 }; 2807 2808 qup_uart14_default: qup-uart14-default { 2809 pinmux { 2810 pins = "gpio31", "gpio32"; 2811 function = "qup14"; 2812 }; 2813 }; 2814 2815 qup_uart15_default: qup-uart15-default { 2816 pinmux { 2817 pins = "gpio83", "gpio84"; 2818 function = "qup15"; 2819 }; 2820 }; 2821 2822 quat_mi2s_sleep: quat_mi2s_sleep { 2823 mux { 2824 pins = "gpio58", "gpio59"; 2825 function = "gpio"; 2826 }; 2827 2828 config { 2829 pins = "gpio58", "gpio59"; 2830 drive-strength = <2>; 2831 bias-pull-down; 2832 input-enable; 2833 }; 2834 }; 2835 2836 quat_mi2s_active: quat_mi2s_active { 2837 mux { 2838 pins = "gpio58", "gpio59"; 2839 function = "qua_mi2s"; 2840 }; 2841 2842 config { 2843 pins = "gpio58", "gpio59"; 2844 drive-strength = <8>; 2845 bias-disable; 2846 output-high; 2847 }; 2848 }; 2849 2850 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { 2851 mux { 2852 pins = "gpio60"; 2853 function = "gpio"; 2854 }; 2855 2856 config { 2857 pins = "gpio60"; 2858 drive-strength = <2>; 2859 bias-pull-down; 2860 input-enable; 2861 }; 2862 }; 2863 2864 quat_mi2s_sd0_active: quat_mi2s_sd0_active { 2865 mux { 2866 pins = "gpio60"; 2867 function = "qua_mi2s"; 2868 }; 2869 2870 config { 2871 pins = "gpio60"; 2872 drive-strength = <8>; 2873 bias-disable; 2874 }; 2875 }; 2876 2877 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { 2878 mux { 2879 pins = "gpio61"; 2880 function = "gpio"; 2881 }; 2882 2883 config { 2884 pins = "gpio61"; 2885 drive-strength = <2>; 2886 bias-pull-down; 2887 input-enable; 2888 }; 2889 }; 2890 2891 quat_mi2s_sd1_active: quat_mi2s_sd1_active { 2892 mux { 2893 pins = "gpio61"; 2894 function = "qua_mi2s"; 2895 }; 2896 2897 config { 2898 pins = "gpio61"; 2899 drive-strength = <8>; 2900 bias-disable; 2901 }; 2902 }; 2903 2904 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { 2905 mux { 2906 pins = "gpio62"; 2907 function = "gpio"; 2908 }; 2909 2910 config { 2911 pins = "gpio62"; 2912 drive-strength = <2>; 2913 bias-pull-down; 2914 input-enable; 2915 }; 2916 }; 2917 2918 quat_mi2s_sd2_active: quat_mi2s_sd2_active { 2919 mux { 2920 pins = "gpio62"; 2921 function = "qua_mi2s"; 2922 }; 2923 2924 config { 2925 pins = "gpio62"; 2926 drive-strength = <8>; 2927 bias-disable; 2928 }; 2929 }; 2930 2931 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { 2932 mux { 2933 pins = "gpio63"; 2934 function = "gpio"; 2935 }; 2936 2937 config { 2938 pins = "gpio63"; 2939 drive-strength = <2>; 2940 bias-pull-down; 2941 input-enable; 2942 }; 2943 }; 2944 2945 quat_mi2s_sd3_active: quat_mi2s_sd3_active { 2946 mux { 2947 pins = "gpio63"; 2948 function = "qua_mi2s"; 2949 }; 2950 2951 config { 2952 pins = "gpio63"; 2953 drive-strength = <8>; 2954 bias-disable; 2955 }; 2956 }; 2957 }; 2958 2959 mss_pil: remoteproc@4080000 { 2960 compatible = "qcom,sdm845-mss-pil"; 2961 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 2962 reg-names = "qdsp6", "rmb"; 2963 2964 interrupts-extended = 2965 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2966 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2967 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2968 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2969 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2970 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2971 interrupt-names = "wdog", "fatal", "ready", 2972 "handover", "stop-ack", 2973 "shutdown-ack"; 2974 2975 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2976 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 2977 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2978 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 2979 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2980 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 2981 <&gcc GCC_PRNG_AHB_CLK>, 2982 <&rpmhcc RPMH_CXO_CLK>; 2983 clock-names = "iface", "bus", "mem", "gpll0_mss", 2984 "snoc_axi", "mnoc_axi", "prng", "xo"; 2985 2986 qcom,qmp = <&aoss_qmp>; 2987 2988 qcom,smem-states = <&modem_smp2p_out 0>; 2989 qcom,smem-state-names = "stop"; 2990 2991 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2992 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2993 reset-names = "mss_restart", "pdc_reset"; 2994 2995 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2996 2997 power-domains = <&rpmhpd SDM845_CX>, 2998 <&rpmhpd SDM845_MX>, 2999 <&rpmhpd SDM845_MSS>; 3000 power-domain-names = "cx", "mx", "mss"; 3001 3002 mba { 3003 memory-region = <&mba_region>; 3004 }; 3005 3006 mpss { 3007 memory-region = <&mpss_region>; 3008 }; 3009 3010 glink-edge { 3011 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 3012 label = "modem"; 3013 qcom,remote-pid = <1>; 3014 mboxes = <&apss_shared 12>; 3015 }; 3016 }; 3017 3018 gpucc: clock-controller@5090000 { 3019 compatible = "qcom,sdm845-gpucc"; 3020 reg = <0 0x05090000 0 0x9000>; 3021 #clock-cells = <1>; 3022 #reset-cells = <1>; 3023 #power-domain-cells = <1>; 3024 clocks = <&rpmhcc RPMH_CXO_CLK>, 3025 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3026 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3027 clock-names = "bi_tcxo", 3028 "gcc_gpu_gpll0_clk_src", 3029 "gcc_gpu_gpll0_div_clk_src"; 3030 }; 3031 3032 stm@6002000 { 3033 compatible = "arm,coresight-stm", "arm,primecell"; 3034 reg = <0 0x06002000 0 0x1000>, 3035 <0 0x16280000 0 0x180000>; 3036 reg-names = "stm-base", "stm-stimulus-base"; 3037 3038 clocks = <&aoss_qmp>; 3039 clock-names = "apb_pclk"; 3040 3041 out-ports { 3042 port { 3043 stm_out: endpoint { 3044 remote-endpoint = 3045 <&funnel0_in7>; 3046 }; 3047 }; 3048 }; 3049 }; 3050 3051 funnel@6041000 { 3052 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3053 reg = <0 0x06041000 0 0x1000>; 3054 3055 clocks = <&aoss_qmp>; 3056 clock-names = "apb_pclk"; 3057 3058 out-ports { 3059 port { 3060 funnel0_out: endpoint { 3061 remote-endpoint = 3062 <&merge_funnel_in0>; 3063 }; 3064 }; 3065 }; 3066 3067 in-ports { 3068 #address-cells = <1>; 3069 #size-cells = <0>; 3070 3071 port@7 { 3072 reg = <7>; 3073 funnel0_in7: endpoint { 3074 remote-endpoint = <&stm_out>; 3075 }; 3076 }; 3077 }; 3078 }; 3079 3080 funnel@6043000 { 3081 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3082 reg = <0 0x06043000 0 0x1000>; 3083 3084 clocks = <&aoss_qmp>; 3085 clock-names = "apb_pclk"; 3086 3087 out-ports { 3088 port { 3089 funnel2_out: endpoint { 3090 remote-endpoint = 3091 <&merge_funnel_in2>; 3092 }; 3093 }; 3094 }; 3095 3096 in-ports { 3097 #address-cells = <1>; 3098 #size-cells = <0>; 3099 3100 port@5 { 3101 reg = <5>; 3102 funnel2_in5: endpoint { 3103 remote-endpoint = 3104 <&apss_merge_funnel_out>; 3105 }; 3106 }; 3107 }; 3108 }; 3109 3110 funnel@6045000 { 3111 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3112 reg = <0 0x06045000 0 0x1000>; 3113 3114 clocks = <&aoss_qmp>; 3115 clock-names = "apb_pclk"; 3116 3117 out-ports { 3118 port { 3119 merge_funnel_out: endpoint { 3120 remote-endpoint = <&etf_in>; 3121 }; 3122 }; 3123 }; 3124 3125 in-ports { 3126 #address-cells = <1>; 3127 #size-cells = <0>; 3128 3129 port@0 { 3130 reg = <0>; 3131 merge_funnel_in0: endpoint { 3132 remote-endpoint = 3133 <&funnel0_out>; 3134 }; 3135 }; 3136 3137 port@2 { 3138 reg = <2>; 3139 merge_funnel_in2: endpoint { 3140 remote-endpoint = 3141 <&funnel2_out>; 3142 }; 3143 }; 3144 }; 3145 }; 3146 3147 replicator@6046000 { 3148 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3149 reg = <0 0x06046000 0 0x1000>; 3150 3151 clocks = <&aoss_qmp>; 3152 clock-names = "apb_pclk"; 3153 3154 out-ports { 3155 port { 3156 replicator_out: endpoint { 3157 remote-endpoint = <&etr_in>; 3158 }; 3159 }; 3160 }; 3161 3162 in-ports { 3163 port { 3164 replicator_in: endpoint { 3165 remote-endpoint = <&etf_out>; 3166 }; 3167 }; 3168 }; 3169 }; 3170 3171 etf@6047000 { 3172 compatible = "arm,coresight-tmc", "arm,primecell"; 3173 reg = <0 0x06047000 0 0x1000>; 3174 3175 clocks = <&aoss_qmp>; 3176 clock-names = "apb_pclk"; 3177 3178 out-ports { 3179 port { 3180 etf_out: endpoint { 3181 remote-endpoint = 3182 <&replicator_in>; 3183 }; 3184 }; 3185 }; 3186 3187 in-ports { 3188 #address-cells = <1>; 3189 #size-cells = <0>; 3190 3191 port@1 { 3192 reg = <1>; 3193 etf_in: endpoint { 3194 remote-endpoint = 3195 <&merge_funnel_out>; 3196 }; 3197 }; 3198 }; 3199 }; 3200 3201 etr@6048000 { 3202 compatible = "arm,coresight-tmc", "arm,primecell"; 3203 reg = <0 0x06048000 0 0x1000>; 3204 3205 clocks = <&aoss_qmp>; 3206 clock-names = "apb_pclk"; 3207 arm,scatter-gather; 3208 3209 in-ports { 3210 port { 3211 etr_in: endpoint { 3212 remote-endpoint = 3213 <&replicator_out>; 3214 }; 3215 }; 3216 }; 3217 }; 3218 3219 etm@7040000 { 3220 compatible = "arm,coresight-etm4x", "arm,primecell"; 3221 reg = <0 0x07040000 0 0x1000>; 3222 3223 cpu = <&CPU0>; 3224 3225 clocks = <&aoss_qmp>; 3226 clock-names = "apb_pclk"; 3227 arm,coresight-loses-context-with-cpu; 3228 3229 out-ports { 3230 port { 3231 etm0_out: endpoint { 3232 remote-endpoint = 3233 <&apss_funnel_in0>; 3234 }; 3235 }; 3236 }; 3237 }; 3238 3239 etm@7140000 { 3240 compatible = "arm,coresight-etm4x", "arm,primecell"; 3241 reg = <0 0x07140000 0 0x1000>; 3242 3243 cpu = <&CPU1>; 3244 3245 clocks = <&aoss_qmp>; 3246 clock-names = "apb_pclk"; 3247 arm,coresight-loses-context-with-cpu; 3248 3249 out-ports { 3250 port { 3251 etm1_out: endpoint { 3252 remote-endpoint = 3253 <&apss_funnel_in1>; 3254 }; 3255 }; 3256 }; 3257 }; 3258 3259 etm@7240000 { 3260 compatible = "arm,coresight-etm4x", "arm,primecell"; 3261 reg = <0 0x07240000 0 0x1000>; 3262 3263 cpu = <&CPU2>; 3264 3265 clocks = <&aoss_qmp>; 3266 clock-names = "apb_pclk"; 3267 arm,coresight-loses-context-with-cpu; 3268 3269 out-ports { 3270 port { 3271 etm2_out: endpoint { 3272 remote-endpoint = 3273 <&apss_funnel_in2>; 3274 }; 3275 }; 3276 }; 3277 }; 3278 3279 etm@7340000 { 3280 compatible = "arm,coresight-etm4x", "arm,primecell"; 3281 reg = <0 0x07340000 0 0x1000>; 3282 3283 cpu = <&CPU3>; 3284 3285 clocks = <&aoss_qmp>; 3286 clock-names = "apb_pclk"; 3287 arm,coresight-loses-context-with-cpu; 3288 3289 out-ports { 3290 port { 3291 etm3_out: endpoint { 3292 remote-endpoint = 3293 <&apss_funnel_in3>; 3294 }; 3295 }; 3296 }; 3297 }; 3298 3299 etm@7440000 { 3300 compatible = "arm,coresight-etm4x", "arm,primecell"; 3301 reg = <0 0x07440000 0 0x1000>; 3302 3303 cpu = <&CPU4>; 3304 3305 clocks = <&aoss_qmp>; 3306 clock-names = "apb_pclk"; 3307 arm,coresight-loses-context-with-cpu; 3308 3309 out-ports { 3310 port { 3311 etm4_out: endpoint { 3312 remote-endpoint = 3313 <&apss_funnel_in4>; 3314 }; 3315 }; 3316 }; 3317 }; 3318 3319 etm@7540000 { 3320 compatible = "arm,coresight-etm4x", "arm,primecell"; 3321 reg = <0 0x07540000 0 0x1000>; 3322 3323 cpu = <&CPU5>; 3324 3325 clocks = <&aoss_qmp>; 3326 clock-names = "apb_pclk"; 3327 arm,coresight-loses-context-with-cpu; 3328 3329 out-ports { 3330 port { 3331 etm5_out: endpoint { 3332 remote-endpoint = 3333 <&apss_funnel_in5>; 3334 }; 3335 }; 3336 }; 3337 }; 3338 3339 etm@7640000 { 3340 compatible = "arm,coresight-etm4x", "arm,primecell"; 3341 reg = <0 0x07640000 0 0x1000>; 3342 3343 cpu = <&CPU6>; 3344 3345 clocks = <&aoss_qmp>; 3346 clock-names = "apb_pclk"; 3347 arm,coresight-loses-context-with-cpu; 3348 3349 out-ports { 3350 port { 3351 etm6_out: endpoint { 3352 remote-endpoint = 3353 <&apss_funnel_in6>; 3354 }; 3355 }; 3356 }; 3357 }; 3358 3359 etm@7740000 { 3360 compatible = "arm,coresight-etm4x", "arm,primecell"; 3361 reg = <0 0x07740000 0 0x1000>; 3362 3363 cpu = <&CPU7>; 3364 3365 clocks = <&aoss_qmp>; 3366 clock-names = "apb_pclk"; 3367 arm,coresight-loses-context-with-cpu; 3368 3369 out-ports { 3370 port { 3371 etm7_out: endpoint { 3372 remote-endpoint = 3373 <&apss_funnel_in7>; 3374 }; 3375 }; 3376 }; 3377 }; 3378 3379 funnel@7800000 { /* APSS Funnel */ 3380 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3381 reg = <0 0x07800000 0 0x1000>; 3382 3383 clocks = <&aoss_qmp>; 3384 clock-names = "apb_pclk"; 3385 3386 out-ports { 3387 port { 3388 apss_funnel_out: endpoint { 3389 remote-endpoint = 3390 <&apss_merge_funnel_in>; 3391 }; 3392 }; 3393 }; 3394 3395 in-ports { 3396 #address-cells = <1>; 3397 #size-cells = <0>; 3398 3399 port@0 { 3400 reg = <0>; 3401 apss_funnel_in0: endpoint { 3402 remote-endpoint = 3403 <&etm0_out>; 3404 }; 3405 }; 3406 3407 port@1 { 3408 reg = <1>; 3409 apss_funnel_in1: endpoint { 3410 remote-endpoint = 3411 <&etm1_out>; 3412 }; 3413 }; 3414 3415 port@2 { 3416 reg = <2>; 3417 apss_funnel_in2: endpoint { 3418 remote-endpoint = 3419 <&etm2_out>; 3420 }; 3421 }; 3422 3423 port@3 { 3424 reg = <3>; 3425 apss_funnel_in3: endpoint { 3426 remote-endpoint = 3427 <&etm3_out>; 3428 }; 3429 }; 3430 3431 port@4 { 3432 reg = <4>; 3433 apss_funnel_in4: endpoint { 3434 remote-endpoint = 3435 <&etm4_out>; 3436 }; 3437 }; 3438 3439 port@5 { 3440 reg = <5>; 3441 apss_funnel_in5: endpoint { 3442 remote-endpoint = 3443 <&etm5_out>; 3444 }; 3445 }; 3446 3447 port@6 { 3448 reg = <6>; 3449 apss_funnel_in6: endpoint { 3450 remote-endpoint = 3451 <&etm6_out>; 3452 }; 3453 }; 3454 3455 port@7 { 3456 reg = <7>; 3457 apss_funnel_in7: endpoint { 3458 remote-endpoint = 3459 <&etm7_out>; 3460 }; 3461 }; 3462 }; 3463 }; 3464 3465 funnel@7810000 { 3466 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3467 reg = <0 0x07810000 0 0x1000>; 3468 3469 clocks = <&aoss_qmp>; 3470 clock-names = "apb_pclk"; 3471 3472 out-ports { 3473 port { 3474 apss_merge_funnel_out: endpoint { 3475 remote-endpoint = 3476 <&funnel2_in5>; 3477 }; 3478 }; 3479 }; 3480 3481 in-ports { 3482 port { 3483 apss_merge_funnel_in: endpoint { 3484 remote-endpoint = 3485 <&apss_funnel_out>; 3486 }; 3487 }; 3488 }; 3489 }; 3490 3491 sdhc_2: sdhci@8804000 { 3492 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3493 reg = <0 0x08804000 0 0x1000>; 3494 3495 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3497 interrupt-names = "hc_irq", "pwr_irq"; 3498 3499 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3500 <&gcc GCC_SDCC2_APPS_CLK>; 3501 clock-names = "iface", "core"; 3502 iommus = <&apps_smmu 0xa0 0xf>; 3503 power-domains = <&rpmhpd SDM845_CX>; 3504 operating-points-v2 = <&sdhc2_opp_table>; 3505 3506 status = "disabled"; 3507 3508 sdhc2_opp_table: sdhc2-opp-table { 3509 compatible = "operating-points-v2"; 3510 3511 opp-9600000 { 3512 opp-hz = /bits/ 64 <9600000>; 3513 required-opps = <&rpmhpd_opp_min_svs>; 3514 }; 3515 3516 opp-19200000 { 3517 opp-hz = /bits/ 64 <19200000>; 3518 required-opps = <&rpmhpd_opp_low_svs>; 3519 }; 3520 3521 opp-100000000 { 3522 opp-hz = /bits/ 64 <100000000>; 3523 required-opps = <&rpmhpd_opp_svs>; 3524 }; 3525 3526 opp-201500000 { 3527 opp-hz = /bits/ 64 <201500000>; 3528 required-opps = <&rpmhpd_opp_svs_l1>; 3529 }; 3530 }; 3531 }; 3532 3533 qspi_opp_table: qspi-opp-table { 3534 compatible = "operating-points-v2"; 3535 3536 opp-19200000 { 3537 opp-hz = /bits/ 64 <19200000>; 3538 required-opps = <&rpmhpd_opp_min_svs>; 3539 }; 3540 3541 opp-100000000 { 3542 opp-hz = /bits/ 64 <100000000>; 3543 required-opps = <&rpmhpd_opp_low_svs>; 3544 }; 3545 3546 opp-150000000 { 3547 opp-hz = /bits/ 64 <150000000>; 3548 required-opps = <&rpmhpd_opp_svs>; 3549 }; 3550 3551 opp-300000000 { 3552 opp-hz = /bits/ 64 <300000000>; 3553 required-opps = <&rpmhpd_opp_nom>; 3554 }; 3555 }; 3556 3557 qspi: spi@88df000 { 3558 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3559 reg = <0 0x088df000 0 0x600>; 3560 #address-cells = <1>; 3561 #size-cells = <0>; 3562 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3563 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3564 <&gcc GCC_QSPI_CORE_CLK>; 3565 clock-names = "iface", "core"; 3566 power-domains = <&rpmhpd SDM845_CX>; 3567 operating-points-v2 = <&qspi_opp_table>; 3568 status = "disabled"; 3569 }; 3570 3571 slim: slim@171c0000 { 3572 compatible = "qcom,slim-ngd-v2.1.0"; 3573 reg = <0 0x171c0000 0 0x2c000>; 3574 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3575 3576 qcom,apps-ch-pipes = <0x780000>; 3577 qcom,ea-pc = <0x270>; 3578 status = "okay"; 3579 dmas = <&slimbam 3>, <&slimbam 4>, 3580 <&slimbam 5>, <&slimbam 6>; 3581 dma-names = "rx", "tx", "tx2", "rx2"; 3582 3583 iommus = <&apps_smmu 0x1806 0x0>; 3584 #address-cells = <1>; 3585 #size-cells = <0>; 3586 3587 ngd@1 { 3588 reg = <1>; 3589 #address-cells = <2>; 3590 #size-cells = <0>; 3591 3592 wcd9340_ifd: ifd@0{ 3593 compatible = "slim217,250"; 3594 reg = <0 0>; 3595 }; 3596 3597 wcd9340: codec@1{ 3598 compatible = "slim217,250"; 3599 reg = <1 0>; 3600 slim-ifc-dev = <&wcd9340_ifd>; 3601 3602 #sound-dai-cells = <1>; 3603 3604 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; 3605 interrupt-controller; 3606 #interrupt-cells = <1>; 3607 3608 #clock-cells = <0>; 3609 clock-frequency = <9600000>; 3610 clock-output-names = "mclk"; 3611 qcom,micbias1-millivolt = <1800>; 3612 qcom,micbias2-millivolt = <1800>; 3613 qcom,micbias3-millivolt = <1800>; 3614 qcom,micbias4-millivolt = <1800>; 3615 3616 #address-cells = <1>; 3617 #size-cells = <1>; 3618 3619 wcdgpio: gpio-controller@42 { 3620 compatible = "qcom,wcd9340-gpio"; 3621 gpio-controller; 3622 #gpio-cells = <2>; 3623 reg = <0x42 0x2>; 3624 }; 3625 3626 swm: swm@c85 { 3627 compatible = "qcom,soundwire-v1.3.0"; 3628 reg = <0xc85 0x40>; 3629 interrupts-extended = <&wcd9340 20>; 3630 3631 qcom,dout-ports = <6>; 3632 qcom,din-ports = <2>; 3633 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; 3634 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; 3635 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; 3636 3637 #sound-dai-cells = <1>; 3638 clocks = <&wcd9340>; 3639 clock-names = "iface"; 3640 #address-cells = <2>; 3641 #size-cells = <0>; 3642 3643 3644 }; 3645 }; 3646 }; 3647 }; 3648 3649 lmh_cluster1: lmh@17d70800 { 3650 compatible = "qcom,sdm845-lmh"; 3651 reg = <0 0x17d70800 0 0x400>; 3652 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3653 cpus = <&CPU4>; 3654 qcom,lmh-temp-arm-millicelsius = <65000>; 3655 qcom,lmh-temp-low-millicelsius = <94500>; 3656 qcom,lmh-temp-high-millicelsius = <95000>; 3657 interrupt-controller; 3658 #interrupt-cells = <1>; 3659 }; 3660 3661 lmh_cluster0: lmh@17d78800 { 3662 compatible = "qcom,sdm845-lmh"; 3663 reg = <0 0x17d78800 0 0x400>; 3664 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3665 cpus = <&CPU0>; 3666 qcom,lmh-temp-arm-millicelsius = <65000>; 3667 qcom,lmh-temp-low-millicelsius = <94500>; 3668 qcom,lmh-temp-high-millicelsius = <95000>; 3669 interrupt-controller; 3670 #interrupt-cells = <1>; 3671 }; 3672 3673 sound: sound { 3674 }; 3675 3676 usb_1_hsphy: phy@88e2000 { 3677 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3678 reg = <0 0x088e2000 0 0x400>; 3679 status = "disabled"; 3680 #phy-cells = <0>; 3681 3682 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3683 <&rpmhcc RPMH_CXO_CLK>; 3684 clock-names = "cfg_ahb", "ref"; 3685 3686 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3687 3688 nvmem-cells = <&qusb2p_hstx_trim>; 3689 }; 3690 3691 usb_2_hsphy: phy@88e3000 { 3692 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3693 reg = <0 0x088e3000 0 0x400>; 3694 status = "disabled"; 3695 #phy-cells = <0>; 3696 3697 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3698 <&rpmhcc RPMH_CXO_CLK>; 3699 clock-names = "cfg_ahb", "ref"; 3700 3701 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3702 3703 nvmem-cells = <&qusb2s_hstx_trim>; 3704 }; 3705 3706 usb_1_qmpphy: phy@88e9000 { 3707 compatible = "qcom,sdm845-qmp-usb3-phy"; 3708 reg = <0 0x088e9000 0 0x18c>, 3709 <0 0x088e8000 0 0x10>; 3710 reg-names = "reg-base", "dp_com"; 3711 status = "disabled"; 3712 #address-cells = <2>; 3713 #size-cells = <2>; 3714 ranges; 3715 3716 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3717 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3718 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3719 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3720 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3721 3722 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3723 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3724 reset-names = "phy", "common"; 3725 3726 usb_1_ssphy: lanes@88e9200 { 3727 reg = <0 0x088e9200 0 0x128>, 3728 <0 0x088e9400 0 0x200>, 3729 <0 0x088e9c00 0 0x218>, 3730 <0 0x088e9600 0 0x128>, 3731 <0 0x088e9800 0 0x200>, 3732 <0 0x088e9a00 0 0x100>; 3733 #clock-cells = <0>; 3734 #phy-cells = <0>; 3735 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3736 clock-names = "pipe0"; 3737 clock-output-names = "usb3_phy_pipe_clk_src"; 3738 }; 3739 }; 3740 3741 usb_2_qmpphy: phy@88eb000 { 3742 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 3743 reg = <0 0x088eb000 0 0x18c>; 3744 status = "disabled"; 3745 #address-cells = <2>; 3746 #size-cells = <2>; 3747 ranges; 3748 3749 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3750 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3751 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3752 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3753 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3754 3755 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3756 <&gcc GCC_USB3_PHY_SEC_BCR>; 3757 reset-names = "phy", "common"; 3758 3759 usb_2_ssphy: lane@88eb200 { 3760 reg = <0 0x088eb200 0 0x128>, 3761 <0 0x088eb400 0 0x1fc>, 3762 <0 0x088eb800 0 0x218>, 3763 <0 0x088eb600 0 0x70>; 3764 #clock-cells = <0>; 3765 #phy-cells = <0>; 3766 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3767 clock-names = "pipe0"; 3768 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3769 }; 3770 }; 3771 3772 usb_1: usb@a6f8800 { 3773 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3774 reg = <0 0x0a6f8800 0 0x400>; 3775 status = "disabled"; 3776 #address-cells = <2>; 3777 #size-cells = <2>; 3778 ranges; 3779 dma-ranges; 3780 3781 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3782 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3783 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3784 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3785 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 3786 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3787 "sleep"; 3788 3789 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3790 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3791 assigned-clock-rates = <19200000>, <150000000>; 3792 3793 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3797 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3798 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3799 3800 power-domains = <&gcc USB30_PRIM_GDSC>; 3801 3802 resets = <&gcc GCC_USB30_PRIM_BCR>; 3803 3804 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 3805 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3806 interconnect-names = "usb-ddr", "apps-usb"; 3807 3808 usb_1_dwc3: dwc3@a600000 { 3809 compatible = "snps,dwc3"; 3810 reg = <0 0x0a600000 0 0xcd00>; 3811 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3812 iommus = <&apps_smmu 0x740 0>; 3813 snps,dis_u2_susphy_quirk; 3814 snps,dis_enblslpm_quirk; 3815 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3816 phy-names = "usb2-phy", "usb3-phy"; 3817 }; 3818 }; 3819 3820 usb_2: usb@a8f8800 { 3821 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3822 reg = <0 0x0a8f8800 0 0x400>; 3823 status = "disabled"; 3824 #address-cells = <2>; 3825 #size-cells = <2>; 3826 ranges; 3827 dma-ranges; 3828 3829 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3830 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3831 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3832 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3833 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 3834 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3835 "sleep"; 3836 3837 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3838 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3839 assigned-clock-rates = <19200000>, <150000000>; 3840 3841 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3842 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3843 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3845 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3846 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3847 3848 power-domains = <&gcc USB30_SEC_GDSC>; 3849 3850 resets = <&gcc GCC_USB30_SEC_BCR>; 3851 3852 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 3853 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3854 interconnect-names = "usb-ddr", "apps-usb"; 3855 3856 usb_2_dwc3: dwc3@a800000 { 3857 compatible = "snps,dwc3"; 3858 reg = <0 0x0a800000 0 0xcd00>; 3859 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3860 iommus = <&apps_smmu 0x760 0>; 3861 snps,dis_u2_susphy_quirk; 3862 snps,dis_enblslpm_quirk; 3863 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3864 phy-names = "usb2-phy", "usb3-phy"; 3865 }; 3866 }; 3867 3868 venus: video-codec@aa00000 { 3869 compatible = "qcom,sdm845-venus-v2"; 3870 reg = <0 0x0aa00000 0 0xff000>; 3871 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3872 power-domains = <&videocc VENUS_GDSC>, 3873 <&videocc VCODEC0_GDSC>, 3874 <&videocc VCODEC1_GDSC>, 3875 <&rpmhpd SDM845_CX>; 3876 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 3877 operating-points-v2 = <&venus_opp_table>; 3878 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3879 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3880 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3881 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3882 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 3883 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 3884 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 3885 clock-names = "core", "iface", "bus", 3886 "vcodec0_core", "vcodec0_bus", 3887 "vcodec1_core", "vcodec1_bus"; 3888 iommus = <&apps_smmu 0x10a0 0x8>, 3889 <&apps_smmu 0x10b0 0x0>; 3890 memory-region = <&venus_mem>; 3891 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, 3892 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 3893 interconnect-names = "video-mem", "cpu-cfg"; 3894 3895 video-core0 { 3896 compatible = "venus-decoder"; 3897 }; 3898 3899 video-core1 { 3900 compatible = "venus-encoder"; 3901 }; 3902 3903 venus_opp_table: venus-opp-table { 3904 compatible = "operating-points-v2"; 3905 3906 opp-100000000 { 3907 opp-hz = /bits/ 64 <100000000>; 3908 required-opps = <&rpmhpd_opp_min_svs>; 3909 }; 3910 3911 opp-200000000 { 3912 opp-hz = /bits/ 64 <200000000>; 3913 required-opps = <&rpmhpd_opp_low_svs>; 3914 }; 3915 3916 opp-320000000 { 3917 opp-hz = /bits/ 64 <320000000>; 3918 required-opps = <&rpmhpd_opp_svs>; 3919 }; 3920 3921 opp-380000000 { 3922 opp-hz = /bits/ 64 <380000000>; 3923 required-opps = <&rpmhpd_opp_svs_l1>; 3924 }; 3925 3926 opp-444000000 { 3927 opp-hz = /bits/ 64 <444000000>; 3928 required-opps = <&rpmhpd_opp_nom>; 3929 }; 3930 3931 opp-533000097 { 3932 opp-hz = /bits/ 64 <533000097>; 3933 required-opps = <&rpmhpd_opp_turbo>; 3934 }; 3935 }; 3936 }; 3937 3938 videocc: clock-controller@ab00000 { 3939 compatible = "qcom,sdm845-videocc"; 3940 reg = <0 0x0ab00000 0 0x10000>; 3941 clocks = <&rpmhcc RPMH_CXO_CLK>; 3942 clock-names = "bi_tcxo"; 3943 #clock-cells = <1>; 3944 #power-domain-cells = <1>; 3945 #reset-cells = <1>; 3946 }; 3947 3948 camss: camss@a00000 { 3949 compatible = "qcom,sdm845-camss"; 3950 3951 reg = <0 0xacb3000 0 0x1000>, 3952 <0 0xacba000 0 0x1000>, 3953 <0 0xacc8000 0 0x1000>, 3954 <0 0xac65000 0 0x1000>, 3955 <0 0xac66000 0 0x1000>, 3956 <0 0xac67000 0 0x1000>, 3957 <0 0xac68000 0 0x1000>, 3958 <0 0xacaf000 0 0x4000>, 3959 <0 0xacb6000 0 0x4000>, 3960 <0 0xacc4000 0 0x4000>; 3961 reg-names = "csid0", 3962 "csid1", 3963 "csid2", 3964 "csiphy0", 3965 "csiphy1", 3966 "csiphy2", 3967 "csiphy3", 3968 "vfe0", 3969 "vfe1", 3970 "vfe_lite"; 3971 3972 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3973 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3974 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3975 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 3976 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 3977 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 3978 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 3979 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3980 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3981 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 3982 interrupt-names = "csid0", 3983 "csid1", 3984 "csid2", 3985 "csiphy0", 3986 "csiphy1", 3987 "csiphy2", 3988 "csiphy3", 3989 "vfe0", 3990 "vfe1", 3991 "vfe_lite"; 3992 3993 power-domains = <&clock_camcc IFE_0_GDSC>, 3994 <&clock_camcc IFE_1_GDSC>, 3995 <&clock_camcc TITAN_TOP_GDSC>; 3996 3997 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 3998 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 3999 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, 4000 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, 4001 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, 4002 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, 4003 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, 4004 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, 4005 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, 4006 <&clock_camcc CAM_CC_CSIPHY0_CLK>, 4007 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, 4008 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, 4009 <&clock_camcc CAM_CC_CSIPHY1_CLK>, 4010 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, 4011 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, 4012 <&clock_camcc CAM_CC_CSIPHY2_CLK>, 4013 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, 4014 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, 4015 <&clock_camcc CAM_CC_CSIPHY3_CLK>, 4016 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, 4017 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, 4018 <&gcc GCC_CAMERA_AHB_CLK>, 4019 <&gcc GCC_CAMERA_AXI_CLK>, 4020 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4021 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4022 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, 4023 <&clock_camcc CAM_CC_IFE_0_CLK>, 4024 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4025 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, 4026 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, 4027 <&clock_camcc CAM_CC_IFE_1_CLK>, 4028 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4029 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, 4030 <&clock_camcc CAM_CC_IFE_LITE_CLK>, 4031 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4032 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; 4033 clock-names = "camnoc_axi", 4034 "cpas_ahb", 4035 "cphy_rx_src", 4036 "csi0", 4037 "csi0_src", 4038 "csi1", 4039 "csi1_src", 4040 "csi2", 4041 "csi2_src", 4042 "csiphy0", 4043 "csiphy0_timer", 4044 "csiphy0_timer_src", 4045 "csiphy1", 4046 "csiphy1_timer", 4047 "csiphy1_timer_src", 4048 "csiphy2", 4049 "csiphy2_timer", 4050 "csiphy2_timer_src", 4051 "csiphy3", 4052 "csiphy3_timer", 4053 "csiphy3_timer_src", 4054 "gcc_camera_ahb", 4055 "gcc_camera_axi", 4056 "slow_ahb_src", 4057 "soc_ahb", 4058 "vfe0_axi", 4059 "vfe0", 4060 "vfe0_cphy_rx", 4061 "vfe0_src", 4062 "vfe1_axi", 4063 "vfe1", 4064 "vfe1_cphy_rx", 4065 "vfe1_src", 4066 "vfe_lite", 4067 "vfe_lite_cphy_rx", 4068 "vfe_lite_src"; 4069 4070 iommus = <&apps_smmu 0x0808 0x0>, 4071 <&apps_smmu 0x0810 0x8>, 4072 <&apps_smmu 0x0c08 0x0>, 4073 <&apps_smmu 0x0c10 0x8>; 4074 4075 status = "disabled"; 4076 4077 ports { 4078 #address-cells = <1>; 4079 #size-cells = <0>; 4080 }; 4081 }; 4082 4083 cci: cci@ac4a000 { 4084 compatible = "qcom,sdm845-cci"; 4085 #address-cells = <1>; 4086 #size-cells = <0>; 4087 4088 reg = <0 0x0ac4a000 0 0x4000>; 4089 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4090 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 4091 4092 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4093 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4094 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4095 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4096 <&clock_camcc CAM_CC_CCI_CLK>, 4097 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 4098 clock-names = "camnoc_axi", 4099 "soc_ahb", 4100 "slow_ahb_src", 4101 "cpas_ahb", 4102 "cci", 4103 "cci_src"; 4104 4105 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4106 <&clock_camcc CAM_CC_CCI_CLK>; 4107 assigned-clock-rates = <80000000>, <37500000>; 4108 4109 pinctrl-names = "default", "sleep"; 4110 pinctrl-0 = <&cci0_default &cci1_default>; 4111 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4112 4113 status = "disabled"; 4114 4115 cci_i2c0: i2c-bus@0 { 4116 reg = <0>; 4117 clock-frequency = <1000000>; 4118 #address-cells = <1>; 4119 #size-cells = <0>; 4120 }; 4121 4122 cci_i2c1: i2c-bus@1 { 4123 reg = <1>; 4124 clock-frequency = <1000000>; 4125 #address-cells = <1>; 4126 #size-cells = <0>; 4127 }; 4128 }; 4129 4130 clock_camcc: clock-controller@ad00000 { 4131 compatible = "qcom,sdm845-camcc"; 4132 reg = <0 0x0ad00000 0 0x10000>; 4133 #clock-cells = <1>; 4134 #reset-cells = <1>; 4135 #power-domain-cells = <1>; 4136 }; 4137 4138 dsi_opp_table: dsi-opp-table { 4139 compatible = "operating-points-v2"; 4140 4141 opp-19200000 { 4142 opp-hz = /bits/ 64 <19200000>; 4143 required-opps = <&rpmhpd_opp_min_svs>; 4144 }; 4145 4146 opp-180000000 { 4147 opp-hz = /bits/ 64 <180000000>; 4148 required-opps = <&rpmhpd_opp_low_svs>; 4149 }; 4150 4151 opp-275000000 { 4152 opp-hz = /bits/ 64 <275000000>; 4153 required-opps = <&rpmhpd_opp_svs>; 4154 }; 4155 4156 opp-328580000 { 4157 opp-hz = /bits/ 64 <328580000>; 4158 required-opps = <&rpmhpd_opp_svs_l1>; 4159 }; 4160 4161 opp-358000000 { 4162 opp-hz = /bits/ 64 <358000000>; 4163 required-opps = <&rpmhpd_opp_nom>; 4164 }; 4165 }; 4166 4167 mdss: mdss@ae00000 { 4168 compatible = "qcom,sdm845-mdss"; 4169 reg = <0 0x0ae00000 0 0x1000>; 4170 reg-names = "mdss"; 4171 4172 power-domains = <&dispcc MDSS_GDSC>; 4173 4174 clocks = <&gcc GCC_DISP_AHB_CLK>, 4175 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4176 clock-names = "iface", "core"; 4177 4178 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 4179 assigned-clock-rates = <300000000>; 4180 4181 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4182 interrupt-controller; 4183 #interrupt-cells = <1>; 4184 4185 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 4186 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 4187 interconnect-names = "mdp0-mem", "mdp1-mem"; 4188 4189 iommus = <&apps_smmu 0x880 0x8>, 4190 <&apps_smmu 0xc80 0x8>; 4191 4192 status = "disabled"; 4193 4194 #address-cells = <2>; 4195 #size-cells = <2>; 4196 ranges; 4197 4198 mdss_mdp: mdp@ae01000 { 4199 compatible = "qcom,sdm845-dpu"; 4200 reg = <0 0x0ae01000 0 0x8f000>, 4201 <0 0x0aeb0000 0 0x2008>; 4202 reg-names = "mdp", "vbif"; 4203 4204 clocks = <&gcc GCC_DISP_AXI_CLK>, 4205 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4206 <&dispcc DISP_CC_MDSS_AXI_CLK>, 4207 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4208 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4209 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 4210 4211 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 4212 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4213 assigned-clock-rates = <300000000>, 4214 <19200000>; 4215 operating-points-v2 = <&mdp_opp_table>; 4216 power-domains = <&rpmhpd SDM845_CX>; 4217 4218 interrupt-parent = <&mdss>; 4219 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 4220 4221 status = "disabled"; 4222 4223 ports { 4224 #address-cells = <1>; 4225 #size-cells = <0>; 4226 4227 port@0 { 4228 reg = <0>; 4229 dpu_intf1_out: endpoint { 4230 remote-endpoint = <&dsi0_in>; 4231 }; 4232 }; 4233 4234 port@1 { 4235 reg = <1>; 4236 dpu_intf2_out: endpoint { 4237 remote-endpoint = <&dsi1_in>; 4238 }; 4239 }; 4240 }; 4241 4242 mdp_opp_table: mdp-opp-table { 4243 compatible = "operating-points-v2"; 4244 4245 opp-19200000 { 4246 opp-hz = /bits/ 64 <19200000>; 4247 required-opps = <&rpmhpd_opp_min_svs>; 4248 }; 4249 4250 opp-171428571 { 4251 opp-hz = /bits/ 64 <171428571>; 4252 required-opps = <&rpmhpd_opp_low_svs>; 4253 }; 4254 4255 opp-344000000 { 4256 opp-hz = /bits/ 64 <344000000>; 4257 required-opps = <&rpmhpd_opp_svs_l1>; 4258 }; 4259 4260 opp-430000000 { 4261 opp-hz = /bits/ 64 <430000000>; 4262 required-opps = <&rpmhpd_opp_nom>; 4263 }; 4264 }; 4265 }; 4266 4267 dsi0: dsi@ae94000 { 4268 compatible = "qcom,mdss-dsi-ctrl"; 4269 reg = <0 0x0ae94000 0 0x400>; 4270 reg-names = "dsi_ctrl"; 4271 4272 interrupt-parent = <&mdss>; 4273 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 4274 4275 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4276 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4277 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4278 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4279 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4280 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4281 clock-names = "byte", 4282 "byte_intf", 4283 "pixel", 4284 "core", 4285 "iface", 4286 "bus"; 4287 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4288 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 4289 4290 operating-points-v2 = <&dsi_opp_table>; 4291 power-domains = <&rpmhpd SDM845_CX>; 4292 4293 phys = <&dsi0_phy>; 4294 phy-names = "dsi"; 4295 4296 status = "disabled"; 4297 4298 ports { 4299 #address-cells = <1>; 4300 #size-cells = <0>; 4301 4302 port@0 { 4303 reg = <0>; 4304 dsi0_in: endpoint { 4305 remote-endpoint = <&dpu_intf1_out>; 4306 }; 4307 }; 4308 4309 port@1 { 4310 reg = <1>; 4311 dsi0_out: endpoint { 4312 }; 4313 }; 4314 }; 4315 }; 4316 4317 dsi0_phy: dsi-phy@ae94400 { 4318 compatible = "qcom,dsi-phy-10nm"; 4319 reg = <0 0x0ae94400 0 0x200>, 4320 <0 0x0ae94600 0 0x280>, 4321 <0 0x0ae94a00 0 0x1e0>; 4322 reg-names = "dsi_phy", 4323 "dsi_phy_lane", 4324 "dsi_pll"; 4325 4326 #clock-cells = <1>; 4327 #phy-cells = <0>; 4328 4329 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4330 <&rpmhcc RPMH_CXO_CLK>; 4331 clock-names = "iface", "ref"; 4332 4333 status = "disabled"; 4334 }; 4335 4336 dsi1: dsi@ae96000 { 4337 compatible = "qcom,mdss-dsi-ctrl"; 4338 reg = <0 0x0ae96000 0 0x400>; 4339 reg-names = "dsi_ctrl"; 4340 4341 interrupt-parent = <&mdss>; 4342 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 4343 4344 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4345 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4346 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4347 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4348 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4349 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4350 clock-names = "byte", 4351 "byte_intf", 4352 "pixel", 4353 "core", 4354 "iface", 4355 "bus"; 4356 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4357 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 4358 4359 operating-points-v2 = <&dsi_opp_table>; 4360 power-domains = <&rpmhpd SDM845_CX>; 4361 4362 phys = <&dsi1_phy>; 4363 phy-names = "dsi"; 4364 4365 status = "disabled"; 4366 4367 ports { 4368 #address-cells = <1>; 4369 #size-cells = <0>; 4370 4371 port@0 { 4372 reg = <0>; 4373 dsi1_in: endpoint { 4374 remote-endpoint = <&dpu_intf2_out>; 4375 }; 4376 }; 4377 4378 port@1 { 4379 reg = <1>; 4380 dsi1_out: endpoint { 4381 }; 4382 }; 4383 }; 4384 }; 4385 4386 dsi1_phy: dsi-phy@ae96400 { 4387 compatible = "qcom,dsi-phy-10nm"; 4388 reg = <0 0x0ae96400 0 0x200>, 4389 <0 0x0ae96600 0 0x280>, 4390 <0 0x0ae96a00 0 0x10e>; 4391 reg-names = "dsi_phy", 4392 "dsi_phy_lane", 4393 "dsi_pll"; 4394 4395 #clock-cells = <1>; 4396 #phy-cells = <0>; 4397 4398 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4399 <&rpmhcc RPMH_CXO_CLK>; 4400 clock-names = "iface", "ref"; 4401 4402 status = "disabled"; 4403 }; 4404 }; 4405 4406 gpu: gpu@5000000 { 4407 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4408 #stream-id-cells = <16>; 4409 4410 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; 4411 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4412 4413 /* 4414 * Look ma, no clocks! The GPU clocks and power are 4415 * controlled entirely by the GMU 4416 */ 4417 4418 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4419 4420 iommus = <&adreno_smmu 0>; 4421 4422 operating-points-v2 = <&gpu_opp_table>; 4423 4424 qcom,gmu = <&gmu>; 4425 4426 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4427 interconnect-names = "gfx-mem"; 4428 4429 gpu_opp_table: opp-table { 4430 compatible = "operating-points-v2"; 4431 4432 opp-710000000 { 4433 opp-hz = /bits/ 64 <710000000>; 4434 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4435 opp-peak-kBps = <7216000>; 4436 }; 4437 4438 opp-675000000 { 4439 opp-hz = /bits/ 64 <675000000>; 4440 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4441 opp-peak-kBps = <7216000>; 4442 }; 4443 4444 opp-596000000 { 4445 opp-hz = /bits/ 64 <596000000>; 4446 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4447 opp-peak-kBps = <6220000>; 4448 }; 4449 4450 opp-520000000 { 4451 opp-hz = /bits/ 64 <520000000>; 4452 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4453 opp-peak-kBps = <6220000>; 4454 }; 4455 4456 opp-414000000 { 4457 opp-hz = /bits/ 64 <414000000>; 4458 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4459 opp-peak-kBps = <4068000>; 4460 }; 4461 4462 opp-342000000 { 4463 opp-hz = /bits/ 64 <342000000>; 4464 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4465 opp-peak-kBps = <2724000>; 4466 }; 4467 4468 opp-257000000 { 4469 opp-hz = /bits/ 64 <257000000>; 4470 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4471 opp-peak-kBps = <1648000>; 4472 }; 4473 }; 4474 }; 4475 4476 adreno_smmu: iommu@5040000 { 4477 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 4478 reg = <0 0x5040000 0 0x10000>; 4479 #iommu-cells = <1>; 4480 #global-interrupts = <2>; 4481 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4482 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4483 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4484 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4485 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4486 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4487 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4488 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4489 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4490 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4491 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4492 <&gcc GCC_GPU_CFG_AHB_CLK>; 4493 clock-names = "bus", "iface"; 4494 4495 power-domains = <&gpucc GPU_CX_GDSC>; 4496 }; 4497 4498 gmu: gmu@506a000 { 4499 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4500 4501 reg = <0 0x506a000 0 0x30000>, 4502 <0 0xb280000 0 0x10000>, 4503 <0 0xb480000 0 0x10000>; 4504 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4505 4506 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4507 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4508 interrupt-names = "hfi", "gmu"; 4509 4510 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4511 <&gpucc GPU_CC_CXO_CLK>, 4512 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4513 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4514 clock-names = "gmu", "cxo", "axi", "memnoc"; 4515 4516 power-domains = <&gpucc GPU_CX_GDSC>, 4517 <&gpucc GPU_GX_GDSC>; 4518 power-domain-names = "cx", "gx"; 4519 4520 iommus = <&adreno_smmu 5>; 4521 4522 operating-points-v2 = <&gmu_opp_table>; 4523 4524 gmu_opp_table: opp-table { 4525 compatible = "operating-points-v2"; 4526 4527 opp-400000000 { 4528 opp-hz = /bits/ 64 <400000000>; 4529 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4530 }; 4531 4532 opp-200000000 { 4533 opp-hz = /bits/ 64 <200000000>; 4534 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4535 }; 4536 }; 4537 }; 4538 4539 dispcc: clock-controller@af00000 { 4540 compatible = "qcom,sdm845-dispcc"; 4541 reg = <0 0x0af00000 0 0x10000>; 4542 clocks = <&rpmhcc RPMH_CXO_CLK>, 4543 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4544 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4545 <&dsi0_phy 0>, 4546 <&dsi0_phy 1>, 4547 <&dsi1_phy 0>, 4548 <&dsi1_phy 1>, 4549 <0>, 4550 <0>; 4551 clock-names = "bi_tcxo", 4552 "gcc_disp_gpll0_clk_src", 4553 "gcc_disp_gpll0_div_clk_src", 4554 "dsi0_phy_pll_out_byteclk", 4555 "dsi0_phy_pll_out_dsiclk", 4556 "dsi1_phy_pll_out_byteclk", 4557 "dsi1_phy_pll_out_dsiclk", 4558 "dp_link_clk_divsel_ten", 4559 "dp_vco_divided_clk_src_mux"; 4560 #clock-cells = <1>; 4561 #reset-cells = <1>; 4562 #power-domain-cells = <1>; 4563 }; 4564 4565 pdc_intc: interrupt-controller@b220000 { 4566 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 4567 reg = <0 0x0b220000 0 0x30000>; 4568 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 4569 #interrupt-cells = <2>; 4570 interrupt-parent = <&intc>; 4571 interrupt-controller; 4572 }; 4573 4574 pdc_reset: reset-controller@b2e0000 { 4575 compatible = "qcom,sdm845-pdc-global"; 4576 reg = <0 0x0b2e0000 0 0x20000>; 4577 #reset-cells = <1>; 4578 }; 4579 4580 tsens0: thermal-sensor@c263000 { 4581 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4582 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4583 <0 0x0c222000 0 0x1ff>; /* SROT */ 4584 #qcom,sensors = <13>; 4585 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4586 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4587 interrupt-names = "uplow", "critical"; 4588 #thermal-sensor-cells = <1>; 4589 }; 4590 4591 tsens1: thermal-sensor@c265000 { 4592 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4593 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4594 <0 0x0c223000 0 0x1ff>; /* SROT */ 4595 #qcom,sensors = <8>; 4596 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4597 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4598 interrupt-names = "uplow", "critical"; 4599 #thermal-sensor-cells = <1>; 4600 }; 4601 4602 aoss_reset: reset-controller@c2a0000 { 4603 compatible = "qcom,sdm845-aoss-cc"; 4604 reg = <0 0x0c2a0000 0 0x31000>; 4605 #reset-cells = <1>; 4606 }; 4607 4608 aoss_qmp: power-controller@c300000 { 4609 compatible = "qcom,sdm845-aoss-qmp"; 4610 reg = <0 0x0c300000 0 0x100000>; 4611 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4612 mboxes = <&apss_shared 0>; 4613 4614 #clock-cells = <0>; 4615 4616 cx_cdev: cx { 4617 #cooling-cells = <2>; 4618 }; 4619 4620 ebi_cdev: ebi { 4621 #cooling-cells = <2>; 4622 }; 4623 }; 4624 4625 spmi_bus: spmi@c440000 { 4626 compatible = "qcom,spmi-pmic-arb"; 4627 reg = <0 0x0c440000 0 0x1100>, 4628 <0 0x0c600000 0 0x2000000>, 4629 <0 0x0e600000 0 0x100000>, 4630 <0 0x0e700000 0 0xa0000>, 4631 <0 0x0c40a000 0 0x26000>; 4632 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4633 interrupt-names = "periph_irq"; 4634 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4635 qcom,ee = <0>; 4636 qcom,channel = <0>; 4637 #address-cells = <2>; 4638 #size-cells = <0>; 4639 interrupt-controller; 4640 #interrupt-cells = <4>; 4641 cell-index = <0>; 4642 }; 4643 4644 imem@146bf000 { 4645 compatible = "simple-mfd"; 4646 reg = <0 0x146bf000 0 0x1000>; 4647 4648 #address-cells = <1>; 4649 #size-cells = <1>; 4650 4651 ranges = <0 0 0x146bf000 0x1000>; 4652 4653 pil-reloc@94c { 4654 compatible = "qcom,pil-reloc-info"; 4655 reg = <0x94c 0xc8>; 4656 }; 4657 }; 4658 4659 apps_smmu: iommu@15000000 { 4660 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 4661 reg = <0 0x15000000 0 0x80000>; 4662 #iommu-cells = <2>; 4663 #global-interrupts = <1>; 4664 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4665 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4666 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4667 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4668 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4669 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4670 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4671 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4672 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4673 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4674 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4675 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4676 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4677 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4678 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4679 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4680 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4681 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4682 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4683 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4684 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4685 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4686 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4687 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4688 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4689 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4690 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4691 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4692 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4693 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4694 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4695 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4696 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4697 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4698 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4699 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4700 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4701 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4702 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4703 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4704 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4705 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4706 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4707 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4708 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4709 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4710 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4711 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4712 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4713 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4714 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4715 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4716 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4717 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4718 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4719 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4720 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4721 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4722 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4723 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4724 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4725 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4726 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4727 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4728 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 4729 }; 4730 4731 lpasscc: clock-controller@17014000 { 4732 compatible = "qcom,sdm845-lpasscc"; 4733 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 4734 reg-names = "cc", "qdsp6ss"; 4735 #clock-cells = <1>; 4736 status = "disabled"; 4737 }; 4738 4739 gladiator_noc: interconnect@17900000 { 4740 compatible = "qcom,sdm845-gladiator-noc"; 4741 reg = <0 0x17900000 0 0xd080>; 4742 #interconnect-cells = <2>; 4743 qcom,bcm-voters = <&apps_bcm_voter>; 4744 }; 4745 4746 watchdog@17980000 { 4747 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 4748 reg = <0 0x17980000 0 0x1000>; 4749 clocks = <&sleep_clk>; 4750 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4751 }; 4752 4753 apss_shared: mailbox@17990000 { 4754 compatible = "qcom,sdm845-apss-shared"; 4755 reg = <0 0x17990000 0 0x1000>; 4756 #mbox-cells = <1>; 4757 }; 4758 4759 apps_rsc: rsc@179c0000 { 4760 label = "apps_rsc"; 4761 compatible = "qcom,rpmh-rsc"; 4762 reg = <0 0x179c0000 0 0x10000>, 4763 <0 0x179d0000 0 0x10000>, 4764 <0 0x179e0000 0 0x10000>; 4765 reg-names = "drv-0", "drv-1", "drv-2"; 4766 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4767 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4768 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4769 qcom,tcs-offset = <0xd00>; 4770 qcom,drv-id = <2>; 4771 qcom,tcs-config = <ACTIVE_TCS 2>, 4772 <SLEEP_TCS 3>, 4773 <WAKE_TCS 3>, 4774 <CONTROL_TCS 1>; 4775 4776 apps_bcm_voter: bcm-voter { 4777 compatible = "qcom,bcm-voter"; 4778 }; 4779 4780 rpmhcc: clock-controller { 4781 compatible = "qcom,sdm845-rpmh-clk"; 4782 #clock-cells = <1>; 4783 clock-names = "xo"; 4784 clocks = <&xo_board>; 4785 }; 4786 4787 rpmhpd: power-controller { 4788 compatible = "qcom,sdm845-rpmhpd"; 4789 #power-domain-cells = <1>; 4790 operating-points-v2 = <&rpmhpd_opp_table>; 4791 4792 rpmhpd_opp_table: opp-table { 4793 compatible = "operating-points-v2"; 4794 4795 rpmhpd_opp_ret: opp1 { 4796 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4797 }; 4798 4799 rpmhpd_opp_min_svs: opp2 { 4800 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4801 }; 4802 4803 rpmhpd_opp_low_svs: opp3 { 4804 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4805 }; 4806 4807 rpmhpd_opp_svs: opp4 { 4808 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4809 }; 4810 4811 rpmhpd_opp_svs_l1: opp5 { 4812 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4813 }; 4814 4815 rpmhpd_opp_nom: opp6 { 4816 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4817 }; 4818 4819 rpmhpd_opp_nom_l1: opp7 { 4820 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4821 }; 4822 4823 rpmhpd_opp_nom_l2: opp8 { 4824 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4825 }; 4826 4827 rpmhpd_opp_turbo: opp9 { 4828 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4829 }; 4830 4831 rpmhpd_opp_turbo_l1: opp10 { 4832 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4833 }; 4834 }; 4835 }; 4836 }; 4837 4838 intc: interrupt-controller@17a00000 { 4839 compatible = "arm,gic-v3"; 4840 #address-cells = <2>; 4841 #size-cells = <2>; 4842 ranges; 4843 #interrupt-cells = <3>; 4844 interrupt-controller; 4845 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4846 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4847 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4848 4849 msi-controller@17a40000 { 4850 compatible = "arm,gic-v3-its"; 4851 msi-controller; 4852 #msi-cells = <1>; 4853 reg = <0 0x17a40000 0 0x20000>; 4854 status = "disabled"; 4855 }; 4856 }; 4857 4858 slimbam: dma-controller@17184000 { 4859 compatible = "qcom,bam-v1.7.0"; 4860 qcom,controlled-remotely; 4861 reg = <0 0x17184000 0 0x2a000>; 4862 num-channels = <31>; 4863 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 4864 #dma-cells = <1>; 4865 qcom,ee = <1>; 4866 qcom,num-ees = <2>; 4867 iommus = <&apps_smmu 0x1806 0x0>; 4868 }; 4869 4870 timer@17c90000 { 4871 #address-cells = <2>; 4872 #size-cells = <2>; 4873 ranges; 4874 compatible = "arm,armv7-timer-mem"; 4875 reg = <0 0x17c90000 0 0x1000>; 4876 4877 frame@17ca0000 { 4878 frame-number = <0>; 4879 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 4880 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4881 reg = <0 0x17ca0000 0 0x1000>, 4882 <0 0x17cb0000 0 0x1000>; 4883 }; 4884 4885 frame@17cc0000 { 4886 frame-number = <1>; 4887 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 4888 reg = <0 0x17cc0000 0 0x1000>; 4889 status = "disabled"; 4890 }; 4891 4892 frame@17cd0000 { 4893 frame-number = <2>; 4894 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4895 reg = <0 0x17cd0000 0 0x1000>; 4896 status = "disabled"; 4897 }; 4898 4899 frame@17ce0000 { 4900 frame-number = <3>; 4901 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4902 reg = <0 0x17ce0000 0 0x1000>; 4903 status = "disabled"; 4904 }; 4905 4906 frame@17cf0000 { 4907 frame-number = <4>; 4908 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4909 reg = <0 0x17cf0000 0 0x1000>; 4910 status = "disabled"; 4911 }; 4912 4913 frame@17d00000 { 4914 frame-number = <5>; 4915 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4916 reg = <0 0x17d00000 0 0x1000>; 4917 status = "disabled"; 4918 }; 4919 4920 frame@17d10000 { 4921 frame-number = <6>; 4922 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4923 reg = <0 0x17d10000 0 0x1000>; 4924 status = "disabled"; 4925 }; 4926 }; 4927 4928 osm_l3: interconnect@17d41000 { 4929 compatible = "qcom,sdm845-osm-l3"; 4930 reg = <0 0x17d41000 0 0x1400>; 4931 4932 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4933 clock-names = "xo", "alternate"; 4934 4935 #interconnect-cells = <1>; 4936 }; 4937 4938 cpufreq_hw: cpufreq@17d43000 { 4939 compatible = "qcom,cpufreq-hw"; 4940 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 4941 reg-names = "freq-domain0", "freq-domain1"; 4942 4943 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; 4944 4945 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4946 clock-names = "xo", "alternate"; 4947 4948 #freq-domain-cells = <1>; 4949 }; 4950 4951 wifi: wifi@18800000 { 4952 compatible = "qcom,wcn3990-wifi"; 4953 status = "disabled"; 4954 reg = <0 0x18800000 0 0x800000>; 4955 reg-names = "membase"; 4956 memory-region = <&wlan_msa_mem>; 4957 clock-names = "cxo_ref_clk_pin"; 4958 clocks = <&rpmhcc RPMH_RF_CLK2>; 4959 interrupts = 4960 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4961 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4962 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4963 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4964 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4965 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4966 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4967 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4968 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4969 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4970 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4971 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4972 iommus = <&apps_smmu 0x0040 0x1>; 4973 }; 4974 }; 4975 4976 thermal-zones { 4977 cpu0-thermal { 4978 polling-delay-passive = <250>; 4979 polling-delay = <1000>; 4980 4981 thermal-sensors = <&tsens0 1>; 4982 4983 trips { 4984 cpu0_alert0: trip-point0 { 4985 temperature = <90000>; 4986 hysteresis = <2000>; 4987 type = "passive"; 4988 }; 4989 4990 cpu0_alert1: trip-point1 { 4991 temperature = <95000>; 4992 hysteresis = <2000>; 4993 type = "passive"; 4994 }; 4995 4996 cpu0_crit: cpu_crit { 4997 temperature = <110000>; 4998 hysteresis = <1000>; 4999 type = "critical"; 5000 }; 5001 }; 5002 }; 5003 5004 cpu1-thermal { 5005 polling-delay-passive = <250>; 5006 polling-delay = <1000>; 5007 5008 thermal-sensors = <&tsens0 2>; 5009 5010 trips { 5011 cpu1_alert0: trip-point0 { 5012 temperature = <90000>; 5013 hysteresis = <2000>; 5014 type = "passive"; 5015 }; 5016 5017 cpu1_alert1: trip-point1 { 5018 temperature = <95000>; 5019 hysteresis = <2000>; 5020 type = "passive"; 5021 }; 5022 5023 cpu1_crit: cpu_crit { 5024 temperature = <110000>; 5025 hysteresis = <1000>; 5026 type = "critical"; 5027 }; 5028 }; 5029 }; 5030 5031 cpu2-thermal { 5032 polling-delay-passive = <250>; 5033 polling-delay = <1000>; 5034 5035 thermal-sensors = <&tsens0 3>; 5036 5037 trips { 5038 cpu2_alert0: trip-point0 { 5039 temperature = <90000>; 5040 hysteresis = <2000>; 5041 type = "passive"; 5042 }; 5043 5044 cpu2_alert1: trip-point1 { 5045 temperature = <95000>; 5046 hysteresis = <2000>; 5047 type = "passive"; 5048 }; 5049 5050 cpu2_crit: cpu_crit { 5051 temperature = <110000>; 5052 hysteresis = <1000>; 5053 type = "critical"; 5054 }; 5055 }; 5056 }; 5057 5058 cpu3-thermal { 5059 polling-delay-passive = <250>; 5060 polling-delay = <1000>; 5061 5062 thermal-sensors = <&tsens0 4>; 5063 5064 trips { 5065 cpu3_alert0: trip-point0 { 5066 temperature = <90000>; 5067 hysteresis = <2000>; 5068 type = "passive"; 5069 }; 5070 5071 cpu3_alert1: trip-point1 { 5072 temperature = <95000>; 5073 hysteresis = <2000>; 5074 type = "passive"; 5075 }; 5076 5077 cpu3_crit: cpu_crit { 5078 temperature = <110000>; 5079 hysteresis = <1000>; 5080 type = "critical"; 5081 }; 5082 }; 5083 }; 5084 5085 cpu4-thermal { 5086 polling-delay-passive = <250>; 5087 polling-delay = <1000>; 5088 5089 thermal-sensors = <&tsens0 7>; 5090 5091 trips { 5092 cpu4_alert0: trip-point0 { 5093 temperature = <90000>; 5094 hysteresis = <2000>; 5095 type = "passive"; 5096 }; 5097 5098 cpu4_alert1: trip-point1 { 5099 temperature = <95000>; 5100 hysteresis = <2000>; 5101 type = "passive"; 5102 }; 5103 5104 cpu4_crit: cpu_crit { 5105 temperature = <110000>; 5106 hysteresis = <1000>; 5107 type = "critical"; 5108 }; 5109 }; 5110 }; 5111 5112 cpu5-thermal { 5113 polling-delay-passive = <250>; 5114 polling-delay = <1000>; 5115 5116 thermal-sensors = <&tsens0 8>; 5117 5118 trips { 5119 cpu5_alert0: trip-point0 { 5120 temperature = <90000>; 5121 hysteresis = <2000>; 5122 type = "passive"; 5123 }; 5124 5125 cpu5_alert1: trip-point1 { 5126 temperature = <95000>; 5127 hysteresis = <2000>; 5128 type = "passive"; 5129 }; 5130 5131 cpu5_crit: cpu_crit { 5132 temperature = <110000>; 5133 hysteresis = <1000>; 5134 type = "critical"; 5135 }; 5136 }; 5137 }; 5138 5139 cpu6-thermal { 5140 polling-delay-passive = <250>; 5141 polling-delay = <1000>; 5142 5143 thermal-sensors = <&tsens0 9>; 5144 5145 trips { 5146 cpu6_alert0: trip-point0 { 5147 temperature = <90000>; 5148 hysteresis = <2000>; 5149 type = "passive"; 5150 }; 5151 5152 cpu6_alert1: trip-point1 { 5153 temperature = <95000>; 5154 hysteresis = <2000>; 5155 type = "passive"; 5156 }; 5157 5158 cpu6_crit: cpu_crit { 5159 temperature = <110000>; 5160 hysteresis = <1000>; 5161 type = "critical"; 5162 }; 5163 }; 5164 }; 5165 5166 cpu7-thermal { 5167 polling-delay-passive = <250>; 5168 polling-delay = <1000>; 5169 5170 thermal-sensors = <&tsens0 10>; 5171 5172 trips { 5173 cpu7_alert0: trip-point0 { 5174 temperature = <90000>; 5175 hysteresis = <2000>; 5176 type = "passive"; 5177 }; 5178 5179 cpu7_alert1: trip-point1 { 5180 temperature = <95000>; 5181 hysteresis = <2000>; 5182 type = "passive"; 5183 }; 5184 5185 cpu7_crit: cpu_crit { 5186 temperature = <110000>; 5187 hysteresis = <1000>; 5188 type = "critical"; 5189 }; 5190 }; 5191 }; 5192 5193 aoss0-thermal { 5194 polling-delay-passive = <250>; 5195 polling-delay = <1000>; 5196 5197 thermal-sensors = <&tsens0 0>; 5198 5199 trips { 5200 aoss0_alert0: trip-point0 { 5201 temperature = <90000>; 5202 hysteresis = <2000>; 5203 type = "hot"; 5204 }; 5205 }; 5206 }; 5207 5208 cluster0-thermal { 5209 polling-delay-passive = <250>; 5210 polling-delay = <1000>; 5211 5212 thermal-sensors = <&tsens0 5>; 5213 5214 trips { 5215 cluster0_alert0: trip-point0 { 5216 temperature = <90000>; 5217 hysteresis = <2000>; 5218 type = "hot"; 5219 }; 5220 cluster0_crit: cluster0_crit { 5221 temperature = <110000>; 5222 hysteresis = <2000>; 5223 type = "critical"; 5224 }; 5225 }; 5226 }; 5227 5228 cluster1-thermal { 5229 polling-delay-passive = <250>; 5230 polling-delay = <1000>; 5231 5232 thermal-sensors = <&tsens0 6>; 5233 5234 trips { 5235 cluster1_alert0: trip-point0 { 5236 temperature = <90000>; 5237 hysteresis = <2000>; 5238 type = "hot"; 5239 }; 5240 cluster1_crit: cluster1_crit { 5241 temperature = <110000>; 5242 hysteresis = <2000>; 5243 type = "critical"; 5244 }; 5245 }; 5246 }; 5247 5248 gpu-thermal-top { 5249 polling-delay-passive = <250>; 5250 polling-delay = <1000>; 5251 5252 thermal-sensors = <&tsens0 11>; 5253 5254 trips { 5255 gpu1_alert0: trip-point0 { 5256 temperature = <90000>; 5257 hysteresis = <2000>; 5258 type = "hot"; 5259 }; 5260 }; 5261 }; 5262 5263 gpu-thermal-bottom { 5264 polling-delay-passive = <250>; 5265 polling-delay = <1000>; 5266 5267 thermal-sensors = <&tsens0 12>; 5268 5269 trips { 5270 gpu2_alert0: trip-point0 { 5271 temperature = <90000>; 5272 hysteresis = <2000>; 5273 type = "hot"; 5274 }; 5275 }; 5276 }; 5277 5278 aoss1-thermal { 5279 polling-delay-passive = <250>; 5280 polling-delay = <1000>; 5281 5282 thermal-sensors = <&tsens1 0>; 5283 5284 trips { 5285 aoss1_alert0: trip-point0 { 5286 temperature = <90000>; 5287 hysteresis = <2000>; 5288 type = "hot"; 5289 }; 5290 }; 5291 }; 5292 5293 q6-modem-thermal { 5294 polling-delay-passive = <250>; 5295 polling-delay = <1000>; 5296 5297 thermal-sensors = <&tsens1 1>; 5298 5299 trips { 5300 q6_modem_alert0: trip-point0 { 5301 temperature = <90000>; 5302 hysteresis = <2000>; 5303 type = "hot"; 5304 }; 5305 }; 5306 }; 5307 5308 mem-thermal { 5309 polling-delay-passive = <250>; 5310 polling-delay = <1000>; 5311 5312 thermal-sensors = <&tsens1 2>; 5313 5314 trips { 5315 mem_alert0: trip-point0 { 5316 temperature = <90000>; 5317 hysteresis = <2000>; 5318 type = "hot"; 5319 }; 5320 }; 5321 }; 5322 5323 wlan-thermal { 5324 polling-delay-passive = <250>; 5325 polling-delay = <1000>; 5326 5327 thermal-sensors = <&tsens1 3>; 5328 5329 trips { 5330 wlan_alert0: trip-point0 { 5331 temperature = <90000>; 5332 hysteresis = <2000>; 5333 type = "hot"; 5334 }; 5335 }; 5336 }; 5337 5338 q6-hvx-thermal { 5339 polling-delay-passive = <250>; 5340 polling-delay = <1000>; 5341 5342 thermal-sensors = <&tsens1 4>; 5343 5344 trips { 5345 q6_hvx_alert0: trip-point0 { 5346 temperature = <90000>; 5347 hysteresis = <2000>; 5348 type = "hot"; 5349 }; 5350 }; 5351 }; 5352 5353 camera-thermal { 5354 polling-delay-passive = <250>; 5355 polling-delay = <1000>; 5356 5357 thermal-sensors = <&tsens1 5>; 5358 5359 trips { 5360 camera_alert0: trip-point0 { 5361 temperature = <90000>; 5362 hysteresis = <2000>; 5363 type = "hot"; 5364 }; 5365 }; 5366 }; 5367 5368 video-thermal { 5369 polling-delay-passive = <250>; 5370 polling-delay = <1000>; 5371 5372 thermal-sensors = <&tsens1 6>; 5373 5374 trips { 5375 video_alert0: trip-point0 { 5376 temperature = <90000>; 5377 hysteresis = <2000>; 5378 type = "hot"; 5379 }; 5380 }; 5381 }; 5382 5383 modem-thermal { 5384 polling-delay-passive = <250>; 5385 polling-delay = <1000>; 5386 5387 thermal-sensors = <&tsens1 7>; 5388 5389 trips { 5390 modem_alert0: trip-point0 { 5391 temperature = <90000>; 5392 hysteresis = <2000>; 5393 type = "hot"; 5394 }; 5395 }; 5396 }; 5397 }; 5398}; 5399