1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas R-Car GPIO Support 4 * 5 * Copyright (C) 2014 Renesas Electronics Corporation 6 * Copyright (C) 2013 Magnus Damm 7 */ 8 9 #include <linux/err.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/ioport.h> 15 #include <linux/irq.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/spinlock.h> 23 #include <linux/slab.h> 24 25 struct gpio_rcar_bank_info { 26 u32 iointsel; 27 u32 inoutsel; 28 u32 outdt; 29 u32 posneg; 30 u32 edglevel; 31 u32 bothedge; 32 u32 intmsk; 33 }; 34 35 struct gpio_rcar_info { 36 bool has_outdtsel; 37 bool has_both_edge_trigger; 38 bool has_always_in; 39 bool has_inen; 40 }; 41 42 struct gpio_rcar_priv { 43 void __iomem *base; 44 spinlock_t lock; 45 struct device *dev; 46 struct gpio_chip gpio_chip; 47 unsigned int irq_parent; 48 atomic_t wakeup_path; 49 struct gpio_rcar_info info; 50 struct gpio_rcar_bank_info bank_info; 51 }; 52 53 #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */ 54 #define INOUTSEL 0x04 /* General Input/Output Switching Register */ 55 #define OUTDT 0x08 /* General Output Register */ 56 #define INDT 0x0c /* General Input Register */ 57 #define INTDT 0x10 /* Interrupt Display Register */ 58 #define INTCLR 0x14 /* Interrupt Clear Register */ 59 #define INTMSK 0x18 /* Interrupt Mask Register */ 60 #define MSKCLR 0x1c /* Interrupt Mask Clear Register */ 61 #define POSNEG 0x20 /* Positive/Negative Logic Select Register */ 62 #define EDGLEVEL 0x24 /* Edge/level Select Register */ 63 #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */ 64 #define OUTDTSEL 0x40 /* Output Data Select Register */ 65 #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */ 66 #define INEN 0x50 /* General Input Enable Register */ 67 68 #define RCAR_MAX_GPIO_PER_BANK 32 69 70 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs) 71 { 72 return ioread32(p->base + offs); 73 } 74 75 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs, 76 u32 value) 77 { 78 iowrite32(value, p->base + offs); 79 } 80 81 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs, 82 int bit, bool value) 83 { 84 u32 tmp = gpio_rcar_read(p, offs); 85 86 if (value) 87 tmp |= BIT(bit); 88 else 89 tmp &= ~BIT(bit); 90 91 gpio_rcar_write(p, offs, tmp); 92 } 93 94 static void gpio_rcar_irq_disable(struct irq_data *d) 95 { 96 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 97 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 98 irq_hw_number_t hwirq = irqd_to_hwirq(d); 99 100 gpio_rcar_write(p, INTMSK, ~BIT(hwirq)); 101 gpiochip_disable_irq(gc, hwirq); 102 } 103 104 static void gpio_rcar_irq_enable(struct irq_data *d) 105 { 106 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 107 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 108 irq_hw_number_t hwirq = irqd_to_hwirq(d); 109 110 gpiochip_enable_irq(gc, hwirq); 111 gpio_rcar_write(p, MSKCLR, BIT(hwirq)); 112 } 113 114 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, 115 unsigned int hwirq, 116 bool active_high_rising_edge, 117 bool level_trigger, 118 bool both) 119 { 120 unsigned long flags; 121 122 /* follow steps in the GPIO documentation for 123 * "Setting Edge-Sensitive Interrupt Input Mode" and 124 * "Setting Level-Sensitive Interrupt Input Mode" 125 */ 126 127 spin_lock_irqsave(&p->lock, flags); 128 129 /* Configure positive or negative logic in POSNEG */ 130 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge); 131 132 /* Configure edge or level trigger in EDGLEVEL */ 133 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); 134 135 /* Select one edge or both edges in BOTHEDGE */ 136 if (p->info.has_both_edge_trigger) 137 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both); 138 139 /* Select "Interrupt Input Mode" in IOINTSEL */ 140 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); 141 142 /* Write INTCLR in case of edge trigger */ 143 if (!level_trigger) 144 gpio_rcar_write(p, INTCLR, BIT(hwirq)); 145 146 spin_unlock_irqrestore(&p->lock, flags); 147 } 148 149 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) 150 { 151 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 152 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 153 unsigned int hwirq = irqd_to_hwirq(d); 154 155 dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type); 156 157 switch (type & IRQ_TYPE_SENSE_MASK) { 158 case IRQ_TYPE_LEVEL_HIGH: 159 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true, 160 false); 161 break; 162 case IRQ_TYPE_LEVEL_LOW: 163 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true, 164 false); 165 break; 166 case IRQ_TYPE_EDGE_RISING: 167 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, 168 false); 169 break; 170 case IRQ_TYPE_EDGE_FALLING: 171 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false, 172 false); 173 break; 174 case IRQ_TYPE_EDGE_BOTH: 175 if (!p->info.has_both_edge_trigger) 176 return -EINVAL; 177 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, 178 true); 179 break; 180 default: 181 return -EINVAL; 182 } 183 return 0; 184 } 185 186 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on) 187 { 188 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 189 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 190 int error; 191 192 if (p->irq_parent) { 193 error = irq_set_irq_wake(p->irq_parent, on); 194 if (error) { 195 dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n", 196 p->irq_parent); 197 p->irq_parent = 0; 198 } 199 } 200 201 if (on) 202 atomic_inc(&p->wakeup_path); 203 else 204 atomic_dec(&p->wakeup_path); 205 206 return 0; 207 } 208 209 static const struct irq_chip gpio_rcar_irq_chip = { 210 .name = "gpio-rcar", 211 .irq_mask = gpio_rcar_irq_disable, 212 .irq_unmask = gpio_rcar_irq_enable, 213 .irq_set_type = gpio_rcar_irq_set_type, 214 .irq_set_wake = gpio_rcar_irq_set_wake, 215 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED | 216 IRQCHIP_MASK_ON_SUSPEND, 217 GPIOCHIP_IRQ_RESOURCE_HELPERS, 218 }; 219 220 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) 221 { 222 struct gpio_rcar_priv *p = dev_id; 223 u32 pending; 224 unsigned int offset, irqs_handled = 0; 225 226 while ((pending = gpio_rcar_read(p, INTDT) & 227 gpio_rcar_read(p, INTMSK))) { 228 offset = __ffs(pending); 229 gpio_rcar_write(p, INTCLR, BIT(offset)); 230 generic_handle_domain_irq(p->gpio_chip.irq.domain, 231 offset); 232 irqs_handled++; 233 } 234 235 return irqs_handled ? IRQ_HANDLED : IRQ_NONE; 236 } 237 238 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip, 239 unsigned int gpio, 240 bool output) 241 { 242 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 243 unsigned long flags; 244 245 /* follow steps in the GPIO documentation for 246 * "Setting General Output Mode" and 247 * "Setting General Input Mode" 248 */ 249 250 spin_lock_irqsave(&p->lock, flags); 251 252 /* Configure positive logic in POSNEG */ 253 gpio_rcar_modify_bit(p, POSNEG, gpio, false); 254 255 /* Select "General Input/Output Mode" in IOINTSEL */ 256 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false); 257 258 /* Select Input Mode or Output Mode in INOUTSEL */ 259 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output); 260 261 /* Select General Output Register to output data in OUTDTSEL */ 262 if (p->info.has_outdtsel && output) 263 gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false); 264 265 spin_unlock_irqrestore(&p->lock, flags); 266 } 267 268 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset) 269 { 270 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 271 int error; 272 273 error = pm_runtime_get_sync(p->dev); 274 if (error < 0) { 275 pm_runtime_put(p->dev); 276 return error; 277 } 278 279 error = pinctrl_gpio_request(chip->base + offset); 280 if (error) 281 pm_runtime_put(p->dev); 282 283 return error; 284 } 285 286 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset) 287 { 288 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 289 290 pinctrl_gpio_free(chip->base + offset); 291 292 /* 293 * Set the GPIO as an input to ensure that the next GPIO request won't 294 * drive the GPIO pin as an output. 295 */ 296 gpio_rcar_config_general_input_output_mode(chip, offset, false); 297 298 pm_runtime_put(p->dev); 299 } 300 301 static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset) 302 { 303 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 304 305 if (gpio_rcar_read(p, INOUTSEL) & BIT(offset)) 306 return GPIO_LINE_DIRECTION_OUT; 307 308 return GPIO_LINE_DIRECTION_IN; 309 } 310 311 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) 312 { 313 gpio_rcar_config_general_input_output_mode(chip, offset, false); 314 return 0; 315 } 316 317 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset) 318 { 319 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 320 u32 bit = BIT(offset); 321 322 /* 323 * Before R-Car Gen3, INDT does not show correct pin state when 324 * configured as output, so use OUTDT in case of output pins 325 */ 326 if (!p->info.has_always_in && (gpio_rcar_read(p, INOUTSEL) & bit)) 327 return !!(gpio_rcar_read(p, OUTDT) & bit); 328 else 329 return !!(gpio_rcar_read(p, INDT) & bit); 330 } 331 332 static int gpio_rcar_get_multiple(struct gpio_chip *chip, unsigned long *mask, 333 unsigned long *bits) 334 { 335 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 336 u32 bankmask, outputs, m, val = 0; 337 unsigned long flags; 338 339 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); 340 if (chip->valid_mask) 341 bankmask &= chip->valid_mask[0]; 342 343 if (!bankmask) 344 return 0; 345 346 if (p->info.has_always_in) { 347 bits[0] = gpio_rcar_read(p, INDT) & bankmask; 348 return 0; 349 } 350 351 spin_lock_irqsave(&p->lock, flags); 352 outputs = gpio_rcar_read(p, INOUTSEL); 353 m = outputs & bankmask; 354 if (m) 355 val |= gpio_rcar_read(p, OUTDT) & m; 356 357 m = ~outputs & bankmask; 358 if (m) 359 val |= gpio_rcar_read(p, INDT) & m; 360 spin_unlock_irqrestore(&p->lock, flags); 361 362 bits[0] = val; 363 return 0; 364 } 365 366 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value) 367 { 368 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 369 unsigned long flags; 370 371 spin_lock_irqsave(&p->lock, flags); 372 gpio_rcar_modify_bit(p, OUTDT, offset, value); 373 spin_unlock_irqrestore(&p->lock, flags); 374 } 375 376 static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask, 377 unsigned long *bits) 378 { 379 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 380 unsigned long flags; 381 u32 val, bankmask; 382 383 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); 384 if (chip->valid_mask) 385 bankmask &= chip->valid_mask[0]; 386 387 if (!bankmask) 388 return; 389 390 spin_lock_irqsave(&p->lock, flags); 391 val = gpio_rcar_read(p, OUTDT); 392 val &= ~bankmask; 393 val |= (bankmask & bits[0]); 394 gpio_rcar_write(p, OUTDT, val); 395 spin_unlock_irqrestore(&p->lock, flags); 396 } 397 398 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset, 399 int value) 400 { 401 /* write GPIO value to output before selecting output mode of pin */ 402 gpio_rcar_set(chip, offset, value); 403 gpio_rcar_config_general_input_output_mode(chip, offset, true); 404 return 0; 405 } 406 407 static const struct gpio_rcar_info gpio_rcar_info_gen1 = { 408 .has_outdtsel = false, 409 .has_both_edge_trigger = false, 410 .has_always_in = false, 411 .has_inen = false, 412 }; 413 414 static const struct gpio_rcar_info gpio_rcar_info_gen2 = { 415 .has_outdtsel = true, 416 .has_both_edge_trigger = true, 417 .has_always_in = false, 418 .has_inen = false, 419 }; 420 421 static const struct gpio_rcar_info gpio_rcar_info_gen3 = { 422 .has_outdtsel = true, 423 .has_both_edge_trigger = true, 424 .has_always_in = true, 425 .has_inen = false, 426 }; 427 428 static const struct gpio_rcar_info gpio_rcar_info_gen4 = { 429 .has_outdtsel = true, 430 .has_both_edge_trigger = true, 431 .has_always_in = true, 432 .has_inen = true, 433 }; 434 435 static const struct of_device_id gpio_rcar_of_table[] = { 436 { 437 .compatible = "renesas,gpio-r8a779a0", 438 .data = &gpio_rcar_info_gen4, 439 }, { 440 .compatible = "renesas,rcar-gen1-gpio", 441 .data = &gpio_rcar_info_gen1, 442 }, { 443 .compatible = "renesas,rcar-gen2-gpio", 444 .data = &gpio_rcar_info_gen2, 445 }, { 446 .compatible = "renesas,rcar-gen3-gpio", 447 .data = &gpio_rcar_info_gen3, 448 }, { 449 .compatible = "renesas,rcar-gen4-gpio", 450 .data = &gpio_rcar_info_gen4, 451 }, { 452 .compatible = "renesas,gpio-rcar", 453 .data = &gpio_rcar_info_gen1, 454 }, { 455 /* Terminator */ 456 }, 457 }; 458 459 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table); 460 461 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins) 462 { 463 struct device_node *np = p->dev->of_node; 464 const struct gpio_rcar_info *info; 465 struct of_phandle_args args; 466 int ret; 467 468 info = of_device_get_match_data(p->dev); 469 p->info = *info; 470 471 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args); 472 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK; 473 474 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) { 475 dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n", 476 *npins, RCAR_MAX_GPIO_PER_BANK); 477 *npins = RCAR_MAX_GPIO_PER_BANK; 478 } 479 480 return 0; 481 } 482 483 static void gpio_rcar_enable_inputs(struct gpio_rcar_priv *p) 484 { 485 u32 mask = GENMASK(p->gpio_chip.ngpio - 1, 0); 486 487 /* Select "Input Enable" in INEN */ 488 if (p->gpio_chip.valid_mask) 489 mask &= p->gpio_chip.valid_mask[0]; 490 if (mask) 491 gpio_rcar_write(p, INEN, gpio_rcar_read(p, INEN) | mask); 492 } 493 494 static int gpio_rcar_probe(struct platform_device *pdev) 495 { 496 struct gpio_rcar_priv *p; 497 struct gpio_chip *gpio_chip; 498 struct gpio_irq_chip *girq; 499 struct device *dev = &pdev->dev; 500 const char *name = dev_name(dev); 501 unsigned int npins; 502 int ret; 503 504 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); 505 if (!p) 506 return -ENOMEM; 507 508 p->dev = dev; 509 spin_lock_init(&p->lock); 510 511 /* Get device configuration from DT node */ 512 ret = gpio_rcar_parse_dt(p, &npins); 513 if (ret < 0) 514 return ret; 515 516 platform_set_drvdata(pdev, p); 517 518 pm_runtime_enable(dev); 519 520 ret = platform_get_irq(pdev, 0); 521 if (ret < 0) 522 goto err0; 523 p->irq_parent = ret; 524 525 p->base = devm_platform_ioremap_resource(pdev, 0); 526 if (IS_ERR(p->base)) { 527 ret = PTR_ERR(p->base); 528 goto err0; 529 } 530 531 gpio_chip = &p->gpio_chip; 532 gpio_chip->request = gpio_rcar_request; 533 gpio_chip->free = gpio_rcar_free; 534 gpio_chip->get_direction = gpio_rcar_get_direction; 535 gpio_chip->direction_input = gpio_rcar_direction_input; 536 gpio_chip->get = gpio_rcar_get; 537 gpio_chip->get_multiple = gpio_rcar_get_multiple; 538 gpio_chip->direction_output = gpio_rcar_direction_output; 539 gpio_chip->set = gpio_rcar_set; 540 gpio_chip->set_multiple = gpio_rcar_set_multiple; 541 gpio_chip->label = name; 542 gpio_chip->parent = dev; 543 gpio_chip->owner = THIS_MODULE; 544 gpio_chip->base = -1; 545 gpio_chip->ngpio = npins; 546 547 girq = &gpio_chip->irq; 548 gpio_irq_chip_set_chip(girq, &gpio_rcar_irq_chip); 549 /* This will let us handle the parent IRQ in the driver */ 550 girq->parent_handler = NULL; 551 girq->num_parents = 0; 552 girq->parents = NULL; 553 girq->default_type = IRQ_TYPE_NONE; 554 girq->handler = handle_level_irq; 555 556 ret = gpiochip_add_data(gpio_chip, p); 557 if (ret) { 558 dev_err(dev, "failed to add GPIO controller\n"); 559 goto err0; 560 } 561 562 irq_domain_set_pm_device(gpio_chip->irq.domain, dev); 563 ret = devm_request_irq(dev, p->irq_parent, gpio_rcar_irq_handler, 564 IRQF_SHARED, name, p); 565 if (ret) { 566 dev_err(dev, "failed to request IRQ\n"); 567 goto err1; 568 } 569 570 if (p->info.has_inen) { 571 pm_runtime_get_sync(dev); 572 gpio_rcar_enable_inputs(p); 573 pm_runtime_put(dev); 574 } 575 576 dev_info(dev, "driving %d GPIOs\n", npins); 577 578 return 0; 579 580 err1: 581 gpiochip_remove(gpio_chip); 582 err0: 583 pm_runtime_disable(dev); 584 return ret; 585 } 586 587 static int gpio_rcar_remove(struct platform_device *pdev) 588 { 589 struct gpio_rcar_priv *p = platform_get_drvdata(pdev); 590 591 gpiochip_remove(&p->gpio_chip); 592 593 pm_runtime_disable(&pdev->dev); 594 return 0; 595 } 596 597 #ifdef CONFIG_PM_SLEEP 598 static int gpio_rcar_suspend(struct device *dev) 599 { 600 struct gpio_rcar_priv *p = dev_get_drvdata(dev); 601 602 p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL); 603 p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL); 604 p->bank_info.outdt = gpio_rcar_read(p, OUTDT); 605 p->bank_info.intmsk = gpio_rcar_read(p, INTMSK); 606 p->bank_info.posneg = gpio_rcar_read(p, POSNEG); 607 p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL); 608 if (p->info.has_both_edge_trigger) 609 p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE); 610 611 if (atomic_read(&p->wakeup_path)) 612 device_set_wakeup_path(dev); 613 614 return 0; 615 } 616 617 static int gpio_rcar_resume(struct device *dev) 618 { 619 struct gpio_rcar_priv *p = dev_get_drvdata(dev); 620 unsigned int offset; 621 u32 mask; 622 623 for (offset = 0; offset < p->gpio_chip.ngpio; offset++) { 624 if (!gpiochip_line_is_valid(&p->gpio_chip, offset)) 625 continue; 626 627 mask = BIT(offset); 628 /* I/O pin */ 629 if (!(p->bank_info.iointsel & mask)) { 630 if (p->bank_info.inoutsel & mask) 631 gpio_rcar_direction_output( 632 &p->gpio_chip, offset, 633 !!(p->bank_info.outdt & mask)); 634 else 635 gpio_rcar_direction_input(&p->gpio_chip, 636 offset); 637 } else { 638 /* Interrupt pin */ 639 gpio_rcar_config_interrupt_input_mode( 640 p, 641 offset, 642 !(p->bank_info.posneg & mask), 643 !(p->bank_info.edglevel & mask), 644 !!(p->bank_info.bothedge & mask)); 645 646 if (p->bank_info.intmsk & mask) 647 gpio_rcar_write(p, MSKCLR, mask); 648 } 649 } 650 651 if (p->info.has_inen) 652 gpio_rcar_enable_inputs(p); 653 654 return 0; 655 } 656 #endif /* CONFIG_PM_SLEEP*/ 657 658 static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume); 659 660 static struct platform_driver gpio_rcar_device_driver = { 661 .probe = gpio_rcar_probe, 662 .remove = gpio_rcar_remove, 663 .driver = { 664 .name = "gpio_rcar", 665 .pm = &gpio_rcar_pm_ops, 666 .of_match_table = gpio_rcar_of_table, 667 } 668 }; 669 670 module_platform_driver(gpio_rcar_device_driver); 671 672 MODULE_AUTHOR("Magnus Damm"); 673 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver"); 674 MODULE_LICENSE("GPL v2"); 675